From d8c0144f8b45ef8a94fc696efaa0c782c4c787af Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Jun 2017 13:43:35 -0700 Subject: gpu: nvgpu: add clear_sm_hww gr ops Required for multiple SM support and t19x SM register address changes JIRA GPUT19X-75 Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1514043 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 ++ drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 21 ++++----------------- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 ---- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 13 +++++++++++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 3 ++- 5 files changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 483cdd6e..95b93496 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -300,6 +300,8 @@ struct gpu_ops { u32 global_esr_mask, bool check_errors); int (*wait_for_sm_lock_down)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, bool check_errors); + void (*clear_sm_hww)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, + u32 global_esr); void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, u32 *esr_sm_sel); int (*handle_sm_exception)(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d2c77c93..4bedcc9a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -5501,21 +5501,6 @@ bool gk20a_gr_sm_debugger_attached(struct gk20a *g) return false; } -void gk20a_gr_clear_sm_hww(struct gk20a *g, - u32 gpc, u32 tpc, u32 global_esr) -{ - u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); - u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); - u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; - - gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, - global_esr); - - /* clear the warp hww */ - gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, - gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f()); -} - int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, bool *post_event, struct channel_gk20a *fault_ch, u32 *hww_global_esr) @@ -5678,7 +5663,8 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, /* clear the hwws, also causes tpc and gpc * exceptions to be cleared */ - gk20a_gr_clear_sm_hww(g, gpc, tpc, *hww_global_esr); + g->ops.gr.clear_sm_hww(g, + gpc, tpc, sm, *hww_global_esr); } @@ -8439,7 +8425,8 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g) /* clearing hwws, also causes tpc and gpc * exceptions to be cleared */ - gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr); + g->ops.gr.clear_sm_hww(g, + gpc, tpc, sm, global_esr); } } } diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 77db5cf6..436377bd 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -539,8 +539,6 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config); /* sm */ bool gk20a_gr_sm_debugger_attached(struct gk20a *g); -void gk20a_gr_clear_sm_hww(struct gk20a *g, - u32 gpc, u32 tpc, u32 global_esr); u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); #define gr_gk20a_elpg_protected_call(g, func) \ @@ -683,8 +681,6 @@ int gk20a_gr_lock_down_sm(struct gk20a *g, bool check_errors); int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, bool check_errors); -void gk20a_gr_clear_sm_hww(struct gk20a *g, - u32 gpc, u32 tpc, u32 global_esr); int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, u32 *mailbox_ret, u32 opc_success, u32 mailbox_ok, u32 opc_fail, diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 333f0340..90046232 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1530,6 +1530,18 @@ static void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr, priv_addr_table, priv_addr_table_index); } +static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, + u32 global_esr) +{ + u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); + + gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, + global_esr); + + /* clear the warp hww */ + gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); +} + void gm20b_init_gr(struct gpu_ops *gops) { gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; @@ -1640,4 +1652,5 @@ void gm20b_init_gr(struct gpu_ops *gops) gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask; gops->gr.lock_down_sm = gk20a_gr_lock_down_sm; gops->gr.wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down; + gops->gr.clear_sm_hww = gm20b_gr_clear_sm_hww; } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 27d609d1..4ff306e0 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1835,7 +1835,8 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, /* reset the HWW errors after locking down */ global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g, gpc, tpc, sm); - gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); + g->ops.gr.clear_sm_hww(g, + gpc, tpc, sm, global_esr_copy); gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: HWWs cleared for gpc %d tpc %d\n", gpc, tpc); -- cgit v1.2.2