From d859c5f4a03b975dc493f72a35016e83adad279a Mon Sep 17 00:00:00 2001 From: Vinod G Date: Tue, 10 Jul 2018 16:13:03 -0700 Subject: nvgpu: gv11b: Rearrange gr function Moved gv11b_detect_ecc_enabled_units function from gv11b.c to gr_gv11b.c, as this is being used only in gr_gv11b file. In order to avoid GR code touching fuse registers, as it need to include fuse HW headers in GR code, introduced two fuse HALs which are being called from GR code. is_opt_ecc_enable for checking whether ecc enable bit is set in fuse register and is_opt_feature_overide_disable for checking whether feature override disable bit is set in fuse register. Initialized fuse HAL functions for chips that make use of those HAL functions. JIRA NVGPU-615 Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/1775564 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 + drivers/gpu/nvgpu/gp106/hal_gp106.c | 4 + drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | 13 ++- drivers/gpu/nvgpu/gp10b/fuse_gp10b.h | 4 +- drivers/gpu/nvgpu/gp10b/gp10b.c | 26 +++--- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 12 +-- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 6 ++ drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 116 +++++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/gv11b.c | 121 -------------------------- drivers/gpu/nvgpu/gv11b/gv11b.h | 1 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 + drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 4 + drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 6 ++ 14 files changed, 177 insertions(+), 144 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 4ff85ee3..d6e0342b 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -1246,6 +1246,8 @@ struct gpu_ops { } priv_ring; struct { int (*check_priv_security)(struct gk20a *g); + bool (*is_opt_ecc_enable)(struct gk20a *g); + bool (*is_opt_feature_override_disable)(struct gk20a *g); } fuse; struct { int (*init)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 63e6206a..9490ec10 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -56,6 +56,7 @@ #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_gp10b.h" #include "gp10b/priv_ring_gp10b.h" +#include "gp10b/fuse_gp10b.h" #include "gp106/fifo_gp106.h" #include "gp106/regops_gp106.h" @@ -781,6 +782,9 @@ static const struct gpu_ops gp106_ops = { }, .fuse = { .check_priv_security = gp106_fuse_check_priv_security, + .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, + .is_opt_feature_override_disable = + gp10b_fuse_is_opt_feature_override_disable, }, .get_litter_value = gp106_get_litter_value, .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c index c1fc6be7..52087676 100644 --- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B FUSE * - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -91,3 +91,14 @@ int gp10b_fuse_check_priv_security(struct gk20a *g) return 0; } + +bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g) +{ + return gk20a_readl(g, fuse_opt_ecc_en_r()) != 0U; +} + +bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g) +{ + return gk20a_readl(g, + fuse_opt_feature_fuses_override_disable_r()) != 0U; +} diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h index 1acb45d1..d9037e22 100644 --- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h @@ -1,7 +1,7 @@ /* * GP10B FUSE * - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,5 +28,7 @@ struct gk20a; int gp10b_fuse_check_priv_security(struct gk20a *g); +bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g); +bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c index 51dc4301..7991944c 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b.c @@ -1,7 +1,7 @@ /* * GP10B Graphics * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,15 +28,13 @@ #include "gp10b.h" -#include #include static void gp10b_detect_ecc_enabled_units(struct gk20a *g) { - u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); - u32 opt_feature_fuses_override_disable = - gk20a_readl(g, - fuse_opt_feature_fuses_override_disable_r()); + bool opt_ecc_en = g->ops.fuse.is_opt_ecc_enable(g); + bool opt_feature_fuses_override_disable = + g->ops.fuse.is_opt_feature_override_disable(g); u32 fecs_feature_override_ecc = gk20a_readl(g, gr_fecs_feature_override_ecc_r()); @@ -51,9 +49,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) } else { /* SM LRF */ if (gr_fecs_feature_override_ecc_sm_lrf_override_v( - fecs_feature_override_ecc)) { + fecs_feature_override_ecc) == 1U) { if (gr_fecs_feature_override_ecc_sm_lrf_v( - fecs_feature_override_ecc)) { + fecs_feature_override_ecc) == 1U) { __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_LRF, true); } @@ -66,9 +64,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) /* SM SHM */ if (gr_fecs_feature_override_ecc_sm_shm_override_v( - fecs_feature_override_ecc)) { + fecs_feature_override_ecc) == 1U) { if (gr_fecs_feature_override_ecc_sm_shm_v( - fecs_feature_override_ecc)) { + fecs_feature_override_ecc) == 1U) { __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_SHM, true); } @@ -81,9 +79,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) /* TEX */ if (gr_fecs_feature_override_ecc_tex_override_v( - fecs_feature_override_ecc)) { + fecs_feature_override_ecc) == 1U) { if (gr_fecs_feature_override_ecc_tex_v( - fecs_feature_override_ecc)) { + fecs_feature_override_ecc) == 1U) { __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_TEX, true); } @@ -96,9 +94,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) /* LTC */ if (gr_fecs_feature_override_ecc_ltc_override_v( - fecs_feature_override_ecc)) { + fecs_feature_override_ecc) == 1U) { if (gr_fecs_feature_override_ecc_ltc_v( - fecs_feature_override_ecc)) { + fecs_feature_override_ecc) == 1U) { __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 424c8490..16eddeca 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -43,7 +43,6 @@ #include #include #include -#include #define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000 @@ -2022,11 +2021,14 @@ u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g, u32 get_ecc_override_val(struct gk20a *g) { - u32 val; + bool en = false; - val = gk20a_readl(g, fuse_opt_ecc_en_r()); - if (val) - return gk20a_readl(g, gr_fecs_feature_override_ecc_r()); + if (g->ops.fuse.is_opt_ecc_enable) { + en = g->ops.fuse.is_opt_ecc_enable(g); + if (en) { + return gk20a_readl(g, gr_fecs_feature_override_ecc_r()); + } + } return 0; } diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index bbfce287..94adf727 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -694,6 +694,9 @@ static const struct gpu_ops gp10b_ops = { }, .fuse = { .check_priv_security = gp10b_fuse_check_priv_security, + .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, + .is_opt_feature_override_disable = + gp10b_fuse_is_opt_feature_override_disable, }, .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, .get_litter_value = gp10b_get_litter_value, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 6f340e6a..ebcab011 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -73,6 +73,7 @@ #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/mm_gp10b.h" #include "gp10b/pmu_gp10b.h" +#include "gp10b/fuse_gp10b.h" #include "gv11b/css_gr_gv11b.h" #include "gv11b/dbg_gpu_gv11b.h" @@ -872,6 +873,11 @@ static const struct gpu_ops gv100_ops = { .set_ppriv_timeout_settings = gk20a_priv_set_timeout_settings, }, + .fuse = { + .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, + .is_opt_feature_override_disable = + gp10b_fuse_is_opt_feature_override_disable, + }, #if defined(CONFIG_TEGRA_NVLINK) .nvlink = { .discover_ioctrl = gv100_nvlink_discover_ioctrl, diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 6ceaa47a..d3fe5f65 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -4488,11 +4488,125 @@ static int gr_gv11b_ecc_scrub_sm_icahe(struct gk20a *g) scrub_mask, scrub_done); } +static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g) +{ + bool opt_ecc_en = g->ops.fuse.is_opt_ecc_enable(g); + bool opt_feature_fuses_override_disable = + g->ops.fuse.is_opt_feature_override_disable(g); + u32 fecs_feature_override_ecc = + gk20a_readl(g, + gr_fecs_feature_override_ecc_r()); + + if (opt_feature_fuses_override_disable) { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_LRF, true); + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_DATA, true); + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_TAG, true); + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_ICACHE, true); + __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); + __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true); + } + } else { + /* SM LRF */ + if (gr_fecs_feature_override_ecc_sm_lrf_override_v( + fecs_feature_override_ecc) == 1U) { + if (gr_fecs_feature_override_ecc_sm_lrf_v( + fecs_feature_override_ecc) == 1U) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_LRF, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_LRF, true); + } + } + /* SM L1 DATA*/ + if (gr_fecs_feature_override_ecc_sm_l1_data_override_v( + fecs_feature_override_ecc) == 1U) { + if (gr_fecs_feature_override_ecc_sm_l1_data_v( + fecs_feature_override_ecc) == 1U) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_DATA, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_DATA, true); + } + } + /* SM L1 TAG*/ + if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v( + fecs_feature_override_ecc) == 1U) { + if (gr_fecs_feature_override_ecc_sm_l1_tag_v( + fecs_feature_override_ecc) == 1U) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_TAG, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_TAG, true); + } + } + /* SM ICACHE*/ + if ((gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v( + fecs_feature_override_ecc) == 1U) && + (gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v( + fecs_feature_override_ecc) == 1U)) { + if ((gr_fecs_feature_override_ecc_1_sm_l0_icache_v( + fecs_feature_override_ecc) == 1U) && + (gr_fecs_feature_override_ecc_1_sm_l1_icache_v( + fecs_feature_override_ecc) == 1U)) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_ICACHE, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_ICACHE, true); + } + } + /* LTC */ + if (gr_fecs_feature_override_ecc_ltc_override_v( + fecs_feature_override_ecc) == 1U) { + if (gr_fecs_feature_override_ecc_ltc_v( + fecs_feature_override_ecc) == 1U) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_LTC, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_LTC, true); + } + } + /* SM CBU */ + if (gr_fecs_feature_override_ecc_sm_cbu_override_v( + fecs_feature_override_ecc) == 1U) { + if (gr_fecs_feature_override_ecc_sm_cbu_v( + fecs_feature_override_ecc) == 1U) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_CBU, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_CBU, true); + } + } + } +} + void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) { nvgpu_log_fn(g, "ecc srub start "); - gv11b_detect_ecc_enabled_units(g); + gr_gv11b_detect_ecc_enabled_units(g); if (gr_gv11b_ecc_scrub_sm_lrf(g)) nvgpu_warn(g, "ECC SCRUB SM LRF Failed"); diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index 44120498..5d2bfbd7 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c @@ -25,128 +25,7 @@ #include #include "gk20a/gk20a.h" -#include "gp10b/gp10b.h" - #include "gv11b/gv11b.h" -#include -#include - -void gv11b_detect_ecc_enabled_units(struct gk20a *g) -{ - u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); - u32 opt_feature_fuses_override_disable = - gk20a_readl(g, - fuse_opt_feature_fuses_override_disable_r()); - u32 fecs_feature_override_ecc = - gk20a_readl(g, - gr_fecs_feature_override_ecc_r()); - - if (opt_feature_fuses_override_disable) { - if (opt_ecc_en) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_LRF, true); - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_L1_DATA, true); - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_L1_TAG, true); - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_ICACHE, true); - __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); - __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true); - } - } else { - /* SM LRF */ - if (gr_fecs_feature_override_ecc_sm_lrf_override_v( - fecs_feature_override_ecc)) { - if (gr_fecs_feature_override_ecc_sm_lrf_v( - fecs_feature_override_ecc)) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_LRF, true); - } - } else { - if (opt_ecc_en) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_LRF, true); - } - } - /* SM L1 DATA*/ - if (gr_fecs_feature_override_ecc_sm_l1_data_override_v( - fecs_feature_override_ecc)) { - if (gr_fecs_feature_override_ecc_sm_l1_data_v( - fecs_feature_override_ecc)) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_L1_DATA, true); - } - } else { - if (opt_ecc_en) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_L1_DATA, true); - } - } - /* SM L1 TAG*/ - if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v( - fecs_feature_override_ecc)) { - if (gr_fecs_feature_override_ecc_sm_l1_tag_v( - fecs_feature_override_ecc)) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_L1_TAG, true); - } - } else { - if (opt_ecc_en) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_L1_TAG, true); - } - } - /* SM ICACHE*/ - if (gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v( - fecs_feature_override_ecc) && - gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v( - fecs_feature_override_ecc)) { - if (gr_fecs_feature_override_ecc_1_sm_l0_icache_v( - fecs_feature_override_ecc) && - gr_fecs_feature_override_ecc_1_sm_l1_icache_v( - fecs_feature_override_ecc)) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_ICACHE, true); - } - } else { - if (opt_ecc_en) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_ICACHE, true); - } - } - /* LTC */ - if (gr_fecs_feature_override_ecc_ltc_override_v( - fecs_feature_override_ecc)) { - if (gr_fecs_feature_override_ecc_ltc_v( - fecs_feature_override_ecc)) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_LTC, true); - } - } else { - if (opt_ecc_en) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_LTC, true); - } - } - /* SM CBU */ - if (gr_fecs_feature_override_ecc_sm_cbu_override_v( - fecs_feature_override_ecc)) { - if (gr_fecs_feature_override_ecc_sm_cbu_v( - fecs_feature_override_ecc)) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_CBU, true); - } - } else { - if (opt_ecc_en) { - __nvgpu_set_enabled(g, - NVGPU_ECC_ENABLED_SM_CBU, true); - } - } - } -} - - int gv11b_init_gpu_characteristics(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.h b/drivers/gpu/nvgpu/gv11b/gv11b.h index 17dfa7aa..3d5490e6 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gv11b.h @@ -27,7 +27,6 @@ #include "gk20a/gk20a.h" -void gv11b_detect_ecc_enabled_units(struct gk20a *g); int gv11b_init_gpu_characteristics(struct gk20a *g); #endif /* GV11B_H */ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 325285a6..00367e5b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -790,6 +790,9 @@ static const struct gpu_ops gv11b_ops = { }, .fuse = { .check_priv_security = gp10b_fuse_check_priv_security, + .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, + .is_opt_feature_override_disable = + gp10b_fuse_is_opt_feature_override_disable, }, .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 421f3692..090ac7b4 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -56,6 +56,7 @@ #include "gp10b/regops_gp10b.h" #include "gp10b/therm_gp10b.h" #include "gp10b/priv_ring_gp10b.h" +#include "gp10b/fuse_gp10b.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" @@ -559,6 +560,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { }, .fuse = { .check_priv_security = vgpu_gp10b_fuse_check_priv_security, + .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, + .is_opt_feature_override_disable = + gp10b_fuse_is_opt_feature_override_disable, }, .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, .get_litter_value = gp10b_get_litter_value, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 38f9a184..386389b7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -64,6 +64,7 @@ #include #include #include +#include #include #include @@ -628,6 +629,11 @@ static const struct gpu_ops vgpu_gv11b_ops = { .set_ppriv_timeout_settings = gk20a_priv_set_timeout_settings, }, + .fuse = { + .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, + .is_opt_feature_override_disable = + gp10b_fuse_is_opt_feature_override_disable, + }, .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; 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