From d77785800b2ae4c27354500305303c395a18acf4 Mon Sep 17 00:00:00 2001 From: Sai Nikhil Date: Thu, 30 Aug 2018 13:35:00 +0530 Subject: gpu: nvgpu: volt: fix MISRA Rule 10.4 Violations MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Ic9a911beb6d161df950ca85eb4813547603a8743 Signed-off-by: Sai Nikhil Reviewed-on: https://git-master.nvidia.com/r/1809751 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/ctrl/ctrlboardobj.h | 18 +-- drivers/gpu/nvgpu/ctrl/ctrlvolt.h | 60 +++++----- drivers/gpu/nvgpu/include/nvgpu/bios.h | 194 ++++++++++++++++----------------- drivers/gpu/nvgpu/volt/volt_dev.c | 8 +- drivers/gpu/nvgpu/volt/volt_dev.h | 4 +- drivers/gpu/nvgpu/volt/volt_pmu.c | 2 +- drivers/gpu/nvgpu/volt/volt_policy.c | 4 +- drivers/gpu/nvgpu/volt/volt_rail.c | 10 +- drivers/gpu/nvgpu/volt/volt_rail.h | 4 +- 9 files changed, 152 insertions(+), 152 deletions(-) diff --git a/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h b/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h index 9e4402a5..8f57e880 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h @@ -27,20 +27,20 @@ struct ctrl_boardobj { u8 type; }; -#define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00 -#define CTRL_BOARDOBJGRP_TYPE_E32 0x01 -#define CTRL_BOARDOBJGRP_TYPE_E255 0x02 +#define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00U +#define CTRL_BOARDOBJGRP_TYPE_E32 0x01U +#define CTRL_BOARDOBJGRP_TYPE_E255 0x02U -#define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS 32 +#define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS 32U -#define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255 +#define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255U #define CTRL_BOARDOBJ_MAX_BOARD_OBJECTS \ CTRL_BOARDOBJGRP_E32_MAX_OBJECTS -#define CTRL_BOARDOBJ_IDX_INVALID 255 +#define CTRL_BOARDOBJ_IDX_INVALID 255U -#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32 +#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32U #define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit) \ ((_bit) / CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) @@ -49,10 +49,10 @@ struct ctrl_boardobj { ((_bit) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) #define CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) \ - (CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1) + 1) + (CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1U) + 1U) -#define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1 +#define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1U #define CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits) \ (CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - \ CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE) diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h index ea06dbc4..84994eb6 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h @@ -30,25 +30,25 @@ #include "ctrlperf.h" #include "ctrlboardobj.h" -#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04 -#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8) -#define CTRL_VOLT_DOMAIN_INVALID 0x00 -#define CTRL_VOLT_DOMAIN_LOGIC 0x01 -#define CLK_PROG_VFE_ENTRY_LOGIC 0x00 -#define CLK_PROG_VFE_ENTRY_SRAM 0x01 +#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U +#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8U) +#define CTRL_VOLT_DOMAIN_INVALID 0x00U +#define CTRL_VOLT_DOMAIN_LOGIC 0x01U +#define CLK_PROG_VFE_ENTRY_LOGIC 0x00U +#define CLK_PROG_VFE_ENTRY_SRAM 0x01U /* * Macros for Voltage Domain HAL. */ -#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00 -#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01 +#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U +#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01U /* * Macros for Voltage Domains. */ -#define CTRL_VOLT_DOMAIN_INVALID 0x00 -#define CTRL_VOLT_DOMAIN_LOGIC 0x01 -#define CTRL_VOLT_DOMAIN_SRAM 0x02 +#define CTRL_VOLT_DOMAIN_INVALID 0x00U +#define CTRL_VOLT_DOMAIN_LOGIC 0x01U +#define CTRL_VOLT_DOMAIN_SRAM 0x02U /*! * Special value corresponding to an invalid Voltage Rail Index. @@ -79,43 +79,43 @@ enum nv_pmu_pmgr_pwm_source { /*! * Macros for Voltage Device Types. */ -#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00 -#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03 +#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00U +#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03U /* * Macros for Volt Device Operation types. */ -#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00 -#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01 -#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02 -#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03 -#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04 +#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00U +#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01U +#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02U +#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03U +#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04U /*! * Macros for Voltage Domains. */ -#define CTRL_VOLT_DOMAIN_INVALID 0x00 -#define CTRL_VOLT_DOMAIN_LOGIC 0x01 -#define CTRL_VOLT_DOMAIN_SRAM 0x02 +#define CTRL_VOLT_DOMAIN_INVALID 0x00U +#define CTRL_VOLT_DOMAIN_LOGIC 0x01U +#define CTRL_VOLT_DOMAIN_SRAM 0x02U /*! * Macros for Volt Policy types. * * Virtual VOLT_POLICY types are indexed starting from 0xFF. */ -#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00 -#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01 -#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02 -#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03 -#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04 -#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFE -#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFF +#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00U +#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01U +#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02U +#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03U +#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U +#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFEU +#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFFU /*! * Macros for Volt Policy Client types. */ -#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00 -#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01 +#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00U +#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01U struct ctrl_volt_volt_rail_list_item { u8 rail_idx; diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 5965d177..7d729b6e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h @@ -80,8 +80,8 @@ struct fll_descriptor_header { u8 size; } __packed; -#define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4 -#define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6 +#define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4U +#define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6U struct fll_descriptor_header_10 { u8 version; @@ -91,7 +91,7 @@ struct fll_descriptor_header_10 { u16 max_min_freq_mhz; } __packed; -#define FLL_DESCRIPTOR_ENTRY_10_SIZE 15 +#define FLL_DESCRIPTOR_ENTRY_10_SIZE 15U struct fll_descriptor_entry_10 { u8 fll_device_type; @@ -161,7 +161,7 @@ struct vin_descriptor_entry_10 { #define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80 #define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7 -#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07 +#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07U struct vbios_clocks_table_1x_header { u8 version; u8 header_size; @@ -171,7 +171,7 @@ struct vbios_clocks_table_1x_header { u16 cntr_sampling_periodms; } __packed; -#define VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09 0x09 +#define VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09 0x09U struct vbios_clocks_table_35_header { u8 version; u8 header_size; @@ -182,7 +182,7 @@ struct vbios_clocks_table_35_header { u16 reference_window; } __packed; -#define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09 +#define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09U struct vbios_clocks_table_1x_entry { u8 flags0; u16 param0; @@ -190,7 +190,7 @@ struct vbios_clocks_table_1x_entry { u16 param2; } __packed; -#define VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11 0x0B +#define VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11 0x0BU struct vbios_clocks_table_35_entry { u8 flags0; u16 param0; @@ -243,7 +243,7 @@ struct vbios_clocks_table_35_entry { #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_MASK 0xFF00 #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_SHIFT 0x08 -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08 +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08U struct vbios_clock_programming_table_1x_header { u8 version; u8 header_size; @@ -255,8 +255,8 @@ struct vbios_clock_programming_table_1x_header { u8 vf_entry_count; } __packed; -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05 -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0D +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05U +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0DU struct vbios_clock_programming_table_1x_entry { u8 flags0; u16 freq_max_mhz; @@ -289,7 +289,7 @@ struct vbios_clock_programming_table_1x_entry { #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFF #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0 -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03 +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03U struct vbios_clock_programming_table_1x_slave_entry { u8 clk_dom_idx; u16 param0; @@ -301,7 +301,7 @@ struct vbios_clock_programming_table_1x_slave_entry { #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK 0x3FFF #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT 0 -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02 +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02U struct vbios_clock_programming_table_1x_vf_entry { u8 vfe_idx; u8 param0; @@ -320,8 +320,8 @@ struct vbios_vfe_3x_header_struct { u8 polling_periodms; } __packed; -#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11 -#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19 +#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11U +#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19U struct vbios_vfe_3x_var_entry_struct { u8 type; u32 out_range_min; @@ -332,13 +332,13 @@ struct vbios_vfe_3x_var_entry_struct { u32 param3; } __packed; -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00U +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01U +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02U +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03U +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04U +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05U +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06U #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 @@ -387,8 +387,8 @@ struct vbios_vfe_3x_var_entry_struct { #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 -#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17 -#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18 +#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17U +#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18U struct vbios_vfe_3x_equ_entry_struct { u8 type; @@ -403,14 +403,14 @@ struct vbios_vfe_3x_equ_entry_struct { } __packed; -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00 -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01 -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02 -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03 -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04 -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00U +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01U +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02U +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03U +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04U +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05U -#define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFF +#define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFFU #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 @@ -452,35 +452,35 @@ struct vbios_vfe_3x_equ_entry_struct { #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 -#define NV_VFIELD_DESC_SIZE_BYTE 0x00000000 -#define NV_VFIELD_DESC_SIZE_WORD 0x00000001 -#define NV_VFIELD_DESC_SIZE_DWORD 0x00000002 -#define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18) >> 3) +#define NV_VFIELD_DESC_SIZE_BYTE 0x00000000U +#define NV_VFIELD_DESC_SIZE_WORD 0x00000001U +#define NV_VFIELD_DESC_SIZE_DWORD 0x00000002U +#define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18U) >> 3U) -#define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000 -#define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001 -#define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002 +#define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000U +#define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001U +#define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002U #define NV_VFIELD_DESC_CODE_INVALID NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID #define NV_VFIELD_DESC_CODE_REG NV_PMU_BIOS_VFIELD_DESC_CODE_REG #define NV_VFIELD_DESC_CODE_INDEX_REG NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG -#define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0) >> 5) +#define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0U) >> 5U) -#define VFIELD_ID_STRAP_IDDQ 0x09 -#define VFIELD_ID_STRAP_IDDQ_1 0x0B +#define VFIELD_ID_STRAP_IDDQ 0x09U +#define VFIELD_ID_STRAP_IDDQ_1 0x0BU -#define VFIELD_REG_HEADER_SIZE 3 +#define VFIELD_REG_HEADER_SIZE 3U struct vfield_reg_header { u8 version; u8 entry_size; u8 count; } __packed; -#define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10 +#define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10U -#define VFIELD_REG_ENTRY_SIZE 13 +#define VFIELD_REG_ENTRY_SIZE 13U struct vfield_reg_entry { u8 strap_reg_desc; u32 reg; @@ -488,7 +488,7 @@ struct vfield_reg_entry { u32 index; } __packed; -#define VFIELD_HEADER_SIZE 3 +#define VFIELD_HEADER_SIZE 3U struct vfield_header { u8 version; @@ -496,24 +496,24 @@ struct vfield_header { u8 count; } __packed; -#define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10 +#define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10U -#define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1F) -#define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0) >> 5) -#define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00) >> 10) +#define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1FU) +#define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0U) >> 5U) +#define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00U) >> 10U) -#define VFIELD_ENTRY_SIZE 3 +#define VFIELD_ENTRY_SIZE 3U struct vfield_entry { u8 strap_id; u16 strap_desc; } __packed; -#define PERF_CLK_DOMAINS_IDX_MAX (32) +#define PERF_CLK_DOMAINS_IDX_MAX (32U) #define PERF_CLK_DOMAINS_IDX_INVALID PERF_CLK_DOMAINS_IDX_MAX -#define VBIOS_PSTATE_TABLE_VERSION_5X 0x50 -#define VBIOS_PSTATE_HEADER_5X_SIZE_10 (10) +#define VBIOS_PSTATE_TABLE_VERSION_5X 0x50U +#define VBIOS_PSTATE_HEADER_5X_SIZE_10 (10U) struct vbios_pstate_header_5x { u8 version; @@ -528,10 +528,10 @@ struct vbios_pstate_header_5x { u8 cpi_features; } __packed; -#define VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6 6 +#define VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6 6U -#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2 0x2 -#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3 0x3 +#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2 0x2U +#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3 0x3U struct vbios_pstate_entry_clock_5x { u16 param0; @@ -554,13 +554,13 @@ struct vbios_pstate_entry_5x { #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT 14 #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK 0x0FFFC000 -#define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFF +#define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFFU -#define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION 0x11 +#define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION 0x11U -#define VBIOS_MEMORY_CLOCK_HEADER_11_0_SIZE 16 -#define VBIOS_MEMORY_CLOCK_HEADER_11_1_SIZE 21 -#define VBIOS_MEMORY_CLOCK_HEADER_11_2_SIZE 26 +#define VBIOS_MEMORY_CLOCK_HEADER_11_0_SIZE 16U +#define VBIOS_MEMORY_CLOCK_HEADER_11_1_SIZE 21U +#define VBIOS_MEMORY_CLOCK_HEADER_11_2_SIZE 26U struct vbios_memory_clock_header_1x { u8 version; @@ -580,7 +580,7 @@ struct vbios_memory_clock_header_1x { u8 cmd_script_list_count; } __packed; -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_2_SIZE 20 +#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_2_SIZE 20U struct vbios_memory_clock_base_entry_11 { u16 minimum; @@ -604,8 +604,8 @@ struct vbios_memory_clock_base_entry_11 { ((u8)0x3) #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 -#define VBIOS_POWER_SENSORS_VERSION_2X 0x20 -#define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008 +#define VBIOS_POWER_SENSORS_VERSION_2X 0x20U +#define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008U struct pwr_sensors_2x_header { u8 version; @@ -615,7 +615,7 @@ struct pwr_sensors_2x_header { u32 ba_script_pointer; } __packed; -#define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015 +#define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015U struct pwr_sensors_2x_entry { u8 flags0; @@ -628,7 +628,7 @@ struct pwr_sensors_2x_entry { #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001U #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFF #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0 @@ -653,8 +653,8 @@ struct pwr_sensors_2x_entry { #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000 #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16 -#define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20 -#define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006 +#define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20U +#define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006U struct pwr_topology_2x_header { u8 version; @@ -665,7 +665,7 @@ struct pwr_topology_2x_header { u8 num_rel_entries; } __packed; -#define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016 +#define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016U struct pwr_topology_2x_entry { u8 flags0; @@ -679,15 +679,15 @@ struct pwr_topology_2x_entry { #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR 0x00000001 +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR U8(0x00000001) #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFF #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0 #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00 #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8 -#define VBIOS_POWER_POLICY_VERSION_3X 0x30 -#define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025 +#define VBIOS_POWER_POLICY_VERSION_3X 0x30U +#define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025U struct pwr_policy_3x_header_struct { u8 version; @@ -714,7 +714,7 @@ struct pwr_policy_3x_header_struct { u8 num_table_viol_entries; } __packed; -#define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002E +#define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002EU struct pwr_policy_3x_entry_struct { u8 flags0; @@ -738,7 +738,7 @@ struct pwr_policy_3x_entry_struct { #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005U #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10 #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4 @@ -768,12 +768,12 @@ struct vbios_voltage_rail_table_1x_header { u8 volt_domain_hal; } __packed; -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007 -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008 -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009 -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C 0X0000000C +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007U +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008U +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009U +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000AU +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000BU +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C 0X0000000CU struct vbios_voltage_rail_table_1x_entry { u32 boot_voltage_uv; @@ -806,8 +806,8 @@ struct vbios_voltage_device_table_1x_entry { u32 param4; } __packed; -#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00 -#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02 +#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00U +#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02U #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \ GENMASK(23, 0) @@ -865,11 +865,11 @@ struct vbios_voltage_policy_table_1x_entry { u32 param3; } __packed; -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04 +#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00U +#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01U +#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02U +#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03U +#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ GENMASK(7, 0) @@ -906,9 +906,9 @@ struct vbios_voltage_policy_table_1x_entry { #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \ 0 -#define VBIOS_THERM_DEVICE_VERSION_1X 0x10 +#define VBIOS_THERM_DEVICE_VERSION_1X 0x10U -#define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04 0x00000004 +#define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04 0x00000004U struct therm_device_1x_header { u8 version; @@ -923,19 +923,19 @@ struct therm_device_1x_entry { u8 flags; } ; -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_INVALID 0x00 -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01 -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC 0x02 -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI 0x03 -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE 0x70 -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED 0x71 +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_INVALID 0x00U +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01U +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC 0x02U +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI 0x03U +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE 0x70U +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED 0x71U #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFF #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0 -#define VBIOS_THERM_CHANNEL_VERSION_1X 0x10 +#define VBIOS_THERM_CHANNEL_VERSION_1X 0x10U -#define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09 0x00000009 +#define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09 0x00000009U struct therm_channel_1x_header { u8 version; @@ -957,7 +957,7 @@ struct therm_channel_1x_entry { u8 flags; } __packed; -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01 +#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01U #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFF #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0 diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c index fccd3b03..bb5d1821 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/volt/volt_dev.c @@ -35,8 +35,8 @@ #include "volt.h" -#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0 -#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1 +#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0U +#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1U static int volt_device_pmu_data_init_super(struct gk20a *g, struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) @@ -425,7 +425,7 @@ static int _volt_device_devgrp_pmudata_instget(struct gk20a *g, /*check whether pmuboardobjgrp has a valid boardobj in index*/ if (((u32)BIT(idx) & - pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { + pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { return -EINVAL; } @@ -445,7 +445,7 @@ static int _volt_device_devgrp_pmustatus_instget(struct gk20a *g, /*check whether pmuboardobjgrp has a valid boardobj in index*/ if (((u32)BIT(idx) & - pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { + pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) { return -EINVAL; } diff --git a/drivers/gpu/nvgpu/volt/volt_dev.h b/drivers/gpu/nvgpu/volt/volt_dev.h index eb1868cb..48d93aea 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.h +++ b/drivers/gpu/nvgpu/volt/volt_dev.h @@ -27,8 +27,8 @@ #include "boardobj/boardobjgrp.h" #include "ctrl/ctrlvolt.h" -#define VOLTAGE_TABLE_MAX_ENTRIES_ONE 1 -#define VOLTAGE_TABLE_MAX_ENTRIES 256 +#define VOLTAGE_TABLE_MAX_ENTRIES_ONE 1U +#define VOLTAGE_TABLE_MAX_ENTRIES 256U struct voltage_device { struct boardobj super; diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c index 184aa5d0..2249ae24 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.c +++ b/drivers/gpu/nvgpu/volt/volt_pmu.c @@ -108,7 +108,7 @@ static u32 volt_pmu_rpc_execute(struct gk20a *g, gk20a_get_gr_idle_timeout(g), &handler.success, 1); - if (handler.success == 0) { + if (handler.success == 0U) { status = -EINVAL; nvgpu_err(g, "rpc call to volt failed"); } diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c index 4f9d7ad8..cc60730d 100644 --- a/drivers/gpu/nvgpu/volt/volt_policy.c +++ b/drivers/gpu/nvgpu/volt/volt_policy.c @@ -382,7 +382,7 @@ static int _volt_policy_devgrp_pmudata_instget(struct gk20a *g, /*check whether pmuboardobjgrp has a valid boardobj in index*/ if (((u32)BIT(idx) & - pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { + pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { return -EINVAL; } @@ -402,7 +402,7 @@ static int _volt_policy_devgrp_pmustatus_instget(struct gk20a *g, /*check whether pmuboardobjgrp has a valid boardobj in index*/ if (((u32)BIT(idx) & - p_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { + p_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) { return -EINVAL; } diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c index 37e85761..caf297f0 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/volt/volt_rail.c @@ -105,7 +105,7 @@ static u32 volt_rail_state_init(struct gk20a *g, pvolt_rail->volt_dev_idx_default = CTRL_BOARDOBJ_IDX_INVALID; for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { - pvolt_rail->volt_delta_uv[i] = NV_PMU_VOLT_VALUE_0V_IN_UV; + pvolt_rail->volt_delta_uv[i] = (int)NV_PMU_VOLT_VALUE_0V_IN_UV; g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i] = NV_PMU_VOLT_VALUE_0V_IN_UV; } @@ -162,7 +162,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g, for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + - g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i]; + (int)g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i]; } status = boardobjgrpmask_export(&prail->volt_dev_mask.super, @@ -225,7 +225,7 @@ u8 volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g, { switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: - if (vbios_volt_domain == 0) { + if (vbios_volt_domain == 0U) { return CTRL_VOLT_DOMAIN_LOGIC; } break; @@ -382,7 +382,7 @@ static int _volt_rail_devgrp_pmudata_instget(struct gk20a *g, /*check whether pmuboardobjgrp has a valid boardobj in index*/ if (((u32)BIT(idx) & - pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { + pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { return -EINVAL; } @@ -402,7 +402,7 @@ static int _volt_rail_devgrp_pmustatus_instget(struct gk20a *g, /*check whether pmuboardobjgrp has a valid boardobj in index*/ if (((u32)BIT(idx) & - pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { + pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) { return -EINVAL; } diff --git a/drivers/gpu/nvgpu/volt/volt_rail.h b/drivers/gpu/nvgpu/volt/volt_rail.h index 522d635a..72bb2546 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.h +++ b/drivers/gpu/nvgpu/volt/volt_rail.h @@ -27,8 +27,8 @@ #include "boardobj/boardobj.h" #include "boardobj/boardobjgrp.h" -#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04 -#define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFF +#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U +#define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFFU #define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \ ((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \ -- cgit v1.2.2