From d65f23cb9ad9d270560ec00c775e60ab559e8e93 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 19 Sep 2014 09:34:01 +0300 Subject: gpu: nvgpu: Support 512 channels in gm20b Retrieve channel count from gm20b specific header instead of the gk20a header. This increases channel count from 128 to 512. Change-Id: I96d4887432852795f7f526e33f0d3d2458f3af0e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/500623 --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 8 +++++++- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 6 ++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 3224e29c..0c8bc6f4 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -513,7 +513,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g) mutex_init(&f->intr.isr.mutex); gk20a_init_fifo_pbdma_intr_descs(f); /* just filling in data/tables */ - f->num_channels = ccsr_channel__size_1_v(); + f->num_channels = g->ops.fifo.get_num_fifos(g); f->num_pbdma = proj_host_num_pbdma_v(); f->max_engines = ENGINE_INVAL_GK20A; @@ -2132,6 +2132,11 @@ static void gk20a_fifo_apply_pb_timeout(struct gk20a *g) } } +static u32 gk20a_fifo_get_num_fifos(struct gk20a *g) +{ + return ccsr_channel__size_1_v(); +} + void gk20a_init_fifo(struct gpu_ops *gops) { gk20a_init_channel(gops); @@ -2140,4 +2145,5 @@ void gk20a_init_fifo(struct gpu_ops *gops) gops->fifo.trigger_mmu_fault = gk20a_fifo_trigger_mmu_fault; gops->fifo.apply_pb_timeout = gk20a_fifo_apply_pb_timeout; gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; + gops->fifo.get_num_fifos = gk20a_fifo_get_num_fifos; } diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 83c4e147..ae640277 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -189,6 +189,7 @@ struct gpu_ops { unsigned long engine_ids); void (*apply_pb_timeout)(struct gk20a *g); int (*wait_engine_idle)(struct gk20a *g); + u32 (*get_num_fifos)(struct gk20a *g); } fifo; struct pmu_v { /*used for change of enum zbc update cmd id from ver 0 to ver1*/ diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 86d049cf..cdc8c810 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -99,6 +99,11 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0); } +static u32 gm20b_fifo_get_num_fifos(struct gk20a *g) +{ + return ccsr_channel__size_1_v(); +} + void gm20b_init_fifo(struct gpu_ops *gops) { gops->fifo.bind_channel = channel_gm20b_bind; @@ -112,4 +117,5 @@ void gm20b_init_fifo(struct gpu_ops *gops) gops->fifo.update_runlist = gk20a_fifo_update_runlist; gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault; gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; + gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos; } -- cgit v1.2.2