From be7ee41989008b76ba118f6f520ba9b1b1efd44c Mon Sep 17 00:00:00 2001
From: Terje Bergstrom <tbergstrom@nvidia.com>
Date: Tue, 5 Apr 2016 19:41:01 -0700
Subject: gpu: nvgpu: gp10b: Sync with register generator

Use re-generated register definitions. This synchronizes
kernel with the register generator.

Change-Id: I5ad34ad0b92327091758a2d10581a1b4170fa919
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120811
---
 drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h |  6 +++-
 drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h |  2 +-
 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h   | 64 +++++++++++++++++++++------------
 3 files changed, 48 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h
index 6f7e09ff..34977523 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -110,6 +110,10 @@ static inline u32 fifo_eng_runlist_length_f(u32 v)
 {
 	return (v & 0xffff) << 0;
 }
+static inline u32 fifo_eng_runlist_length_max_v(void)
+{
+	return 0x0000ffff;
+}
 static inline u32 fifo_eng_runlist_pending_true_f(void)
 {
 	return 0x100000;
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
index 9ce9448e..30e4307d 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index b3fd704b..78792f50 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -1114,6 +1114,10 @@ static inline u32 gr_fecs_host_int_status_r(void)
 {
 	return 0x00409c18;
 }
+static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
+{
+	return (v & 0x1) << 16;
+}
 static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
 {
 	return (v & 0x1) << 17;
@@ -3462,6 +3466,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
 {
 	return 0x00504610;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
+{
+	return 0x1 << 0;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
 {
 	return (r >> 0) & 0x1;
@@ -3494,6 +3502,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
 {
 	return 0x40000000;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
+{
+	return 0x1 << 1;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
 {
 	return (r >> 1) & 0x1;
@@ -3502,6 +3514,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
+{
+	return 0x1 << 2;
+}
 static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
 {
 	return (r >> 2) & 0x1;
@@ -3510,6 +3526,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
 {
 	return 0x0;
 }
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
+{
+	return 0x00000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
 {
 	return 0x00504614;
@@ -3522,13 +3546,9 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
 {
 	return 0x00504634;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void)
+static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
 {
-	return 0x00000000;
-}
-static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void)
-{
-	return 0x00000000;
+	return 0x00419e24;
 }
 static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
 {
@@ -3606,22 +3626,6 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(
 {
 	return 0x40;
 }
-static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
-{
-	return 0x00504224;
-}
-static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
-{
-	return 0x1;
-}
-static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void)
-{
-	return 0x80;
-}
-static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
-{
-	return 0x100;
-}
 static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
 {
 	return 0x1;
@@ -3642,6 +3646,22 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
 {
 	return 0x80000000;
 }
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
+{
+	return 0x00504224;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void)
+{
+	return 0x80;
+}
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
+{
+	return 0x100;
+}
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
 {
 	return 0x00504648;
-- 
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