From be3750bc9eb60f8696c20b7298cc282eea17ac1b Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 27 Sep 2017 13:21:44 -0700 Subject: gpu: nvgpu: Abstract IO aperture accessors Add abstraction of IO aperture accessors. Add new functions gk20a_io_exists() and gk20a_io_valid_reg() to remove dependencies to aperture fields from common code. Implement Linux version of the abstraction by moving gk20a_readl() and gk20a_writel() to new Linux specific io.c. Move the fields defining IO aperture to nvgpu_os_linux. Add t19x specific IO aperture initialization functions and add t19x specific section to nvgpu_os_linux. JIRA NVGPU-259 Change-Id: I09e79cda60d11a20d1099a9aaa6d2375236e94ce Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1569698 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile.nvgpu | 1 + drivers/gpu/nvgpu/common/linux/driver_common.c | 4 +- drivers/gpu/nvgpu/common/linux/io.c | 110 +++++++++++++++++++++++++ drivers/gpu/nvgpu/common/linux/module.c | 77 +++++++++++++---- drivers/gpu/nvgpu/common/linux/module.h | 4 + drivers/gpu/nvgpu/common/linux/nvgpu_mem.c | 13 +-- drivers/gpu/nvgpu/common/linux/os_linux.h | 14 ++++ drivers/gpu/nvgpu/common/linux/pci.c | 13 +-- drivers/gpu/nvgpu/common/pramin.c | 2 +- drivers/gpu/nvgpu/gk20a/gk20a.c | 26 ------ drivers/gpu/nvgpu/gk20a/gk20a.h | 81 +----------------- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 3 +- drivers/gpu/nvgpu/include/nvgpu/io.h | 49 +++++++++++ drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 3 +- drivers/gpu/nvgpu/vgpu/vgpu.c | 18 ++-- 15 files changed, 274 insertions(+), 144 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/linux/io.c create mode 100644 drivers/gpu/nvgpu/include/nvgpu/io.h diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index a792ab33..fa774566 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu @@ -46,6 +46,7 @@ nvgpu-y := \ common/linux/intr.o \ common/linux/sysfs.o \ common/linux/cde.o \ + common/linux/io.o \ common/mm/nvgpu_allocator.o \ common/mm/bitmap_allocator.o \ common/mm/buddy_allocator.o \ diff --git a/drivers/gpu/nvgpu/common/linux/driver_common.c b/drivers/gpu/nvgpu/common/linux/driver_common.c index 7c4645a8..734bc1d2 100644 --- a/drivers/gpu/nvgpu/common/linux/driver_common.c +++ b/drivers/gpu/nvgpu/common/linux/driver_common.c @@ -54,8 +54,8 @@ static void nvgpu_init_vars(struct gk20a *g) nvgpu_mutex_init(&g->poweron_lock); nvgpu_mutex_init(&g->poweroff_lock); - g->regs_saved = g->regs; - g->bar1_saved = g->bar1; + l->regs_saved = l->regs; + l->bar1_saved = l->bar1; g->emc3d_ratio = EMC3D_DEFAULT_RATIO; diff --git a/drivers/gpu/nvgpu/common/linux/io.c b/drivers/gpu/nvgpu/common/linux/io.c new file mode 100644 index 00000000..04a9fbe8 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/io.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include "os_linux.h" +#include "gk20a/gk20a.h" + +void nvgpu_writel(struct gk20a *g, u32 r, u32 v) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + if (unlikely(!l->regs)) { + __gk20a_warn_on_no_regs(); + gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); + } else { + writel_relaxed(v, l->regs + r); + nvgpu_smp_wmb(); + gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); + } +} + +u32 nvgpu_readl(struct gk20a *g, u32 r) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + u32 v = 0xffffffff; + + if (unlikely(!l->regs)) { + __gk20a_warn_on_no_regs(); + gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); + } else { + v = readl(l->regs + r); + if (v == 0xffffffff) + __nvgpu_check_gpu_state(g); + gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); + } + + return v; +} + +void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + if (unlikely(!l->regs)) { + __gk20a_warn_on_no_regs(); + gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); + } else { + nvgpu_smp_wmb(); + do { + writel_relaxed(v, l->regs + r); + } while (readl(l->regs + r) != v); + gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); + } +} + +void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + if (unlikely(!l->bar1)) { + __gk20a_warn_on_no_regs(); + gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v); + } else { + nvgpu_smp_wmb(); + writel_relaxed(v, l->bar1 + b); + gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x", b, v); + } +} + +u32 nvgpu_bar1_readl(struct gk20a *g, u32 b) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + u32 v = 0xffffffff; + + if (unlikely(!l->bar1)) { + __gk20a_warn_on_no_regs(); + gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v); + } else { + v = readl(l->bar1 + b); + gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x", b, v); + } + + return v; +} + +bool nvgpu_io_exists(struct gk20a *g) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + return l->regs != NULL; +} + +bool nvgpu_io_valid_reg(struct gk20a *g, u32 r) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + return r < resource_size(l->regs); +} diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c index 52f987b2..fe3e4e6f 100644 --- a/drivers/gpu/nvgpu/common/linux/module.c +++ b/drivers/gpu/nvgpu/common/linux/module.c @@ -137,6 +137,23 @@ void gk20a_idle(struct gk20a *g) } } +/* + * Undoes gk20a_lockout_registers(). + */ +static int gk20a_restore_registers(struct gk20a *g) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + l->regs = l->regs_saved; + l->bar1 = l->bar1_saved; + +#ifdef CONFIG_TEGRA_19x_GPU + t19x_restore_registers(g); +#endif + + return 0; +} + int gk20a_pm_finalize_poweron(struct device *dev) { struct gk20a *g = get_gk20a(dev); @@ -198,6 +215,27 @@ done: return err; } +/* + * Locks out the driver from accessing GPU registers. This prevents access to + * thse registers after the GPU has been clock or power gated. This should help + * find annoying bugs where register reads and writes are silently dropped + * after the GPU has been turned off. On older chips these reads and writes can + * also lock the entire CPU up. + */ +static int gk20a_lockout_registers(struct gk20a *g) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + l->regs = NULL; + l->bar1 = NULL; + +#ifdef CONFIG_TEGRA_19x_GPU + t19x_lockout_registers(g); +#endif + + return 0; +} + static int gk20a_pm_prepare_poweroff(struct device *dev) { struct gk20a *g = get_gk20a(dev); @@ -511,6 +549,8 @@ static irqreturn_t gk20a_intr_thread_stall(int irq, void *dev_id) void gk20a_remove_support(struct gk20a *g) { + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + tegra_unregister_idle_unidle(gk20a_do_idle); nvgpu_kfree(g, g->dbg_regops_tmp_buf); @@ -535,36 +575,41 @@ void gk20a_remove_support(struct gk20a *g) /* free mappings to registers, etc */ - if (g->regs) { - iounmap(g->regs); - g->regs = NULL; + if (l->regs) { + iounmap(l->regs); + l->regs = NULL; } - if (g->bar1) { - iounmap(g->bar1); - g->bar1 = NULL; + if (l->bar1) { + iounmap(l->bar1); + l->bar1 = NULL; } + +#ifdef CONFIG_TEGRA_19x_GPU + t19x_remove_support(g); +#endif } static int gk20a_init_support(struct platform_device *dev) { int err = 0; struct gk20a *g = get_gk20a(&dev->dev); + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); tegra_register_idle_unidle(gk20a_do_idle, gk20a_do_unidle, g); - g->regs = gk20a_ioremap_resource(dev, GK20A_BAR0_IORESOURCE_MEM, - &g->reg_mem); - if (IS_ERR(g->regs)) { + l->regs = gk20a_ioremap_resource(dev, GK20A_BAR0_IORESOURCE_MEM, + &l->reg_mem); + if (IS_ERR(l->regs)) { nvgpu_err(g, "failed to remap gk20a registers"); - err = PTR_ERR(g->regs); + err = PTR_ERR(l->regs); goto fail; } - g->bar1 = gk20a_ioremap_resource(dev, GK20A_BAR1_IORESOURCE_MEM, - &g->bar1_mem); - if (IS_ERR(g->bar1)) { + l->bar1 = gk20a_ioremap_resource(dev, GK20A_BAR1_IORESOURCE_MEM, + &l->bar1_mem); + if (IS_ERR(l->bar1)) { nvgpu_err(g, "failed to remap gk20a bar1"); - err = PTR_ERR(g->bar1); + err = PTR_ERR(l->bar1); goto fail; } @@ -584,6 +629,10 @@ static int gk20a_init_support(struct platform_device *dev) goto fail; } +#ifdef CONFIG_TEGRA_19x_GPU + t19x_init_support(g); +#endif + return 0; fail: diff --git a/drivers/gpu/nvgpu/common/linux/module.h b/drivers/gpu/nvgpu/common/linux/module.h index 55a3b692..5814d63a 100644 --- a/drivers/gpu/nvgpu/common/linux/module.h +++ b/drivers/gpu/nvgpu/common/linux/module.h @@ -13,6 +13,10 @@ #ifndef __NVGPU_COMMON_LINUX_MODULE_H__ #define __NVGPU_COMMON_LINUX_MODULE_H__ +#ifdef CONFIG_TEGRA_19x_GPU +#include +#endif + struct gk20a; struct device; diff --git a/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c b/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c index 8740ac3d..1dbbd1a0 100644 --- a/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c +++ b/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c @@ -105,9 +105,10 @@ void nvgpu_mem_end(struct gk20a *g, struct nvgpu_mem *mem) static void pramin_access_batch_rd_n(struct gk20a *g, u32 start, u32 words, u32 **arg) { + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); u32 r = start, *dest_u32 = *arg; - if (!g->regs) { + if (!l->regs) { __gk20a_warn_on_no_regs(); return; } @@ -182,15 +183,16 @@ void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, static void pramin_access_batch_wr_n(struct gk20a *g, u32 start, u32 words, u32 **arg) { + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); u32 r = start, *src_u32 = *arg; - if (!g->regs) { + if (!l->regs) { __gk20a_warn_on_no_regs(); return; } while (words--) { - writel_relaxed(*src_u32++, g->regs + r); + writel_relaxed(*src_u32++, l->regs + r); r += sizeof(u32); } @@ -256,15 +258,16 @@ void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, static void pramin_access_batch_set(struct gk20a *g, u32 start, u32 words, u32 **arg) { + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); u32 r = start, repeat = **arg; - if (!g->regs) { + if (!l->regs) { __gk20a_warn_on_no_regs(); return; } while (words--) { - writel_relaxed(repeat, g->regs + r); + writel_relaxed(repeat, l->regs + r); r += sizeof(u32); } } diff --git a/drivers/gpu/nvgpu/common/linux/os_linux.h b/drivers/gpu/nvgpu/common/linux/os_linux.h index 48479843..4a3128c3 100644 --- a/drivers/gpu/nvgpu/common/linux/os_linux.h +++ b/drivers/gpu/nvgpu/common/linux/os_linux.h @@ -18,6 +18,9 @@ #include +#ifdef CONFIG_TEGRA_19x_GPU +#include +#endif #include "gk20a/gk20a.h" #include "cde.h" @@ -85,6 +88,17 @@ struct nvgpu_os_linux { struct work_struct nonstall_fn_work; struct workqueue_struct *nonstall_work_queue; + struct resource *reg_mem; + void __iomem *regs; + void __iomem *regs_saved; + + struct resource *bar1_mem; + void __iomem *bar1; + void __iomem *bar1_saved; + +#ifdef CONFIG_TEGRA_19x_GPU + struct nvgpu_os_linux_t19x t19x; +#endif #ifdef CONFIG_DEBUG_FS struct dentry *debugfs; struct dentry *debugfs_alias; diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c index 401080ed..50d079bb 100644 --- a/drivers/gpu/nvgpu/common/linux/pci.c +++ b/drivers/gpu/nvgpu/common/linux/pci.c @@ -348,20 +348,21 @@ static int nvgpu_pci_init_support(struct pci_dev *pdev) { int err = 0; struct gk20a *g = get_gk20a(&pdev->dev); + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); - g->regs = ioremap(pci_resource_start(pdev, 0), + l->regs = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0)); - if (IS_ERR(g->regs)) { + if (IS_ERR(l->regs)) { nvgpu_err(g, "failed to remap gk20a registers"); - err = PTR_ERR(g->regs); + err = PTR_ERR(l->regs); goto fail; } - g->bar1 = ioremap(pci_resource_start(pdev, 1), + l->bar1 = ioremap(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1)); - if (IS_ERR(g->bar1)) { + if (IS_ERR(l->bar1)) { nvgpu_err(g, "failed to remap gk20a bar1"); - err = PTR_ERR(g->bar1); + err = PTR_ERR(l->bar1); goto fail; } diff --git a/drivers/gpu/nvgpu/common/pramin.c b/drivers/gpu/nvgpu/common/pramin.c index b6166f51..9b04d5a3 100644 --- a/drivers/gpu/nvgpu/common/pramin.c +++ b/drivers/gpu/nvgpu/common/pramin.c @@ -51,7 +51,7 @@ void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem, * driver should be refactored to prevent this from happening, but for * now it is ok just to ignore the writes */ - if (!g->regs && nvgpu_is_enabled(g, NVGPU_DRIVER_IS_DYING)) + if (!gk20a_io_exists(g) && nvgpu_is_enabled(g, NVGPU_DRIVER_IS_DYING)) return; alloc = mem->vidmem_alloc; diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index cac62db7..a4becda0 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -65,32 +65,6 @@ void __nvgpu_check_gpu_state(struct gk20a *g) } } -/* - * Locks out the driver from accessing GPU registers. This prevents access to - * thse registers after the GPU has been clock or power gated. This should help - * find annoying bugs where register reads and writes are silently dropped - * after the GPU has been turned off. On older chips these reads and writes can - * also lock the entire CPU up. - */ -int gk20a_lockout_registers(struct gk20a *g) -{ - g->regs = NULL; - g->bar1 = NULL; - - return 0; -} - -/* - * Undoes gk20a_lockout_registers(). - */ -int gk20a_restore_registers(struct gk20a *g) -{ - g->regs = g->regs_saved; - g->bar1 = g->bar1_saved; - - return 0; -} - void __gk20a_warn_on_no_regs(void) { WARN_ONCE(1, "Attempted access to GPU regs after unmapping!"); diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a45a7b4e..bf10055a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -44,6 +44,7 @@ struct nvgpu_mem_sgt; #include #include +#include #ifdef CONFIG_DEBUG_FS #include #endif @@ -1067,14 +1068,6 @@ struct gk20a { struct nvgpu_ref refcount; - struct resource *reg_mem; - void __iomem *regs; - void __iomem *regs_saved; - - struct resource *bar1_mem; - void __iomem *bar1; - void __iomem *bar1_saved; - const char *name; bool gpu_reset_done; @@ -1339,81 +1332,9 @@ enum gk20a_nonstall_ops { }; /* register accessors */ -int gk20a_lockout_registers(struct gk20a *g); -int gk20a_restore_registers(struct gk20a *g); - void __nvgpu_check_gpu_state(struct gk20a *g); void __gk20a_warn_on_no_regs(void); -static inline void gk20a_writel(struct gk20a *g, u32 r, u32 v) -{ - if (unlikely(!g->regs)) { - __gk20a_warn_on_no_regs(); - gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); - } else { - writel_relaxed(v, g->regs + r); - nvgpu_smp_wmb(); - gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); - } -} -static inline u32 gk20a_readl(struct gk20a *g, u32 r) -{ - - u32 v = 0xffffffff; - - if (unlikely(!g->regs)) { - __gk20a_warn_on_no_regs(); - gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); - } else { - v = readl(g->regs + r); - if (v == 0xffffffff) - __nvgpu_check_gpu_state(g); - gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); - } - - return v; -} -static inline void gk20a_writel_check(struct gk20a *g, u32 r, u32 v) -{ - if (unlikely(!g->regs)) { - __gk20a_warn_on_no_regs(); - gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x (failed)", r, v); - } else { - nvgpu_smp_wmb(); - do { - writel_relaxed(v, g->regs + r); - } while (readl(g->regs + r) != v); - gk20a_dbg(gpu_dbg_reg, "r=0x%x v=0x%x", r, v); - } -} - -static inline void gk20a_bar1_writel(struct gk20a *g, u32 b, u32 v) -{ - if (unlikely(!g->bar1)) { - __gk20a_warn_on_no_regs(); - gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v); - } else { - nvgpu_smp_wmb(); - writel_relaxed(v, g->bar1 + b); - gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x", b, v); - } -} - -static inline u32 gk20a_bar1_readl(struct gk20a *g, u32 b) -{ - u32 v = 0xffffffff; - - if (unlikely(!g->bar1)) { - __gk20a_warn_on_no_regs(); - gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x (failed)", b, v); - } else { - v = readl(g->bar1 + b); - gk20a_dbg(gpu_dbg_reg, "b=0x%x v=0x%x", b, v); - } - - return v; -} - /* convenience */ static inline struct gk20a *gk20a_from_as(struct gk20a_as *as) { diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 707bfb87..6f829282 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -5256,8 +5256,7 @@ static inline bool is_valid_cyclestats_bar0_offset_gk20a(struct gk20a *g, is_bar0_global_offset_whitelisted_gk20a(g, offset); /* resource size check in case there was a problem * with allocating the assumed size of bar0 */ - valid = valid && - offset < resource_size(g->regs); + valid = valid && gk20a_io_valid_reg(g, offset); return valid; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/io.h b/drivers/gpu/nvgpu/include/nvgpu/io.h new file mode 100644 index 00000000..94ae8f95 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/io.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __NVGPU_IO_H__ +#define __NVGPU_IO_H__ + +#include +#ifdef CONFIG_TEGRA_19x_GPU +#include +#endif + +/* Legacy defines - should be removed once everybody uses nvgpu_* */ +#define gk20a_writel nvgpu_writel +#define gk20a_readl nvgpu_readl +#define gk20a_writel_check nvgpu_writel_check +#define gk20a_bar1_writel nvgpu_bar1_writel +#define gk20a_bar1_readl nvgpu_bar1_readl +#define gk20a_io_exists nvgpu_io_exists +#define gk20a_io_valid_reg nvgpu_io_valid_reg + +struct gk20a; + +void nvgpu_writel(struct gk20a *g, u32 r, u32 v); +u32 nvgpu_readl(struct gk20a *g, u32 r); +void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v); +void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v); +u32 nvgpu_bar1_readl(struct gk20a *g, u32 b); +bool nvgpu_io_exists(struct gk20a *g); +bool nvgpu_io_valid_reg(struct gk20a *g, u32 r); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 9010c4a3..73a67d91 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c @@ -268,6 +268,7 @@ clean_up_runlist: static int vgpu_init_fifo_setup_sw(struct gk20a *g) { + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct fifo_gk20a *f = &g->fifo; struct device *d = dev_from_gk20a(g); struct vgpu_priv_data *priv = vgpu_get_priv_data(g); @@ -305,7 +306,7 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g) /* if reduced BAR1 range is specified, use offset of 0 * (server returns offset assuming full BAR1 range) */ - if (resource_size(g->bar1_mem) == + if (resource_size(l->bar1_mem) == (resource_size_t)f->userd.size) f->userd.gpu_va = 0; } diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index c13d8ff0..b63202c1 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c @@ -216,6 +216,7 @@ static int vgpu_intr_thread(void *dev_id) static void vgpu_remove_support(struct gk20a *g) { + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct vgpu_priv_data *priv = vgpu_get_priv_data_from_dev(dev_from_gk20a(g)); struct tegra_vgpu_intr_msg msg; @@ -245,18 +246,20 @@ static void vgpu_remove_support(struct gk20a *g) /* free mappings to registers, etc*/ - if (g->bar1) { - iounmap(g->bar1); - g->bar1 = NULL; + if (l->bar1) { + iounmap(l->bar1); + l->bar1 = NULL; } } static void vgpu_init_vars(struct gk20a *g, struct gk20a_platform *platform) { + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + nvgpu_mutex_init(&g->poweron_lock); nvgpu_mutex_init(&g->poweroff_lock); - g->regs_saved = g->regs; - g->bar1_saved = g->bar1; + l->regs_saved = l->regs; + l->bar1_saved = l->bar1; nvgpu_init_list_node(&g->pending_sema_waits); nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock); @@ -276,6 +279,7 @@ static int vgpu_init_support(struct platform_device *pdev) { struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); struct gk20a *g = get_gk20a(&pdev->dev); + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); void __iomem *regs; int err = 0; @@ -292,8 +296,8 @@ static int vgpu_init_support(struct platform_device *pdev) err = PTR_ERR(regs); goto fail; } - g->bar1 = regs; - g->bar1_mem = r; + l->bar1 = regs; + l->bar1_mem = r; } nvgpu_mutex_init(&g->dbg_sessions_lock); -- cgit v1.2.2