-- cgit v1.2.2 From 548c95266cd1055c317d3d38835f628f9acfe3bf Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 6 Apr 2016 17:46:57 -0700 Subject: gpu: nvgpu: gv11b: add hw headers for gv11b Add initial versions of header for gv11b Bug 1735757 Change-Id: I76f85bbe98c1fa13c11d8ee1b2889703f62c6f67 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1121486 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h | 125 + drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h | 109 + drivers/gpu/nvgpu/gv11b/hw_ce2_gv11b.h | 81 + drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h | 457 +++ drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | 453 +++ drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 673 ++++ drivers/gpu/nvgpu/gv11b/hw_flush_gv11b.h | 181 ++ drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h | 137 + drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 1225 ++++++++ drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 3317 ++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h | 553 ++++ drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h | 241 ++ drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 537 ++++ drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h | 205 ++ drivers/gpu/nvgpu/gv11b/hw_pri_ringmaster_gv11b.h | 145 + .../gpu/nvgpu/gv11b/hw_pri_ringstation_sys_gv11b.h | 69 + drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | 141 + drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h | 821 +++++ drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 449 +++ drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h | 285 ++ drivers/gpu/nvgpu/gv11b/hw_timer_gv11b.h | 109 + drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h | 161 + 22 files changed, 10474 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_ce2_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_flush_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_pri_ringmaster_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_pri_ringstation_sys_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_timer_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h diff --git a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h new file mode 100644 index 00000000..730fb0a7 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_bus_gv11b_h_ +#define _hw_bus_gv11b_h_ + +static inline u32 bus_bar1_block_r(void) +{ + return 0x00001704; +} +static inline u32 bus_bar1_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar1_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar1_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar2_block_r(void) +{ + return 0x00001714; +} +static inline u32 bus_bar2_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar2_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar2_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar1_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bar2_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_intr_0_r(void) +{ + return 0x00001100; +} +static inline u32 bus_intr_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +static inline u32 bus_intr_en_0_r(void) +{ + return 0x00001140; +} +static inline u32 bus_intr_en_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_en_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_en_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h new file mode 100644 index 00000000..29df4bdd --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ccsr_gv11b_h_ +#define _hw_ccsr_gv11b_h_ + +static inline u32 ccsr_channel_inst_r(u32 i) +{ + return 0x00800000 + i*8; +} +static inline u32 ccsr_channel_inst__size_1_v(void) +{ + return 0x00001000; +} +static inline u32 ccsr_channel_inst_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 ccsr_channel_inst_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_bind_false_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_bind_true_f(void) +{ + return 0x80000000; +} +static inline u32 ccsr_channel_r(u32 i) +{ + return 0x00800004 + i*8; +} +static inline u32 ccsr_channel__size_1_v(void) +{ + return 0x00001000; +} +static inline u32 ccsr_channel_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ccsr_channel_enable_set_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ccsr_channel_enable_set_true_f(void) +{ + return 0x400; +} +static inline u32 ccsr_channel_enable_clr_true_f(void) +{ + return 0x800; +} +static inline u32 ccsr_channel_status_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ccsr_channel_busy_v(u32 r) +{ + return (r >> 28) & 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ce2_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ce2_gv11b.h new file mode 100644 index 00000000..e58bf271 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_ce2_gv11b.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce2_gv11b_h_ +#define _hw_ce2_gv11b_h_ + +static inline u32 ce2_intr_status_r(u32 i) +{ + return 0x00104410 + i*128; +} +static inline u32 ce2_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce2_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce2_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce2_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h new file mode 100644 index 00000000..5c60c30c --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h @@ -0,0 +1,457 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ctxsw_prog_gv11b_h_ +#define _hw_ctxsw_prog_gv11b_h_ + +static inline u32 ctxsw_prog_fecs_header_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_patch_count_o(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_context_id_o(void) +{ + return 0x000000f0; +} +static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) +{ + return 0x00000014; +} +static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) +{ + return 0x00000018; +} +static inline u32 ctxsw_prog_main_image_zcull_o(void) +{ + return 0x0000001c; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) +{ + return 0x00000001; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_pm_o(void) +{ + return 0x00000028; +} +static inline u32 ctxsw_prog_main_image_pm_mode_m(void) +{ + return 0x7 << 0; +} +static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) +{ + return 0x7 << 3; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) +{ + return 0x8; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) +{ + return 0x0000002c; +} +static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) +{ + return 0x000000d0; +} +static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) +{ + return 0x000000d4; +} +static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) +{ + return 0x000000d8; +} +static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) +{ + return 0x000000dc; +} +static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_main_image_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) +{ + return 0x600dc0de; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_ppc_info_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_local_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) +{ + return 0xad0becab; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) +{ + return 0x000000ec; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) +{ + return 0x000000a0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) +{ + return 2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) +{ + return 0x3 << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) +{ + return 0x2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) +{ + return 0x000000a4; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) +{ + return 0x000000a8; +} +static inline u32 ctxsw_prog_main_image_misc_options_o(void) +{ + return 0x0000003c; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) +{ + return 0x1 << 3; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) +{ + return 0x00000080; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) +{ + return 0x00000068; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) +{ + return 0x00000084; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) +{ + return 0x2; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) +{ + return 0x000000ac; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) +{ + return 0x000000b0; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) +{ + return 0x1ffff << 0; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) +{ + return 0x000000b4; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) +{ + return 0x00000080; +} +static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) +{ + return 0x600dbeef; +} +static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) +{ + return 0x00000018; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) +{ + return 0x0000001c; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) +{ + return 0xff << 24; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) +{ + return (r >> 24) & 0xff; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) +{ + return 0x00000001; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) +{ + return 0x1000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) +{ + return 0x2000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) +{ + return 0x0000000a; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) +{ + return 0xa000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) +{ + return 0x0000000b; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) +{ + return 0xb000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) +{ + return 0xc000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) +{ + return 0x0000000d; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) +{ + return 0xd000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) +{ + return 0x00000003; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) +{ + return 0x3000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) +{ + return 0x4000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) +{ + return 0x00000005; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) +{ + return 0x5000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) +{ + return 0x000000ff; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) +{ + return 0xff000000; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h new file mode 100644 index 00000000..7537f749 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h @@ -0,0 +1,453 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fb_gv11b_h_ +#define _hw_fb_gv11b_h_ + +static inline u32 fb_fbhub_num_active_ltcs_r(void) +{ + return 0x00100800; +} +static inline u32 fb_mmu_ctrl_r(void) +{ + return 0x00100c80; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) +{ + return 0x0; +} +static inline u32 fb_priv_mmu_phy_secure_r(void) +{ + return 0x00100ce4; +} +static inline u32 fb_mmu_invalidate_pdb_r(void) +{ + return 0x00100cb8; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_invalidate_r(void) +{ + return 0x00100cbc; +} +static inline u32 fb_mmu_invalidate_all_va_true_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_invalidate_replay_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_replay_f(u32 v) +{ + return (v & 0x7) << 3; +} +static inline u32 fb_mmu_invalidate_replay_m(void) +{ + return 0x7 << 3; +} +static inline u32 fb_mmu_invalidate_replay_v(u32 r) +{ + return (r >> 3) & 0x7; +} +static inline u32 fb_mmu_invalidate_replay_none_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_replay_start_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void) +{ + return 0x18; +} +static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_invalidate_sys_membar_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_m(void) +{ + return 0x1 << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_invalidate_ack_s(void) +{ + return 2; +} +static inline u32 fb_mmu_invalidate_ack_f(u32 v) +{ + return (v & 0x3) << 7; +} +static inline u32 fb_mmu_invalidate_ack_m(void) +{ + return 0x3 << 7; +} +static inline u32 fb_mmu_invalidate_ack_v(u32 r) +{ + return (r >> 7) & 0x3; +} +static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) +{ + return 6; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) +{ + return (v & 0x3f) << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) +{ + return 0x3f << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) +{ + return (r >> 9) & 0x3f; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) +{ + return 5; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) +{ + return 0x1f << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) +{ + return 0x1 << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) +{ + return 0x100000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) +{ + return 0x7 << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) +{ + return (r >> 24) & 0x7; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) +{ + return 0x1000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) +{ + return 0x2000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) +{ + return 0x3000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) +{ + return 0x4000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) +{ + return 0x5000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) +{ + return 0x6000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) +{ + return 0x7000000; +} +static inline u32 fb_mmu_invalidate_trigger_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_trigger_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_invalidate_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_invalidate_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_invalidate_trigger_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_debug_wr_r(void) +{ + return 0x00100cc8; +} +static inline u32 fb_mmu_debug_wr_aperture_s(void) +{ + return 2; +} +static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_m(void) +{ + return 0x3 << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_wr_vol_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_debug_wr_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_rd_r(void) +{ + return 0x00100ccc; +} +static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_ctrl_r(void) +{ + return 0x00100cc4; +} +static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 fb_mmu_debug_ctrl_debug_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_r(void) +{ + return 0x00100cd0; +} +static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_vpr_info_fetch_false_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_fetch_true_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h new file mode 100644 index 00000000..a4989aba --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h @@ -0,0 +1,673 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fifo_gv11b_h_ +#define _hw_fifo_gv11b_h_ + +static inline u32 fifo_bar1_base_r(void) +{ + return 0x00002254; +} +static inline u32 fifo_bar1_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_bar1_base_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 fifo_bar1_base_valid_false_f(void) +{ + return 0x0; +} +static inline u32 fifo_bar1_base_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_runlist_base_r(void) +{ + return 0x00002270; +} +static inline u32 fifo_runlist_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_runlist_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fifo_runlist_r(void) +{ + return 0x00002274; +} +static inline u32 fifo_runlist_engine_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 fifo_eng_runlist_base_r(u32 i) +{ + return 0x00002280 + i*8; +} +static inline u32 fifo_eng_runlist_base__size_1_v(void) +{ + return 0x0000000d; +} +static inline u32 fifo_eng_runlist_r(u32 i) +{ + return 0x00002284 + i*8; +} +static inline u32 fifo_eng_runlist__size_1_v(void) +{ + return 0x0000000d; +} +static inline u32 fifo_eng_runlist_length_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fifo_eng_runlist_length_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 fifo_eng_runlist_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_pb_timeslice_r(u32 i) +{ + return 0x00002350 + i*4; +} +static inline u32 fifo_pb_timeslice_timeout_16_f(void) +{ + return 0x10; +} +static inline u32 fifo_pb_timeslice_timescale_0_f(void) +{ + return 0x0; +} +static inline u32 fifo_pb_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_pbdma_map_r(u32 i) +{ + return 0x00002390 + i*4; +} +static inline u32 fifo_intr_0_r(void) +{ + return 0x00002100; +} +static inline u32 fifo_intr_0_bind_error_pending_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_bind_error_reset_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_sched_error_pending_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_sched_error_reset_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_chsw_error_pending_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_chsw_error_reset_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_lb_error_pending_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_lb_error_reset_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void) +{ + return 0x2000000; +} +static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) +{ + return 0x8000000; +} +static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) +{ + return 0x8000000; +} +static inline u32 fifo_intr_0_mmu_fault_pending_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_intr_0_runlist_event_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fifo_intr_0_channel_intr_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fifo_intr_en_0_r(void) +{ + return 0x00002140; +} +static inline u32 fifo_intr_en_0_sched_error_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fifo_intr_en_0_sched_error_m(void) +{ + return 0x1 << 8; +} +static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fifo_intr_en_0_mmu_fault_m(void) +{ + return 0x1 << 28; +} +static inline u32 fifo_intr_en_1_r(void) +{ + return 0x00002528; +} +static inline u32 fifo_intr_bind_error_r(void) +{ + return 0x0000252c; +} +static inline u32 fifo_intr_sched_error_r(void) +{ + return 0x0000254c; +} +static inline u32 fifo_intr_sched_error_code_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) +{ + return 0x0000000a; +} +static inline u32 fifo_intr_chsw_error_r(void) +{ + return 0x0000256c; +} +static inline u32 fifo_intr_mmu_fault_id_r(void) +{ + return 0x0000259c; +} +static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) +{ + return 0x00000040; +} +static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) +{ + return 0x0; +} +static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) +{ + return 0x00002800 + i*16; +} +static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) +{ + return 0x00002804 + i*16; +} +static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) +{ + return 0x00002808 + i*16; +} +static inline u32 fifo_intr_mmu_fault_info_r(u32 i) +{ + return 0x0000280c + i*16; +} +static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) +{ + return (r >> 8) & 0x7f; +} +static inline u32 fifo_intr_pbdma_id_r(void) +{ + return 0x000025a0; +} +static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 fifo_intr_runlist_r(void) +{ + return 0x00002a00; +} +static inline u32 fifo_fb_timeout_r(void) +{ + return 0x00002a04; +} +static inline u32 fifo_fb_timeout_period_m(void) +{ + return 0x3fffffff << 0; +} +static inline u32 fifo_fb_timeout_period_max_f(void) +{ + return 0x3fffffff; +} +static inline u32 fifo_error_sched_disable_r(void) +{ + return 0x0000262c; +} +static inline u32 fifo_sched_disable_r(void) +{ + return 0x00002630; +} +static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_sched_disable_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_sched_disable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_preempt_r(void) +{ + return 0x00002634; +} +static inline u32 fifo_preempt_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_preempt_type_channel_f(void) +{ + return 0x0; +} +static inline u32 fifo_preempt_type_tsg_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_preempt_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_preempt_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_trigger_mmu_fault_r(u32 i) +{ + return 0x00002a30 + i*4; +} +static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fifo_engine_status_r(u32 i) +{ + return 0x00002640 + i*8; +} +static inline u32 fifo_engine_status__size_1_v(void) +{ + return 0x0000000f; +} +static inline u32 fifo_engine_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_engine_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_engine_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_engine_status_ctx_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_engine_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_engine_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_engine_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_faulted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fifo_engine_status_faulted_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_engine_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fifo_engine_status_engine_idle_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_engine_busy_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) +{ + return 0x8000; +} +static inline u32 fifo_pbdma_status_r(u32 i) +{ + return 0x00003080 + i*4; +} +static inline u32 fifo_pbdma_status__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 fifo_pbdma_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_pbdma_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_pbdma_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_pbdma_status_chan_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_pbdma_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_chsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_lo_r(void) +{ + return 0x00002a70; +} +static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_hi_r(void) +{ + return 0x00002a74; +} +static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_size_r(void) +{ + return 0x00002a78; +} +static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) +{ + return (v & 0x3fff) << 0; +} +static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) +{ + return 0x00002000; +} +static inline u32 fifo_replay_fault_buffer_get_r(void) +{ + return 0x00002a7c; +} +static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) +{ + return (v & 0x3fff) << 0; +} +static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_put_r(void) +{ + return 0x00002a80; +} +static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) +{ + return (v & 0x3fff) << 0; +} +static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_r(void) +{ + return 0x00002a84; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_flush_gv11b.h new file mode 100644 index 00000000..380f8824 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_flush_gv11b.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_flush_gv11b_h_ +#define _hw_flush_gv11b_h_ + +static inline u32 flush_l2_system_invalidate_r(void) +{ + return 0x00070004; +} +static inline u32 flush_l2_system_invalidate_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_system_invalidate_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_system_invalidate_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_r(void) +{ + return 0x00070010; +} +static inline u32 flush_l2_flush_dirty_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_flush_dirty_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_r(void) +{ + return 0x0007000c; +} +static inline u32 flush_l2_clean_comptags_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_clean_comptags_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_r(void) +{ + return 0x00070000; +} +static inline u32 flush_fb_flush_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_fb_flush_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_fb_flush_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_fb_flush_outstanding_true_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h new file mode 100644 index 00000000..75617e6e --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fuse_gv11b_h_ +#define _hw_fuse_gv11b_h_ + +static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) +{ + return 0x00021c38 + i*4; +} +static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) +{ + return 0x00021838 + i*4; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) +{ + return 0x00021944; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) +{ + return 0xff << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) +{ + return 0x00021948; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) +{ + return 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) +{ + return 0x0; +} +static inline u32 fuse_status_opt_fbio_r(void) +{ + return 0x00021c14; +} +static inline u32 fuse_status_opt_fbio_data_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fuse_status_opt_fbio_data_m(void) +{ + return 0xffff << 0; +} +static inline u32 fuse_status_opt_fbio_data_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) +{ + return 0x00021d70 + i*4; +} +static inline u32 fuse_status_opt_fbp_r(void) +{ + return 0x00021d38; +} +static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) +{ + return (r >> (0 + i*0)) & 0x1; +} +static inline u32 fuse_opt_ecc_en_r(void) +{ + return 0x00021228; +} +static inline u32 fuse_opt_feature_fuses_override_disable_r(void) +{ + return 0x000213f0; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h new file mode 100644 index 00000000..99cc3442 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h @@ -0,0 +1,1225 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gmmu_gv11b_h_ +#define _hw_gmmu_gv11b_h_ + +static inline u32 gmmu_new_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_aperture_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_pde_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pde_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pde_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_pde__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_vol_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_vol_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde__size_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_new_pte__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_pte_valid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_valid_true_f(void) +{ + return 0x1; +} +static inline u32 gmmu_new_pte_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_privilege_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_privilege_true_f(void) +{ + return 0x20; +} +static inline u32 gmmu_new_pte_privilege_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pte_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_aperture_video_memory_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_read_only_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_read_only_true_f(void) +{ + return 0x40; +} +static inline u32 gmmu_new_pte_comptagline_f(u32 v) +{ + return (v & 0x3ffff) << 4; +} +static inline u32 gmmu_new_pte_comptagline_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_kind_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gmmu_new_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_f(u32 v) +{ + return (v & 0xff) << 4; +} +static inline u32 gmmu_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_kind_invalid_v(void) +{ + return 0x000000ff; +} +static inline u32 gmmu_pte_kind_pitch_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_pte_kind_z16_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_pte_kind_z16_2c_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) +{ + return 0x00000006; +} +static inline u32 gmmu_pte_kind_z16_2z_v(void) +{ + return 0x00000007; +} +static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) +{ + return 0x00000009; +} +static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) +{ + return 0x0000000a; +} +static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) +{ + return 0x0000000b; +} +static inline u32 gmmu_pte_kind_z16_2cz_v(void) +{ + return 0x00000036; +} +static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) +{ + return 0x00000037; +} +static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) +{ + return 0x00000038; +} +static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) +{ + return 0x00000039; +} +static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) +{ + return 0x0000005f; +} +static inline u32 gmmu_pte_kind_z16_4cz_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) +{ + return 0x0000000d; +} +static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) +{ + return 0x0000000e; +} +static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) +{ + return 0x0000000f; +} +static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_pte_kind_s8z24_v(void) +{ + return 0x00000011; +} +static inline u32 gmmu_pte_kind_s8z24_1z_v(void) +{ + return 0x00000012; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) +{ + return 0x00000013; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) +{ + return 0x00000014; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) +{ + return 0x00000015; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) +{ + return 0x00000016; +} +static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) +{ + return 0x00000017; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) +{ + return 0x00000018; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) +{ + return 0x00000019; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) +{ + return 0x0000001a; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) +{ + return 0x0000001b; +} +static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) +{ + return 0x0000001c; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) +{ + return 0x0000001d; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) +{ + return 0x0000001e; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) +{ + return 0x00000021; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) +{ + return 0x00000022; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) +{ + return 0x00000023; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) +{ + return 0x00000024; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) +{ + return 0x00000025; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) +{ + return 0x00000026; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) +{ + return 0x00000027; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) +{ + return 0x00000028; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) +{ + return 0x00000029; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) +{ + return 0x0000002e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) +{ + return 0x0000002f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) +{ + return 0x00000030; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) +{ + return 0x00000031; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) +{ + return 0x00000032; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) +{ + return 0x00000033; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) +{ + return 0x00000034; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) +{ + return 0x00000035; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) +{ + return 0x0000003a; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) +{ + return 0x0000003b; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) +{ + return 0x0000003c; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) +{ + return 0x0000003d; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) +{ + return 0x0000003e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) +{ + return 0x0000003f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) +{ + return 0x00000040; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) +{ + return 0x00000041; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) +{ + return 0x00000042; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) +{ + return 0x00000043; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) +{ + return 0x00000044; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) +{ + return 0x00000045; +} +static inline u32 gmmu_pte_kind_z24s8_v(void) +{ + return 0x00000046; +} +static inline u32 gmmu_pte_kind_z24s8_1z_v(void) +{ + return 0x00000047; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) +{ + return 0x00000048; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) +{ + return 0x00000049; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) +{ + return 0x0000004a; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) +{ + return 0x0000004b; +} +static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) +{ + return 0x0000004c; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) +{ + return 0x0000004d; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) +{ + return 0x0000004e; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) +{ + return 0x0000004f; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) +{ + return 0x00000050; +} +static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) +{ + return 0x00000051; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) +{ + return 0x00000052; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) +{ + return 0x00000053; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) +{ + return 0x00000054; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) +{ + return 0x00000055; +} +static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) +{ + return 0x00000056; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) +{ + return 0x00000057; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) +{ + return 0x00000058; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) +{ + return 0x00000059; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) +{ + return 0x0000005a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) +{ + return 0x0000005b; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) +{ + return 0x0000005c; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) +{ + return 0x0000005d; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) +{ + return 0x0000005e; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) +{ + return 0x00000063; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) +{ + return 0x00000064; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) +{ + return 0x00000065; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) +{ + return 0x00000066; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) +{ + return 0x00000067; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) +{ + return 0x00000068; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) +{ + return 0x00000069; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) +{ + return 0x0000006a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) +{ + return 0x0000006f; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) +{ + return 0x00000070; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) +{ + return 0x00000071; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) +{ + return 0x00000072; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) +{ + return 0x00000073; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) +{ + return 0x00000074; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) +{ + return 0x00000075; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) +{ + return 0x00000076; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) +{ + return 0x00000077; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) +{ + return 0x00000078; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) +{ + return 0x00000079; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) +{ + return 0x0000007a; +} +static inline u32 gmmu_pte_kind_zf32_v(void) +{ + return 0x0000007b; +} +static inline u32 gmmu_pte_kind_zf32_1z_v(void) +{ + return 0x0000007c; +} +static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) +{ + return 0x0000007d; +} +static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) +{ + return 0x0000007e; +} +static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) +{ + return 0x0000007f; +} +static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) +{ + return 0x00000080; +} +static inline u32 gmmu_pte_kind_zf32_2cs_v(void) +{ + return 0x00000081; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) +{ + return 0x00000082; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) +{ + return 0x00000083; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) +{ + return 0x00000084; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) +{ + return 0x00000085; +} +static inline u32 gmmu_pte_kind_zf32_2cz_v(void) +{ + return 0x00000086; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) +{ + return 0x00000087; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) +{ + return 0x00000088; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) +{ + return 0x00000089; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) +{ + return 0x0000008a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) +{ + return 0x0000008b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) +{ + return 0x0000008c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) +{ + return 0x0000008d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) +{ + return 0x0000008e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x0000008f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x00000090; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x00000091; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x00000092; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x00000097; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x00000098; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x00000099; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x0000009a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x0000009b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x0000009c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x0000009d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x0000009e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x0000009f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000a0; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000a1; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000a2; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000a3; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000a4; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000a5; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000a6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) +{ + return 0x000000a7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) +{ + return 0x000000a8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) +{ + return 0x000000a9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) +{ + return 0x000000aa; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x000000ab; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x000000ac; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x000000ad; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x000000ae; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x000000b3; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x000000b4; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x000000b5; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x000000b6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x000000b7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x000000b8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x000000b9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x000000ba; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x000000bb; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000bc; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000bd; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000be; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000bf; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000c0; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000c1; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000c2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) +{ + return 0x000000c3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) +{ + return 0x000000c4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) +{ + return 0x000000c5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) +{ + return 0x000000c6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) +{ + return 0x000000c7; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) +{ + return 0x000000c8; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) +{ + return 0x000000ce; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) +{ + return 0x000000cf; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) +{ + return 0x000000d0; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) +{ + return 0x000000d1; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) +{ + return 0x000000d2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) +{ + return 0x000000d3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) +{ + return 0x000000d4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) +{ + return 0x000000d5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) +{ + return 0x000000d6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) +{ + return 0x000000d7; +} +static inline u32 gmmu_pte_kind_generic_16bx2_v(void) +{ + return 0x000000fe; +} +static inline u32 gmmu_pte_kind_c32_2c_v(void) +{ + return 0x000000d8; +} +static inline u32 gmmu_pte_kind_c32_2cbr_v(void) +{ + return 0x000000d9; +} +static inline u32 gmmu_pte_kind_c32_2cba_v(void) +{ + return 0x000000da; +} +static inline u32 gmmu_pte_kind_c32_2cra_v(void) +{ + return 0x000000db; +} +static inline u32 gmmu_pte_kind_c32_2bra_v(void) +{ + return 0x000000dc; +} +static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) +{ + return 0x000000dd; +} +static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) +{ + return 0x000000df; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) +{ + return 0x000000e0; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) +{ + return 0x000000e1; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) +{ + return 0x000000e2; +} +static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) +{ + return 0x000000e3; +} +static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) +{ + return 0x0000002c; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) +{ + return 0x000000e4; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) +{ + return 0x000000e5; +} +static inline u32 gmmu_pte_kind_c64_2c_v(void) +{ + return 0x000000e6; +} +static inline u32 gmmu_pte_kind_c64_2cbr_v(void) +{ + return 0x000000e7; +} +static inline u32 gmmu_pte_kind_c64_2cba_v(void) +{ + return 0x000000e8; +} +static inline u32 gmmu_pte_kind_c64_2cra_v(void) +{ + return 0x000000e9; +} +static inline u32 gmmu_pte_kind_c64_2bra_v(void) +{ + return 0x000000ea; +} +static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) +{ + return 0x000000eb; +} +static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) +{ + return 0x000000ec; +} +static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) +{ + return 0x000000ed; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) +{ + return 0x000000ee; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) +{ + return 0x000000ef; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) +{ + return 0x000000f0; +} +static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) +{ + return 0x000000f1; +} +static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) +{ + return 0x0000002d; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) +{ + return 0x000000f2; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) +{ + return 0x000000f3; +} +static inline u32 gmmu_pte_kind_c128_2c_v(void) +{ + return 0x000000f4; +} +static inline u32 gmmu_pte_kind_c128_2cr_v(void) +{ + return 0x000000f5; +} +static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) +{ + return 0x000000f6; +} +static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) +{ + return 0x000000f7; +} +static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) +{ + return 0x000000f8; +} +static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) +{ + return 0x000000f9; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) +{ + return 0x000000fa; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) +{ + return 0x000000fb; +} +static inline u32 gmmu_pte_kind_x8c24_v(void) +{ + return 0x000000fc; +} +static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) +{ + return 0x000000fd; +} +static inline u32 gmmu_pte_kind_smsked_message_v(void) +{ + return 0x000000ca; +} +static inline u32 gmmu_pte_kind_smhost_message_v(void) +{ + return 0x000000cb; +} +static inline u32 gmmu_pte_kind_s8_v(void) +{ + return 0x0000002a; +} +static inline u32 gmmu_pte_kind_s8_2s_v(void) +{ + return 0x0000002b; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h new file mode 100644 index 00000000..3772d9ab --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -0,0 +1,3317 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gr_gv11b_h_ +#define _hw_gr_gv11b_h_ + +static inline u32 gr_intr_r(void) +{ + return 0x00400100; +} +static inline u32 gr_intr_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_notify_reset_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_semaphore_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_semaphore_reset_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_illegal_method_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_method_reset_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_notify_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_illegal_notify_reset_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_firmware_method_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_intr_firmware_method_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_firmware_method_reset_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_illegal_class_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_illegal_class_reset_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_fecs_error_pending_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_fecs_error_reset_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_class_error_pending_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_class_error_reset_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_exception_pending_f(void) +{ + return 0x200000; +} +static inline u32 gr_intr_exception_reset_f(void) +{ + return 0x200000; +} +static inline u32 gr_fecs_intr_r(void) +{ + return 0x00400144; +} +static inline u32 gr_class_error_r(void) +{ + return 0x00400110; +} +static inline u32 gr_class_error_code_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_intr_nonstall_r(void) +{ + return 0x00400120; +} +static inline u32 gr_intr_nonstall_trap_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_en_r(void) +{ + return 0x0040013c; +} +static inline u32 gr_exception_r(void) +{ + return 0x00400108; +} +static inline u32 gr_exception_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception1_r(void) +{ + return 0x00400118; +} +static inline u32 gr_exception1_gpc_0_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_exception2_r(void) +{ + return 0x0040011c; +} +static inline u32 gr_exception_en_r(void) +{ + return 0x00400138; +} +static inline u32 gr_exception_en_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception1_en_r(void) +{ + return 0x00400130; +} +static inline u32 gr_exception2_en_r(void) +{ + return 0x00400134; +} +static inline u32 gr_gpfifo_ctl_r(void) +{ + return 0x00400500; +} +static inline u32 gr_gpfifo_ctl_access_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpfifo_ctl_access_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpfifo_ctl_access_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpfifo_status_r(void) +{ + return 0x00400504; +} +static inline u32 gr_trapped_addr_r(void) +{ + return 0x00400704; +} +static inline u32 gr_trapped_addr_mthd_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 gr_trapped_addr_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 gr_trapped_data_lo_r(void) +{ + return 0x00400708; +} +static inline u32 gr_trapped_data_hi_r(void) +{ + return 0x0040070c; +} +static inline u32 gr_status_r(void) +{ + return 0x00400700; +} +static inline u32 gr_status_fe_method_upper_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_status_fe_method_lower_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_status_fe_method_lower_idle_v(void) +{ + return 0x00000000; +} +static inline u32 gr_status_fe_gi_v(u32 r) +{ + return (r >> 21) & 0x1; +} +static inline u32 gr_status_mask_r(void) +{ + return 0x00400610; +} +static inline u32 gr_status_1_r(void) +{ + return 0x00400604; +} +static inline u32 gr_status_2_r(void) +{ + return 0x00400608; +} +static inline u32 gr_engine_status_r(void) +{ + return 0x0040060c; +} +static inline u32 gr_engine_status_value_busy_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_be0_becs_be_exception_r(void) +{ + return 0x00410204; +} +static inline u32 gr_pri_be0_becs_be_exception_en_r(void) +{ + return 0x00410208; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) +{ + return 0x00502c94; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_activity_0_r(void) +{ + return 0x00400380; +} +static inline u32 gr_activity_1_r(void) +{ + return 0x00400384; +} +static inline u32 gr_activity_2_r(void) +{ + return 0x00400388; +} +static inline u32 gr_activity_4_r(void) +{ + return 0x00400390; +} +static inline u32 gr_activity_4_gpc0_s(void) +{ + return 3; +} +static inline u32 gr_activity_4_gpc0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_activity_4_gpc0_m(void) +{ + return 0x7 << 0; +} +static inline u32 gr_activity_4_gpc0_v(u32 r) +{ + return (r >> 0) & 0x7; +} +static inline u32 gr_activity_4_gpc0_empty_v(void) +{ + return 0x00000000; +} +static inline u32 gr_activity_4_gpc0_preempted_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pri_gpc0_gcc_dbg_r(void) +{ + return 0x00501000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_r(void) +{ + return 0x00419000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) +{ + return 0x0050433c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) +{ + return 0x00419b3c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_sked_activity_r(void) +{ + return 0x00407054; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) +{ + return 0x00502c80; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) +{ + return 0x00502c84; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) +{ + return 0x00502c88; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) +{ + return 0x00502c8c; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x00504500; +} +static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x00504d00; +} +static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00501d00; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) +{ + return 0x0041ac80; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) +{ + return 0x0041ac84; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) +{ + return 0x0041ac88; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) +{ + return 0x0041ac8c; +} +static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x0041c500; +} +static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x0041cd00; +} +static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00419d00; +} +static inline u32 gr_pri_be0_becs_be_activity0_r(void) +{ + return 0x00410200; +} +static inline u32 gr_pri_be1_becs_be_activity0_r(void) +{ + return 0x00410600; +} +static inline u32 gr_pri_bes_becs_be_activity0_r(void) +{ + return 0x00408a00; +} +static inline u32 gr_pri_ds_mpipe_status_r(void) +{ + return 0x00405858; +} +static inline u32 gr_pri_fe_go_idle_info_r(void) +{ + return 0x00404194; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) +{ + return 0x00504238; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) +{ + return 0x00504358; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void) +{ + return 0x80; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void) +{ + return 0x200; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void) +{ + return 0x400; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void) +{ + return 0x800; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) +{ + return 0x0050436c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void) +{ + return 0x200; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) +{ + return 0x0050435c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) +{ + return 0x00504360; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) +{ + return 0x00504370; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) +{ + return 0xff << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void) +{ + return 0xff << 8; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r) +{ + return (r >> 8) & 0xff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void) +{ + return 0xff << 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) +{ + return 0x005042c4; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) +{ + return 0x0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) +{ + return 0x2; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void) +{ + return 0x00504218; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void) +{ + return 0x005042ec; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_pri_be0_crop_status1_r(void) +{ + return 0x00410134; +} +static inline u32 gr_pri_bes_crop_status1_r(void) +{ + return 0x00408934; +} +static inline u32 gr_pri_be0_zrop_status_r(void) +{ + return 0x00410048; +} +static inline u32 gr_pri_be0_zrop_status2_r(void) +{ + return 0x0041004c; +} +static inline u32 gr_pri_bes_zrop_status_r(void) +{ + return 0x00408848; +} +static inline u32 gr_pri_bes_zrop_status2_r(void) +{ + return 0x0040884c; +} +static inline u32 gr_pipe_bundle_address_r(void) +{ + return 0x00400200; +} +static inline u32 gr_pipe_bundle_address_value_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pipe_bundle_data_r(void) +{ + return 0x00400204; +} +static inline u32 gr_pipe_bundle_config_r(void) +{ + return 0x00400208; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fe_hww_esr_r(void) +{ + return 0x00404000; +} +static inline u32 gr_fe_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_fe_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fe_go_idle_timeout_r(void) +{ + return 0x00404154; +} +static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) +{ + return 0x1800; +} +static inline u32 gr_fe_object_table_r(u32 i) +{ + return 0x00404200 + i*4; +} +static inline u32 gr_fe_object_table_nvclass_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_mme_shadow_raw_index_r(void) +{ + return 0x00404488; +} +static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pri_mme_shadow_raw_data_r(void) +{ + return 0x0040448c; +} +static inline u32 gr_mme_hww_esr_r(void) +{ + return 0x00404490; +} +static inline u32 gr_mme_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_mme_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_memfmt_hww_esr_r(void) +{ + return 0x00404600; +} +static inline u32 gr_memfmt_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_memfmt_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fecs_cpuctl_r(void) +{ + return 0x00409100; +} +static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_cpuctl_alias_r(void) +{ + return 0x00409130; +} +static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_dmactl_r(void) +{ + return 0x0040910c; +} +static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_fecs_os_r(void) +{ + return 0x00409080; +} +static inline u32 gr_fecs_idlestate_r(void) +{ + return 0x0040904c; +} +static inline u32 gr_fecs_mailbox0_r(void) +{ + return 0x00409040; +} +static inline u32 gr_fecs_mailbox1_r(void) +{ + return 0x00409044; +} +static inline u32 gr_fecs_irqstat_r(void) +{ + return 0x00409008; +} +static inline u32 gr_fecs_irqmode_r(void) +{ + return 0x0040900c; +} +static inline u32 gr_fecs_irqmask_r(void) +{ + return 0x00409018; +} +static inline u32 gr_fecs_irqdest_r(void) +{ + return 0x0040901c; +} +static inline u32 gr_fecs_curctx_r(void) +{ + return 0x00409050; +} +static inline u32 gr_fecs_nxtctx_r(void) +{ + return 0x00409054; +} +static inline u32 gr_fecs_engctl_r(void) +{ + return 0x004090a4; +} +static inline u32 gr_fecs_debug1_r(void) +{ + return 0x00409090; +} +static inline u32 gr_fecs_debuginfo_r(void) +{ + return 0x00409094; +} +static inline u32 gr_fecs_icd_cmd_r(void) +{ + return 0x00409200; +} +static inline u32 gr_fecs_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 gr_fecs_icd_rdata_r(void) +{ + return 0x0040920c; +} +static inline u32 gr_fecs_imemc_r(u32 i) +{ + return 0x00409180 + i*16; +} +static inline u32 gr_fecs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_imemd_r(u32 i) +{ + return 0x00409184 + i*16; +} +static inline u32 gr_fecs_imemt_r(u32 i) +{ + return 0x00409188 + i*16; +} +static inline u32 gr_fecs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_dmemc_r(u32 i) +{ + return 0x004091c0 + i*8; +} +static inline u32 gr_fecs_dmemc_offs_s(void) +{ + return 6; +} +static inline u32 gr_fecs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 gr_fecs_dmemc_offs_v(u32 r) +{ + return (r >> 2) & 0x3f; +} +static inline u32 gr_fecs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_dmemd_r(u32 i) +{ + return 0x004091c4 + i*8; +} +static inline u32 gr_fecs_dmatrfbase_r(void) +{ + return 0x00409110; +} +static inline u32 gr_fecs_dmatrfmoffs_r(void) +{ + return 0x00409114; +} +static inline u32 gr_fecs_dmatrffboffs_r(void) +{ + return 0x0040911c; +} +static inline u32 gr_fecs_dmatrfcmd_r(void) +{ + return 0x00409118; +} +static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_fecs_bootvec_r(void) +{ + return 0x00409104; +} +static inline u32 gr_fecs_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_falcon_hwcfg_r(void) +{ + return 0x00409108; +} +static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) +{ + return 0x0041a108; +} +static inline u32 gr_fecs_falcon_rm_r(void) +{ + return 0x00409084; +} +static inline u32 gr_fecs_current_ctx_r(void) +{ + return 0x00409b00; +} +static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_current_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_current_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_current_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_current_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_current_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_current_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_current_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_current_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_current_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_method_data_r(void) +{ + return 0x00409500; +} +static inline u32 gr_fecs_method_push_r(void) +{ + return 0x00409504; +} +static inline u32 gr_fecs_method_push_adr_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) +{ + return 0x00000003; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) +{ + return 0x3; +} +static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) +{ + return 0x00000009; +} +static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) +{ + return 0x00000015; +} +static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) +{ + return 0x00000016; +} +static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) +{ + return 0x00000025; +} +static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) +{ + return 0x00000030; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) +{ + return 0x00000031; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) +{ + return 0x00000032; +} +static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) +{ + return 0x00000038; +} +static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) +{ + return 0x00000039; +} +static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) +{ + return 0x21; +} +static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) +{ + return 0x0000001a; +} +static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) +{ + return 0x00000004; +} +static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) +{ + return 0x0000003a; +} +static inline u32 gr_fecs_host_int_status_r(void) +{ + return 0x00409c18; +} +static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_host_int_clear_r(void) +{ + return 0x00409c20; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_r(void) +{ + return 0x00409c24; +} +static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) +{ + return 0x10000; +} +static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) +{ + return 0x20000; +} +static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) +{ + return 0x40000; +} +static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) +{ + return 0x80000; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) +{ + return 0x00409614; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) +{ + return 0x10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) +{ + return 0x20; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) +{ + return 0x40; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) +{ + return 0x100; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) +{ + return 0x200; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) +{ + return 0x400; +} +static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) +{ + return 0x0040960c; +} +static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) +{ + return 0x00409800 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) +{ + return 0x00000001; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) +{ + return 0x00000002; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) +{ + return 0x004098c0 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) +{ + return 0x00409840 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_fs_r(void) +{ + return 0x00409604; +} +static inline u32 gr_fecs_fs_num_available_gpcs_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_fs_num_available_fbps_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_m(void) +{ + return 0x1f << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_fecs_cfg_r(void) +{ + return 0x00409620; +} +static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_fecs_rc_lanes_r(void) +{ + return 0x00409880; +} +static inline u32 gr_fecs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_fecs_ctxsw_status_1_r(void) +{ + return 0x00409400; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_adr_r(void) +{ + return 0x00409a24; +} +static inline u32 gr_fecs_new_ctx_r(void) +{ + return 0x00409b04; +} +static inline u32 gr_fecs_new_ctx_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_new_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_new_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_new_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_new_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_new_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_new_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_new_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_new_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_ptr_r(void) +{ + return 0x00409a0c; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_arb_ctx_cmd_r(void) +{ + return 0x00409a10; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) +{ + return 5; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) +{ + return 0x00409c00; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) +{ + return 0x00502c04; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) +{ + return 0x00502400; +} +static inline u32 gr_fecs_ctxsw_idlestate_r(void) +{ + return 0x00409420; +} +static inline u32 gr_fecs_feature_override_ecc_r(void) +{ + return 0x00409658; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) +{ + return 0x00502420; +} +static inline u32 gr_rstr2d_map_table_cfg_r(void) +{ + return 0x004078bc; +} +static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_hww_esr_r(void) +{ + return 0x00406018; +} +static inline u32 gr_pd_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pd_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) +{ + return 0x00406028 + i*4; +} +static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) +{ + return (v & 0xf) << 24; +} +static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) +{ + return (v & 0xf) << 28; +} +static inline u32 gr_pd_ab_dist_cfg0_r(void) +{ + return 0x004064c0; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) +{ + return 0x0; +} +static inline u32 gr_pd_ab_dist_cfg1_r(void) +{ + return 0x004064c4; +} +static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) +{ + return 0xffff; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) +{ + return 0x00000080; +} +static inline u32 gr_pd_ab_dist_cfg2_r(void) +{ + return 0x004064c8; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) +{ + return (v & 0x1fff) << 0; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) +{ + return 0x00001d80; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) +{ + return (v & 0x1fff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) +{ + return 0x00001d80; +} +static inline u32 gr_pd_dist_skip_table_r(u32 i) +{ + return 0x004064d0 + i*4; +} +static inline u32 gr_pd_dist_skip_table__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_ds_debug_r(void) +{ + return 0x00405800; +} +static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) +{ + return 0x8000000; +} +static inline u32 gr_ds_zbc_color_r_r(void) +{ + return 0x00405804; +} +static inline u32 gr_ds_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_g_r(void) +{ + return 0x00405808; +} +static inline u32 gr_ds_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_b_r(void) +{ + return 0x0040580c; +} +static inline u32 gr_ds_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_a_r(void) +{ + return 0x00405810; +} +static inline u32 gr_ds_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_r(void) +{ + return 0x00405814; +} +static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) +{ + return (v & 0x7f) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) +{ + return 0x00000002; +} +static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) +{ + return 0x00000004; +} +static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) +{ + return 0x00000028; +} +static inline u32 gr_ds_zbc_z_r(void) +{ + return 0x00405818; +} +static inline u32 gr_ds_zbc_z_val_s(void) +{ + return 32; +} +static inline u32 gr_ds_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_z_val_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_ds_zbc_z_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_ds_zbc_z_val__init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_ds_zbc_z_val__init_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_r(void) +{ + return 0x0040581c; +} +static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_tbl_index_r(void) +{ + return 0x00405820; +} +static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_ds_zbc_tbl_ld_r(void) +{ + return 0x00405824; +} +static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_tga_constraintlogic_beta_r(void) +{ + return 0x00405830; +} +static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) +{ + return 0x0040585c; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_ds_hww_esr_r(void) +{ + return 0x00405840; +} +static inline u32 gr_ds_hww_esr_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_esr_2_r(void) +{ + return 0x00405848; +} +static inline u32 gr_ds_hww_esr_2_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_2_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_2_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_report_mask_r(void) +{ + return 0x00405844; +} +static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) +{ + return 0x2; +} +static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) +{ + return 0x8; +} +static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) +{ + return 0x10; +} +static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) +{ + return 0x20; +} +static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) +{ + return 0x40; +} +static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) +{ + return 0x80; +} +static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) +{ + return 0x100; +} +static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) +{ + return 0x200; +} +static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) +{ + return 0x400; +} +static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) +{ + return 0x800; +} +static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) +{ + return 0x1000; +} +static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) +{ + return 0x20000; +} +static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) +{ + return 0x80000; +} +static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) +{ + return 0x100000; +} +static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) +{ + return 0x200000; +} +static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_ds_hww_report_mask_2_r(void) +{ + return 0x0040584c; +} +static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) +{ + return 0x00405870 + i*4; +} +static inline u32 gr_scc_bundle_cb_base_r(void) +{ + return 0x00408004; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_bundle_cb_size_r(void) +{ + return 0x00408008; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) +{ + return 0x00000030; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_pagepool_base_r(void) +{ + return 0x0040800c; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_pagepool_r(void) +{ + return 0x00408010; +} +static inline u32 gr_scc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) +{ + return 0x00000200; +} +static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_pagepool_max_valid_pages_s(void) +{ + return 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) +{ + return (v & 0x3ff) << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_m(void) +{ + return 0x3ff << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) +{ + return (r >> 10) & 0x3ff; +} +static inline u32 gr_scc_pagepool_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_init_r(void) +{ + return 0x0040802c; +} +static inline u32 gr_scc_init_ram_trigger_f(void) +{ + return 0x1; +} +static inline u32 gr_scc_hww_esr_r(void) +{ + return 0x00408030; +} +static inline u32 gr_scc_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_scc_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_sked_hww_esr_r(void) +{ + return 0x00407020; +} +static inline u32 gr_sked_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_cwd_fs_r(void) +{ + return 0x00405b00; +} +static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) +{ + return 0x00405b60 + i*4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_cwd_sm_id_r(u32 i) +{ + return 0x00405ba0 + i*4; +} +static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpc0_fs_gpc_r(void) +{ + return 0x00502608; +} +static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_gpc0_cfg_r(void) +{ + return 0x00502620; +} +static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpccs_rc_lanes_r(void) +{ + return 0x00502880; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_rc_lane_size_r(void) +{ + return 0x00502910; +} +static inline u32 gr_gpccs_rc_lane_size_v_s(void) +{ + return 24; +} +static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_m(void) +{ + return 0xffffff << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_zcull_fs_r(void) +{ + return 0x00500910; +} +static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_gpc0_zcull_ram_addr_r(void) +{ + return 0x00500914; +} +static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) +{ + return 0x00500918; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) +{ + return 0x00800000; +} +static inline u32 gr_gpc0_zcull_total_ram_size_r(void) +{ + return 0x00500920; +} +static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) +{ + return 0x00500a04 + i*32; +} +static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) +{ + return 0x00000040; +} +static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) +{ + return 0x00000010; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) +{ + return 0x00500c10 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) +{ + return 0x00500c30 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) +{ + return 0x00504088; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) +{ + return 0x00504608; +} +static inline u32 gr_gpc0_tpc0_sm_arch_r(void) +{ + return 0x00504330; +} +static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) +{ + return (r >> 8) & 0xfff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) +{ + return (r >> 20) & 0xfff; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) +{ + return 0x00503018; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) +{ + return 0x005030c0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) +{ + return 0x00000480; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) +{ + return 0x00000d10; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) +{ + return 0x005030f4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) +{ + return 0x005030e4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) +{ + return 0x005030f8; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) +{ + return 0x005030f0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) +{ + return 0x00000480; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) +{ + return 0x00419e00; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) +{ + return 0x00419e04; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) +{ + return 21; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) +{ + return (v & 0x1fffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) +{ + return 0x1fffff << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) +{ + return (r >> 0) & 0x1fffff; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) +{ + return 0x80; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpccs_falcon_addr_r(void) +{ + return 0x0041a0ac; +} +static inline u32 gr_gpccs_falcon_addr_lsb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_msb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_m(void) +{ + return 0x3f << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) +{ + return (r >> 6) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_ext_s(void) +{ + return 12; +} +static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_m(void) +{ + return 0xfff << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_gpccs_cpuctl_r(void) +{ + return 0x0041a100; +} +static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpccs_dmactl_r(void) +{ + return 0x0041a10c; +} +static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpccs_imemc_r(u32 i) +{ + return 0x0041a180 + i*16; +} +static inline u32 gr_gpccs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_imemd_r(u32 i) +{ + return 0x0041a184 + i*16; +} +static inline u32 gr_gpccs_imemt_r(u32 i) +{ + return 0x0041a188 + i*16; +} +static inline u32 gr_gpccs_imemt__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_gpccs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpccs_dmemc_r(u32 i) +{ + return 0x0041a1c0 + i*8; +} +static inline u32 gr_gpccs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_dmemd_r(u32 i) +{ + return 0x0041a1c4 + i*8; +} +static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) +{ + return 0x0041a800 + i*4; +} +static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) +{ + return 0x00418e24; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) +{ + return 32; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) +{ + return 0x00418e28; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) +{ + return 11; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) +{ + return 0x7ff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) +{ + return (r >> 0) & 0x7ff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) +{ + return 0x00000030; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) +{ + return 0x30; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) +{ + return 0x005001dc; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) +{ + return 0x00000de0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) +{ + return 0x005001d8; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) +{ + return 0x004181e4; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) +{ + return 0x0041befc; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) +{ + return 0x00418ea0 + i*4; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) +{ + return 0x00418010 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) +{ + return 0x0041804c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) +{ + return 0x00418088 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) +{ + return 0x004180c4 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) +{ + return 0x00500100; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) +{ + return 0x00418110 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) +{ + return 0x0050014c; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) +{ + return 0x00418810; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) +{ + return 0x0000000c; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_crstr_map_table_cfg_r(void) +{ + return 0x00418bb8; +} +static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpcs_gpm_pd_cfg_r(void) +{ + return 0x00418c6c; +} +static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) +{ + return 0x1; +} +static inline u32 gr_gpcs_gcc_pagepool_base_r(void) +{ + return 0x00419004; +} +static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_gcc_pagepool_r(void) +{ + return 0x00419008; +} +static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) +{ + return 0x0041980c; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) +{ + return 0x00419848; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) +{ + return 0x00419c00; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) +{ + return 0x00419c2c; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) +{ + return 0x00419d0c; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) +{ + return 0x0041ac94; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) +{ + return 0x00419e14; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) +{ + return 0x00504614; +} +static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) +{ + return 0x00504224; +} +static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void) +{ + return 0x80; +} +static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) +{ + return 0x005043a0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) +{ + return 0x00419ba0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) +{ + return 0x005043b0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) +{ + return 0x00419bb0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) +{ + return 0x0041be08; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) +{ + return 0x4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) +{ + return 0x0041bfd0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) +{ + return (v & 0x7) << 21; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) +{ + return 0x0041bfd4; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_bes_zrop_settings_r(void) +{ + return 0x00408850; +} +static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_be0_crop_debug3_r(void) +{ + return 0x00410108; +} +static inline u32 gr_bes_crop_debug3_r(void) +{ + return 0x00408908; +} +static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_bes_crop_settings_r(void) +{ + return 0x00408958; +} +static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) +{ + return 0x000000c0; +} +static inline u32 gr_zcull_subregion_qty_v(void) +{ + return 0x00000010; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) +{ + return 0x00504308; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) +{ + return 0x0050430c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) +{ + return 0x00504318; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) +{ + return 0x00504320; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) +{ + return 0x00504324; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) +{ + return 0x00504328; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) +{ + return 0x0050432c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) +{ + return 0x0050431c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) +{ + return 0x00504378; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) +{ + return 0x0050437c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) +{ + return 0x00504380; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) +{ + return 0x00504384; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) +{ + return 0x00504388; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) +{ + return 0x0050438c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) +{ + return 0x00504390; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) +{ + return 0x00504394; +} +static inline u32 gr_fe_pwr_mode_r(void) +{ + return 0x00404170; +} +static inline u32 gr_fe_pwr_mode_mode_auto_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) +{ + return 0x2; +} +static inline u32 gr_fe_pwr_mode_req_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_fe_pwr_mode_req_send_f(void) +{ + return 0x10; +} +static inline u32 gr_fe_pwr_mode_req_done_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) +{ + return 0x00418880; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) +{ + return 0x3 << 3; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) +{ + return 0x3 << 5; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) +{ + return 0x00418890; +} +static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) +{ + return 0x00418894; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) +{ + return 0x004188b0; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) +{ + return 0x004188b4; +} +static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) +{ + return 0x004188b8; +} +static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) +{ + return 0x004188ac; +} +static inline u32 gr_fe_gfxp_wfi_timeout_r(void) +{ + return 0x004041c0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) +{ + return 0x00419bd8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) +{ + return 0x7 << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) +{ + return 0x00419ba4; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) +{ + return 0x3 << 11; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) +{ + return 0x1000; +} +static inline u32 gr_gpcs_tc_debug0_r(void) +{ + return 0x00418708; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) +{ + return 0x1ff << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h new file mode 100644 index 00000000..02db6af6 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h @@ -0,0 +1,553 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ltc_gv11b_h_ +#define _hw_ltc_gv11b_h_ + +static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) +{ + return 0x00140518; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) +{ + return 0x0017e318; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) +{ + return 0x1 << 15; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) +{ + return 0x00140494; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) +{ + return (r >> 16) & 0x3; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) +{ + return 0x00000000; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) +{ + return 0x00000002; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) +{ + return 0x0017e26c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) +{ + return 0x2; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) +{ + return 0x4; +} +static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) +{ + return 0x0017e270; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) +{ + return 0x0017e274; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) +{ + return 0x0003ffff; +} +static inline u32 ltc_ltcs_ltss_cbc_base_r(void) +{ + return 0x0017e278; +} +static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) +{ + return (r >> 0) & 0x3ffffff; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) +{ + return 0x0017e27c; +} +static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) +{ + return 0x0017e000; +} +static inline u32 ltc_ltcs_ltss_cbc_param_r(void) +{ + return 0x0017e280; +} +static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) +{ + return (r >> 28) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) +{ + return 0x0017e3f4; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) +{ + return 0x0017e2ac; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) +{ + return 0x0017e338; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) +{ + return 0x0017e33c + i*4; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) +{ + return 0x0017e34c; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) +{ + return 32; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) +{ + return 0x0017e2b0; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_g_elpg_r(void) +{ + return 0x0017e214; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_r(void) +{ + return 0x00140214; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_r(void) +{ + return 0x00142214; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_intr_r(void) +{ + return 0x0017e20c; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) +{ + return 0x100; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) +{ + return 0x200; +} +static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) +{ + return 0x1 << 20; +} +static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) +{ + return 0x1 << 30; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 ltc_ltc0_lts0_intr_r(void) +{ + return 0x0014040c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) +{ + return 0x0014051c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) +{ + return 0xff << 16; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) +{ + return 0x0017e2a0; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) +{ + return 0x0017e2a4; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) +{ + return 0x10000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) +{ + return 0x001402a0; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) +{ + return 0x001402a4; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) +{ + return 0x001422a0; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) +{ + return 0x001422a4; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) +{ + return 0x0014058c; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h new file mode 100644 index 00000000..7fe4d158 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_mc_gv11b_h_ +#define _hw_mc_gv11b_h_ + +static inline u32 mc_boot_0_r(void) +{ + return 0x00000000; +} +static inline u32 mc_boot_0_architecture_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 mc_boot_0_implementation_v(u32 r) +{ + return (r >> 20) & 0xf; +} +static inline u32 mc_boot_0_major_revision_v(u32 r) +{ + return (r >> 4) & 0xf; +} +static inline u32 mc_boot_0_minor_revision_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 mc_intr_r(u32 i) +{ + return 0x00000100 + i*4; +} +static inline u32 mc_intr_pfifo_pending_f(void) +{ + return 0x100; +} +static inline u32 mc_intr_pgraph_pending_f(void) +{ + return 0x1000; +} +static inline u32 mc_intr_pmu_pending_f(void) +{ + return 0x1000000; +} +static inline u32 mc_intr_ltc_pending_f(void) +{ + return 0x2000000; +} +static inline u32 mc_intr_priv_ring_pending_f(void) +{ + return 0x40000000; +} +static inline u32 mc_intr_pbus_pending_f(void) +{ + return 0x10000000; +} +static inline u32 mc_intr_en_r(u32 i) +{ + return 0x00000140 + i*4; +} +static inline u32 mc_intr_en_set_r(u32 i) +{ + return 0x00000160 + i*4; +} +static inline u32 mc_intr_en_clear_r(u32 i) +{ + return 0x00000180 + i*4; +} +static inline u32 mc_enable_r(void) +{ + return 0x00000200; +} +static inline u32 mc_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_enable_l2_enabled_f(void) +{ + return 0x8; +} +static inline u32 mc_enable_pmedia_s(void) +{ + return 1; +} +static inline u32 mc_enable_pmedia_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 mc_enable_pmedia_m(void) +{ + return 0x1 << 4; +} +static inline u32 mc_enable_pmedia_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 mc_enable_priv_ring_enabled_f(void) +{ + return 0x20; +} +static inline u32 mc_enable_ce0_m(void) +{ + return 0x1 << 6; +} +static inline u32 mc_enable_pfifo_enabled_f(void) +{ + return 0x100; +} +static inline u32 mc_enable_pgraph_enabled_f(void) +{ + return 0x1000; +} +static inline u32 mc_enable_pwr_v(u32 r) +{ + return (r >> 13) & 0x1; +} +static inline u32 mc_enable_pwr_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 mc_enable_pwr_enabled_f(void) +{ + return 0x2000; +} +static inline u32 mc_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_enable_ce2_m(void) +{ + return 0x1 << 21; +} +static inline u32 mc_enable_ce2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 mc_enable_blg_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 mc_enable_perfmon_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 mc_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 mc_intr_ltc_r(void) +{ + return 0x000001c0; +} +static inline u32 mc_enable_pb_r(void) +{ + return 0x00000204; +} +static inline u32 mc_enable_pb_0_s(void) +{ + return 1; +} +static inline u32 mc_enable_pb_0_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 mc_enable_pb_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 mc_enable_pb_0_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 mc_enable_pb_0_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 mc_elpg_enable_r(void) +{ + return 0x0000020c; +} +static inline u32 mc_elpg_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_elpg_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_elpg_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h new file mode 100644 index 00000000..a921d502 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h @@ -0,0 +1,537 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pbdma_gv11b_h_ +#define _hw_pbdma_gv11b_h_ + +static inline u32 pbdma_gp_entry1_r(void) +{ + return 0x10000004; +} +static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pbdma_gp_entry1_length_f(u32 v) +{ + return (v & 0x1fffff) << 10; +} +static inline u32 pbdma_gp_entry1_length_v(u32 r) +{ + return (r >> 10) & 0x1fffff; +} +static inline u32 pbdma_gp_base_r(u32 i) +{ + return 0x00040048 + i*8192; +} +static inline u32 pbdma_gp_base__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 pbdma_gp_base_offset_f(u32 v) +{ + return (v & 0x1fffffff) << 3; +} +static inline u32 pbdma_gp_base_rsvd_s(void) +{ + return 3; +} +static inline u32 pbdma_gp_base_hi_r(u32 i) +{ + return 0x0004004c + i*8192; +} +static inline u32 pbdma_gp_base_hi_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 pbdma_gp_fetch_r(u32 i) +{ + return 0x00040050 + i*8192; +} +static inline u32 pbdma_gp_get_r(u32 i) +{ + return 0x00040014 + i*8192; +} +static inline u32 pbdma_gp_put_r(u32 i) +{ + return 0x00040000 + i*8192; +} +static inline u32 pbdma_pb_fetch_r(u32 i) +{ + return 0x00040054 + i*8192; +} +static inline u32 pbdma_pb_fetch_hi_r(u32 i) +{ + return 0x00040058 + i*8192; +} +static inline u32 pbdma_get_r(u32 i) +{ + return 0x00040018 + i*8192; +} +static inline u32 pbdma_get_hi_r(u32 i) +{ + return 0x0004001c + i*8192; +} +static inline u32 pbdma_put_r(u32 i) +{ + return 0x0004005c + i*8192; +} +static inline u32 pbdma_put_hi_r(u32 i) +{ + return 0x00040060 + i*8192; +} +static inline u32 pbdma_formats_r(u32 i) +{ + return 0x0004009c + i*8192; +} +static inline u32 pbdma_formats_gp_fermi0_f(void) +{ + return 0x0; +} +static inline u32 pbdma_formats_pb_fermi1_f(void) +{ + return 0x100; +} +static inline u32 pbdma_formats_mp_fermi0_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_r(u32 i) +{ + return 0x00040084 + i*8192; +} +static inline u32 pbdma_pb_header_priv_user_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_method_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_subchannel_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_level_main_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_pb_header_type_inc_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_pb_header_type_non_inc_f(void) +{ + return 0x60000000; +} +static inline u32 pbdma_hdr_shadow_r(u32 i) +{ + return 0x00040118 + i*8192; +} +static inline u32 pbdma_subdevice_r(u32 i) +{ + return 0x00040094 + i*8192; +} +static inline u32 pbdma_subdevice_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 pbdma_subdevice_status_active_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_subdevice_channel_dma_enable_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_method0_r(u32 i) +{ + return 0x000400c0 + i*8192; +} +static inline u32 pbdma_method0_fifo_size_v(void) +{ + return 0x00000004; +} +static inline u32 pbdma_method0_addr_f(u32 v) +{ + return (v & 0xfff) << 2; +} +static inline u32 pbdma_method0_addr_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 pbdma_method0_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 pbdma_method0_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_method0_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_method1_r(u32 i) +{ + return 0x000400c8 + i*8192; +} +static inline u32 pbdma_method2_r(u32 i) +{ + return 0x000400d0 + i*8192; +} +static inline u32 pbdma_method3_r(u32 i) +{ + return 0x000400d8 + i*8192; +} +static inline u32 pbdma_data0_r(u32 i) +{ + return 0x000400c4 + i*8192; +} +static inline u32 pbdma_target_r(u32 i) +{ + return 0x000400ac + i*8192; +} +static inline u32 pbdma_target_engine_sw_f(void) +{ + return 0x1f; +} +static inline u32 pbdma_acquire_r(u32 i) +{ + return 0x00040030 + i*8192; +} +static inline u32 pbdma_acquire_retry_man_2_f(void) +{ + return 0x2; +} +static inline u32 pbdma_acquire_retry_exp_2_f(void) +{ + return 0x100; +} +static inline u32 pbdma_acquire_timeout_exp_f(u32 v) +{ + return (v & 0xf) << 11; +} +static inline u32 pbdma_acquire_timeout_exp_max_v(void) +{ + return 0x0000000f; +} +static inline u32 pbdma_acquire_timeout_exp_max_f(void) +{ + return 0x7800; +} +static inline u32 pbdma_acquire_timeout_man_f(u32 v) +{ + return (v & 0xffff) << 15; +} +static inline u32 pbdma_acquire_timeout_man_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 pbdma_acquire_timeout_man_max_f(void) +{ + return 0x7fff8000; +} +static inline u32 pbdma_acquire_timeout_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_acquire_timeout_en_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_status_r(u32 i) +{ + return 0x00040100 + i*8192; +} +static inline u32 pbdma_channel_r(u32 i) +{ + return 0x00040120 + i*8192; +} +static inline u32 pbdma_signature_r(u32 i) +{ + return 0x00040010 + i*8192; +} +static inline u32 pbdma_signature_hw_valid_f(void) +{ + return 0xface; +} +static inline u32 pbdma_signature_sw_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_r(u32 i) +{ + return 0x00040008 + i*8192; +} +static inline u32 pbdma_userd_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_addr_f(u32 v) +{ + return (v & 0x7fffff) << 9; +} +static inline u32 pbdma_userd_hi_r(u32 i) +{ + return 0x0004000c + i*8192; +} +static inline u32 pbdma_userd_hi_addr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_hce_ctrl_r(u32 i) +{ + return 0x000400e4 + i*8192; +} +static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_r(u32 i) +{ + return 0x00040108 + i*8192; +} +static inline u32 pbdma_intr_0_memreq_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pbdma_intr_0_memreq_pending_f(void) +{ + return 0x1; +} +static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) +{ + return 0x2; +} +static inline u32 pbdma_intr_0_memack_extra_pending_f(void) +{ + return 0x4; +} +static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) +{ + return 0x8; +} +static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) +{ + return 0x10; +} +static inline u32 pbdma_intr_0_memflush_pending_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_memop_pending_f(void) +{ + return 0x40; +} +static inline u32 pbdma_intr_0_lbconnect_pending_f(void) +{ + return 0x80; +} +static inline u32 pbdma_intr_0_lbreq_pending_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) +{ + return 0x200; +} +static inline u32 pbdma_intr_0_lback_extra_pending_f(void) +{ + return 0x400; +} +static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) +{ + return 0x800; +} +static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_intr_0_gpfifo_pending_f(void) +{ + return 0x2000; +} +static inline u32 pbdma_intr_0_gpptr_pending_f(void) +{ + return 0x4000; +} +static inline u32 pbdma_intr_0_gpentry_pending_f(void) +{ + return 0x8000; +} +static inline u32 pbdma_intr_0_gpcrc_pending_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_intr_0_pbptr_pending_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_intr_0_pbentry_pending_f(void) +{ + return 0x40000; +} +static inline u32 pbdma_intr_0_pbcrc_pending_f(void) +{ + return 0x80000; +} +static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) +{ + return 0x100000; +} +static inline u32 pbdma_intr_0_method_pending_f(void) +{ + return 0x200000; +} +static inline u32 pbdma_intr_0_methodcrc_pending_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_intr_0_device_pending_f(void) +{ + return 0x800000; +} +static inline u32 pbdma_intr_0_semaphore_pending_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_intr_0_acquire_pending_f(void) +{ + return 0x4000000; +} +static inline u32 pbdma_intr_0_pri_pending_f(void) +{ + return 0x8000000; +} +static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_intr_0_pbseg_pending_f(void) +{ + return 0x40000000; +} +static inline u32 pbdma_intr_0_signature_pending_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_intr_en_0_r(u32 i) +{ + return 0x0004010c + i*8192; +} +static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_en_1_r(u32 i) +{ + return 0x0004014c + i*8192; +} +static inline u32 pbdma_intr_stall_r(u32 i) +{ + return 0x0004013c + i*8192; +} +static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_udma_nop_r(void) +{ + return 0x00000008; +} +static inline u32 pbdma_allowed_syncpoints_r(u32 i) +{ + return 0x000400e8 + i*8192; +} +static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) +{ + return (v & 0x7fff) << 16; +} +static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r) +{ + return (r >> 16) & 0x7fff; +} +static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) +{ + return (v & 0x1) << 15; +} +static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) +{ + return (v & 0x7fff) << 0; +} +static inline u32 pbdma_runlist_timeslice_r(u32 i) +{ + return 0x000400f8 + i*8192; +} +static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) +{ + return 0x80; +} +static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) +{ + return 0x3000; +} +static inline u32 pbdma_runlist_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h new file mode 100644 index 00000000..836c014b --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_perf_gv11b_h_ +#define _hw_perf_gv11b_h_ + +static inline u32 perf_pmasys_control_r(void) +{ + return 0x0024a000; +} +static inline u32 perf_pmasys_control_membuf_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) +{ + return 0x10; +} +static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) +{ + return 0x20; +} +static inline u32 perf_pmasys_mem_block_r(void) +{ + return 0x0024a070; +} +static inline u32 perf_pmasys_mem_block_base_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 perf_pmasys_mem_block_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 perf_pmasys_mem_block_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 perf_pmasys_mem_block_target_lfb_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_target_lfb_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 perf_pmasys_mem_block_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 perf_pmasys_mem_block_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 perf_pmasys_mem_block_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_mem_block_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_outbase_r(void) +{ + return 0x0024a074; +} +static inline u32 perf_pmasys_outbase_ptr_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_outbaseupper_r(void) +{ + return 0x0024a078; +} +static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 perf_pmasys_outsize_r(void) +{ + return 0x0024a07c; +} +static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_mem_bytes_r(void) +{ + return 0x0024a084; +} +static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_mem_bump_r(void) +{ + return 0x0024a088; +} +static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_enginestatus_r(void) +{ + return 0x0024a0a4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) +{ + return 0x10; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pri_ringmaster_gv11b.h new file mode 100644 index 00000000..835366c1 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_pri_ringmaster_gv11b.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringmaster_gv11b_h_ +#define _hw_pri_ringmaster_gv11b_h_ + +static inline u32 pri_ringmaster_command_r(void) +{ + return 0x0012004c; +} +static inline u32 pri_ringmaster_command_cmd_m(void) +{ + return 0x3f << 0; +} +static inline u32 pri_ringmaster_command_cmd_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) +{ + return 0x00000000; +} +static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) +{ + return 0x2; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) +{ + return 0x3; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_command_data_r(void) +{ + return 0x00120048; +} +static inline u32 pri_ringmaster_start_results_r(void) +{ + return 0x00120050; +} +static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) +{ + return 0x00000001; +} +static inline u32 pri_ringmaster_intr_status0_r(void) +{ + return 0x00120058; +} +static inline u32 pri_ringmaster_intr_status1_r(void) +{ + return 0x0012005c; +} +static inline u32 pri_ringmaster_global_ctl_r(void) +{ + return 0x00120060; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_enum_fbp_r(void) +{ + return 0x00120074; +} +static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_gpc_r(void) +{ + return 0x00120078; +} +static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_ltc_r(void) +{ + return 0x0012006c; +} +static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pri_ringstation_sys_gv11b.h new file mode 100644 index 00000000..e192bd13 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_sys_gv11b_h_ +#define _hw_pri_ringstation_sys_gv11b_h_ + +static inline u32 pri_ringstation_sys_master_config_r(u32 i) +{ + return 0x00122300 + i*4; +} +static inline u32 pri_ringstation_sys_decode_config_r(void) +{ + return 0x00122204; +} +static inline u32 pri_ringstation_sys_decode_config_ring_m(void) +{ + return 0x7 << 0; +} +static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) +{ + return 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h new file mode 100644 index 00000000..f107300e --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_proj_gv11b_h_ +#define _hw_proj_gv11b_h_ + +static inline u32 proj_gpc_base_v(void) +{ + return 0x00500000; +} +static inline u32 proj_gpc_shared_base_v(void) +{ + return 0x00418000; +} +static inline u32 proj_gpc_stride_v(void) +{ + return 0x00008000; +} +static inline u32 proj_ltc_stride_v(void) +{ + return 0x00002000; +} +static inline u32 proj_lts_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_ppc_in_gpc_base_v(void) +{ + return 0x00003000; +} +static inline u32 proj_ppc_in_gpc_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_rop_base_v(void) +{ + return 0x00410000; +} +static inline u32 proj_rop_shared_base_v(void) +{ + return 0x00408800; +} +static inline u32 proj_rop_stride_v(void) +{ + return 0x00000400; +} +static inline u32 proj_tpc_in_gpc_base_v(void) +{ + return 0x00004000; +} +static inline u32 proj_tpc_in_gpc_stride_v(void) +{ + return 0x00000800; +} +static inline u32 proj_tpc_in_gpc_shared_base_v(void) +{ + return 0x00001800; +} +static inline u32 proj_host_num_pbdma_v(void) +{ + return 0x0000000e; +} +static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) +{ + return 0x00000007; +} +static inline u32 proj_scal_litter_num_fbps_v(void) +{ + return 0x00000008; +} +static inline u32 proj_scal_litter_num_gpcs_v(void) +{ + return 0x00000008; +} +static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) +{ + return 0x00000003; +} +static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) +{ + return 0x00000003; +} +static inline u32 proj_scal_litter_num_zcull_banks_v(void) +{ + return 0x00000004; +} +static inline u32 proj_scal_max_gpcs_v(void) +{ + return 0x00000020; +} +static inline u32 proj_scal_max_tpc_per_gpc_v(void) +{ + return 0x00000008; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h new file mode 100644 index 00000000..bb8b5dea --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h @@ -0,0 +1,821 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pwr_gv11b_h_ +#define _hw_pwr_gv11b_h_ + +static inline u32 pwr_falcon_irqsset_r(void) +{ + return 0x0010a000; +} +static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqsclr_r(void) +{ + return 0x0010a004; +} +static inline u32 pwr_falcon_irqstat_r(void) +{ + return 0x0010a008; +} +static inline u32 pwr_falcon_irqstat_halt_true_f(void) +{ + return 0x10; +} +static inline u32 pwr_falcon_irqstat_exterr_true_f(void) +{ + return 0x20; +} +static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqmode_r(void) +{ + return 0x0010a00c; +} +static inline u32 pwr_falcon_irqmset_r(void) +{ + return 0x0010a010; +} +static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_r(void) +{ + return 0x0010a014; +} +static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmask_r(void) +{ + return 0x0010a018; +} +static inline u32 pwr_falcon_irqdest_r(void) +{ + return 0x0010a01c; +} +static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 pwr_falcon_curctx_r(void) +{ + return 0x0010a050; +} +static inline u32 pwr_falcon_nxtctx_r(void) +{ + return 0x0010a054; +} +static inline u32 pwr_falcon_mailbox0_r(void) +{ + return 0x0010a040; +} +static inline u32 pwr_falcon_mailbox1_r(void) +{ + return 0x0010a044; +} +static inline u32 pwr_falcon_itfen_r(void) +{ + return 0x0010a048; +} +static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1; +} +static inline u32 pwr_falcon_idlestate_r(void) +{ + return 0x0010a04c; +} +static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1) & 0x7fff; +} +static inline u32 pwr_falcon_os_r(void) +{ + return 0x0010a080; +} +static inline u32 pwr_falcon_engctl_r(void) +{ + return 0x0010a0a4; +} +static inline u32 pwr_falcon_cpuctl_r(void) +{ + return 0x0010a100; +} +static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1 << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1 << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_alias_r(void) +{ + return 0x0010a130; +} +static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_pmu_scpctl_stat_r(void) +{ + return 0x0010ac08; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) +{ + return 0x1 << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 pwr_falcon_imemc_r(u32 i) +{ + return 0x0010a180 + i*16; +} +static inline u32 pwr_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_imemd_r(u32 i) +{ + return 0x0010a184 + i*16; +} +static inline u32 pwr_falcon_imemt_r(u32 i) +{ + return 0x0010a188 + i*16; +} +static inline u32 pwr_falcon_sctl_r(void) +{ + return 0x0010a240; +} +static inline u32 pwr_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4; +} +static inline u32 pwr_falcon_bootvec_r(void) +{ + return 0x0010a104; +} +static inline u32 pwr_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_falcon_dmactl_r(void) +{ + return 0x0010a10c; +} +static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_falcon_hwcfg_r(void) +{ + return 0x0010a108; +} +static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9) & 0x1ff; +} +static inline u32 pwr_falcon_dmatrfbase_r(void) +{ + return 0x0010a110; +} +static inline u32 pwr_falcon_dmatrfbase1_r(void) +{ + return 0x0010a128; +} +static inline u32 pwr_falcon_dmatrfmoffs_r(void) +{ + return 0x0010a114; +} +static inline u32 pwr_falcon_dmatrfcmd_r(void) +{ + return 0x0010a118; +} +static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 pwr_falcon_dmatrffboffs_r(void) +{ + return 0x0010a11c; +} +static inline u32 pwr_falcon_exterraddr_r(void) +{ + return 0x0010a168; +} +static inline u32 pwr_falcon_exterrstat_r(void) +{ + return 0x0010a16c; +} +static inline u32 pwr_falcon_exterrstat_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 pwr_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 pwr_pmu_falcon_icd_cmd_r(void) +{ + return 0x0010a200; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 pwr_pmu_falcon_icd_rdata_r(void) +{ + return 0x0010a20c; +} +static inline u32 pwr_falcon_dmemc_r(u32 i) +{ + return 0x0010a1c0 + i*8; +} +static inline u32 pwr_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 pwr_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_dmemc_blk_m(void) +{ + return 0xff << 8; +} +static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_dmemd_r(u32 i) +{ + return 0x0010a1c4 + i*8; +} +static inline u32 pwr_pmu_new_instblk_r(void) +{ + return 0x0010a480; +} +static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 pwr_pmu_new_instblk_target_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_pmu_mutex_id_r(void) +{ + return 0x0010a488; +} +static inline u32 pwr_pmu_mutex_id_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_id_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) +{ + return 0x000000ff; +} +static inline u32 pwr_pmu_mutex_id_release_r(void) +{ + return 0x0010a48c; +} +static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_m(void) +{ + return 0xff << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_mutex_r(u32 i) +{ + return 0x0010a580 + i*4; +} +static inline u32 pwr_pmu_mutex__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 pwr_pmu_mutex_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_queue_head_r(u32 i) +{ + return 0x0010a4a0 + i*4; +} +static inline u32 pwr_pmu_queue_head__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_queue_head_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_head_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_queue_tail_r(u32 i) +{ + return 0x0010a4b0 + i*4; +} +static inline u32 pwr_pmu_queue_tail__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_queue_tail_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_tail_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_head_r(void) +{ + return 0x0010a4c8; +} +static inline u32 pwr_pmu_msgq_head_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_head_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_tail_r(void) +{ + return 0x0010a4cc; +} +static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_idle_mask_r(u32 i) +{ + return 0x0010a504 + i*16; +} +static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) +{ + return 0x1; +} +static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 pwr_pmu_idle_count_r(u32 i) +{ + return 0x0010a508 + i*16; +} +static inline u32 pwr_pmu_idle_count_value_f(u32 v) +{ + return (v & 0x7fffffff) << 0; +} +static inline u32 pwr_pmu_idle_count_value_v(u32 r) +{ + return (r >> 0) & 0x7fffffff; +} +static inline u32 pwr_pmu_idle_count_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pwr_pmu_idle_ctrl_r(u32 i) +{ + return 0x0010a50c + i*16; +} +static inline u32 pwr_pmu_idle_ctrl_value_m(void) +{ + return 0x3 << 0; +} +static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) +{ + return 0x2; +} +static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) +{ + return 0x3; +} +static inline u32 pwr_pmu_idle_ctrl_filter_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) +{ + return 0x0010a9f0 + i*8; +} +static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) +{ + return 0x0010a9f4 + i*8; +} +static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) +{ + return 0x0010aa30 + i*8; +} +static inline u32 pwr_pmu_debug_r(u32 i) +{ + return 0x0010a5c0 + i*4; +} +static inline u32 pwr_pmu_debug__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_mailbox_r(u32 i) +{ + return 0x0010a450 + i*4; +} +static inline u32 pwr_pmu_mailbox__size_1_v(void) +{ + return 0x0000000c; +} +static inline u32 pwr_pmu_bar0_addr_r(void) +{ + return 0x0010a7a0; +} +static inline u32 pwr_pmu_bar0_data_r(void) +{ + return 0x0010a7a4; +} +static inline u32 pwr_pmu_bar0_ctl_r(void) +{ + return 0x0010a7ac; +} +static inline u32 pwr_pmu_bar0_timeout_r(void) +{ + return 0x0010a7a8; +} +static inline u32 pwr_pmu_bar0_fecs_error_r(void) +{ + return 0x0010a988; +} +static inline u32 pwr_pmu_bar0_error_status_r(void) +{ + return 0x0010a7b0; +} +static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) +{ + return 0x0010a6c0 + i*4; +} +static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) +{ + return 0x0010a6e8 + i*4; +} +static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) +{ + return 0x0010a710 + i*4; +} +static inline u32 pwr_pmu_pg_intren_r(u32 i) +{ + return 0x0010a760 + i*4; +} +static inline u32 pwr_fbif_transcfg_r(u32 i) +{ + return 0x0010ae00 + i*4; +} +static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) +{ + return 0x1; +} +static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) +{ + return 0x2; +} +static inline u32 pwr_fbif_transcfg_mem_type_s(void) +{ + return 1; +} +static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h new file mode 100644 index 00000000..d60f3bd2 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ram_gv11b_h_ +#define _hw_ram_gv11b_h_ + +static inline u32 ram_in_ramfc_s(void) +{ + return 4096; +} +static inline u32 ram_in_ramfc_w(void) +{ + return 0; +} +static inline u32 ram_in_page_dir_base_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_page_dir_base_target_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_vol_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_vol_true_f(void) +{ + return 0x4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) +{ + return 0x10; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) +{ + return 0x20; +} +static inline u32 ram_in_big_page_size_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 ram_in_big_page_size_w(void) +{ + return 128; +} +static inline u32 ram_in_big_page_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 ram_in_big_page_size_64kb_f(void) +{ + return 0x800; +} +static inline u32 ram_in_page_dir_base_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_page_dir_base_lo_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_page_dir_base_hi_w(void) +{ + return 129; +} +static inline u32 ram_in_adr_limit_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_adr_limit_lo_w(void) +{ + return 130; +} +static inline u32 ram_in_adr_limit_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_adr_limit_hi_w(void) +{ + return 131; +} +static inline u32 ram_in_engine_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_cs_wfi_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_engine_cs_fg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_cs_fg_f(void) +{ + return 0x8; +} +static inline u32 ram_in_gr_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_gr_wfi_target_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_wfi_mode_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_wfi_mode_physical_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_gr_wfi_mode_physical_f(void) +{ + return 0x0; +} +static inline u32 ram_in_gr_wfi_mode_virtual_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_gr_wfi_mode_virtual_f(void) +{ + return 0x4; +} +static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_gr_wfi_ptr_lo_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_gr_wfi_ptr_hi_w(void) +{ + return 133; +} +static inline u32 ram_in_base_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_in_alloc_size_v(void) +{ + return 0x00001000; +} +static inline u32 ram_fc_size_val_v(void) +{ + return 0x00000200; +} +static inline u32 ram_fc_gp_put_w(void) +{ + return 0; +} +static inline u32 ram_fc_userd_w(void) +{ + return 2; +} +static inline u32 ram_fc_userd_hi_w(void) +{ + return 3; +} +static inline u32 ram_fc_signature_w(void) +{ + return 4; +} +static inline u32 ram_fc_gp_get_w(void) +{ + return 5; +} +static inline u32 ram_fc_pb_get_w(void) +{ + return 6; +} +static inline u32 ram_fc_pb_get_hi_w(void) +{ + return 7; +} +static inline u32 ram_fc_pb_top_level_get_w(void) +{ + return 8; +} +static inline u32 ram_fc_pb_top_level_get_hi_w(void) +{ + return 9; +} +static inline u32 ram_fc_acquire_w(void) +{ + return 12; +} +static inline u32 ram_fc_semaphorea_w(void) +{ + return 14; +} +static inline u32 ram_fc_semaphoreb_w(void) +{ + return 15; +} +static inline u32 ram_fc_semaphorec_w(void) +{ + return 16; +} +static inline u32 ram_fc_semaphored_w(void) +{ + return 17; +} +static inline u32 ram_fc_gp_base_w(void) +{ + return 18; +} +static inline u32 ram_fc_gp_base_hi_w(void) +{ + return 19; +} +static inline u32 ram_fc_gp_fetch_w(void) +{ + return 20; +} +static inline u32 ram_fc_pb_fetch_w(void) +{ + return 21; +} +static inline u32 ram_fc_pb_fetch_hi_w(void) +{ + return 22; +} +static inline u32 ram_fc_pb_put_w(void) +{ + return 23; +} +static inline u32 ram_fc_pb_put_hi_w(void) +{ + return 24; +} +static inline u32 ram_fc_pb_header_w(void) +{ + return 33; +} +static inline u32 ram_fc_pb_count_w(void) +{ + return 34; +} +static inline u32 ram_fc_subdevice_w(void) +{ + return 37; +} +static inline u32 ram_fc_formats_w(void) +{ + return 39; +} +static inline u32 ram_fc_allowed_syncpoints_w(void) +{ + return 58; +} +static inline u32 ram_fc_target_w(void) +{ + return 43; +} +static inline u32 ram_fc_hce_ctrl_w(void) +{ + return 57; +} +static inline u32 ram_fc_chid_w(void) +{ + return 58; +} +static inline u32 ram_fc_chid_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_fc_chid_id_w(void) +{ + return 0; +} +static inline u32 ram_fc_runlist_timeslice_w(void) +{ + return 62; +} +static inline u32 ram_userd_base_shift_v(void) +{ + return 0x00000009; +} +static inline u32 ram_userd_chan_size_v(void) +{ + return 0x00000200; +} +static inline u32 ram_userd_put_w(void) +{ + return 16; +} +static inline u32 ram_userd_get_w(void) +{ + return 17; +} +static inline u32 ram_userd_ref_w(void) +{ + return 18; +} +static inline u32 ram_userd_put_hi_w(void) +{ + return 19; +} +static inline u32 ram_userd_ref_threshold_w(void) +{ + return 20; +} +static inline u32 ram_userd_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_userd_get_hi_w(void) +{ + return 24; +} +static inline u32 ram_userd_gp_get_w(void) +{ + return 34; +} +static inline u32 ram_userd_gp_put_w(void) +{ + return 35; +} +static inline u32 ram_userd_gp_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_gp_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_rl_entry_size_v(void) +{ + return 0x00000010; +} +static inline u32 ram_rl_entry_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_type_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 ram_rl_entry_type_tsg_f(void) +{ + return 0x1; +} +static inline u32 ram_rl_entry_tsg_length_f(u32 v) +{ + return (v & 0xff) << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h new file mode 100644 index 00000000..ee3dbc0e --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_therm_gv11b_h_ +#define _hw_therm_gv11b_h_ + +static inline u32 therm_use_a_r(void) +{ + return 0x00020798; +} +static inline u32 therm_weight_1_r(void) +{ + return 0x00020024; +} +static inline u32 therm_config1_r(void) +{ + return 0x00020050; +} +static inline u32 therm_config2_r(void) +{ + return 0x00020130; +} +static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 therm_config2_grad_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 therm_gate_ctrl_r(u32 i) +{ + return 0x00020200 + i*4; +} +static inline u32 therm_gate_ctrl_eng_clk_m(void) +{ + return 0x3 << 0; +} +static inline u32 therm_gate_ctrl_eng_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) +{ + return 0x1; +} +static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) +{ + return 0x2; +} +static inline u32 therm_gate_ctrl_blk_clk_m(void) +{ + return 0x3 << 2; +} +static inline u32 therm_gate_ctrl_blk_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) +{ + return 0x4; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) +{ + return 0x1f << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) +{ + return (v & 0x7) << 13; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) +{ + return 0x7 << 13; +} +static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_before_m(void) +{ + return 0xf << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 therm_gate_ctrl_eng_delay_after_m(void) +{ + return 0xf << 20; +} +static inline u32 therm_fecs_idle_filter_r(void) +{ + return 0x00020288; +} +static inline u32 therm_fecs_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_hubmmu_idle_filter_r(void) +{ + return 0x0002028c; +} +static inline u32 therm_hubmmu_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_clk_slowdown_r(u32 i) +{ + return 0x00020160 + i*4; +} +static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) +{ + return (v & 0x3f) << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_m(void) +{ + return 0x3f << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) +{ + return (r >> 16) & 0x3f; +} +static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) +{ + return 0x0; +} +static inline u32 therm_grad_stepping_table_r(u32 i) +{ + return 0x000202c8 + i*4; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) +{ + return 0x3f << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) +{ + return 0x2; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) +{ + return 0x6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) +{ + return 0xe; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) +{ + return 0x3f << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) +{ + return (v & 0x3f) << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) +{ + return 0x3f << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) +{ + return (v & 0x3f) << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) +{ + return 0x3f << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) +{ + return 0x3f << 24; +} +static inline u32 therm_grad_stepping0_r(void) +{ + return 0x000202c0; +} +static inline u32 therm_grad_stepping0_feature_s(void) +{ + return 1; +} +static inline u32 therm_grad_stepping0_feature_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 therm_grad_stepping0_feature_m(void) +{ + return 0x1 << 0; +} +static inline u32 therm_grad_stepping0_feature_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 therm_grad_stepping0_feature_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping1_r(void) +{ + return 0x000202c4; +} +static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 therm_clk_timing_r(u32 i) +{ + return 0x000203c0 + i*4; +} +static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_m(void) +{ + return 0x1 << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) +{ + return 0x10000; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_timer_gv11b.h new file mode 100644 index 00000000..7d5750c2 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_timer_gv11b.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_timer_gv11b_h_ +#define _hw_timer_gv11b_h_ + +static inline u32 timer_pri_timeout_r(void) +{ + return 0x00009080; +} +static inline u32 timer_pri_timeout_period_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 timer_pri_timeout_period_m(void) +{ + return 0xffffff << 0; +} +static inline u32 timer_pri_timeout_period_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 timer_pri_timeout_en_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 timer_pri_timeout_en_m(void) +{ + return 0x1 << 31; +} +static inline u32 timer_pri_timeout_en_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 timer_pri_timeout_en_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 timer_pri_timeout_en_en_disabled_f(void) +{ + return 0x0; +} +static inline u32 timer_pri_timeout_save_0_r(void) +{ + return 0x00009084; +} +static inline u32 timer_pri_timeout_save_1_r(void) +{ + return 0x00009088; +} +static inline u32 timer_pri_timeout_fecs_errcode_r(void) +{ + return 0x0000908c; +} +static inline u32 timer_time_0_r(void) +{ + return 0x00009400; +} +static inline u32 timer_time_1_r(void) +{ + return 0x00009410; +} +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h new file mode 100644 index 00000000..ef81ce9d --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_top_gv11b_h_ +#define _hw_top_gv11b_h_ + +static inline u32 top_num_gpcs_r(void) +{ + return 0x00022430; +} +static inline u32 top_num_gpcs_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_tpc_per_gpc_r(void) +{ + return 0x00022434; +} +static inline u32 top_tpc_per_gpc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_fbps_r(void) +{ + return 0x00022438; +} +static inline u32 top_num_fbps_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_ltc_per_fbp_r(void) +{ + return 0x00022450; +} +static inline u32 top_ltc_per_fbp_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_slices_per_ltc_r(void) +{ + return 0x0002245c; +} +static inline u32 top_slices_per_ltc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_ltcs_r(void) +{ + return 0x00022454; +} +static inline u32 top_device_info_r(u32 i) +{ + return 0x00022700 + i*4; +} +static inline u32 top_device_info__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 top_device_info_chain_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 top_device_info_chain_enable_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_engine_enum_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_runlist_enum_v(u32 r) +{ + return (r >> 21) & 0xf; +} +static inline u32 top_device_info_intr_enum_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 top_device_info_reset_enum_v(u32 r) +{ + return (r >> 9) & 0x1f; +} +static inline u32 top_device_info_type_enum_v(u32 r) +{ + return (r >> 2) & 0x1fffffff; +} +static inline u32 top_device_info_type_enum_graphics_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_type_enum_graphics_f(void) +{ + return 0x0; +} +static inline u32 top_device_info_type_enum_copy0_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_type_enum_copy0_f(void) +{ + return 0x4; +} +static inline u32 top_device_info_entry_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 top_device_info_entry_not_valid_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_entry_enum_v(void) +{ + return 0x00000002; +} +#endif -- cgit v1.2.2 From 3f26f6955fc6736384e1d56f9ddff2baaa2102a0 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 6 Apr 2016 18:01:17 -0700 Subject: include: uapi: nvgpu: add gv11b header Add gv11b header to export gv11b arch info. Bug 1735757 Change-Id: I66551eb6bd46652c2f1af3fe512060f5b7febef2 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1121508 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- include/uapi/linux/nvgpu-t19x.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/uapi/linux/nvgpu-t19x.h diff --git a/include/uapi/linux/nvgpu-t19x.h b/include/uapi/linux/nvgpu-t19x.h new file mode 100644 index 00000000..6a10fb77 --- /dev/null +++ b/include/uapi/linux/nvgpu-t19x.h @@ -0,0 +1,30 @@ +/* + * NVGPU Public Interface Header + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* This file is meant to extend nvgpu.h, not replace it + * as such, be sure that nvgpu.h is actually the file performing the + * inclusion, to the extent that's possible. + */ +#ifndef _UAPI__LINUX_NVGPU_IOCTL_H +# error "This file is to be included within nvgpu.h only." +#endif + +#ifndef _UAPI__LINUX_NVGPU_T19X_IOCTL_H_ +#define _UAPI__LINUX_NVGPU_T19X_IOCTL_H_ + +#define NVGPU_GPU_ARCH_GV110 0x00000150 +#define NVGPU_GPU_IMPL_GV11B 0x0000000B + +#endif /* _UAPI__LINUX_NVGPU_T19X_IOCTL_H_ */ -- cgit v1.2.2 From 55a5c57bc1fd532cc6d041fdfb70d90286894b35 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 7 Apr 2016 16:57:18 -0700 Subject: gpu: nvgpu: gv11b: added initial source code Bug 1735757 Change-Id: Iea7488551a437afa0dfc005c87ad1b9ab9673b6c Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1122123 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/Makefile | 8 ++ drivers/gpu/nvgpu/gr_t19x.h | 20 ++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 31 +++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 30 +++++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 45 ++++++++ drivers/gpu/nvgpu/gv11b/hal_gv11b.h | 21 ++++ drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 26 +++++ drivers/gpu/nvgpu/gv11b/mc_gv11b.h | 19 ++++ drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 149 +++++++++++++++++++++++++ drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h | 32 ++++++ 10 files changed, 381 insertions(+) create mode 100644 drivers/gpu/nvgpu/Makefile create mode 100644 drivers/gpu/nvgpu/gr_t19x.h create mode 100644 drivers/gpu/nvgpu/gv11b/gr_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/gr_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hal_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/hal_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/mc_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/mc_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c create mode 100644 drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile new file mode 100644 index 00000000..d70a2787 --- /dev/null +++ b/drivers/gpu/nvgpu/Makefile @@ -0,0 +1,8 @@ +nvgpu-t19x := ../../../../kernel-nvgpu-t19x/drivers/gpu/nvgpu + +nvgpu-y += \ + $(nvgpu-t19x)/gv11b/mc_gv11b.o \ + $(nvgpu-t19x)/gv11b/hal_gv11b.o \ + $(nvgpu-t19x)/gv11b/gr_gv11b.o + +nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o diff --git a/drivers/gpu/nvgpu/gr_t19x.h b/drivers/gpu/nvgpu/gr_t19x.h new file mode 100644 index 00000000..a4506f1c --- /dev/null +++ b/drivers/gpu/nvgpu/gr_t19x.h @@ -0,0 +1,20 @@ +/* + * NVIDIA T19x GR + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _NVGPU_GR_T19X_H_ +#define _NVGPU_GR_T19X_H_ + +#include "gv11b/gr_gv11b.h" + +#endif diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c new file mode 100644 index 00000000..d775aae8 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -0,0 +1,31 @@ +/* + * GV11B GPU GR + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ +#include +#include + +#include "gk20a/gr_gk20a.h" +#include "gk20a/semaphore_gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" + +#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ +#include "gp10b/gr_gp10b.h" +#include "gv11b/gr_gv11b.h" + +void gv11b_init_gr(struct gpu_ops *gops) +{ + gp10b_init_gr(gops); +} diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h new file mode 100644 index 00000000..c8912f91 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -0,0 +1,30 @@ +/* + * GV11B GPU GR + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_GR_GV11B_H_ +#define _NVGPU_GR_GV11B_H_ + +struct gpu_ops; + +enum { + VOLTA_CHANNEL_GPFIFO_A = 0xC36F, + VOLTA_A = 0xC397, + VOLTA_COMPUTE_A = 0xC3C0, + VOLTA_DMA_COPY_A = 0xC3B5, +}; + +void gv11b_init_gr(struct gpu_ops *ops); + +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c new file mode 100644 index 00000000..0debe7ce --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -0,0 +1,45 @@ +/* + * GV11B Tegra HAL interface + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include + +#include "gk20a/gk20a.h" + +#include "gv11b/gr_gv11b.h" +#include "gv11b/mc_gv11b.h" + +#include "gm20b/gr_gm20b.h" + +int gv11b_init_hal(struct gk20a *g) +{ + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + + gv11b_init_mc(gops); + gv11b_init_gr(gops); + gops->name = "gv11b"; + + c->twod_class = FERMI_TWOD_A; + c->threed_class = VOLTA_A; + c->compute_class = VOLTA_COMPUTE_A; + c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = VOLTA_DMA_COPY_A; + + return 0; +} diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.h b/drivers/gpu/nvgpu/gv11b/hal_gv11b.h new file mode 100644 index 00000000..7acbf03b --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.h @@ -0,0 +1,21 @@ +/* + * GV11B Tegra HAL interface + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_HAL_GV11B_H +#define _NVGPU_HAL_GV11B_H +struct gk20a; + +int gv11b_init_hal(struct gk20a *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c new file mode 100644 index 00000000..bc0aee2e --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -0,0 +1,26 @@ +/* + * GV11B master + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "gp10b/mc_gp10b.h" +#include "gv11b/mc_gv11b.h" +#include "hw_mc_gv11b.h" + +void gv11b_init_mc(struct gpu_ops *gops) +{ + gp10b_init_mc(gops); +} diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/mc_gv11b.h new file mode 100644 index 00000000..6cb2cde0 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef MC_GV11B_H +#define MC_GV11B_H +struct gk20a; + +void gv11b_init_mc(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c new file mode 100644 index 00000000..322bebc8 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -0,0 +1,149 @@ +/* + * GV11B Tegra Platform Interface + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gk20a/platform_gk20a.h" +#include "gk20a/gk20a.h" +#include "platform_tegra.h" +#include "gr_gv11b.h" +#include "hw_gr_gv11b.h" + +/* + * gv11b_tegra_get_clocks() + * + * This function finds clocks in tegra platform and populates + * the clock information to gv11b platform data. + */ + +static int gv11b_tegra_get_clocks(struct device *dev) +{ + /* TODO */ + return 0; +} + +static int gv11b_tegra_probe(struct device *dev) +{ + struct gk20a_platform *platform = dev_get_drvdata(dev); + struct device_node *np = dev->of_node; + struct device_node *host1x_node; + struct platform_device *host1x_pdev; + const __be32 *host1x_ptr; + + host1x_ptr = of_get_property(np, "nvidia,host1x", NULL); + if (!host1x_ptr) { + gk20a_err(dev, "host1x device not available"); + return -ENOSYS; + } + + host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr)); + host1x_pdev = of_find_device_by_node(host1x_node); + if (!host1x_pdev) { + gk20a_err(dev, "host1x device not available"); + return -ENOSYS; + } + + platform->g->host1x_dev = host1x_pdev; + platform->bypass_smmu = !device_is_iommuable(dev); + platform->disable_bigpage = platform->bypass_smmu; + + platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close + = false; + platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close + = false; + + platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false; + platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false; + + + gv11b_tegra_get_clocks(dev); + + return 0; +} + +static int gv11b_tegra_late_probe(struct device *dev) +{ + /* Make gk20a power domain a subdomain of host1x */ + nvhost_register_client_domain(dev_to_genpd(dev)); + return 0; +} + +static int gv11b_tegra_remove(struct device *dev) +{ + /* remove gk20a power subdomain from host1x */ + nvhost_unregister_client_domain(dev_to_genpd(dev)); + + return 0; + +} + +static bool gv11b_tegra_is_railgated(struct device *dev) +{ + bool ret = false; + + return ret; +} + +static int gv11b_tegra_railgate(struct device *dev) +{ + return 0; +} + +static int gv11b_tegra_unrailgate(struct device *dev) +{ + int ret = 0; + return ret; +} + +static int gv11b_tegra_suspend(struct device *dev) +{ + return 0; +} + +struct gk20a_platform t19x_gpu_tegra_platform = { + .has_syncpoints = false, + + /* power management configuration */ + + /* ptimer src frequency in hz*/ + .ptimer_src_freq = 31250000, + + .probe = gv11b_tegra_probe, + .late_probe = gv11b_tegra_late_probe, + .remove = gv11b_tegra_remove, + + /* power management callbacks */ + .suspend = gv11b_tegra_suspend, + .railgate = gv11b_tegra_railgate, + .unrailgate = gv11b_tegra_unrailgate, + .is_railgated = gv11b_tegra_is_railgated, + + .busy = gk20a_tegra_busy, + .idle = gk20a_tegra_idle, + + .dump_platform_dependencies = gk20a_tegra_debug_dump, + + .default_big_page_size = SZ_64K, + +}; diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h new file mode 100644 index 00000000..d376f3dd --- /dev/null +++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h @@ -0,0 +1,32 @@ +/* + * NVIDIA GPU ID functions, definitions. + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _NVGPU_GPUID_T19X_H_ +#define _NVGPU_GPUID_T19X_H_ + +#define NVGPU_GPUID_GV11B \ + GK20A_GPUID(NVGPU_GPU_ARCH_GV110, NVGPU_GPU_IMPL_GV11B) + +#define NVGPU_COMPAT_TEGRA_GV11B "nvidia,g11b" +#define NVGPU_COMPAT_GENERIC_GV11B "nvidia,generic-gv11b" + +#define TEGRA_19x_GPUID NVGPU_GPUID_GV11B +#define TEGRA_19x_GPUID_HAL gv11b_init_hal +#define TEGRA_19x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GV11B +#define TEGRA_19x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GV11B +struct gpu_ops; +extern int gv11b_init_hal(struct gk20a *); +extern struct gk20a_platform t19x_gpu_tegra_platform; + +#endif -- cgit v1.2.2 From 07cd80ab096346d64f93b051e80ba43c090deb09 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 13 Apr 2016 17:38:33 -0700 Subject: gpu: nvgpu: gv11b: header update related to sm Updated priv registers related to sm re-organization Bug 1735757 Change-Id: I5656f87c17fb3d95a162f06d96d29dab25d648f8 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1126960 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 12 ++ drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 372 +++++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h | 4 + 3 files changed, 384 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h index 99cc3442..b7aa46bc 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h @@ -1074,6 +1074,14 @@ static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) { return 0x000000dd; } +static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) +{ + return 0x000000de; +} +static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) +{ + return 0x000000cc; +} static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) { return 0x000000df; @@ -1134,6 +1142,10 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) { return 0x000000ec; } +static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void) +{ + return 0x000000cd; +} static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) { return 0x000000ed; diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index 3772d9ab..37556fb9 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -706,6 +706,10 @@ static inline u32 gr_fe_object_table_nvclass_v(u32 r) { return (r >> 0) & 0xffff; } +static inline u32 gr_fe_tpc_fs_r(u32 i) +{ + return 0x0040a200 + i*4; +} static inline u32 gr_pri_mme_shadow_raw_index_r(void) { return 0x00404488; @@ -1518,6 +1522,10 @@ static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) { return 0x00502420; } +static inline u32 gr_rstr2d_gpc_map_r(u32 i) +{ + return 0x0040780c + i*4; +} static inline u32 gr_rstr2d_map_table_cfg_r(void) { return 0x004078bc; @@ -2302,6 +2310,14 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) { return 0x00504608; } +static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_gpc0_tpc0_sm_arch_r(void) { return 0x00504330; @@ -2810,6 +2826,34 @@ static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) { return 0x80000000; } +static inline u32 gr_crstr_gpc_map_r(u32 i) +{ + return 0x00418b08 + i*4; +} +static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) +{ + return (v & 0x1f) << 5; +} +static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) +{ + return (v & 0x1f) << 10; +} +static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) +{ + return (v & 0x1f) << 20; +} +static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) +{ + return (v & 0x1f) << 25; +} static inline u32 gr_crstr_map_table_cfg_r(void) { return 0x00418bb8; @@ -2822,6 +2866,42 @@ static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) { return (v & 0xff) << 8; } +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) +{ + return 0x00418980 + i*4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) +{ + return (v & 0x7) << 28; +} static inline u32 gr_gpcs_gpm_pd_cfg_r(void) { return 0x00418c6c; @@ -2902,6 +2982,90 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { return 0x10000000; } +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_r(void) +{ + return 0x00419fa8; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_stack_error_report_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_api_stack_error_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_pc_wrap_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_pc_overflow_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +{ + return 0x200; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +{ + return 0x800; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_oor_reg_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_oor_addr_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_mmu_fault_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_stack_overflow_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_r(void) +{ + return 0x00419fac; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_bpt_int_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_bpt_pause_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_single_step_complete_report_f(void) +{ + return 0x40; +} static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) { return 0x00419d0c; @@ -2966,13 +3130,117 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { return 0x00000001; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) +static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_r(void) { - return 0x00419e14; + return 0x00504784; } -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) +static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_m(void) { - return 0x00504614; + return 0x1 << 0; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_off_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_sm1_warp_valid_mask_r(void) +{ + return 0x00504788; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_bpt_pause_mask_r(void) +{ + return 0x00504790; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_bpt_trap_mask_r(void) +{ + return 0x00504798; +} +static inline u32 gr_gpcs_tpcs_sm1_dbgr_bpt_pause_mask_r(void) +{ + return 0x00419f90; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_r(void) +{ + return 0x00504780; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_sm_in_trap_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_locked_down_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_locked_down_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_r(void) +{ + return 0x00419fb4; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_r(void) +{ + return 0x005047b4; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; } static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) { @@ -2990,6 +3258,38 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) { return 0x100; } +static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_r(void) +{ + return 0x005047b0; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_none_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_valid_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_m(void) +{ + return 0x7 << 25; +} +static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) +{ + return 0x005047b8; +} static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) { return 0x005043a0; @@ -3030,6 +3330,10 @@ static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) { return 0x4; } +static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) +{ + return 0x0041bf00 + i*4; +} static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) { return 0x0041bfd0; @@ -3166,6 +3470,14 @@ static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) { return 0x00504394; } +static inline u32 gr_pri_gpc0_tpc0_sm1_dsm_perf_counter_status_s1_r(void) +{ + return 0x005047c4; +} +static inline u32 gr_pri_gpc0_tpc0_sm1_dsm_perf_counter_status1_r(void) +{ + return 0x005047d0; +} static inline u32 gr_fe_pwr_mode_r(void) { return 0x00404170; @@ -3262,6 +3574,58 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) { return 0x004188ac; } +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) +{ + return 0x00419f84; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} static inline u32 gr_fe_gfxp_wfi_timeout_r(void) { return 0x004041c0; diff --git a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h index 7fe4d158..98bec43a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h @@ -78,6 +78,10 @@ static inline u32 mc_intr_pfifo_pending_f(void) { return 0x100; } +static inline u32 mc_intr_hub_pending_f(void) +{ + return 0x200; +} static inline u32 mc_intr_pgraph_pending_f(void) { return 0x1000; -- cgit v1.2.2 From c84ddceda648d6e47828115654ca7745010ec09f Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 14 Apr 2016 13:01:58 -0700 Subject: gpu: nvgpu: gv11b: sm priv reg related changes Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 12 +- drivers/gpu/nvgpu/gv11b/ce2_gv11b.c | 28 + drivers/gpu/nvgpu/gv11b/ce2_gv11b.h | 27 + drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 28 + drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 21 + drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c | 30 + drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h | 23 + drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 28 + drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 20 + drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c | 72 ++ drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h | 28 + drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 1743 +++++++++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/gv11b.c | 25 + drivers/gpu/nvgpu/gv11b/gv11b.h | 26 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 21 + drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 6 +- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 26 + drivers/gpu/nvgpu/gv11b/ltc_gv11b.h | 19 + drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 25 + drivers/gpu/nvgpu/gv11b/mm_gv11b.h | 21 + drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 27 + drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 21 + drivers/gpu/nvgpu/gv11b/therm_gv11b.c | 25 + drivers/gpu/nvgpu/gv11b/therm_gv11b.h | 19 + 24 files changed, 2315 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv11b/ce2_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/ce2_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/fb_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/fb_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/fifo_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/fifo_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/ltc_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/ltc_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/mm_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/mm_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/pmu_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/pmu_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/therm_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/therm_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index d70a2787..9ff7b81e 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -1,8 +1,18 @@ nvgpu-t19x := ../../../../kernel-nvgpu-t19x/drivers/gpu/nvgpu nvgpu-y += \ + $(nvgpu-t19x)/gv11b/gv11b.o \ $(nvgpu-t19x)/gv11b/mc_gv11b.o \ + $(nvgpu-t19x)/gv11b/ltc_gv11b.o \ $(nvgpu-t19x)/gv11b/hal_gv11b.o \ - $(nvgpu-t19x)/gv11b/gr_gv11b.o + $(nvgpu-t19x)/gv11b/gr_gv11b.o \ + $(nvgpu-t19x)/gv11b/fecs_trace_gv11b.o \ + $(nvgpu-t19x)/gv11b/fb_gv11b.o \ + $(nvgpu-t19x)/gv11b/fifo_gv11b.o \ + $(nvgpu-t19x)/gv11b/mm_gv11b.o \ + $(nvgpu-t19x)/gv11b/ce2_gv11b.o \ + $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \ + $(nvgpu-t19x)/gv11b/pmu_gv11b.o \ + $(nvgpu-t19x)/gv11b/therm_gv11b.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o diff --git a/drivers/gpu/nvgpu/gv11b/ce2_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce2_gv11b.c new file mode 100644 index 00000000..d4ba4003 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/ce2_gv11b.c @@ -0,0 +1,28 @@ +/* + * GV11B Graphics Copy Engine (gr host) + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ +#include "hw_ce2_gv11b.h" +#include "gp10b/ce2_gp10b.h" +#include "ce2_gv11b.h" + +void gv11b_init_ce2(struct gpu_ops *gops) +{ + gp10b_init_ce2(gops); +} diff --git a/drivers/gpu/nvgpu/gv11b/ce2_gv11b.h b/drivers/gpu/nvgpu/gv11b/ce2_gv11b.h new file mode 100644 index 00000000..a7b2f99a --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/ce2_gv11b.h @@ -0,0 +1,27 @@ +/* + * + * GV11B graphics copy engine + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __CE2_GV11B_H__ +#define __CE2_GV11B_H__ + +struct gpu_ops; + +void gv11b_init_ce2(struct gpu_ops *gops); + +#endif /*__CE2_GV11B_H__*/ diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c new file mode 100644 index 00000000..097bc21d --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -0,0 +1,28 @@ +/* + * GV11B FB + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "gp10b/fb_gp10b.h" +#include "gv11b/fb_gv11b.h" +#include "gk20a/kind_gk20a.h" + +#include "hw_gmmu_gv11b.h" + +void gv11b_init_fb(struct gpu_ops *gops) +{ + gp10b_init_fb(gops); +} diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h new file mode 100644 index 00000000..ab688aba --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -0,0 +1,21 @@ +/* + * GV11B FB + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_GV11B_FB +#define _NVGPU_GV11B_FB +struct gpu_ops; + +void gv11b_init_fb(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c b/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c new file mode 100644 index 00000000..f3f8b797 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c @@ -0,0 +1,30 @@ +/* + * GV11B GPU FECS traces + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gp10b/fecs_trace_gp10b.h" +#include "gv11b/fecs_trace_gv11b.h" + +#ifdef CONFIG_GK20A_CTXSW_TRACE +int gv11b_init_fecs_trace_ops(struct gpu_ops *ops) +{ + gp10b_init_fecs_trace_ops(ops); + return 0; +} +#else +int gv11b_init_fecs_trace_ops(struct gpu_ops *ops) +{ + return 0; +} +#endif /* CONFIG_GK20A_CTXSW_TRACE */ diff --git a/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h b/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h new file mode 100644 index 00000000..607d715b --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h @@ -0,0 +1,23 @@ +/* + * GV11B GPU FECS traces + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_FECS_TRACE_GV11B_H_ +#define _NVGPU_FECS_TRACE_GV11B_H_ + +struct gpu_ops; + +int gv11b_init_fecs_trace_ops(struct gpu_ops *); + +#endif diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c new file mode 100644 index 00000000..af5f094d --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -0,0 +1,28 @@ +/* + * GV11B fifo + * + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include "gk20a/gk20a.h" +#include "gp10b/fifo_gp10b.h" +#include "hw_pbdma_gv11b.h" +#include "fifo_gv11b.h" +#include "hw_fifo_gv11b.h" + +void gv11b_init_fifo(struct gpu_ops *gops) +{ + gp10b_init_fifo(gops); +} diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h new file mode 100644 index 00000000..5b95ad9e --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -0,0 +1,20 @@ +/* + * GV11B Fifo + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef FIFO_GV11B_H +#define FIFO_GV11B_H +struct gpu_ops; +void gv11b_init_fifo(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c new file mode 100644 index 00000000..3fb0fa23 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c @@ -0,0 +1,72 @@ +/* + * + * GV11B Graphics Context + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gk20a/gk20a.h" +#include "gr_ctx_gv11b.h" + +static int gr_gv11b_get_netlist_name(int index, char *name) +{ + switch (index) { +#ifdef GV11B_NETLIST_IMAGE_FW_NAME + case NETLIST_FINAL: + sprintf(name, GV11B_NETLIST_IMAGE_FW_NAME); + return 0; +#endif +#ifdef GK20A_NETLIST_IMAGE_A + case NETLIST_SLOT_A: + sprintf(name, GK20A_NETLIST_IMAGE_A); + return 0; +#endif +#ifdef GK20A_NETLIST_IMAGE_B + case NETLIST_SLOT_B: + sprintf(name, GK20A_NETLIST_IMAGE_B); + return 0; +#endif +#ifdef GK20A_NETLIST_IMAGE_C + case NETLIST_SLOT_C: + sprintf(name, GK20A_NETLIST_IMAGE_C); + return 0; +#endif +#ifdef GK20A_NETLIST_IMAGE_D + case NETLIST_SLOT_D: + sprintf(name, GK20A_NETLIST_IMAGE_D); + return 0; +#endif + default: + return -1; + } + + return -1; +} + +static bool gr_gv11b_is_firmware_defined(void) +{ +#ifdef GV11B_NETLIST_IMAGE_FW_NAME + return true; +#else + return false; +#endif +} + +void gv11b_init_gr_ctx(struct gpu_ops *gops) { + gops->gr_ctx.get_netlist_name = gr_gv11b_get_netlist_name; + gops->gr_ctx.is_fw_defined = gr_gv11b_is_firmware_defined; + gops->gr_ctx.use_dma_for_fw_bootstrap = false; +} diff --git a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h new file mode 100644 index 00000000..e889e9ab --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h @@ -0,0 +1,28 @@ +/* + * GV11B Graphics Context + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __GR_CTX_GV11B_H__ +#define __GR_CTX_GV11B_H__ + +#include "gk20a/gr_ctx_gk20a.h" + +/* production netlist, one and only one from below */ +#define GV11B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A + +void gv11b_init_gr_ctx(struct gpu_ops *gops); + +#endif /*__GR_CTX_GV11B_H__*/ diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index d775aae8..f0736e19 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1,5 +1,5 @@ /* - * GV11B GPU GR + * GV11b GPU GR * * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * @@ -21,11 +21,1750 @@ #include "gk20a/semaphore_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" -#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ +#include "gm20b/gr_gm20b.h" #include "gp10b/gr_gp10b.h" #include "gv11b/gr_gv11b.h" +#include "hw_gr_gv11b.h" +#include "hw_fifo_gv11b.h" +#include "hw_proj_gv11b.h" +#include "hw_ctxsw_prog_gv11b.h" +#include "hw_mc_gv11b.h" +#include + +static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) +{ + bool valid = false; + + switch (class_num) { + case VOLTA_COMPUTE_A: + case VOLTA_A: + case VOLTA_DMA_COPY_A: + valid = true; + break; + + case MAXWELL_COMPUTE_B: + case MAXWELL_B: + case FERMI_TWOD_A: + case KEPLER_DMA_COPY_A: + case MAXWELL_DMA_COPY_A: + case PASCAL_COMPUTE_A: + case PASCAL_A: + case PASCAL_DMA_COPY_A: + valid = true; + break; + + default: + break; + } + gk20a_dbg_info("class=0x%x valid=%d", class_num, valid); + return valid; +} + +static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch) +{ + int ret = 0; + u32 offset = proj_gpc_stride_v() * gpc + + proj_tpc_in_gpc_stride_v() * tpc; + u32 lrf_ecc_status, shm_ecc_status; + + gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch); + + /* Check for LRF ECC errors. */ + lrf_ecc_status = gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); + if ( (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f()) ) { + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Single bit error detected in SM LRF!"); + + g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] += + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset); + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset, + 0); + } + if ( (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f()) ) { + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Double bit error detected in SM LRF!"); + + g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] += + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset); + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, + 0); + } + gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, + lrf_ecc_status); + + /* Check for SHM ECC errors. */ + shm_ecc_status = gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset); + if ((shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) || + (shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f()) || + (shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) || + (shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) { + u32 ecc_stats_reg_val; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Single bit error detected in SM SHM!"); + + ecc_stats_reg_val = + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); + g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] += + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); + g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] += + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, + ecc_stats_reg_val); + } + if ( (shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) || + (shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) { + u32 ecc_stats_reg_val; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Double bit error detected in SM SHM!"); + + ecc_stats_reg_val = + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); + g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] += + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, + ecc_stats_reg_val); + } + gk20a_writel(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset, + shm_ecc_status); + + + return ret; +} + +static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event) +{ + int ret = 0; + u32 offset = proj_gpc_stride_v() * gpc + + proj_tpc_in_gpc_stride_v() * tpc; + u32 esr; + u32 ecc_stats_reg_val; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); + + esr = gk20a_readl(g, + gr_gpc0_tpc0_tex_m_hww_esr_r() + offset); + gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr); + + if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Single bit error detected in TEX!"); + + /* Pipe 0 counters */ + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); + g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, + ecc_stats_reg_val); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); + g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, + ecc_stats_reg_val); + + + /* Pipe 1 counters */ + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); + g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, + ecc_stats_reg_val); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); + g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, + ecc_stats_reg_val); + + + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); + } + if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f()) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Double bit error detected in TEX!"); + + /* Pipe 0 counters */ + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); + g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, + ecc_stats_reg_val); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); + g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, + ecc_stats_reg_val); + + + /* Pipe 1 counters */ + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); + g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, + ecc_stats_reg_val); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); + g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, + ecc_stats_reg_val); + + + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); + } + + gk20a_writel(g, + gr_gpc0_tpc0_tex_m_hww_esr_r() + offset, + esr); + + return ret; +} + +static int gr_gv11b_commit_global_cb_manager(struct gk20a *g, + struct channel_gk20a *c, bool patch) +{ + struct gr_gk20a *gr = &g->gr; + struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; + struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; + u32 attrib_offset_in_chunk = 0; + u32 alpha_offset_in_chunk = 0; + u32 pd_ab_max_output; + u32 gpc_index, ppc_index; + u32 temp, temp2; + u32 cbm_cfg_size_beta, cbm_cfg_size_alpha, cbm_cfg_size_steadystate; + u32 attrib_size_in_chunk, cb_attrib_cache_size_init; + + gk20a_dbg_fn(""); + + if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { + attrib_size_in_chunk = gr->attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + cb_attrib_cache_size_init = gr->attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + } else { + attrib_size_in_chunk = gr->attrib_cb_size; + cb_attrib_cache_size_init = gr->attrib_cb_default_size; + } + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(), + gr->attrib_cb_default_size, patch); + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_alpha_r(), + gr->alpha_cb_default_size, patch); + + pd_ab_max_output = (gr->alpha_cb_default_size * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()) / + gr_pd_ab_dist_cfg1_max_output_granularity_v(); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg1_r(), + gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | + gr_pd_ab_dist_cfg1_max_batches_init_f(), patch); + + attrib_offset_in_chunk = alpha_offset_in_chunk + + gr->tpc_count * gr->alpha_cb_size; + + for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { + temp = proj_gpc_stride_v() * gpc_index; + temp2 = proj_scal_litter_num_pes_per_gpc_v() * gpc_index; + for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; + ppc_index++) { + cbm_cfg_size_beta = cb_attrib_cache_size_init * + gr->pes_tpc_count[ppc_index][gpc_index]; + cbm_cfg_size_alpha = gr->alpha_cb_default_size * + gr->pes_tpc_count[ppc_index][gpc_index]; + cbm_cfg_size_steadystate = gr->attrib_cb_default_size * + gr->pes_tpc_count[ppc_index][gpc_index]; + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + cbm_cfg_size_beta, patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + attrib_offset_in_chunk, patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + cbm_cfg_size_steadystate, + patch); + + attrib_offset_in_chunk += attrib_size_in_chunk * + gr->pes_tpc_count[ppc_index][gpc_index]; + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + cbm_cfg_size_alpha, patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + alpha_offset_in_chunk, patch); + + alpha_offset_in_chunk += gr->alpha_cb_size * + gr->pes_tpc_count[ppc_index][gpc_index]; + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + temp2), + gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size_steadystate), + patch); + } + } + + return 0; +} + +static void gr_gv11b_commit_global_pagepool(struct gk20a *g, + struct channel_ctx_gk20a *ch_ctx, + u64 addr, u32 size, bool patch) +{ + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_base_r(), + gr_scc_pagepool_base_addr_39_8_f(addr), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_r(), + gr_scc_pagepool_total_pages_f(size) | + gr_scc_pagepool_valid_true_f(), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_base_r(), + gr_gpcs_gcc_pagepool_base_addr_39_8_f(addr), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_r(), + gr_gpcs_gcc_pagepool_total_pages_f(size), patch); +} + +static int gr_gv11b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *color_val, u32 index) +{ + u32 i; + u32 zbc_c; + + /* update l2 table */ + g->ops.ltc.set_zbc_color_entry(g, color_val, index); + + /* update ds table */ + gk20a_writel(g, gr_ds_zbc_color_r_r(), + gr_ds_zbc_color_r_val_f(color_val->color_ds[0])); + gk20a_writel(g, gr_ds_zbc_color_g_r(), + gr_ds_zbc_color_g_val_f(color_val->color_ds[1])); + gk20a_writel(g, gr_ds_zbc_color_b_r(), + gr_ds_zbc_color_b_val_f(color_val->color_ds[2])); + gk20a_writel(g, gr_ds_zbc_color_a_r(), + gr_ds_zbc_color_a_val_f(color_val->color_ds[3])); + + gk20a_writel(g, gr_ds_zbc_color_fmt_r(), + gr_ds_zbc_color_fmt_val_f(color_val->format)); + + gk20a_writel(g, gr_ds_zbc_tbl_index_r(), + gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE)); + + /* trigger the write */ + gk20a_writel(g, gr_ds_zbc_tbl_ld_r(), + gr_ds_zbc_tbl_ld_select_c_f() | + gr_ds_zbc_tbl_ld_action_write_f() | + gr_ds_zbc_tbl_ld_trigger_active_f()); + + /* update local copy */ + for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { + gr->zbc_col_tbl[index].color_l2[i] = color_val->color_l2[i]; + gr->zbc_col_tbl[index].color_ds[i] = color_val->color_ds[i]; + } + gr->zbc_col_tbl[index].format = color_val->format; + gr->zbc_col_tbl[index].ref_cnt++; + + gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), + color_val->color_ds[0]); + gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), + color_val->color_ds[1]); + gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), + color_val->color_ds[2]); + gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), + color_val->color_ds[3]); + zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3)); + zbc_c &= ~(0x7f << ((index % 4) * 7)); + zbc_c |= color_val->format << ((index % 4) * 7); + gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); + + return 0; +} + +static int gr_gv11b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *depth_val, u32 index) +{ + u32 zbc_z; + + /* update l2 table */ + g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); + + /* update ds table */ + gk20a_writel(g, gr_ds_zbc_z_r(), + gr_ds_zbc_z_val_f(depth_val->depth)); + + gk20a_writel(g, gr_ds_zbc_z_fmt_r(), + gr_ds_zbc_z_fmt_val_f(depth_val->format)); + + gk20a_writel(g, gr_ds_zbc_tbl_index_r(), + gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE)); + + /* trigger the write */ + gk20a_writel(g, gr_ds_zbc_tbl_ld_r(), + gr_ds_zbc_tbl_ld_select_z_f() | + gr_ds_zbc_tbl_ld_action_write_f() | + gr_ds_zbc_tbl_ld_trigger_active_f()); + + /* update local copy */ + gr->zbc_dep_tbl[index].depth = depth_val->depth; + gr->zbc_dep_tbl[index].format = depth_val->format; + gr->zbc_dep_tbl[index].ref_cnt++; + + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); + zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3)); + zbc_z &= ~(0x7f << (index % 4) * 7); + zbc_z |= depth_val->format << (index % 4) * 7; + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z); + + return 0; +} + +static u32 gr_gv11b_pagepool_default_size(struct gk20a *g) +{ + return gr_scc_pagepool_total_pages_hwmax_value_v(); +} + +static int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + int size; + + gr->attrib_cb_size = gr->attrib_cb_default_size; + gr->alpha_cb_size = gr->alpha_cb_default_size; + + gr->attrib_cb_size = min(gr->attrib_cb_size, + gr_gpc0_ppc0_cbm_beta_cb_size_v_f(~0) / g->gr.tpc_count); + gr->alpha_cb_size = min(gr->alpha_cb_size, + gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(~0) / g->gr.tpc_count); + + size = gr->attrib_cb_size * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + gr->max_tpc_count; + + size += gr->alpha_cb_size * + gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() * + gr->max_tpc_count; + + size = ALIGN(size, 128); + + return size; +} + +static void gr_gv11b_set_go_idle_timeout(struct gk20a *g, u32 data) +{ + gk20a_writel(g, gr_fe_go_idle_timeout_r(), data); +} + +static void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data) +{ + u32 val; + + gk20a_dbg_fn(""); + + val = gk20a_readl(g, gr_gpcs_tc_debug0_r()); + val = set_field(val, gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(), + gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(data)); + gk20a_writel(g, gr_gpcs_tc_debug0_r(), val); + + gk20a_dbg_fn("done"); +} + +static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data) +{ + gk20a_dbg_fn(""); + + if (class_num == PASCAL_COMPUTE_A) { + switch (offset << 2) { + case NVC0C0_SET_SHADER_EXCEPTIONS: + gk20a_gr_set_shader_exceptions(g, data); + break; + default: + goto fail; + } + } + + if (class_num == PASCAL_A) { + switch (offset << 2) { + case NVC097_SET_SHADER_EXCEPTIONS: + gk20a_gr_set_shader_exceptions(g, data); + break; + case NVC097_SET_CIRCULAR_BUFFER_SIZE: + g->ops.gr.set_circular_buffer_size(g, data); + break; + case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE: + g->ops.gr.set_alpha_circular_buffer_size(g, data); + break; + case NVC097_SET_GO_IDLE_TIMEOUT: + gr_gv11b_set_go_idle_timeout(g, data); + break; + case NVC097_SET_COALESCE_BUFFER_SIZE: + gr_gv11b_set_coalesce_buffer_size(g, data); + break; + default: + goto fail; + } + } + return 0; + +fail: + return -EINVAL; +} + +static void gr_gv11b_cb_size_default(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + + if (!gr->attrib_cb_default_size) + gr->attrib_cb_default_size = 0x800; + gr->alpha_cb_default_size = + gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); +} + +static void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) +{ + struct gr_gk20a *gr = &g->gr; + u32 gpc_index, ppc_index, stride, val; + u32 pd_ab_max_output; + u32 alpha_cb_size = data * 4; + + gk20a_dbg_fn(""); + + if (alpha_cb_size > gr->alpha_cb_size) + alpha_cb_size = gr->alpha_cb_size; + + gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(), + (gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) & + ~gr_ds_tga_constraintlogic_alpha_cbsize_f(~0)) | + gr_ds_tga_constraintlogic_alpha_cbsize_f(alpha_cb_size)); + + pd_ab_max_output = alpha_cb_size * + gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() / + gr_pd_ab_dist_cfg1_max_output_granularity_v(); + + gk20a_writel(g, gr_pd_ab_dist_cfg1_r(), + gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | + gr_pd_ab_dist_cfg1_max_batches_init_f()); + + for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { + stride = proj_gpc_stride_v() * gpc_index; + + for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; + ppc_index++) { + + val = gk20a_readl(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + + stride + + proj_ppc_in_gpc_stride_v() * ppc_index); + + val = set_field(val, gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(), + gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(alpha_cb_size * + gr->pes_tpc_count[ppc_index][gpc_index])); + + gk20a_writel(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + + stride + + proj_ppc_in_gpc_stride_v() * ppc_index, val); + } + } +} + +static void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data) +{ + struct gr_gk20a *gr = &g->gr; + u32 gpc_index, ppc_index, stride, val; + u32 cb_size_steady = data * 4, cb_size; + + gk20a_dbg_fn(""); + + if (cb_size_steady > gr->attrib_cb_size) + cb_size_steady = gr->attrib_cb_size; + if (gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) != + gk20a_readl(g, + gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) { + cb_size = cb_size_steady + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + } else { + cb_size = cb_size_steady; + } + + gk20a_writel(g, gr_ds_tga_constraintlogic_beta_r(), + (gk20a_readl(g, gr_ds_tga_constraintlogic_beta_r()) & + ~gr_ds_tga_constraintlogic_beta_cbsize_f(~0)) | + gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size_steady)); + + for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { + stride = proj_gpc_stride_v() * gpc_index; + + for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; + ppc_index++) { + + val = gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() + + stride + + proj_ppc_in_gpc_stride_v() * ppc_index); + + val = set_field(val, + gr_gpc0_ppc0_cbm_beta_cb_size_v_m(), + gr_gpc0_ppc0_cbm_beta_cb_size_v_f(cb_size * + gr->pes_tpc_count[ppc_index][gpc_index])); + + gk20a_writel(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() + + stride + + proj_ppc_in_gpc_stride_v() * ppc_index, val); + + gk20a_writel(g, proj_ppc_in_gpc_stride_v() * ppc_index + + gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + + stride, + gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f( + cb_size_steady)); + + val = gk20a_readl(g, gr_gpcs_swdx_tc_beta_cb_size_r( + ppc_index + gpc_index)); + + val = set_field(val, + gr_gpcs_swdx_tc_beta_cb_size_v_m(), + gr_gpcs_swdx_tc_beta_cb_size_v_f( + cb_size_steady * + gr->gpc_ppc_count[gpc_index])); + + gk20a_writel(g, gr_gpcs_swdx_tc_beta_cb_size_r( + ppc_index + gpc_index), val); + } + } +} + +static int gr_gv11b_init_ctx_state(struct gk20a *g) +{ + struct fecs_method_op_gk20a op = { + .mailbox = { .id = 0, .data = 0, + .clr = ~0, .ok = 0, .fail = 0}, + .method.data = 0, + .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL, + .cond.fail = GR_IS_UCODE_OP_SKIP, + }; + int err; + + gk20a_dbg_fn(""); + + err = gr_gk20a_init_ctx_state(g); + if (err) + return err; + + if (!g->gr.t18x.ctx_vars.preempt_image_size) { + op.method.addr = + gr_fecs_method_push_adr_discover_preemption_image_size_v(); + op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size; + err = gr_gk20a_submit_fecs_method_op(g, op, false); + if (err) { + gk20a_err(dev_from_gk20a(g), + "query preempt image size failed"); + return err; + } + } + + gk20a_dbg_info("preempt image size: %u", + g->gr.t18x.ctx_vars.preempt_image_size); + + gk20a_dbg_fn("done"); + + return 0; +} + +int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, + struct mem_desc *mem) +{ + int err; + + gk20a_dbg_fn(""); + + err = gk20a_gmmu_alloc_attr(vm->mm->g, 0, size, mem); + if (err) + return err; + + mem->gpu_va = gk20a_gmmu_map(vm, + &mem->sgt, + size, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + gk20a_mem_flag_none, + false); + + if (!mem->gpu_va) { + err = -ENOMEM; + goto fail_free; + } + + return 0; + +fail_free: + gk20a_gmmu_free(vm->mm->g, mem); + return err; +} + +static int gr_gv11b_alloc_gr_ctx(struct gk20a *g, + struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm, + u32 class, + u32 flags) +{ + int err; + + gk20a_dbg_fn(""); + + err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags); + if (err) + return err; + + (*gr_ctx)->t18x.ctx_id_valid = false; + + if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) + flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; + + if (class == PASCAL_COMPUTE_A && + g->gr.t18x.ctx_vars.force_preemption_cilp) + flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP; + + if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { + u32 spill_size = + gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * + gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); + u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * + gr_scc_pagepool_total_pages_byte_granularity_v(); + u32 betacb_size = g->gr.attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + g->gr.max_tpc_count; + attrib_cb_size = ALIGN(attrib_cb_size, 128); + + gk20a_dbg_info("gfxp context spill_size=%d", spill_size); + gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size); + gk20a_dbg_info("gfxp context attrib_cb_size=%d", + attrib_cb_size); + err = gr_gv11b_alloc_buffer(vm, + g->gr.t18x.ctx_vars.preempt_image_size, + &(*gr_ctx)->t18x.preempt_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(vm->mm->g), + "cannot allocate preempt buffer"); + goto fail_free_gk20a_ctx; + } + + err = gr_gv11b_alloc_buffer(vm, + spill_size, + &(*gr_ctx)->t18x.spill_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(vm->mm->g), + "cannot allocate spill buffer"); + goto fail_free_preempt; + } + + err = gr_gv11b_alloc_buffer(vm, + attrib_cb_size, + &(*gr_ctx)->t18x.betacb_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(vm->mm->g), + "cannot allocate beta buffer"); + goto fail_free_spill; + } + + err = gr_gv11b_alloc_buffer(vm, + pagepool_size, + &(*gr_ctx)->t18x.pagepool_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(vm->mm->g), + "cannot allocate page pool"); + goto fail_free_betacb; + } + + (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP; + } + + if (class == PASCAL_COMPUTE_A) { + if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) + (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; + else + (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; + } + + gk20a_dbg_fn("done"); + + return err; + +fail_free_betacb: + gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.betacb_ctxsw_buffer); +fail_free_spill: + gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.spill_ctxsw_buffer); +fail_free_preempt: + gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.preempt_ctxsw_buffer); +fail_free_gk20a_ctx: + gr_gk20a_free_gr_ctx(g, vm, *gr_ctx); + *gr_ctx = NULL; + + return err; +} + +static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, + struct gr_ctx_desc *gr_ctx) { + void *ctx_ptr = vmap(gr_ctx->mem.pages, + PAGE_ALIGN(gr_ctx->mem.size) >> PAGE_SHIFT, + 0, pgprot_writecombine(PAGE_KERNEL)); + if (!ctx_ptr) { + WARN_ON("Cannot map context"); + return; + } + gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_magic_value_o(), 0), + ctxsw_prog_main_image_magic_value_v_value_v()); + + gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(), 0)); + + gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(), 0)); + + gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_context_timestamp_buffer_control_o(), 0)); + + gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_num_save_ops_o(), 0)); + gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_num_wfi_save_ops_o(), 0)); + gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_num_cta_save_ops_o(), 0)); + gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_num_gfxp_save_ops_o(), 0)); + gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_num_cilp_save_ops_o(), 0)); + gk20a_err(dev_from_gk20a(g), + "image gfx preemption option (GFXP is 1) %x\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_graphics_preemption_options_o(), + 0)); + vunmap(ctx_ptr); +} + +static void gr_gv11b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, + struct gr_ctx_desc *gr_ctx) +{ + gk20a_dbg_fn(""); + + if (!gr_ctx) + return; + + if (g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close) + dump_ctx_switch_stats(g, vm, gr_ctx); + + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); + gr_gk20a_free_gr_ctx(g, vm, gr_ctx); + gk20a_dbg_fn("done"); +} + + +static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, + struct channel_ctx_gk20a *ch_ctx, + void *ctx_ptr) +{ + struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; + u32 gfxp_preempt_option = + ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); + u32 cilp_preempt_option = + ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(); + int err; + + gk20a_dbg_fn(""); + + if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { + gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); + gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_graphics_preemption_options_o(), 0, + gfxp_preempt_option); + } + + if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_CILP) { + gk20a_dbg_info("CILP: %x", cilp_preempt_option); + gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_compute_preemption_options_o(), 0, + cilp_preempt_option); + } + + if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) { + u32 addr; + u32 size; + u32 cbes_reserve; + + gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_full_preemption_ptr_o(), 0, + gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8); + + err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); + + addr = (u64_lo32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) >> + gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) | + (u64_hi32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) << + (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); + + gk20a_dbg_info("attrib cb addr : 0x%016x", addr); + g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true); + + addr = (u64_lo32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) >> + gr_scc_pagepool_base_addr_39_8_align_bits_v()) | + (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << + (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); + size = gr_ctx->t18x.pagepool_ctxsw_buffer.size; + + if (size == g->ops.gr.pagepool_default_size(g)) + size = gr_scc_pagepool_total_pages_hwmax_v(); + + g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true); + + addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >> + gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | + (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) << + (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); + size = gr_ctx->t18x.spill_ctxsw_buffer.size / + gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_swdx_rm_spill_buffer_addr_r(), + gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(addr), + true); + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_swdx_rm_spill_buffer_size_r(), + gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size), + true); + + cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(); + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpcs_swdx_beta_cb_ctrl_r(), + gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f( + cbes_reserve), + true); + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(), + gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f( + cbes_reserve), + true); + + gr_gk20a_ctx_patch_write_end(g, ch_ctx); + } + + gk20a_dbg_fn("done"); +} + +static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, + struct gk20a_debug_output *o) +{ + struct gr_gk20a *gr = &g->gr; + + gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n", + gk20a_readl(g, gr_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_STATUS1: 0x%x\n", + gk20a_readl(g, gr_status_1_r())); + gk20a_debug_output(o, "NV_PGRAPH_STATUS2: 0x%x\n", + gk20a_readl(g, gr_status_2_r())); + gk20a_debug_output(o, "NV_PGRAPH_ENGINE_STATUS: 0x%x\n", + gk20a_readl(g, gr_engine_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_STATUS : 0x%x\n", + gk20a_readl(g, gr_gpfifo_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_CONTROL : 0x%x\n", + gk20a_readl(g, gr_gpfifo_ctl_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n", + gk20a_readl(g, gr_fecs_host_int_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_EXCEPTION : 0x%x\n", + gk20a_readl(g, gr_exception_r())); + gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR : 0x%x\n", + gk20a_readl(g, gr_fecs_intr_r())); + gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n", + gk20a_readl(g, fifo_engine_status_r(ENGINE_GR_GK20A))); + gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n", + gk20a_readl(g, gr_activity_1_r())); + gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY2: 0x%x\n", + gk20a_readl(g, gr_activity_2_r())); + gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY4: 0x%x\n", + gk20a_readl(g, gr_activity_4_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_SKED_ACTIVITY: 0x%x\n", + gk20a_readl(g, gr_pri_sked_activity_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity2_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); + if (gr->gpc_tpc_count[0] == 2) + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_2_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r())); + if (gr->gpc_tpc_count[0] == 2) + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_be0_becs_be_activity0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_be1_becs_be_activity0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_bes_becs_be_activity0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_DS_MPIPE_STATUS: 0x%x\n", + gk20a_readl(g, gr_pri_ds_mpipe_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT : 0x%x\n", + gk20a_readl(g, gr_fe_go_idle_timeout_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_INFO : 0x%x\n", + gk20a_readl(g, gr_pri_fe_go_idle_info_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n", + gk20a_readl(g, gr_cwd_fs_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n", + gk20a_readl(g, gr_fe_tpc_fs_r(0))); + gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID(0): 0x%x\n", + gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0))); + gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n", + gk20a_readl(g, gr_cwd_sm_id_r(0))); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0: 0x%x\n", + gk20a_readl(g, gr_fecs_ctxsw_status_fe_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1: 0x%x\n", + gk20a_readl(g, gr_fecs_ctxsw_status_1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0: 0x%x\n", + gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_gpc_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1: 0x%x\n", + gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE : 0x%x\n", + gk20a_readl(g, gr_fecs_ctxsw_idlestate_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE : 0x%x\n", + gk20a_readl(g, gr_gpc0_gpccs_ctxsw_idlestate_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CURRENT_CTX : 0x%x\n", + gk20a_readl(g, gr_fecs_current_ctx_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n", + gk20a_readl(g, gr_fecs_new_ctx_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_CROP_STATUS1 : 0x%x\n", + gk20a_readl(g, gr_pri_be0_crop_status1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_CROP_STATUS1 : 0x%x\n", + gk20a_readl(g, gr_pri_bes_crop_status1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_ZROP_STATUS : 0x%x\n", + gk20a_readl(g, gr_pri_be0_zrop_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_ZROP_STATUS2 : 0x%x\n", + gk20a_readl(g, gr_pri_be0_zrop_status2_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS : 0x%x\n", + gk20a_readl(g, gr_pri_bes_zrop_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS2 : 0x%x\n", + gk20a_readl(g, gr_pri_bes_zrop_status2_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION: 0x%x\n", + gk20a_readl(g, gr_pri_be0_becs_be_exception_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN: 0x%x\n", + gk20a_readl(g, gr_pri_be0_becs_be_exception_en_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_en_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r())); + return 0; +} + +static bool gr_activity_empty_or_preempted(u32 val) +{ + while(val) { + u32 v = val & 7; + if (v != gr_activity_4_gpc0_empty_v() && + v != gr_activity_4_gpc0_preempted_v()) + return false; + val >>= 3; + } + + return true; +} + +static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long end_jiffies, + u32 expect_delay) +{ + u32 delay = expect_delay; + bool gr_enabled; + bool ctxsw_active; + bool gr_busy; + u32 gr_status; + u32 activity0, activity1, activity2, activity4; + + gk20a_dbg_fn(""); + + do { + /* fmodel: host gets fifo_engine_status(gr) from gr + only when gr_status is read */ + gr_status = gk20a_readl(g, gr_status_r()); + + gr_enabled = gk20a_readl(g, mc_enable_r()) & + mc_enable_pgraph_enabled_f(); + + ctxsw_active = gr_status & 1<<7; + + activity0 = gk20a_readl(g, gr_activity_0_r()); + activity1 = gk20a_readl(g, gr_activity_1_r()); + activity2 = gk20a_readl(g, gr_activity_2_r()); + activity4 = gk20a_readl(g, gr_activity_4_r()); + + gr_busy = !(gr_activity_empty_or_preempted(activity0) && + gr_activity_empty_or_preempted(activity1) && + activity2 == 0 && + gr_activity_empty_or_preempted(activity4)); + + if (!gr_enabled || (!gr_busy && !ctxsw_active)) { + gk20a_dbg_fn("done"); + return 0; + } + + usleep_range(delay, delay * 2); + delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); + + } while (time_before(jiffies, end_jiffies) + || !tegra_platform_is_silicon()); + + gk20a_err(dev_from_gk20a(g), + "timeout, ctxsw busy : %d, gr busy : %d, %08x, %08x, %08x, %08x", + ctxsw_active, gr_busy, activity0, activity1, activity2, activity4); + + return -EAGAIN; +} + +static void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, + struct channel_ctx_gk20a *ch_ctx, + u64 addr, bool patch) +{ + struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; + int attrBufferSize; + + if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) + attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size; + else + attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); + + attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(); + + gr_gm20b_commit_global_attrib_cb(g, ch_ctx, addr, patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(), + gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(addr) | + gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_0_r(), + gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(addr), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_1_r(), + gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(attrBufferSize) | + gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch); +} + +static void gr_gv11b_commit_global_bundle_cb(struct gk20a *g, + struct channel_ctx_gk20a *ch_ctx, + u64 addr, u64 size, bool patch) +{ + u32 data; + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_base_r(), + gr_scc_bundle_cb_base_addr_39_8_f(addr), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_size_r(), + gr_scc_bundle_cb_size_div_256b_f(size) | + gr_scc_bundle_cb_size_valid_true_f(), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_base_r(), + gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(addr), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_size_r(), + gr_gpcs_swdx_bundle_cb_size_div_256b_f(size) | + gr_gpcs_swdx_bundle_cb_size_valid_true_f(), patch); + + /* data for state_limit */ + data = (g->gr.bundle_cb_default_size * + gr_scc_bundle_cb_size_div_256b_byte_granularity_v()) / + gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(); + + data = min_t(u32, data, g->gr.min_gpm_fifo_depth); + + gk20a_dbg_info("bundle cb token limit : %d, state limit : %d", + g->gr.bundle_cb_token_limit, data); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg2_r(), + gr_pd_ab_dist_cfg2_token_limit_f(g->gr.bundle_cb_token_limit) | + gr_pd_ab_dist_cfg2_state_limit_f(data), patch); +} + +static int gr_gv11b_init_fs_state(struct gk20a *g) +{ + u32 data; + + data = gk20a_readl(g, gr_gpcs_tpcs_sm_texio_control_r()); + data = set_field(data, gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(), + gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); + gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); + + data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r()); + data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(), + gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); + gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); + + return gr_gm20b_ctx_state_floorsweep(g); +} + +static void gr_gv11b_init_cyclestats(struct gk20a *g) +{ +#if defined(CONFIG_GK20A_CYCLE_STATS) + g->gpu_characteristics.flags |= + NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS; + g->gpu_characteristics.flags |= + NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT; +#else + (void)g; +#endif +} + +static void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) +{ + tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); + tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0); + + if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) + tegra_fuse_writel(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); + else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) + tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); + else + tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); +} + +static void gr_gv11b_get_access_map(struct gk20a *g, + u32 **whitelist, int *num_entries) +{ + static u32 wl_addr_gv11b[] = { + /* this list must be sorted (low to high) */ + 0x404468, /* gr_pri_mme_max_instructions */ + 0x418300, /* gr_pri_gpcs_rasterarb_line_class */ + 0x418800, /* gr_pri_gpcs_setup_debug */ + 0x418e00, /* gr_pri_gpcs_swdx_config */ + 0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ + 0x418e44, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ + 0x418e48, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ + 0x418e4c, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ + 0x418e50, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ + 0x418e58, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e5c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e60, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e64, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e68, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e6c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e70, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e74, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e78, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e7c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e80, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e84, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e88, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e8c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e90, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e94, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */ + 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ + 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ + 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ + 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ + }; + + *whitelist = wl_addr_gv11b; + *num_entries = ARRAY_SIZE(wl_addr_gv11b); +} + +static int gr_gv11b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a *fault_ch) +{ + int ret = 0; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); + + ret = gk20a_disable_channel_tsg(g, fault_ch); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "CILP: failed to disable channel/TSG!\n"); + return ret; + } + + ret = g->ops.fifo.update_runlist(g, 0, ~0, true, false); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "CILP: failed to restart runlist 0!"); + return ret; + } + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist"); + + if (gk20a_is_channel_marked_as_tsg(fault_ch)) + gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true); + else + gk20a_fifo_issue_preempt(g, fault_ch->hw_chid, false); + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: preempted the channel/tsg"); + + return ret; +} + +static int gr_gv11b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk20a *fault_ch) +{ + int ret; + struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); + + if (!gr_ctx) + return -EINVAL; + + if (gr_ctx->t18x.cilp_preempt_pending) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP is already pending for chid %d", + fault_ch->hw_chid); + return 0; + } + + /* get ctx_id from the ucode image */ + if (!gr_ctx->t18x.ctx_id_valid) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: looking up ctx id"); + ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->t18x.ctx_id); + if (ret) { + gk20a_err(dev_from_gk20a(g), "CILP: error looking up ctx id!\n"); + return ret; + } + gr_ctx->t18x.ctx_id_valid = true; + } + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: ctx id is 0x%x", gr_ctx->t18x.ctx_id); + + /* send ucode method to set ctxsw interrupt */ + ret = gr_gk20a_submit_fecs_sideband_method_op(g, + (struct fecs_method_op_gk20a) { + .method.data = gr_ctx->t18x.ctx_id, + .method.addr = + gr_fecs_method_push_adr_configure_interrupt_completion_option_v(), + .mailbox = { + .id = 1 /* sideband */, .data = 0, + .clr = ~0, .ret = NULL, + .ok = gr_fecs_ctxsw_mailbox_value_pass_v(), + .fail = 0}, + .cond.ok = GR_IS_UCODE_OP_EQUAL, + .cond.fail = GR_IS_UCODE_OP_SKIP}); + + if (ret) { + gk20a_err(dev_from_gk20a(g), + "CILP: failed to enable ctxsw interrupt!"); + return ret; + } + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: enabled ctxsw completion interrupt"); + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: disabling channel %d", + fault_ch->hw_chid); + + ret = gr_gv11b_disable_channel_or_tsg(g, fault_ch); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "CILP: failed to disable channel!!"); + return ret; + } + + /* set cilp_preempt_pending = true and record the channel */ + gr_ctx->t18x.cilp_preempt_pending = true; + g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid; + + if (gk20a_is_channel_marked_as_tsg(fault_ch)) { + struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; + + gk20a_tsg_event_id_post_event(tsg, + NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED); + } else { + gk20a_channel_event_id_post_event(fault_ch, + NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED); + } + + return 0; +} + +static int gr_gv11b_clear_cilp_preempt_pending(struct gk20a *g, + struct channel_gk20a *fault_ch) +{ + struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); + + if (!gr_ctx) + return -EINVAL; + + /* The ucode is self-clearing, so all we need to do here is + to clear cilp_preempt_pending. */ + if (!gr_ctx->t18x.cilp_preempt_pending) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP is already cleared for chid %d\n", + fault_ch->hw_chid); + return 0; + } + + gr_ctx->t18x.cilp_preempt_pending = false; + g->gr.t18x.cilp_preempt_pending_chid = -1; + + return 0; +} + +/* @brief pre-process work on the SM exceptions to determine if we clear them or not. + * + * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing + */ +static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, + u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr, + bool sm_debugger_attached, struct channel_gk20a *fault_ch, + bool *early_exit, bool *ignore_debugger) +{ + int ret; + bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->preempt_mode == + NVGPU_GR_PREEMPTION_MODE_CILP) ; + u32 global_mask = 0, dbgr_control0, global_esr_copy; + u32 offset = proj_gpc_stride_v() * gpc + + proj_tpc_in_gpc_stride_v() * tpc; + + *early_exit = false; + *ignore_debugger = false; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n", + gpc, tpc, global_esr); + + if (cilp_enabled && sm_debugger_attached) { + if (global_esr & gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f()) + gk20a_writel(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset, + gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f()); + + if (global_esr & gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f()) + gk20a_writel(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset, + gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f()); + + global_mask = gr_gpcs_tpcs_sm1_hww_global_esr_multiple_warp_errors_pending_f() | + gr_gpcs_tpcs_sm1_hww_global_esr_bpt_pause_pending_f(); + + if (warp_esr != 0 || (global_esr & global_mask) != 0) { + *ignore_debugger = true; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: starting wait for LOCKED_DOWN on gpc %d tpc %d\n", + gpc, tpc); + + if (gk20a_dbg_gpu_broadcast_stop_trigger(fault_ch)) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n", + gpc, tpc); + gk20a_suspend_all_sms(g, global_mask, false); + + gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch); + } else { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: STOP_TRIGGER from gpc %d tpc %d\n", + gpc, tpc); + gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true); + } + + /* reset the HWW errors after locking down */ + global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset); + gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: HWWs cleared for gpc %d tpc %d\n", + gpc, tpc); + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Setting CILP preempt pending\n"); + ret = gr_gv11b_set_cilp_preempt_pending(g, fault_ch); + if (ret) { + gk20a_err(dev_from_gk20a(g), "CILP: error while setting CILP preempt pending!\n"); + return ret; + } + + dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm1_dbgr_control0_r() + offset); + if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", + gpc, tpc); + dbgr_control0 = set_field(dbgr_control0, + gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(), + gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f()); + gk20a_writel(g, gr_gpc0_tpc0_sm1_dbgr_control0_r() + offset, dbgr_control0); + } + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: resume for gpc %d tpc %d\n", + gpc, tpc); + gk20a_resume_single_sm(g, gpc, tpc); + + *ignore_debugger = true; + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc); + } + + *early_exit = true; + } + return 0; +} + +static int gr_gv11b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) +{ + struct gr_ctx_desc *gr_ctx; + struct channel_gk20a *ch; + int chid; + int ret = -EINVAL; + + chid = g->gr.t18x.cilp_preempt_pending_chid; + + ch = gk20a_channel_get(gk20a_fifo_channel_from_hw_chid(g, chid)); + if (!ch) + return ret; + + gr_ctx = ch->ch_ctx.gr_ctx; + + if (gr_ctx->t18x.cilp_preempt_pending) { + *__chid = chid; + ret = 0; + } + + gk20a_channel_put(ch); + + return ret; +} + +static int gr_gv11b_handle_fecs_error(struct gk20a *g, + struct channel_gk20a *__ch, + struct gr_gk20a_isr_data *isr_data) +{ + u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); + struct channel_gk20a *ch; + int chid = -1; + int ret = 0; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); + + /* + * INTR1 (bit 1 of the HOST_INT_STATUS_CTXSW_INTR) + * indicates that a CILP ctxsw save has finished + */ + if (gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(2)) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: ctxsw save completed!\n"); + + /* now clear the interrupt */ + gk20a_writel(g, gr_fecs_host_int_clear_r(), + gr_fecs_host_int_clear_ctxsw_intr1_clear_f()); + + ret = gr_gv11b_get_cilp_preempt_pending_chid(g, &chid); + if (ret) + goto clean_up; + + ch = gk20a_channel_get( + gk20a_fifo_channel_from_hw_chid(g, chid)); + if (!ch) + goto clean_up; + + + /* set preempt_pending to false */ + ret = gr_gv11b_clear_cilp_preempt_pending(g, ch); + if (ret) { + gk20a_err(dev_from_gk20a(g), "CILP: error while unsetting CILP preempt pending!\n"); + gk20a_channel_put(ch); + goto clean_up; + } + + if (gk20a_gr_sm_debugger_attached(g)) { + if (gk20a_is_channel_marked_as_tsg(ch)) { + struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; + struct channel_gk20a *__ch; + + mutex_lock(&tsg->ch_list_lock); + list_for_each_entry(__ch, &tsg->ch_list, ch_entry) { + gk20a_dbg_gpu_post_events(__ch); + } + mutex_unlock(&tsg->ch_list_lock); + + gk20a_tsg_event_id_post_event(tsg, + NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); + } else { + gk20a_dbg_gpu_post_events(ch); + + gk20a_channel_event_id_post_event(ch, + NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); + } + } + + gk20a_channel_put(ch); + } + +clean_up: + /* handle any remaining interrupts */ + return gk20a_gr_handle_fecs_error(g, __ch, isr_data); +} + +static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) +{ + if (!(hww_warp_esr & gr_gpc0_tpc0_sm1_hww_warp_esr_addr_valid_m())) + hww_warp_esr = set_field(hww_warp_esr, + gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_m(), + gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_none_f()); + + return hww_warp_esr; +} void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); + gops->gr.init_fs_state = gr_gv11b_init_fs_state; + gops->gr.is_valid_class = gr_gv11b_is_valid_class; + gops->gr.commit_global_cb_manager = gr_gv11b_commit_global_cb_manager; + gops->gr.commit_global_pagepool = gr_gv11b_commit_global_pagepool; + gops->gr.add_zbc_color = gr_gv11b_add_zbc_color; + gops->gr.add_zbc_depth = gr_gv11b_add_zbc_depth; + gops->gr.pagepool_default_size = gr_gv11b_pagepool_default_size; + gops->gr.calc_global_ctx_buffer_size = + gr_gv11b_calc_global_ctx_buffer_size; + gops->gr.commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb; + gops->gr.commit_global_bundle_cb = gr_gv11b_commit_global_bundle_cb; + gops->gr.handle_sw_method = gr_gv11b_handle_sw_method; + gops->gr.cb_size_default = gr_gv11b_cb_size_default; + gops->gr.set_alpha_circular_buffer_size = + gr_gv11b_set_alpha_circular_buffer_size; + gops->gr.set_circular_buffer_size = + gr_gv11b_set_circular_buffer_size; + gops->gr.init_ctx_state = gr_gv11b_init_ctx_state; + gops->gr.alloc_gr_ctx = gr_gv11b_alloc_gr_ctx; + gops->gr.free_gr_ctx = gr_gv11b_free_gr_ctx; + gops->gr.update_ctxsw_preemption_mode = + gr_gv11b_update_ctxsw_preemption_mode; + gops->gr.dump_gr_regs = gr_gv11b_dump_gr_status_regs; + gops->gr.wait_empty = gr_gv11b_wait_empty; + gops->gr.init_cyclestats = gr_gv11b_init_cyclestats; + gops->gr.set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask; + gops->gr.get_access_map = gr_gv11b_get_access_map; + gops->gr.handle_sm_exception = gr_gv11b_handle_sm_exception; + gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; + gops->gr.mask_hww_warp_esr = gv11b_mask_hww_warp_esr; + gops->gr.pre_process_sm_exception = + gr_gv11b_pre_process_sm_exception; + gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error; } diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c new file mode 100644 index 00000000..8e8cf649 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c @@ -0,0 +1,25 @@ +/* + * GV11B Graphics + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "gk20a/gk20a.h" + +int gv11b_init_gpu_characteristics(struct gk20a *g) +{ + gk20a_init_gpu_characteristics(g); + return 0; +} diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.h b/drivers/gpu/nvgpu/gv11b/gv11b.h new file mode 100644 index 00000000..142a66ba --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gv11b.h @@ -0,0 +1,26 @@ +/* + * GV11B Graphics + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef GV11B_H +#define GV11B_H + +#include "gk20a/gk20a.h" + +int gv11b_init_gpu_characteristics(struct gk20a *g); + +#endif /* GV11B_H */ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0debe7ce..a30e3263 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -22,6 +22,14 @@ #include "gv11b/gr_gv11b.h" #include "gv11b/mc_gv11b.h" +#include "gv11b/ltc_gv11b.h" +#include "gv11b/fecs_trace_gv11b.h" +#include "gv11b/gv11b.h" +#include "gv11b/ce2_gv11b.h" +#include "gv11b/gr_ctx_gv11b.h" +#include "gv11b/mm_gv11b.h" +#include "gv11b/pmu_gv11b.h" +#include "gv11b/therm_gv11b.h" #include "gm20b/gr_gm20b.h" @@ -30,9 +38,22 @@ int gv11b_init_hal(struct gk20a *g) struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + /* boot in non-secure modes for time beeing */ + gops->privsecurity = 0; + gops->securegpccs = 0; + gv11b_init_mc(gops); + gv11b_init_ltc(gops); gv11b_init_gr(gops); + gv11b_init_fecs_trace_ops(gops); + gv11b_init_ce2(gops); + gv11b_init_mm(gops); + gv11b_init_gr_ctx(gops); + gv11b_init_pmu_ops(gops); + gk20a_init_debug_ops(gops); + gv11b_init_therm_ops(gops); gops->name = "gv11b"; + gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; c->twod_class = FERMI_TWOD_A; c->threed_class = VOLTA_A; diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h index b7aa46bc..d54957eb 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h @@ -72,7 +72,7 @@ static inline u32 gmmu_new_pde_aperture_video_memory_f(void) } static inline u32 gmmu_new_pde_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xfffffff) << 8; } static inline u32 gmmu_new_pde_address_sys_w(void) { @@ -164,7 +164,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) } static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xfffffff) << 8; } static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { @@ -212,7 +212,7 @@ static inline u32 gmmu_new_pte_privilege_false_f(void) } static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xfffffff) << 8; } static inline u32 gmmu_new_pte_address_sys_w(void) { diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c new file mode 100644 index 00000000..df2b0f68 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -0,0 +1,26 @@ +/* + * GV11B LTC + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "gp10b/ltc_gp10b.h" +#include "gv11b/ltc_gv11b.h" +#include "hw_ltc_gv11b.h" + +void gv11b_init_ltc(struct gpu_ops *gops) +{ + gp10b_init_ltc(gops); +} diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h new file mode 100644 index 00000000..0b8b9459 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef LTC_GV11B_H +#define LTC_GV11B_H +struct gk20a; + +void gv11b_init_ltc(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c new file mode 100644 index 00000000..0ac18a91 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -0,0 +1,25 @@ +/* + * GV11B MMU + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include "gk20a/gk20a.h" +#include "gp10b/mm_gp10b.h" +#include "mm_gv11b.h" + +void gv11b_init_mm(struct gpu_ops *gops) +{ + gp10b_init_mm(gops); +} diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h new file mode 100644 index 00000000..4284b171 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h @@ -0,0 +1,21 @@ +/* + * GV11B MM + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef MM_GV11B_H +#define MM_GV11B_H + +struct gpu_ops; + +void gv11b_init_mm(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c new file mode 100644 index 00000000..0b0144ce --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -0,0 +1,27 @@ +/* + * GV11B PMU + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for udelay */ +#include +#include "gk20a/gk20a.h" +#include "gp10b/pmu_gp10b.h" + +#include "pmu_gv11b.h" +#include "hw_pwr_gv11b.h" + +void gv11b_init_pmu_ops(struct gpu_ops *gops) +{ + gp10b_init_pmu_ops(gops); +} diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h new file mode 100644 index 00000000..c99923e7 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h @@ -0,0 +1,21 @@ +/* + * GV11B PMU + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PMU_GV11B_H_ +#define __PMU_GV11B_H_ + +void gv11b_init_pmu_ops(struct gpu_ops *gops); + +#endif /*__PMU_GV11B_H_*/ diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.c b/drivers/gpu/nvgpu/gv11b/therm_gv11b.c new file mode 100644 index 00000000..69d2a1fe --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/therm_gv11b.c @@ -0,0 +1,25 @@ +/* + * + * GV11B Therm + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gp10b/therm_gp10b.h" +#include "hw_therm_gv11b.h" +#include "therm_gv11b.h" + +void gv11b_init_therm_ops(struct gpu_ops *gops) +{ + gp10b_init_therm_ops(gops); +} diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/therm_gv11b.h new file mode 100644 index 00000000..2710285a --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/therm_gv11b.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef THERM_GV11B_H +#define THERM_GV11B_H + +struct gpu_ops; +void gv11b_init_therm_ops(struct gpu_ops *gops); + +#endif /* THERM_GV11B_H */ -- cgit v1.2.2 From 66f64c86a838bb9bfec049e3676debd8998e8b08 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 18 Apr 2016 09:36:13 -0700 Subject: gpu: nvgpu: gv11b: fix sparse warnings Fixed following sparse warnings: drivers/gpu/nvgpu/gv11b/gv11b.c:21:5: warning: symbol 'gv11b_init_gpu_characteristics' was not declared. Should it be static? drivers/gpu/nvgpu/gv11b/hal_gv11b.c:36:5: warning: symbol 'gv11b_init_hal' was not declared. Should it be static? drivers/gpu/nvgpu/gv11b/gr_gv11b.c:766:5: warning: symbol 'gr_gv11b_alloc_buffer' was not declared. Should it be static? Bug 200088648 Change-Id: I327f9d69bf1853727d74d2c125cfab54c2f0e5b0 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1128299 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 +++ drivers/gpu/nvgpu/gv11b/gv11b.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 3 files changed, 5 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index c8912f91..11f5fb47 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -26,5 +26,8 @@ enum { }; void gv11b_init_gr(struct gpu_ops *ops); +int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, + struct mem_desc *mem); + #endif diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index 8e8cf649..c1809f95 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c @@ -17,6 +17,7 @@ */ #include "gk20a/gk20a.h" +#include "gv11b/gv11b.h" int gv11b_init_gpu_characteristics(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a30e3263..e340c97e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -20,6 +20,7 @@ #include "gk20a/gk20a.h" +#include "gv11b/hal_gv11b.h" #include "gv11b/gr_gv11b.h" #include "gv11b/mc_gv11b.h" #include "gv11b/ltc_gv11b.h" -- cgit v1.2.2 From 4f2b0494e40c33ced3049211508ee50f75b723ea Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 18 Apr 2016 12:41:06 -0700 Subject: gpu: nvgpu: gv11b: sysmem aperture for soc memory In gv11b, soc memory needs to be accessed as sysmem instead of videmem. Bug 1749338 Change-Id: I325c107958229cf717b0b0f18dd123597d1d7567 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1128377 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h | 16 ++++++++++++++++ drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h | 8 ++++++++ drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | 20 ++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 8 ++++++++ drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 8 ++++++++ drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 8 ++++++++ drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 8 ++++++++ 7 files changed, 76 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h index 730fb0a7..cb5d2dc0 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h @@ -62,6 +62,14 @@ static inline u32 bus_bar1_block_target_vid_mem_f(void) { return 0x0; } +static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} static inline u32 bus_bar1_block_mode_virtual_f(void) { return 0x80000000; @@ -78,6 +86,14 @@ static inline u32 bus_bar2_block_target_vid_mem_f(void) { return 0x0; } +static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} static inline u32 bus_bar2_block_mode_virtual_f(void) { return 0x80000000; diff --git a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h index 29df4bdd..04055b8c 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h @@ -66,6 +66,14 @@ static inline u32 ccsr_channel_inst_target_vid_mem_f(void) { return 0x0; } +static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} static inline u32 ccsr_channel_inst_bind_false_f(void) { return 0x0; diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h index 7537f749..0a5622b4 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h @@ -106,6 +106,10 @@ static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) { return 0x0; } +static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) +{ + return 0x2; +} static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) { return (v & 0xfffffff) << 4; @@ -374,6 +378,14 @@ static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) { return 0x0; } +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} static inline u32 fb_mmu_debug_wr_vol_false_f(void) { return 0x0; @@ -402,6 +414,14 @@ static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) { return 0x0; } +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} static inline u32 fb_mmu_debug_rd_vol_false_f(void) { return 0x0; diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index a4989aba..500d2434 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h @@ -82,6 +82,14 @@ static inline u32 fifo_runlist_base_target_vid_mem_f(void) { return 0x0; } +static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} static inline u32 fifo_runlist_r(void) { return 0x00002274; diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index 37556fb9..39b7074f 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -1010,6 +1010,14 @@ static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) { return 0x0; } +static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} static inline u32 gr_fecs_current_ctx_valid_s(void) { return 1; diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h index a921d502..3863c6d6 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h @@ -322,6 +322,14 @@ static inline u32 pbdma_userd_target_vid_mem_f(void) { return 0x0; } +static inline u32 pbdma_userd_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} static inline u32 pbdma_userd_addr_f(u32 v) { return (v & 0x7fffff) << 9; diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index d60f3bd2..a19e5251 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -70,6 +70,14 @@ static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) { return 0x0; } +static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} static inline u32 ram_in_page_dir_base_vol_w(void) { return 128; -- cgit v1.2.2 From 25cdda215f04ec02c9d430ec582740ba7d4b846d Mon Sep 17 00:00:00 2001 From: Amit Sharma Date: Tue, 19 Apr 2016 11:13:45 +0530 Subject: checkpatch: add checkpatch.pl Add checkpatch.pl and dependent spelling.txt file to newly added kernel repo's. We might need to update the added files incase there is any modification happens in mentioned files within kernel-next. Bug 200192360 Change-Id: Id6eb52070ea7d76b81e9bff8461f1251a0e2c0b1 Signed-off-by: Amit Sharma Reviewed-on: http://git-master/r/1128694 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- scripts/checkpatch.pl | 5253 +++++++++++++++++++++++++++++++++++++++++++++++++ scripts/spelling.txt | 1042 ++++++++++ 2 files changed, 6295 insertions(+) create mode 100755 scripts/checkpatch.pl create mode 100644 scripts/spelling.txt diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl new file mode 100755 index 00000000..a47ea497 --- /dev/null +++ b/scripts/checkpatch.pl @@ -0,0 +1,5253 @@ +#!/usr/bin/perl -w +# (c) 2001, Dave Jones. (the file handling bit) +# (c) 2005, Joel Schopp (the ugly bit) +# (c) 2007,2008, Andy Whitcroft (new conditions, test suite) +# (c) 2008-2010 Andy Whitcroft +# Licensed under the terms of the GNU GPL License version 2 + +use strict; +use POSIX; + +my $P = $0; +$P =~ s@(.*)/@@g; +my $D = $1; + +my $V = '0.32'; + +use Getopt::Long qw(:config no_auto_abbrev); + +my $quiet = 0; +my $tree = 1; +my $chk_signoff = 1; +my $ignore_changeid = 0; +my $chk_patch = 1; +my $tst_only; +my $emacs = 0; +my $terse = 0; +my $file = 0; +my $check = 0; +my $check_orig = 0; +my $summary = 1; +my $mailback = 0; +my $summary_file = 0; +my $show_types = 0; +my $fix = 0; +my $fix_inplace = 0; +my $root; +my %debug; +my %camelcase = (); +my %use_type = (); +my @use = (); +my %ignore_type = (); +my @ignore = (); +my $help = 0; +my $configuration_file = ".checkpatch.conf"; +my $max_line_length = 80; +my $ignore_perl_version = 0; +my $minimum_perl_version = 5.10.0; +my $min_conf_desc_length = 4; +my $spelling_file = "$D/spelling.txt"; + +sub help { + my ($exitcode) = @_; + + print << "EOM"; +Usage: $P [OPTION]... [FILE]... +Version: $V + +Options: + -q, --quiet quiet + --no-tree run without a kernel tree + --no-signoff do not check for 'Signed-off-by' line + --ignore-changeid ignore Gerrit Change-Id + --patch treat FILE as patchfile (default) + --emacs emacs compile window format + --terse one line per report + -f, --file treat FILE as regular source file + --subjective, --strict enable more subjective tests + --types TYPE(,TYPE2...) show only these comma separated message types + --ignore TYPE(,TYPE2...) ignore various comma separated message types + --max-line-length=n set the maximum line length, if exceeded, warn + --min-conf-desc-length=n set the min description length, if shorter, warn + --show-types show the message "types" in the output + --root=PATH PATH to the kernel tree root + --no-summary suppress the per-file summary + --mailback only produce a report in case of warnings/errors + --summary-file include the filename in summary + --debug KEY=[0|1] turn on/off debugging of KEY, where KEY is one of + 'values', 'possible', 'type', and 'attr' (default + is all off) + --test-only=WORD report only warnings/errors containing WORD + literally + --fix EXPERIMENTAL - may create horrible results + If correctable single-line errors exist, create + ".EXPERIMENTAL-checkpatch-fixes" + with potential errors corrected to the preferred + checkpatch style + --fix-inplace EXPERIMENTAL - may create horrible results + Is the same as --fix, but overwrites the input + file. It's your fault if there's no backup or git + --ignore-perl-version override checking of perl version. expect + runtime errors. + -h, --help, --version display this help and exit + +When FILE is - read standard input. +EOM + + exit($exitcode); +} + +my $conf = which_conf($configuration_file); +if (-f $conf) { + my @conf_args; + open(my $conffile, '<', "$conf") + or warn "$P: Can't find a readable $configuration_file file $!\n"; + + while (<$conffile>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + $line =~ s/\s+/ /g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + + my @words = split(" ", $line); + foreach my $word (@words) { + last if ($word =~ m/^#/); + push (@conf_args, $word); + } + } + close($conffile); + unshift(@ARGV, @conf_args) if @conf_args; +} + +GetOptions( + 'q|quiet+' => \$quiet, + 'tree!' => \$tree, + 'signoff!' => \$chk_signoff, + 'ignore-changeid!' => \$ignore_changeid, + 'patch!' => \$chk_patch, + 'emacs!' => \$emacs, + 'terse!' => \$terse, + 'f|file!' => \$file, + 'subjective!' => \$check, + 'strict!' => \$check, + 'ignore=s' => \@ignore, + 'types=s' => \@use, + 'show-types!' => \$show_types, + 'max-line-length=i' => \$max_line_length, + 'min-conf-desc-length=i' => \$min_conf_desc_length, + 'root=s' => \$root, + 'summary!' => \$summary, + 'mailback!' => \$mailback, + 'summary-file!' => \$summary_file, + 'fix!' => \$fix, + 'fix-inplace!' => \$fix_inplace, + 'ignore-perl-version!' => \$ignore_perl_version, + 'debug=s' => \%debug, + 'test-only=s' => \$tst_only, + 'h|help' => \$help, + 'version' => \$help +) or help(1); + +help(0) if ($help); + +$fix = 1 if ($fix_inplace); +$check_orig = $check; + +my $exit = 0; + +if ($^V && $^V lt $minimum_perl_version) { + printf "$P: requires at least perl version %vd\n", $minimum_perl_version; + if (!$ignore_perl_version) { + exit(1); + } +} + +if ($#ARGV < 0) { + print "$P: no input files\n"; + exit(1); +} + +sub hash_save_array_words { + my ($hashRef, $arrayRef) = @_; + + my @array = split(/,/, join(',', @$arrayRef)); + foreach my $word (@array) { + $word =~ s/\s*\n?$//g; + $word =~ s/^\s*//g; + $word =~ s/\s+/ /g; + $word =~ tr/[a-z]/[A-Z]/; + + next if ($word =~ m/^\s*#/); + next if ($word =~ m/^\s*$/); + + $hashRef->{$word}++; + } +} + +sub hash_show_words { + my ($hashRef, $prefix) = @_; + + if ($quiet == 0 && keys %$hashRef) { + print "NOTE: $prefix message types:"; + foreach my $word (sort keys %$hashRef) { + print " $word"; + } + print "\n\n"; + } +} + +hash_save_array_words(\%ignore_type, \@ignore); +hash_save_array_words(\%use_type, \@use); + +my $dbg_values = 0; +my $dbg_possible = 0; +my $dbg_type = 0; +my $dbg_attr = 0; +for my $key (keys %debug) { + ## no critic + eval "\${dbg_$key} = '$debug{$key}';"; + die "$@" if ($@); +} + +my $rpt_cleaners = 0; + +if ($terse) { + $emacs = 1; + $quiet++; +} + +if ($tree) { + if (defined $root) { + if (!top_of_kernel_tree($root)) { + die "$P: $root: --root does not point at a valid tree\n"; + } + } else { + if (top_of_kernel_tree('.')) { + $root = '.'; + } elsif ($0 =~ m@(.*)/scripts/[^/]*$@ && + top_of_kernel_tree($1)) { + $root = $1; + } + } + + if (!defined $root) { + print "Must be run from the top-level dir. of a kernel tree\n"; + exit(2); + } +} + +my $emitted_corrupt = 0; + +our $Ident = qr{ + [A-Za-z_][A-Za-z\d_]* + (?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)* + }x; +our $Storage = qr{extern|static|asmlinkage}; +our $Sparse = qr{ + __user| + __kernel| + __force| + __iomem| + __must_check| + __init_refok| + __kprobes| + __ref| + __rcu + }x; +our $InitAttributePrefix = qr{__(?:mem|cpu|dev|net_|)}; +our $InitAttributeData = qr{$InitAttributePrefix(?:initdata\b)}; +our $InitAttributeConst = qr{$InitAttributePrefix(?:initconst\b)}; +our $InitAttributeInit = qr{$InitAttributePrefix(?:init\b)}; +our $InitAttribute = qr{$InitAttributeData|$InitAttributeConst|$InitAttributeInit}; + +# Notes to $Attribute: +# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check +our $Attribute = qr{ + const| + __percpu| + __nocast| + __safe| + __bitwise__| + __packed__| + __packed2__| + __naked| + __maybe_unused| + __always_unused| + __noreturn| + __used| + __cold| + __noclone| + __deprecated| + __read_mostly| + __kprobes| + $InitAttribute| + ____cacheline_aligned| + ____cacheline_aligned_in_smp| + ____cacheline_internodealigned_in_smp| + __weak + }x; +our $Modifier; +our $Inline = qr{inline|__always_inline|noinline|__inline|__inline__}; +our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; +our $Lval = qr{$Ident(?:$Member)*}; + +our $Int_type = qr{(?i)llu|ull|ll|lu|ul|l|u}; +our $Binary = qr{(?i)0b[01]+$Int_type?}; +our $Hex = qr{(?i)0x[0-9a-f]+$Int_type?}; +our $Int = qr{[0-9]+$Int_type?}; +our $Octal = qr{0[0-7]+$Int_type?}; +our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; +our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; +our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; +our $Float = qr{$Float_hex|$Float_dec|$Float_int}; +our $Constant = qr{$Float|$Binary|$Octal|$Hex|$Int}; +our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=}; +our $Compare = qr{<=|>=|==|!=|<|(?}; +our $Arithmetic = qr{\+|-|\*|\/|%}; +our $Operators = qr{ + <=|>=|==|!=| + =>|->|<<|>>|<|>|!|~| + &&|\|\||,|\^|\+\+|--|&|\||$Arithmetic + }x; + +our $c90_Keywords = qr{do|for|while|if|else|return|goto|continue|switch|default|case|break}x; + +our $NonptrType; +our $NonptrTypeMisordered; +our $NonptrTypeWithAttr; +our $Type; +our $TypeMisordered; +our $Declare; +our $DeclareMisordered; + +our $NON_ASCII_UTF8 = qr{ + [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte + | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs + | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte + | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates + | \xF0[\x90-\xBF][\x80-\xBF]{2} # planes 1-3 + | [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15 + | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16 +}x; + +our $UTF8 = qr{ + [\x09\x0A\x0D\x20-\x7E] # ASCII + | $NON_ASCII_UTF8 +}x; + +our $typeTypedefs = qr{(?x: + (?:__)?(?:u|s|be|le)(?:8|16|32|64)| + atomic_t +)}; + +our $logFunctions = qr{(?x: + printk(?:_ratelimited|_once|)| + (?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| + WARN(?:_RATELIMIT|_ONCE|)| + panic| + MODULE_[A-Z_]+| + seq_vprintf|seq_printf|seq_puts +)}; + +our $signature_tags = qr{(?xi: + Signed-off-by:| + Acked-by:| + Tested-by:| + Reviewed-by:| + Reported-by:| + Suggested-by:| + To:| + Cc: +)}; + +our @typeListMisordered = ( + qr{char\s+(?:un)?signed}, + qr{int\s+(?:(?:un)?signed\s+)?short\s}, + qr{int\s+short(?:\s+(?:un)?signed)}, + qr{short\s+int(?:\s+(?:un)?signed)}, + qr{(?:un)?signed\s+int\s+short}, + qr{short\s+(?:un)?signed}, + qr{long\s+int\s+(?:un)?signed}, + qr{int\s+long\s+(?:un)?signed}, + qr{long\s+(?:un)?signed\s+int}, + qr{int\s+(?:un)?signed\s+long}, + qr{int\s+(?:un)?signed}, + qr{int\s+long\s+long\s+(?:un)?signed}, + qr{long\s+long\s+int\s+(?:un)?signed}, + qr{long\s+long\s+(?:un)?signed\s+int}, + qr{long\s+long\s+(?:un)?signed}, + qr{long\s+(?:un)?signed}, +); + +our @typeList = ( + qr{void}, + qr{(?:(?:un)?signed\s+)?char}, + qr{(?:(?:un)?signed\s+)?short\s+int}, + qr{(?:(?:un)?signed\s+)?short}, + qr{(?:(?:un)?signed\s+)?int}, + qr{(?:(?:un)?signed\s+)?long\s+int}, + qr{(?:(?:un)?signed\s+)?long\s+long\s+int}, + qr{(?:(?:un)?signed\s+)?long\s+long}, + qr{(?:(?:un)?signed\s+)?long}, + qr{(?:un)?signed}, + qr{float}, + qr{double}, + qr{bool}, + qr{struct\s+$Ident}, + qr{union\s+$Ident}, + qr{enum\s+$Ident}, + qr{${Ident}_t}, + qr{${Ident}_handler}, + qr{${Ident}_handler_fn}, + @typeListMisordered, +); +our @typeListWithAttr = ( + @typeList, + qr{struct\s+$InitAttribute\s+$Ident}, + qr{union\s+$InitAttribute\s+$Ident}, +); + +our @modifierList = ( + qr{fastcall}, +); + +our @mode_permission_funcs = ( + ["module_param", 3], + ["module_param_(?:array|named|string)", 4], + ["module_param_array_named", 5], + ["debugfs_create_(?:file|u8|u16|u32|u64|x8|x16|x32|x64|size_t|atomic_t|bool|blob|regset32|u32_array)", 2], + ["proc_create(?:_data|)", 2], + ["(?:CLASS|DEVICE|SENSOR)_ATTR", 2], +); + +#Create a search pattern for all these functions to speed up a loop below +our $mode_perms_search = ""; +foreach my $entry (@mode_permission_funcs) { + $mode_perms_search .= '|' if ($mode_perms_search ne ""); + $mode_perms_search .= $entry->[0]; +} + +our $allowed_asm_includes = qr{(?x: + irq| + memory| + time| + reboot +)}; +# memory.h: ARM has a custom one + +# Load common spelling mistakes and build regular expression list. +my $misspellings; +my @spelling_list; +my %spelling_fix; +open(my $spelling, '<', $spelling_file) + or die "$P: Can't open $spelling_file for reading: $!\n"; +while (<$spelling>) { + my $line = $_; + + $line =~ s/\s*\n?$//g; + $line =~ s/^\s*//g; + + next if ($line =~ m/^\s*#/); + next if ($line =~ m/^\s*$/); + + my ($suspect, $fix) = split(/\|\|/, $line); + + push(@spelling_list, $suspect); + $spelling_fix{$suspect} = $fix; +} +close($spelling); +$misspellings = join("|", @spelling_list); + +sub build_types { + my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)"; + my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)"; + my $Misordered = "(?x: \n" . join("|\n ", @typeListMisordered) . "\n)"; + my $allWithAttr = "(?x: \n" . join("|\n ", @typeListWithAttr) . "\n)"; + $Modifier = qr{(?:$Attribute|$Sparse|$mods)}; + $NonptrType = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:typeof|__typeof__)\s*\([^\)]*\)| + (?:$typeTypedefs\b)| + (?:${all}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; + $NonptrTypeMisordered = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:${Misordered}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; + $NonptrTypeWithAttr = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:typeof|__typeof__)\s*\([^\)]*\)| + (?:$typeTypedefs\b)| + (?:${allWithAttr}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; + $Type = qr{ + $NonptrType + (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+)? + (?:\s+$Inline|\s+$Modifier)* + }x; + $TypeMisordered = qr{ + $NonptrTypeMisordered + (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*\s*(?:const\s*)?|\[\])+|(?:\s*\[\s*\])+)? + (?:\s+$Inline|\s+$Modifier)* + }x; + $Declare = qr{(?:$Storage\s+(?:$Inline\s+)?)?$Type}; + $DeclareMisordered = qr{(?:$Storage\s+(?:$Inline\s+)?)?$TypeMisordered}; +} +build_types(); + +our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*}; + +# Using $balanced_parens, $LvalOrFunc, or $FuncArg +# requires at least perl version v5.10.0 +# Any use must be runtime checked with $^V + +our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/; +our $LvalOrFunc = qr{((?:[\&\*]\s*)?$Lval)\s*($balanced_parens{0,1})\s*}; +our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)}; + +our $declaration_macros = qr{(?x: + (?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,2}\s*\(| + (?:$Storage\s+)?LIST_HEAD\s*\(| + (?:$Storage\s+)?${Type}\s+uninitialized_var\s*\( +)}; + +sub deparenthesize { + my ($string) = @_; + return "" if (!defined($string)); + + while ($string =~ /^\s*\(.*\)\s*$/) { + $string =~ s@^\s*\(\s*@@; + $string =~ s@\s*\)\s*$@@; + } + + $string =~ s@\s+@ @g; + + return $string; +} + +sub seed_camelcase_file { + my ($file) = @_; + + return if (!(-f $file)); + + local $/; + + open(my $include_file, '<', "$file") + or warn "$P: Can't read '$file' $!\n"; + my $text = <$include_file>; + close($include_file); + + my @lines = split('\n', $text); + + foreach my $line (@lines) { + next if ($line !~ /(?:[A-Z][a-z]|[a-z][A-Z])/); + if ($line =~ /^[ \t]*(?:#[ \t]*define|typedef\s+$Type)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*$Declare\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[\(\[,;]/) { + $camelcase{$1} = 1; + } elsif ($line =~ /^\s*(?:union|struct|enum)\s+(\w*(?:[A-Z][a-z]|[a-z][A-Z])\w*)\s*[;\{]/) { + $camelcase{$1} = 1; + } + } +} + +my $camelcase_seeded = 0; +sub seed_camelcase_includes { + return if ($camelcase_seeded); + + my $files; + my $camelcase_cache = ""; + my @include_files = (); + + $camelcase_seeded = 1; + + if (-e ".git") { + my $git_last_include_commit = `git log --no-merges --pretty=format:"%h%n" -1 -- include`; + chomp $git_last_include_commit; + $camelcase_cache = ".checkpatch-camelcase.git.$git_last_include_commit"; + } else { + my $last_mod_date = 0; + $files = `find $root/include -name "*.h"`; + @include_files = split('\n', $files); + foreach my $file (@include_files) { + my $date = POSIX::strftime("%Y%m%d%H%M", + localtime((stat $file)[9])); + $last_mod_date = $date if ($last_mod_date < $date); + } + $camelcase_cache = ".checkpatch-camelcase.date.$last_mod_date"; + } + + if ($camelcase_cache ne "" && -f $camelcase_cache) { + open(my $camelcase_file, '<', "$camelcase_cache") + or warn "$P: Can't read '$camelcase_cache' $!\n"; + while (<$camelcase_file>) { + chomp; + $camelcase{$_} = 1; + } + close($camelcase_file); + + return; + } + + if (-e ".git") { + $files = `git ls-files "include/*.h"`; + @include_files = split('\n', $files); + } + + foreach my $file (@include_files) { + seed_camelcase_file($file); + } + + if ($camelcase_cache ne "") { + unlink glob ".checkpatch-camelcase.*"; + open(my $camelcase_file, '>', "$camelcase_cache") + or warn "$P: Can't write '$camelcase_cache' $!\n"; + foreach (sort { lc($a) cmp lc($b) } keys(%camelcase)) { + print $camelcase_file ("$_\n"); + } + close($camelcase_file); + } +} + +sub git_commit_info { + my ($commit, $id, $desc) = @_; + + return ($id, $desc) if ((which("git") eq "") || !(-e ".git")); + + my $output = `git log --no-color --format='%H %s' -1 $commit 2>&1`; + $output =~ s/^\s*//gm; + my @lines = split("\n", $output); + + if ($lines[0] =~ /^error: short SHA1 $commit is ambiguous\./) { +# Maybe one day convert this block of bash into something that returns +# all matching commit ids, but it's very slow... +# +# echo "checking commits $1..." +# git rev-list --remotes | grep -i "^$1" | +# while read line ; do +# git log --format='%H %s' -1 $line | +# echo "commit $(cut -c 1-12,41-)" +# done + } elsif ($lines[0] =~ /^fatal: ambiguous argument '$commit': unknown revision or path not in the working tree\./) { + } else { + $id = substr($lines[0], 0, 12); + $desc = substr($lines[0], 41); + } + + return ($id, $desc); +} + +$chk_signoff = 0 if ($file); + +my @rawlines = (); +my @lines = (); +my @fixed = (); +my @fixed_inserted = (); +my @fixed_deleted = (); +my $fixlinenr = -1; + +my $vname; +for my $filename (@ARGV) { + my $FILE; + if ($file) { + open($FILE, '-|', "diff -u /dev/null $filename") || + die "$P: $filename: diff failed - $!\n"; + } elsif ($filename eq '-') { + open($FILE, '<&STDIN'); + } else { + open($FILE, '<', "$filename") || + die "$P: $filename: open failed - $!\n"; + } + if ($filename eq '-') { + $vname = 'Your patch'; + } else { + $vname = $filename; + } + while (<$FILE>) { + chomp; + push(@rawlines, $_); + } + close($FILE); + if (!process($filename)) { + $exit = 1; + } + @rawlines = (); + @lines = (); + @fixed = (); + @fixed_inserted = (); + @fixed_deleted = (); + $fixlinenr = -1; +} + +exit($exit); + +sub top_of_kernel_tree { + my ($root) = @_; + + my @tree_check = ( + "COPYING", "CREDITS", "Kbuild", "MAINTAINERS", "Makefile", + "README", "Documentation", "arch", "include", "drivers", + "fs", "init", "ipc", "kernel", "lib", "scripts", + ); + + foreach my $check (@tree_check) { + if (! -e $root . '/' . $check) { + return 0; + } + } + return 1; +} + +sub parse_email { + my ($formatted_email) = @_; + + my $name = ""; + my $address = ""; + my $comment = ""; + + if ($formatted_email =~ /^(.*)<(\S+\@\S+)>(.*)$/) { + $name = $1; + $address = $2; + $comment = $3 if defined $3; + } elsif ($formatted_email =~ /^\s*<(\S+\@\S+)>(.*)$/) { + $address = $1; + $comment = $2 if defined $2; + } elsif ($formatted_email =~ /(\S+\@\S+)(.*)$/) { + $address = $1; + $comment = $2 if defined $2; + $formatted_email =~ s/$address.*$//; + $name = $formatted_email; + $name = trim($name); + $name =~ s/^\"|\"$//g; + # If there's a name left after stripping spaces and + # leading quotes, and the address doesn't have both + # leading and trailing angle brackets, the address + # is invalid. ie: + # "joe smith joe@smith.com" bad + # "joe smith ]+>$/) { + $name = ""; + $address = ""; + $comment = ""; + } + } + + $name = trim($name); + $name =~ s/^\"|\"$//g; + $address = trim($address); + $address =~ s/^\<|\>$//g; + + if ($name =~ /[^\w \-]/i) { ##has "must quote" chars + $name =~ s/(?"; + } + + return $formatted_email; +} + +sub which { + my ($bin) = @_; + + foreach my $path (split(/:/, $ENV{PATH})) { + if (-e "$path/$bin") { + return "$path/$bin"; + } + } + + return ""; +} + +sub which_conf { + my ($conf) = @_; + + foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) { + if (-e "$path/$conf") { + return "$path/$conf"; + } + } + + return ""; +} + +sub expand_tabs { + my ($str) = @_; + + my $res = ''; + my $n = 0; + for my $c (split(//, $str)) { + if ($c eq "\t") { + $res .= ' '; + $n++; + for (; ($n % 8) != 0; $n++) { + $res .= ' '; + } + next; + } + $res .= $c; + $n++; + } + + return $res; +} +sub copy_spacing { + (my $res = shift) =~ tr/\t/ /c; + return $res; +} + +sub line_stats { + my ($line) = @_; + + # Drop the diff line leader and expand tabs + $line =~ s/^.//; + $line = expand_tabs($line); + + # Pick the indent from the front of the line. + my ($white) = ($line =~ /^(\s*)/); + + return (length($line), length($white)); +} + +my $sanitise_quote = ''; + +sub sanitise_line_reset { + my ($in_comment) = @_; + + if ($in_comment) { + $sanitise_quote = '*/'; + } else { + $sanitise_quote = ''; + } +} +sub sanitise_line { + my ($line) = @_; + + my $res = ''; + my $l = ''; + + my $qlen = 0; + my $off = 0; + my $c; + + # Always copy over the diff marker. + $res = substr($line, 0, 1); + + for ($off = 1; $off < length($line); $off++) { + $c = substr($line, $off, 1); + + # Comments we are wacking completly including the begin + # and end, all to $;. + if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') { + $sanitise_quote = '*/'; + + substr($res, $off, 2, "$;$;"); + $off++; + next; + } + if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') { + $sanitise_quote = ''; + substr($res, $off, 2, "$;$;"); + $off++; + next; + } + if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') { + $sanitise_quote = '//'; + + substr($res, $off, 2, $sanitise_quote); + $off++; + next; + } + + # A \ in a string means ignore the next character. + if (($sanitise_quote eq "'" || $sanitise_quote eq '"') && + $c eq "\\") { + substr($res, $off, 2, 'XX'); + $off++; + next; + } + # Regular quotes. + if ($c eq "'" || $c eq '"') { + if ($sanitise_quote eq '') { + $sanitise_quote = $c; + + substr($res, $off, 1, $c); + next; + } elsif ($sanitise_quote eq $c) { + $sanitise_quote = ''; + } + } + + #print "c<$c> SQ<$sanitise_quote>\n"; + if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") { + substr($res, $off, 1, $;); + } elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") { + substr($res, $off, 1, $;); + } elsif ($off != 0 && $sanitise_quote && $c ne "\t") { + substr($res, $off, 1, 'X'); + } else { + substr($res, $off, 1, $c); + } + } + + if ($sanitise_quote eq '//') { + $sanitise_quote = ''; + } + + # The pathname on a #include may be surrounded by '<' and '>'. + if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) { + my $clean = 'X' x length($1); + $res =~ s@\<.*\>@<$clean>@; + + # The whole of a #error is a string. + } elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) { + my $clean = 'X' x length($1); + $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@; + } + + return $res; +} + +sub get_quoted_string { + my ($line, $rawline) = @_; + + return "" if ($line !~ m/(\"[X]+\")/g); + return substr($rawline, $-[0], $+[0] - $-[0]); +} + +sub ctx_statement_block { + my ($linenr, $remain, $off) = @_; + my $line = $linenr - 1; + my $blk = ''; + my $soff = $off; + my $coff = $off - 1; + my $coff_set = 0; + + my $loff = 0; + + my $type = ''; + my $level = 0; + my @stack = (); + my $p; + my $c; + my $len = 0; + + my $remainder; + while (1) { + @stack = (['', 0]) if ($#stack == -1); + + #warn "CSB: blk<$blk> remain<$remain>\n"; + # If we are about to drop off the end, pull in more + # context. + if ($off >= $len) { + for (; $remain > 0; $line++) { + last if (!defined $lines[$line]); + next if ($lines[$line] =~ /^-/); + $remain--; + $loff = $len; + $blk .= $lines[$line] . "\n"; + $len = length($blk); + $line++; + last; + } + # Bail if there is no further context. + #warn "CSB: blk<$blk> off<$off> len<$len>\n"; + if ($off >= $len) { + last; + } + if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) { + $level++; + $type = '#'; + } + } + $p = $c; + $c = substr($blk, $off, 1); + $remainder = substr($blk, $off); + + #warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n"; + + # Handle nested #if/#else. + if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) { + push(@stack, [ $type, $level ]); + } elsif ($remainder =~ /^#\s*(?:else|elif)\b/) { + ($type, $level) = @{$stack[$#stack - 1]}; + } elsif ($remainder =~ /^#\s*endif\b/) { + ($type, $level) = @{pop(@stack)}; + } + + # Statement ends at the ';' or a close '}' at the + # outermost level. + if ($level == 0 && $c eq ';') { + last; + } + + # An else is really a conditional as long as its not else if + if ($level == 0 && $coff_set == 0 && + (!defined($p) || $p =~ /(?:\s|\}|\+)/) && + $remainder =~ /^(else)(?:\s|{)/ && + $remainder !~ /^else\s+if\b/) { + $coff = $off + length($1) - 1; + $coff_set = 1; + #warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n"; + #warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n"; + } + + if (($type eq '' || $type eq '(') && $c eq '(') { + $level++; + $type = '('; + } + if ($type eq '(' && $c eq ')') { + $level--; + $type = ($level != 0)? '(' : ''; + + if ($level == 0 && $coff < $soff) { + $coff = $off; + $coff_set = 1; + #warn "CSB: mark coff<$coff>\n"; + } + } + if (($type eq '' || $type eq '{') && $c eq '{') { + $level++; + $type = '{'; + } + if ($type eq '{' && $c eq '}') { + $level--; + $type = ($level != 0)? '{' : ''; + + if ($level == 0) { + if (substr($blk, $off + 1, 1) eq ';') { + $off++; + } + last; + } + } + # Preprocessor commands end at the newline unless escaped. + if ($type eq '#' && $c eq "\n" && $p ne "\\") { + $level--; + $type = ''; + $off++; + last; + } + $off++; + } + # We are truly at the end, so shuffle to the next line. + if ($off == $len) { + $loff = $len + 1; + $line++; + $remain--; + } + + my $statement = substr($blk, $soff, $off - $soff + 1); + my $condition = substr($blk, $soff, $coff - $soff + 1); + + #warn "STATEMENT<$statement>\n"; + #warn "CONDITION<$condition>\n"; + + #print "coff<$coff> soff<$off> loff<$loff>\n"; + + return ($statement, $condition, + $line, $remain + 1, $off - $loff + 1, $level); +} + +sub statement_lines { + my ($stmt) = @_; + + # Strip the diff line prefixes and rip blank lines at start and end. + $stmt =~ s/(^|\n)./$1/g; + $stmt =~ s/^\s*//; + $stmt =~ s/\s*$//; + + my @stmt_lines = ($stmt =~ /\n/g); + + return $#stmt_lines + 2; +} + +sub statement_rawlines { + my ($stmt) = @_; + + my @stmt_lines = ($stmt =~ /\n/g); + + return $#stmt_lines + 2; +} + +sub statement_block_size { + my ($stmt) = @_; + + $stmt =~ s/(^|\n)./$1/g; + $stmt =~ s/^\s*{//; + $stmt =~ s/}\s*$//; + $stmt =~ s/^\s*//; + $stmt =~ s/\s*$//; + + my @stmt_lines = ($stmt =~ /\n/g); + my @stmt_statements = ($stmt =~ /;/g); + + my $stmt_lines = $#stmt_lines + 2; + my $stmt_statements = $#stmt_statements + 1; + + if ($stmt_lines > $stmt_statements) { + return $stmt_lines; + } else { + return $stmt_statements; + } +} + +sub ctx_statement_full { + my ($linenr, $remain, $off) = @_; + my ($statement, $condition, $level); + + my (@chunks); + + # Grab the first conditional/block pair. + ($statement, $condition, $linenr, $remain, $off, $level) = + ctx_statement_block($linenr, $remain, $off); + #print "F: c<$condition> s<$statement> remain<$remain>\n"; + push(@chunks, [ $condition, $statement ]); + if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) { + return ($level, $linenr, @chunks); + } + + # Pull in the following conditional/block pairs and see if they + # could continue the statement. + for (;;) { + ($statement, $condition, $linenr, $remain, $off, $level) = + ctx_statement_block($linenr, $remain, $off); + #print "C: c<$condition> s<$statement> remain<$remain>\n"; + last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s)); + #print "C: push\n"; + push(@chunks, [ $condition, $statement ]); + } + + return ($level, $linenr, @chunks); +} + +sub ctx_block_get { + my ($linenr, $remain, $outer, $open, $close, $off) = @_; + my $line; + my $start = $linenr - 1; + my $blk = ''; + my @o; + my @c; + my @res = (); + + my $level = 0; + my @stack = ($level); + for ($line = $start; $remain > 0; $line++) { + next if ($rawlines[$line] =~ /^-/); + $remain--; + + $blk .= $rawlines[$line]; + + # Handle nested #if/#else. + if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) { + push(@stack, $level); + } elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) { + $level = $stack[$#stack - 1]; + } elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) { + $level = pop(@stack); + } + + foreach my $c (split(//, $lines[$line])) { + ##print "C<$c>L<$level><$open$close>O<$off>\n"; + if ($off > 0) { + $off--; + next; + } + + if ($c eq $close && $level > 0) { + $level--; + last if ($level == 0); + } elsif ($c eq $open) { + $level++; + } + } + + if (!$outer || $level <= 1) { + push(@res, $rawlines[$line]); + } + + last if ($level == 0); + } + + return ($level, @res); +} +sub ctx_block_outer { + my ($linenr, $remain) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0); + return @r; +} +sub ctx_block { + my ($linenr, $remain) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0); + return @r; +} +sub ctx_statement { + my ($linenr, $remain, $off) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off); + return @r; +} +sub ctx_block_level { + my ($linenr, $remain) = @_; + + return ctx_block_get($linenr, $remain, 0, '{', '}', 0); +} +sub ctx_statement_level { + my ($linenr, $remain, $off) = @_; + + return ctx_block_get($linenr, $remain, 0, '(', ')', $off); +} + +sub ctx_locate_comment { + my ($first_line, $end_line) = @_; + + # Catch a comment on the end of the line itself. + my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); + return $current_comment if (defined $current_comment); + + # Look through the context and try and figure out if there is a + # comment. + my $in_comment = 0; + $current_comment = ''; + for (my $linenr = $first_line; $linenr < $end_line; $linenr++) { + my $line = $rawlines[$linenr - 1]; + #warn " $line\n"; + if ($linenr == $first_line and $line =~ m@^.\s*\*@) { + $in_comment = 1; + } + if ($line =~ m@/\*@) { + $in_comment = 1; + } + if (!$in_comment && $current_comment ne '') { + $current_comment = ''; + } + $current_comment .= $line . "\n" if ($in_comment); + if ($line =~ m@\*/@) { + $in_comment = 0; + } + } + + chomp($current_comment); + return($current_comment); +} +sub ctx_has_comment { + my ($first_line, $end_line) = @_; + my $cmt = ctx_locate_comment($first_line, $end_line); + + ##print "LINE: $rawlines[$end_line - 1 ]\n"; + ##print "CMMT: $cmt\n"; + + return ($cmt ne ''); +} + +sub raw_line { + my ($linenr, $cnt) = @_; + + my $offset = $linenr - 1; + $cnt++; + + my $line; + while ($cnt) { + $line = $rawlines[$offset++]; + next if (defined($line) && $line =~ /^-/); + $cnt--; + } + + return $line; +} + +sub cat_vet { + my ($vet) = @_; + my ($res, $coded); + + $res = ''; + while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) { + $res .= $1; + if ($2 ne '') { + $coded = sprintf("^%c", unpack('C', $2) + 64); + $res .= $coded; + } + } + $res =~ s/$/\$/; + + return $res; +} + +my $av_preprocessor = 0; +my $av_pending; +my @av_paren_type; +my $av_pend_colon; + +sub annotate_reset { + $av_preprocessor = 0; + $av_pending = '_'; + @av_paren_type = ('E'); + $av_pend_colon = 'O'; +} + +sub annotate_values { + my ($stream, $type) = @_; + + my $res; + my $var = '_' x length($stream); + my $cur = $stream; + + print "$stream\n" if ($dbg_values > 1); + + while (length($cur)) { + @av_paren_type = ('E') if ($#av_paren_type < 0); + print " <" . join('', @av_paren_type) . + "> <$type> <$av_pending>" if ($dbg_values > 1); + if ($cur =~ /^(\s+)/o) { + print "WS($1)\n" if ($dbg_values > 1); + if ($1 =~ /\n/ && $av_preprocessor) { + $type = pop(@av_paren_type); + $av_preprocessor = 0; + } + + } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') { + print "CAST($1)\n" if ($dbg_values > 1); + push(@av_paren_type, $type); + $type = 'c'; + + } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) { + print "DECLARE($1)\n" if ($dbg_values > 1); + $type = 'T'; + + } elsif ($cur =~ /^($Modifier)\s*/) { + print "MODIFIER($1)\n" if ($dbg_values > 1); + $type = 'T'; + + } elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) { + print "DEFINE($1,$2)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + push(@av_paren_type, $type); + if ($2 ne '') { + $av_pending = 'N'; + } + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) { + print "UNDEF($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + push(@av_paren_type, $type); + + } elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) { + print "PRE_START($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + + push(@av_paren_type, $type); + push(@av_paren_type, $type); + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:else|elif))/o) { + print "PRE_RESTART($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + + push(@av_paren_type, $av_paren_type[$#av_paren_type]); + + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:endif))/o) { + print "PRE_END($1)\n" if ($dbg_values > 1); + + $av_preprocessor = 1; + + # Assume all arms of the conditional end as this + # one does, and continue as if the #endif was not here. + pop(@av_paren_type); + push(@av_paren_type, $type); + $type = 'E'; + + } elsif ($cur =~ /^(\\\n)/o) { + print "PRECONT($1)\n" if ($dbg_values > 1); + + } elsif ($cur =~ /^(__attribute__)\s*\(?/o) { + print "ATTR($1)\n" if ($dbg_values > 1); + $av_pending = $type; + $type = 'N'; + + } elsif ($cur =~ /^(sizeof)\s*(\()?/o) { + print "SIZEOF($1)\n" if ($dbg_values > 1); + if (defined $2) { + $av_pending = 'V'; + } + $type = 'N'; + + } elsif ($cur =~ /^(if|while|for)\b/o) { + print "COND($1)\n" if ($dbg_values > 1); + $av_pending = 'E'; + $type = 'N'; + + } elsif ($cur =~/^(case)/o) { + print "CASE($1)\n" if ($dbg_values > 1); + $av_pend_colon = 'C'; + $type = 'N'; + + } elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) { + print "KEYWORD($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(\()/o) { + print "PAREN('$1')\n" if ($dbg_values > 1); + push(@av_paren_type, $av_pending); + $av_pending = '_'; + $type = 'N'; + + } elsif ($cur =~ /^(\))/o) { + my $new_type = pop(@av_paren_type); + if ($new_type ne '_') { + $type = $new_type; + print "PAREN('$1') -> $type\n" + if ($dbg_values > 1); + } else { + print "PAREN('$1')\n" if ($dbg_values > 1); + } + + } elsif ($cur =~ /^($Ident)\s*\(/o) { + print "FUNC($1)\n" if ($dbg_values > 1); + $type = 'V'; + $av_pending = 'V'; + + } elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) { + if (defined $2 && $type eq 'C' || $type eq 'T') { + $av_pend_colon = 'B'; + } elsif ($type eq 'E') { + $av_pend_colon = 'L'; + } + print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1); + $type = 'V'; + + } elsif ($cur =~ /^($Ident|$Constant)/o) { + print "IDENT($1)\n" if ($dbg_values > 1); + $type = 'V'; + + } elsif ($cur =~ /^($Assignment)/o) { + print "ASSIGN($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~/^(;|{|})/) { + print "END($1)\n" if ($dbg_values > 1); + $type = 'E'; + $av_pend_colon = 'O'; + + } elsif ($cur =~/^(,)/) { + print "COMMA($1)\n" if ($dbg_values > 1); + $type = 'C'; + + } elsif ($cur =~ /^(\?)/o) { + print "QUESTION($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(:)/o) { + print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1); + + substr($var, length($res), 1, $av_pend_colon); + if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') { + $type = 'E'; + } else { + $type = 'N'; + } + $av_pend_colon = 'O'; + + } elsif ($cur =~ /^(\[)/o) { + print "CLOSE($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) { + my $variant; + + print "OPV($1)\n" if ($dbg_values > 1); + if ($type eq 'V') { + $variant = 'B'; + } else { + $variant = 'U'; + } + + substr($var, length($res), 1, $variant); + $type = 'N'; + + } elsif ($cur =~ /^($Operators)/o) { + print "OP($1)\n" if ($dbg_values > 1); + if ($1 ne '++' && $1 ne '--') { + $type = 'N'; + } + + } elsif ($cur =~ /(^.)/o) { + print "C($1)\n" if ($dbg_values > 1); + } + if (defined $1) { + $cur = substr($cur, length($1)); + $res .= $type x length($1); + } + } + + return ($res, $var); +} + +sub possible { + my ($possible, $line) = @_; + my $notPermitted = qr{(?: + ^(?: + $Modifier| + $Storage| + $Type| + DEFINE_\S+ + )$| + ^(?: + goto| + return| + case| + else| + asm|__asm__| + do| + \#| + \#\#| + )(?:\s|$)| + ^(?:typedef|struct|enum)\b + )}x; + warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2); + if ($possible !~ $notPermitted) { + # Check for modifiers. + $possible =~ s/\s*$Storage\s*//g; + $possible =~ s/\s*$Sparse\s*//g; + if ($possible =~ /^\s*$/) { + + } elsif ($possible =~ /\s/) { + $possible =~ s/\s*$Type\s*//g; + for my $modifier (split(' ', $possible)) { + if ($modifier !~ $notPermitted) { + warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible); + push(@modifierList, $modifier); + } + } + + } else { + warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible); + push(@typeList, $possible); + } + build_types(); + } else { + warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1); + } +} + +my $prefix = ''; + +sub show_type { + my ($type) = @_; + + return defined $use_type{$type} if (scalar keys %use_type > 0); + + return !defined $ignore_type{$type}; +} + +sub report { + my ($level, $type, $msg) = @_; + + if (!show_type($type) || + (defined $tst_only && $msg !~ /\Q$tst_only\E/)) { + return 0; + } + my $line; + if ($show_types) { + $line = "$prefix$level:$type: $msg\n"; + } else { + $line = "$prefix$level: $msg\n"; + } + $line = (split('\n', $line))[0] . "\n" if ($terse); + + push(our @report, $line); + + return 1; +} + +sub report_dump { + our @report; +} + +sub fixup_current_range { + my ($lineRef, $offset, $length) = @_; + + if ($$lineRef =~ /^\@\@ -\d+,\d+ \+(\d+),(\d+) \@\@/) { + my $o = $1; + my $l = $2; + my $no = $o + $offset; + my $nl = $l + $length; + $$lineRef =~ s/\+$o,$l \@\@/\+$no,$nl \@\@/; + } +} + +sub fix_inserted_deleted_lines { + my ($linesRef, $insertedRef, $deletedRef) = @_; + + my $range_last_linenr = 0; + my $delta_offset = 0; + + my $old_linenr = 0; + my $new_linenr = 0; + + my $next_insert = 0; + my $next_delete = 0; + + my @lines = (); + + my $inserted = @{$insertedRef}[$next_insert++]; + my $deleted = @{$deletedRef}[$next_delete++]; + + foreach my $old_line (@{$linesRef}) { + my $save_line = 1; + my $line = $old_line; #don't modify the array + if ($line =~ /^(?:\+\+\+\|\-\-\-)\s+\S+/) { #new filename + $delta_offset = 0; + } elsif ($line =~ /^\@\@ -\d+,\d+ \+\d+,\d+ \@\@/) { #new hunk + $range_last_linenr = $new_linenr; + fixup_current_range(\$line, $delta_offset, 0); + } + + while (defined($deleted) && ${$deleted}{'LINENR'} == $old_linenr) { + $deleted = @{$deletedRef}[$next_delete++]; + $save_line = 0; + fixup_current_range(\$lines[$range_last_linenr], $delta_offset--, -1); + } + + while (defined($inserted) && ${$inserted}{'LINENR'} == $old_linenr) { + push(@lines, ${$inserted}{'LINE'}); + $inserted = @{$insertedRef}[$next_insert++]; + $new_linenr++; + fixup_current_range(\$lines[$range_last_linenr], $delta_offset++, 1); + } + + if ($save_line) { + push(@lines, $line); + $new_linenr++; + } + + $old_linenr++; + } + + return @lines; +} + +sub fix_insert_line { + my ($linenr, $line) = @_; + + my $inserted = { + LINENR => $linenr, + LINE => $line, + }; + push(@fixed_inserted, $inserted); +} + +sub fix_delete_line { + my ($linenr, $line) = @_; + + my $deleted = { + LINENR => $linenr, + LINE => $line, + }; + + push(@fixed_deleted, $deleted); +} + +sub ERROR { + my ($type, $msg) = @_; + + if (report("ERROR", $type, $msg)) { + our $clean = 0; + our $cnt_error++; + return 1; + } + return 0; +} +sub WARN { + my ($type, $msg) = @_; + + if (report("WARNING", $type, $msg)) { + our $clean = 0; + our $cnt_warn++; + return 1; + } + return 0; +} +sub CHK { + my ($type, $msg) = @_; + + if ($check && report("CHECK", $type, $msg)) { + our $clean = 0; + our $cnt_chk++; + return 1; + } + return 0; +} + +sub check_absolute_file { + my ($absolute, $herecurr) = @_; + my $file = $absolute; + + ##print "absolute<$absolute>\n"; + + # See if any suffix of this path is a path within the tree. + while ($file =~ s@^[^/]*/@@) { + if (-f "$root/$file") { + ##print "file<$file>\n"; + last; + } + } + if (! -f _) { + return 0; + } + + # It is, so see if the prefix is acceptable. + my $prefix = $absolute; + substr($prefix, -length($file)) = ''; + + ##print "prefix<$prefix>\n"; + if ($prefix ne ".../") { + WARN("USE_RELATIVE_PATH", + "use relative pathname instead of absolute in changelog text\n" . $herecurr); + } +} + +sub trim { + my ($string) = @_; + + $string =~ s/^\s+|\s+$//g; + + return $string; +} + +sub ltrim { + my ($string) = @_; + + $string =~ s/^\s+//; + + return $string; +} + +sub rtrim { + my ($string) = @_; + + $string =~ s/\s+$//; + + return $string; +} + +sub string_find_replace { + my ($string, $find, $replace) = @_; + + $string =~ s/$find/$replace/g; + + return $string; +} + +sub tabify { + my ($leading) = @_; + + my $source_indent = 8; + my $max_spaces_before_tab = $source_indent - 1; + my $spaces_to_tab = " " x $source_indent; + + #convert leading spaces to tabs + 1 while $leading =~ s@^([\t]*)$spaces_to_tab@$1\t@g; + #Remove spaces before a tab + 1 while $leading =~ s@^([\t]*)( {1,$max_spaces_before_tab})\t@$1\t@g; + + return "$leading"; +} + +sub pos_last_openparen { + my ($line) = @_; + + my $pos = 0; + + my $opens = $line =~ tr/\(/\(/; + my $closes = $line =~ tr/\)/\)/; + + my $last_openparen = 0; + + if (($opens == 0) || ($closes >= $opens)) { + return -1; + } + + my $len = length($line); + + for ($pos = 0; $pos < $len; $pos++) { + my $string = substr($line, $pos); + if ($string =~ /^($FuncArg|$balanced_parens)/) { + $pos += length($1) - 1; + } elsif (substr($line, $pos, 1) eq '(') { + $last_openparen = $pos; + } elsif (index($string, '(') == -1) { + last; + } + } + + return length(expand_tabs(substr($line, 0, $last_openparen))) + 1; +} + +sub process { + my $filename = shift; + + my $linenr=0; + my $prevline=""; + my $prevrawline=""; + my $stashline=""; + my $stashrawline=""; + + my $length; + my $indent; + my $previndent=0; + my $stashindent=0; + + our $clean = 1; + my $signoff = 0; + my $is_patch = 0; + + my $in_header_lines = $file ? 0 : 1; + my $in_commit_log = 0; #Scanning lines before patch + my $reported_maintainer_file = 0; + my $non_utf8_charset = 0; + + my $last_blank_line = 0; + + our @report = (); + our $cnt_lines = 0; + our $cnt_error = 0; + our $cnt_warn = 0; + our $cnt_chk = 0; + + # Trace the real file/line as we go. + my $realfile = ''; + my $realline = 0; + my $realcnt = 0; + my $here = ''; + my $in_comment = 0; + my $comment_edge = 0; + my $first_line = 0; + my $p1_prefix = ''; + + my $prev_values = 'E'; + + # suppression flags + my %suppress_ifbraces; + my %suppress_whiletrailers; + my %suppress_export; + my $suppress_statement = 0; + + my %signatures = (); + + # Pre-scan the patch sanitizing the lines. + # Pre-scan the patch looking for any __setup documentation. + # + my @setup_docs = (); + my $setup_docs = 0; + + my $camelcase_file_seeded = 0; + + sanitise_line_reset(); + my $line; + foreach my $rawline (@rawlines) { + $linenr++; + $line = $rawline; + + push(@fixed, $rawline) if ($fix); + + if ($rawline=~/^\+\+\+\s+(\S+)/) { + $setup_docs = 0; + if ($1 =~ m@Documentation/kernel-parameters.txt$@) { + $setup_docs = 1; + } + #next; + } + if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { + $realline=$1-1; + if (defined $2) { + $realcnt=$3+1; + } else { + $realcnt=1+1; + } + $in_comment = 0; + + # Guestimate if this is a continuing comment. Run + # the context looking for a comment "edge". If this + # edge is a close comment then we must be in a comment + # at context start. + my $edge; + my $cnt = $realcnt; + for (my $ln = $linenr + 1; $cnt > 0; $ln++) { + next if (defined $rawlines[$ln - 1] && + $rawlines[$ln - 1] =~ /^-/); + $cnt--; + #print "RAW<$rawlines[$ln - 1]>\n"; + last if (!defined $rawlines[$ln - 1]); + if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ && + $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) { + ($edge) = $1; + last; + } + } + if (defined $edge && $edge eq '*/') { + $in_comment = 1; + } + + # Guestimate if this is a continuing comment. If this + # is the start of a diff block and this line starts + # ' *' then it is very likely a comment. + if (!defined $edge && + $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@) + { + $in_comment = 1; + } + + ##print "COMMENT:$in_comment edge<$edge> $rawline\n"; + sanitise_line_reset($in_comment); + + } elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) { + # Standardise the strings and chars within the input to + # simplify matching -- only bother with positive lines. + $line = sanitise_line($rawline); + } + push(@lines, $line); + + if ($realcnt > 1) { + $realcnt-- if ($line =~ /^(?:\+| |$)/); + } else { + $realcnt = 0; + } + + #print "==>$rawline\n"; + #print "-->$line\n"; + + if ($setup_docs && $line =~ /^\+/) { + push(@setup_docs, $line); + } + } + + $prefix = ''; + + $realcnt = 0; + $linenr = 0; + $fixlinenr = -1; + foreach my $line (@lines) { + $linenr++; + $fixlinenr++; + my $sline = $line; #copy of $line + $sline =~ s/$;/ /g; #with comments as spaces + + my $rawline = $rawlines[$linenr - 1]; + +#extract the line range in the file after the patch is applied + if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { + $is_patch = 1; + $first_line = $linenr + 1; + $realline=$1-1; + if (defined $2) { + $realcnt=$3+1; + } else { + $realcnt=1+1; + } + annotate_reset(); + $prev_values = 'E'; + + %suppress_ifbraces = (); + %suppress_whiletrailers = (); + %suppress_export = (); + $suppress_statement = 0; + next; + +# track the line number as we move through the hunk, note that +# new versions of GNU diff omit the leading space on completely +# blank context lines so we need to count that too. + } elsif ($line =~ /^( |\+|$)/) { + $realline++; + $realcnt-- if ($realcnt != 0); + + # Measure the line length and indent. + ($length, $indent) = line_stats($rawline); + + # Track the previous line. + ($prevline, $stashline) = ($stashline, $line); + ($previndent, $stashindent) = ($stashindent, $indent); + ($prevrawline, $stashrawline) = ($stashrawline, $rawline); + + #warn "line<$line>\n"; + + } elsif ($realcnt == 1) { + $realcnt--; + } + + my $hunk_line = ($realcnt != 0); + +#make up the handle for any error we report on this line + $prefix = "$filename:$realline: " if ($emacs && $file); + $prefix = "$filename:$linenr: " if ($emacs && !$file); + + $here = "#$linenr: " if (!$file); + $here = "#$realline: " if ($file); + + my $found_file = 0; + # extract the filename as it passes + if ($line =~ /^diff --git.*?(\S+)$/) { + $realfile = $1; + $realfile =~ s@^([^/]*)/@@ if (!$file); + $in_commit_log = 0; + $found_file = 1; + } elsif ($line =~ /^\+\+\+\s+(\S+)/) { + $realfile = $1; + $realfile =~ s@^([^/]*)/@@ if (!$file); + $in_commit_log = 0; + + $p1_prefix = $1; + if (!$file && $tree && $p1_prefix ne '' && + -e "$root/$p1_prefix") { + WARN("PATCH_PREFIX", + "patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n"); + } + + if ($realfile =~ m@^include/asm/@) { + ERROR("MODIFIED_INCLUDE_ASM", + "do not modify files in include/asm, change architecture specific files in include/asm-\n" . "$here$rawline\n"); + } + $found_file = 1; + } + + if ($found_file) { + if ($realfile =~ m@^(drivers/net/|net/)@) { + $check = 1; + } else { + $check = $check_orig; + } + next; + } + + $here .= "FILE: $realfile:$realline:" if ($realcnt != 0); + + my $hereline = "$here\n$rawline\n"; + my $herecurr = "$here\n$rawline\n"; + my $hereprev = "$here\n$prevrawline\n$rawline\n"; + + $cnt_lines++ if ($realcnt != 0); + +# Check for incorrect file permissions + if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) { + my $permhere = $here . "FILE: $realfile\n"; + if ($realfile !~ m@scripts/@ && + $realfile !~ /\.(py|pl|awk|sh)$/) { + ERROR("EXECUTE_PERMISSIONS", + "do not set execute permissions for source files\n" . $permhere); + } + } + +# Check the patch for a signoff: + if ($line =~ /^\s*signed-off-by:/i) { + $signoff++; + $in_commit_log = 0; + } + +# Check signature styles + if (!$in_header_lines && + $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) { + my $space_before = $1; + my $sign_off = $2; + my $space_after = $3; + my $email = $4; + my $ucfirst_sign_off = ucfirst(lc($sign_off)); + + if ($sign_off !~ /$signature_tags/) { + WARN("BAD_SIGN_OFF", + "Non-standard signature: $sign_off\n" . $herecurr); + } + if (defined $space_before && $space_before ne "") { + if (WARN("BAD_SIGN_OFF", + "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = + "$ucfirst_sign_off $email"; + } + } + if ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) { + if (WARN("BAD_SIGN_OFF", + "'$ucfirst_sign_off' is the preferred signature form\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = + "$ucfirst_sign_off $email"; + } + + } + if (!defined $space_after || $space_after ne " ") { + if (WARN("BAD_SIGN_OFF", + "Use a single space after $ucfirst_sign_off\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] = + "$ucfirst_sign_off $email"; + } + } + + my ($email_name, $email_address, $comment) = parse_email($email); + my $suggested_email = format_email(($email_name, $email_address)); + if ($suggested_email eq "") { + ERROR("BAD_SIGN_OFF", + "Unrecognized email address: '$email'\n" . $herecurr); + } else { + my $dequoted = $suggested_email; + $dequoted =~ s/^"//; + $dequoted =~ s/" $comment" ne $email && + "$suggested_email$comment" ne $email) { + WARN("BAD_SIGN_OFF", + "email address '$email' might be better as '$suggested_email$comment'\n" . $herecurr); + } + } + +# Check for duplicate signatures + my $sig_nospace = $line; + $sig_nospace =~ s/\s//g; + $sig_nospace = lc($sig_nospace); + if (defined $signatures{$sig_nospace}) { + WARN("BAD_SIGN_OFF", + "Duplicate signature\n" . $herecurr); + } else { + $signatures{$sig_nospace} = 1; + } + } + +# Check for old stable address + if ($line =~ /^\s*cc:\s*.*?.*$/i) { + ERROR("STABLE_ADDRESS", + "The 'stable' address should be 'stable\@vger.kernel.org'\n" . $herecurr); + } + +# Check for unwanted Gerrit info + if ($in_commit_log && !$ignore_changeid && $line =~ /^\s*change-id:/i) { + ERROR("GERRIT_CHANGE_ID", + "Remove Gerrit Change-Id's before submitting upstream.\n" . $herecurr); + } + +# Check for improperly formed commit descriptions + if ($in_commit_log && + $line =~ /\bcommit\s+[0-9a-f]{5,}/i && + !($line =~ /\b[Cc]ommit [0-9a-f]{12,40} \("/ || + ($line =~ /\b[Cc]ommit [0-9a-f]{12,40}\s*$/ && + defined $rawlines[$linenr] && + $rawlines[$linenr] =~ /^\s*\("/))) { + $line =~ /\b(c)ommit\s+([0-9a-f]{5,})/i; + my $init_char = $1; + my $orig_commit = lc($2); + my $id = '01234567890ab'; + my $desc = 'commit description'; + ($id, $desc) = git_commit_info($orig_commit, $id, $desc); + ERROR("GIT_COMMIT_ID", + "Please use 12 or more chars for the git commit ID like: '${init_char}ommit $id (\"$desc\")'\n" . $herecurr); + } + +# Check for added, moved or deleted files + if (!$reported_maintainer_file && !$in_commit_log && + ($line =~ /^(?:new|deleted) file mode\s*\d+\s*$/ || + $line =~ /^rename (?:from|to) [\w\/\.\-]+\s*$/ || + ($line =~ /\{\s*([\w\/\.\-]*)\s*\=\>\s*([\w\/\.\-]*)\s*\}/ && + (defined($1) || defined($2))))) { + $reported_maintainer_file = 1; + WARN("FILE_PATH_CHANGES", + "added, moved or deleted file(s), does MAINTAINERS need updating?\n" . $herecurr); + } + +# Check for wrappage within a valid hunk of the file + if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { + ERROR("CORRUPTED_PATCH", + "patch seems to be corrupt (line wrapped?)\n" . + $herecurr) if (!$emitted_corrupt++); + } + +# Check for absolute kernel paths. + if ($tree) { + while ($line =~ m{(?:^|\s)(/\S*)}g) { + my $file = $1; + + if ($file =~ m{^(.*?)(?::\d+)+:?$} && + check_absolute_file($1, $herecurr)) { + # + } else { + check_absolute_file($file, $herecurr); + } + } + } + +# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php + if (($realfile =~ /^$/ || $line =~ /^\+/) && + $rawline !~ m/^$UTF8*$/) { + my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/); + + my $blank = copy_spacing($rawline); + my $ptr = substr($blank, 0, length($utf8_prefix)) . "^"; + my $hereptr = "$hereline$ptr\n"; + + CHK("INVALID_UTF8", + "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr); + } + +# Check if it's the start of a commit log +# (not a header line and we haven't seen the patch filename) + if ($in_header_lines && $realfile =~ /^$/ && + !($rawline =~ /^\s+\S/ || + $rawline =~ /^(commit\b|from\b|[\w-]+:).*$/i)) { + $in_header_lines = 0; + $in_commit_log = 1; + } + +# Check if there is UTF-8 in a commit log when a mail header has explicitly +# declined it, i.e defined some charset where it is missing. + if ($in_header_lines && + $rawline =~ /^Content-Type:.+charset="(.+)".*$/ && + $1 !~ /utf-8/i) { + $non_utf8_charset = 1; + } + + if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ && + $rawline =~ /$NON_ASCII_UTF8/) { + WARN("UTF8_BEFORE_PATCH", + "8-bit UTF-8 used in possible commit log\n" . $herecurr); + } + +# Check for various typo / spelling mistakes + if ($in_commit_log || $line =~ /^\+/) { + while ($rawline =~ /(?:^|[^a-z@])($misspellings)(?:$|[^a-z@])/gi) { + my $typo = $1; + my $typo_fix = $spelling_fix{lc($typo)}; + $typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/); + $typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/); + my $msg_type = \&WARN; + $msg_type = \&CHK if ($file); + if (&{$msg_type}("TYPO_SPELLING", + "'$typo' may be misspelled - perhaps '$typo_fix'?\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/; + } + } + } + +# ignore non-hunk lines and lines being removed + next if (!$hunk_line || $line =~ /^-/); + +#trailing whitespace + if ($line =~ /^\+.*\015/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (ERROR("DOS_LINE_ENDINGS", + "DOS line endings\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/[\s\015]+$//; + } + } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (ERROR("TRAILING_WHITESPACE", + "trailing whitespace\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/\s+$//; + } + + $rpt_cleaners = 1; + } + +# Check for FSF mailing addresses. + if ($rawline =~ /\bwrite to the Free/i || + $rawline =~ /\b59\s+Temple\s+Pl/i || + $rawline =~ /\b51\s+Franklin\s+St/i) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + my $msg_type = \&ERROR; + $msg_type = \&CHK if ($file); + &{$msg_type}("FSF_MAILING_ADDRESS", + "Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\n" . $herevet) + } + +# check for Kconfig help text having a real description +# Only applies when adding the entry originally, after that we do not have +# sufficient context to determine whether it is indeed long enough. + if ($realfile =~ /Kconfig/ && + $line =~ /^\+\s*config\s+/) { + my $length = 0; + my $cnt = $realcnt; + my $ln = $linenr + 1; + my $f; + my $is_start = 0; + my $is_end = 0; + for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) { + $f = $lines[$ln - 1]; + $cnt-- if ($lines[$ln - 1] !~ /^-/); + $is_end = $lines[$ln - 1] =~ /^\+/; + + next if ($f =~ /^-/); + last if (!$file && $f =~ /^\@\@/); + + if ($lines[$ln - 1] =~ /^\+\s*(?:bool|tristate)\s*\"/) { + $is_start = 1; + } elsif ($lines[$ln - 1] =~ /^\+\s*(?:---)?help(?:---)?$/) { + $length = -1; + } + + $f =~ s/^.//; + $f =~ s/#.*//; + $f =~ s/^\s+//; + next if ($f =~ /^$/); + if ($f =~ /^\s*config\s/) { + $is_end = 1; + last; + } + $length++; + } + if ($is_start && $is_end && $length < $min_conf_desc_length) { + WARN("CONFIG_DESCRIPTION", + "please write a paragraph that describes the config symbol fully\n" . $herecurr); + } + #print "is_start<$is_start> is_end<$is_end> length<$length>\n"; + } + +# discourage the addition of CONFIG_EXPERIMENTAL in Kconfig. + if ($realfile =~ /Kconfig/ && + $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) { + WARN("CONFIG_EXPERIMENTAL", + "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); + } + + if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && + ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) { + my $flag = $1; + my $replacement = { + 'EXTRA_AFLAGS' => 'asflags-y', + 'EXTRA_CFLAGS' => 'ccflags-y', + 'EXTRA_CPPFLAGS' => 'cppflags-y', + 'EXTRA_LDFLAGS' => 'ldflags-y', + }; + + WARN("DEPRECATED_VARIABLE", + "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag}); + } + +# check for DT compatible documentation + if (defined $root && + (($realfile =~ /\.dtsi?$/ && $line =~ /^\+\s*compatible\s*=\s*\"/) || + ($realfile =~ /\.[ch]$/ && $line =~ /^\+.*\.compatible\s*=\s*\"/))) { + + my @compats = $rawline =~ /\"([a-zA-Z0-9\-\,\.\+_]+)\"/g; + + my $dt_path = $root . "/Documentation/devicetree/bindings/"; + my $vp_file = $dt_path . "vendor-prefixes.txt"; + + foreach my $compat (@compats) { + my $compat2 = $compat; + $compat2 =~ s/\,[a-zA-Z0-9]*\-/\,<\.\*>\-/; + my $compat3 = $compat; + $compat3 =~ s/\,([a-z]*)[0-9]*\-/\,$1<\.\*>\-/; + `grep -Erq "$compat|$compat2|$compat3" $dt_path`; + if ( $? >> 8 ) { + WARN("UNDOCUMENTED_DT_STRING", + "DT compatible string \"$compat\" appears un-documented -- check $dt_path\n" . $herecurr); + } + + next if $compat !~ /^([a-zA-Z0-9\-]+)\,/; + my $vendor = $1; + `grep -Eq "^$vendor\\b" $vp_file`; + if ( $? >> 8 ) { + WARN("UNDOCUMENTED_DT_STRING", + "DT compatible string vendor \"$vendor\" appears un-documented -- check $vp_file\n" . $herecurr); + } + } + } + +# check we are in a valid source file if not then ignore this hunk + next if ($realfile !~ /\.(h|c|s|S|pl|sh|dtsi|dts)$/); + +#line length limit + if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ && + $rawline !~ /^.\s*\*\s*\@$Ident\s/ && + !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ || + $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) && + $length > $max_line_length) + { + WARN("LONG_LINE", + "line over $max_line_length characters\n" . $herecurr); + } + +# Check for user-visible strings broken across lines, which breaks the ability +# to grep for the string. Make exceptions when the previous string ends in a +# newline (multiple lines in one string constant) or '\t', '\r', ';', or '{' +# (common in inline assembly) or is a octal \123 or hexadecimal \xaf value + if ($line =~ /^\+\s*"/ && + $prevline =~ /"\s*$/ && + $prevrawline !~ /(?:\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\s*|\{\s*)"\s*$/) { + WARN("SPLIT_STRING", + "quoted string split across lines\n" . $hereprev); + } + +# check for missing a space in a string concatination + if ($prevrawline =~ /[^\\]\w"$/ && $rawline =~ /^\+[\t ]+"\w/) { + WARN('MISSING_SPACE', + "break quoted strings at a space character\n" . $hereprev); + } + +# check for spaces before a quoted newline + if ($rawline =~ /^.*\".*\s\\n/) { + if (WARN("QUOTED_WHITESPACE_BEFORE_NEWLINE", + "unnecessary whitespace before a quoted newline\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^(\+.*\".*)\s+\\n/$1\\n/; + } + + } + +# check for adding lines without a newline. + if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { + WARN("MISSING_EOF_NEWLINE", + "adding a line without newline at end of file\n" . $herecurr); + } + +# Blackfin: use hi/lo macros + if ($realfile =~ m@arch/blackfin/.*\.S$@) { + if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("LO_MACRO", + "use the LO() macro, not (... & 0xFFFF)\n" . $herevet); + } + if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("HI_MACRO", + "use the HI() macro, not (... >> 16)\n" . $herevet); + } + } + +# check we are in a valid source file C or perl if not then ignore this hunk + next if ($realfile !~ /\.(h|c|pl|dtsi|dts)$/); + +# at the beginning of a line any tabs must come first and anything +# more than 8 must use tabs. + if ($rawline =~ /^\+\s* \t\s*\S/ || + $rawline =~ /^\+\s* \s*/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + $rpt_cleaners = 1; + if (ERROR("CODE_INDENT", + "code indent should use tabs where possible\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e; + } + } + +# check for space before tabs. + if ($rawline =~ /^\+/ && $rawline =~ / \t/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (WARN("SPACE_BEFORE_TAB", + "please, no space before tabs\n" . $herevet) && + $fix) { + while ($fixed[$fixlinenr] =~ + s/(^\+.*) {8,8}\t/$1\t\t/) {} + while ($fixed[$fixlinenr] =~ + s/(^\+.*) +\t/$1\t/) {} + } + } + +# check for && or || at the start of a line + if ($rawline =~ /^\+\s*(&&|\|\|)/) { + CHK("LOGICAL_CONTINUATIONS", + "Logical continuations should be on the previous line\n" . $hereprev); + } + +# check multi-line statement indentation matches previous line + if ($^V && $^V ge 5.10.0 && + $prevline =~ /^\+([ \t]*)((?:$c90_Keywords(?:\s+if)\s*)|(?:$Declare\s*)?(?:$Ident|\(\s*\*\s*$Ident\s*\))\s*|$Ident\s*=\s*$Ident\s*)\(.*(\&\&|\|\||,)\s*$/) { + $prevline =~ /^\+(\t*)(.*)$/; + my $oldindent = $1; + my $rest = $2; + + my $pos = pos_last_openparen($rest); + if ($pos >= 0) { + $line =~ /^(\+| )([ \t]*)/; + my $newindent = $2; + + my $goodtabindent = $oldindent . + "\t" x ($pos / 8) . + " " x ($pos % 8); + my $goodspaceindent = $oldindent . " " x $pos; + + if ($newindent ne $goodtabindent && + $newindent ne $goodspaceindent) { + + if (CHK("PARENTHESIS_ALIGNMENT", + "Alignment should match open parenthesis\n" . $hereprev) && + $fix && $line =~ /^\+/) { + $fixed[$fixlinenr] =~ + s/^\+[ \t]*/\+$goodtabindent/; + } + } + } + } + + if ($line =~ /^\+.*\(\s*$Type\s*\)[ \t]+(?!$Assignment|$Arithmetic|{)/) { + if (CHK("SPACING", + "No space is necessary after a cast\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/(\(\s*$Type\s*\))[ \t]+/$1/; + } + } + + if ($realfile =~ m@^(drivers/net/|net/)@ && + $prevrawline =~ /^\+[ \t]*\/\*[ \t]*$/ && + $rawline =~ /^\+[ \t]*\*/ && + $realline > 2) { + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); + } + + if ($realfile =~ m@^(drivers/net/|net/)@ && + $prevrawline =~ /^\+[ \t]*\/\*/ && #starting /* + $prevrawline !~ /\*\/[ \t]*$/ && #no trailing */ + $rawline =~ /^\+/ && #line is new + $rawline !~ /^\+[ \t]*\*/) { #no leading * + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments start with * on subsequent lines\n" . $hereprev); + } + + if ($realfile =~ m@^(drivers/net/|net/)@ && + $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */ + $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ + $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/ + $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */ + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments put the trailing */ on a separate line\n" . $herecurr); + } + +# check for missing blank lines after struct/union declarations +# with exceptions for various attributes and macros + if ($prevline =~ /^[\+ ]};?\s*$/ && + $line =~ /^\+/ && + !($line =~ /^\+\s*$/ || + $line =~ /^\+\s*EXPORT_SYMBOL/ || + $line =~ /^\+\s*MODULE_/i || + $line =~ /^\+\s*\#\s*(?:end|elif|else)/ || + $line =~ /^\+[a-z_]*init/ || + $line =~ /^\+\s*(?:static\s+)?[A-Z_]*ATTR/ || + $line =~ /^\+\s*DECLARE/ || + $line =~ /^\+\s*__setup/)) { + if (CHK("LINE_SPACING", + "Please use a blank line after function/struct/union/enum declarations\n" . $hereprev) && + $fix) { + fix_insert_line($fixlinenr, "\+"); + } + } + +# check for multiple consecutive blank lines + if ($prevline =~ /^[\+ ]\s*$/ && + $line =~ /^\+\s*$/ && + $last_blank_line != ($linenr - 1)) { + if (CHK("LINE_SPACING", + "Please don't use multiple blank lines\n" . $hereprev) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + } + + $last_blank_line = $linenr; + } + +# check for missing blank lines after declarations + if ($sline =~ /^\+\s+\S/ && #Not at char 1 + # actual declarations + ($prevline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || + # function pointer declarations + $prevline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + # foo bar; where foo is some local typedef or #define + $prevline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + # known declaration macros + $prevline =~ /^\+\s+$declaration_macros/) && + # for "else if" which can look like "$Ident $Ident" + !($prevline =~ /^\+\s+$c90_Keywords\b/ || + # other possible extensions of declaration lines + $prevline =~ /(?:$Compare|$Assignment|$Operators)\s*$/ || + # not starting a section or a macro "\" extended line + $prevline =~ /(?:\{\s*|\\)$/) && + # looks like a declaration + !($sline =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ || + # function pointer declarations + $sline =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ || + # foo bar; where foo is some local typedef or #define + $sline =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ || + # known declaration macros + $sline =~ /^\+\s+$declaration_macros/ || + # start of struct or union or enum + $sline =~ /^\+\s+(?:union|struct|enum|typedef)\b/ || + # start or end of block or continuation of declaration + $sline =~ /^\+\s+(?:$|[\{\}\.\#\"\?\:\(\[])/ || + # bitfield continuation + $sline =~ /^\+\s+$Ident\s*:\s*\d+\s*[,;]/ || + # other possible extensions of declaration lines + $sline =~ /^\+\s+\(?\s*(?:$Compare|$Assignment|$Operators)/) && + # indentation of previous and current line are the same + (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/)) { + if (WARN("LINE_SPACING", + "Missing a blank line after declarations\n" . $hereprev) && + $fix) { + fix_insert_line($fixlinenr, "\+"); + } + } + +# check for spaces at the beginning of a line. +# Exceptions: +# 1) within comments +# 2) indented preprocessor commands +# 3) hanging labels + if ($rawline =~ /^\+ / && $line !~ /^\+ *(?:$;|#|$Ident:)/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + if (WARN("LEADING_SPACE", + "please, no spaces at the start of a line\n" . $herevet) && + $fix) { + $fixed[$fixlinenr] =~ s/^\+([ \t]+)/"\+" . tabify($1)/e; + } + } + +# check we are in a valid C source file if not then ignore this hunk + next if ($realfile !~ /\.(h|c)$/); + +# check indentation of any line with a bare else +# (but not if it is a multiple line "if (foo) return bar; else return baz;") +# if the previous line is a break or return and is indented 1 tab more... + if ($sline =~ /^\+([\t]+)(?:}[ \t]*)?else(?:[ \t]*{)?\s*$/) { + my $tabs = length($1) + 1; + if ($prevline =~ /^\+\t{$tabs,$tabs}break\b/ || + ($prevline =~ /^\+\t{$tabs,$tabs}return\b/ && + defined $lines[$linenr] && + $lines[$linenr] !~ /^[ \+]\t{$tabs,$tabs}return/)) { + WARN("UNNECESSARY_ELSE", + "else is not generally useful after a break or return\n" . $hereprev); + } + } + +# check indentation of a line with a break; +# if the previous line is a goto or return and is indented the same # of tabs + if ($sline =~ /^\+([\t]+)break\s*;\s*$/) { + my $tabs = $1; + if ($prevline =~ /^\+$tabs(?:goto|return)\b/) { + WARN("UNNECESSARY_BREAK", + "break is not useful after a goto or return\n" . $hereprev); + } + } + +# discourage the addition of CONFIG_EXPERIMENTAL in #if(def). + if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) { + WARN("CONFIG_EXPERIMENTAL", + "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); + } + +# check for RCS/CVS revision markers + if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) { + WARN("CVS_KEYWORD", + "CVS style keyword markers, these will _not_ be updated\n". $herecurr); + } + +# Blackfin: don't use __builtin_bfin_[cs]sync + if ($line =~ /__builtin_bfin_csync/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("CSYNC", + "use the CSYNC() macro in asm/blackfin.h\n" . $herevet); + } + if ($line =~ /__builtin_bfin_ssync/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("SSYNC", + "use the SSYNC() macro in asm/blackfin.h\n" . $herevet); + } + +# check for old HOTPLUG __dev section markings + if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { + WARN("HOTPLUG_SECTION", + "Using $1 is unnecessary\n" . $herecurr); + } + +# Check for potential 'bare' types + my ($stat, $cond, $line_nr_next, $remain_next, $off_next, + $realline_next); +#print "LINE<$line>\n"; + if ($linenr >= $suppress_statement && + $realcnt && $sline =~ /.\s*\S/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0); + $stat =~ s/\n./\n /g; + $cond =~ s/\n./\n /g; + +#print "linenr<$linenr> <$stat>\n"; + # If this statement has no statement boundaries within + # it there is no point in retrying a statement scan + # until we hit end of it. + my $frag = $stat; $frag =~ s/;+\s*$//; + if ($frag !~ /(?:{|;)/) { +#print "skip<$line_nr_next>\n"; + $suppress_statement = $line_nr_next; + } + + # Find the real next line. + $realline_next = $line_nr_next; + if (defined $realline_next && + (!defined $lines[$realline_next - 1] || + substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) { + $realline_next++; + } + + my $s = $stat; + $s =~ s/{.*$//s; + + # Ignore goto labels. + if ($s =~ /$Ident:\*$/s) { + + # Ignore functions being called + } elsif ($s =~ /^.\s*$Ident\s*\(/s) { + + } elsif ($s =~ /^.\s*else\b/s) { + + # declarations always start with types + } elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) { + my $type = $1; + $type =~ s/\s+/ /g; + possible($type, "A:" . $s); + + # definitions in global scope can only start with types + } elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) { + possible($1, "B:" . $s); + } + + # any (foo ... *) is a pointer cast, and foo is a type + while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) { + possible($1, "C:" . $s); + } + + # Check for any sort of function declaration. + # int foo(something bar, other baz); + # void (*store_gdt)(x86_descr_ptr *); + if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) { + my ($name_len) = length($1); + + my $ctx = $s; + substr($ctx, 0, $name_len + 1, ''); + $ctx =~ s/\)[^\)]*$//; + + for my $arg (split(/\s*,\s*/, $ctx)) { + if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) { + + possible($1, "D:" . $s); + } + } + } + + } + +# +# Checks which may be anchored in the context. +# + +# Check for switch () and associated case and default +# statements should be at the same indent. + if ($line=~/\bswitch\s*\(.*\)/) { + my $err = ''; + my $sep = ''; + my @ctx = ctx_block_outer($linenr, $realcnt); + shift(@ctx); + for my $ctx (@ctx) { + my ($clen, $cindent) = line_stats($ctx); + if ($ctx =~ /^\+\s*(case\s+|default:)/ && + $indent != $cindent) { + $err .= "$sep$ctx\n"; + $sep = ''; + } else { + $sep = "[...]\n"; + } + } + if ($err ne '') { + ERROR("SWITCH_CASE_INDENT_LEVEL", + "switch and case should be at the same indent\n$hereline$err"); + } + } + +# if/while/etc brace do not go on next line, unless defining a do while loop, +# or if that brace on the next line is for something else + if ($line =~ /(.*)\b((?:if|while|for|switch|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { + my $pre_ctx = "$1$2"; + + my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); + + if ($line =~ /^\+\t{6,}/) { + WARN("DEEP_INDENTATION", + "Too many leading tabs - consider code refactoring\n" . $herecurr); + } + + my $ctx_cnt = $realcnt - $#ctx - 1; + my $ctx = join("\n", @ctx); + + my $ctx_ln = $linenr; + my $ctx_skip = $realcnt; + + while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt && + defined $lines[$ctx_ln - 1] && + $lines[$ctx_ln - 1] =~ /^-/)) { + ##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n"; + $ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/); + $ctx_ln++; + } + + #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n"; + #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n"; + + if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln - 1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) { + ERROR("OPEN_BRACE", + "that open brace { should be on the previous line\n" . + "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); + } + if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ && + $ctx =~ /\)\s*\;\s*$/ && + defined $lines[$ctx_ln - 1]) + { + my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]); + if ($nindent > $indent) { + WARN("TRAILING_SEMICOLON", + "trailing semicolon indicates no statements, indent implies otherwise\n" . + "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); + } + } + } + +# Check relative indent for conditionals and blocks. + if ($line =~ /\b(?:(?:if|while|for|(?:[a-z_]+|)for_each[a-z_]+)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0) + if (!defined $stat); + my ($s, $c) = ($stat, $cond); + + substr($s, 0, length($c), ''); + + # Make sure we remove the line prefixes as we have + # none on the first line, and are going to readd them + # where necessary. + $s =~ s/\n./\n/gs; + + # Find out how long the conditional actually is. + my @newlines = ($c =~ /\n/gs); + my $cond_lines = 1 + $#newlines; + + # We want to check the first line inside the block + # starting at the end of the conditional, so remove: + # 1) any blank line termination + # 2) any opening brace { on end of the line + # 3) any do (...) { + my $continuation = 0; + my $check = 0; + $s =~ s/^.*\bdo\b//; + $s =~ s/^\s*{//; + if ($s =~ s/^\s*\\//) { + $continuation = 1; + } + if ($s =~ s/^\s*?\n//) { + $check = 1; + $cond_lines++; + } + + # Also ignore a loop construct at the end of a + # preprocessor statement. + if (($prevline =~ /^.\s*#\s*define\s/ || + $prevline =~ /\\\s*$/) && $continuation == 0) { + $check = 0; + } + + my $cond_ptr = -1; + $continuation = 0; + while ($cond_ptr != $cond_lines) { + $cond_ptr = $cond_lines; + + # If we see an #else/#elif then the code + # is not linear. + if ($s =~ /^\s*\#\s*(?:else|elif)/) { + $check = 0; + } + + # Ignore: + # 1) blank lines, they should be at 0, + # 2) preprocessor lines, and + # 3) labels. + if ($continuation || + $s =~ /^\s*?\n/ || + $s =~ /^\s*#\s*?/ || + $s =~ /^\s*$Ident\s*:/) { + $continuation = ($s =~ /^.*?\\\n/) ? 1 : 0; + if ($s =~ s/^.*?\n//) { + $cond_lines++; + } + } + } + + my (undef, $sindent) = line_stats("+" . $s); + my $stat_real = raw_line($linenr, $cond_lines); + + # Check if either of these lines are modified, else + # this is not this patch's fault. + if (!defined($stat_real) || + $stat !~ /^\+/ && $stat_real !~ /^\+/) { + $check = 0; + } + if (defined($stat_real) && $cond_lines > 1) { + $stat_real = "[...]\n$stat_real"; + } + + #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n"; + + if ($check && (($sindent % 8) != 0 || + ($sindent <= $indent && $s ne ''))) { + WARN("SUSPECT_CODE_INDENT", + "suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n"); + } + } + + # Track the 'values' across context and added lines. + my $opline = $line; $opline =~ s/^./ /; + my ($curr_values, $curr_vars) = + annotate_values($opline . "\n", $prev_values); + $curr_values = $prev_values . $curr_values; + if ($dbg_values) { + my $outline = $opline; $outline =~ s/\t/ /g; + print "$linenr > .$outline\n"; + print "$linenr > $curr_values\n"; + print "$linenr > $curr_vars\n"; + } + $prev_values = substr($curr_values, -1); + +#ignore lines not being added + next if ($line =~ /^[^\+]/); + +# TEST: allow direct testing of the type matcher. + if ($dbg_type) { + if ($line =~ /^.\s*$Declare\s*$/) { + ERROR("TEST_TYPE", + "TEST: is type\n" . $herecurr); + } elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) { + ERROR("TEST_NOT_TYPE", + "TEST: is not type ($1 is)\n". $herecurr); + } + next; + } +# TEST: allow direct testing of the attribute matcher. + if ($dbg_attr) { + if ($line =~ /^.\s*$Modifier\s*$/) { + ERROR("TEST_ATTR", + "TEST: is attr\n" . $herecurr); + } elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) { + ERROR("TEST_NOT_ATTR", + "TEST: is not attr ($1 is)\n". $herecurr); + } + next; + } + +# check for initialisation to aggregates open brace on the next line + if ($line =~ /^.\s*{/ && + $prevline =~ /(?:^|[^=])=\s*$/) { + if (ERROR("OPEN_BRACE", + "that open brace { should be on the previous line\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + $fixedline =~ s/\s*=\s*$/ = {/; + fix_insert_line($fixlinenr, $fixedline); + $fixedline = $line; + $fixedline =~ s/^(.\s*){\s*/$1/; + fix_insert_line($fixlinenr, $fixedline); + } + } + +# +# Checks which are anchored on the added line. +# + +# check for malformed paths in #include statements (uses RAW line) + if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) { + my $path = $1; + if ($path =~ m{//}) { + ERROR("MALFORMED_INCLUDE", + "malformed #include filename\n" . $herecurr); + } + if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) { + ERROR("UAPI_INCLUDE", + "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr); + } + } + +# no C99 // comments + if ($line =~ m{//}) { + if (ERROR("C99_COMMENTS", + "do not use C99 // comments\n" . $herecurr) && + $fix) { + my $line = $fixed[$fixlinenr]; + if ($line =~ /\/\/(.*)$/) { + my $comment = trim($1); + $fixed[$fixlinenr] =~ s@\/\/(.*)$@/\* $comment \*/@; + } + } + } + # Remove C99 comments. + $line =~ s@//.*@@; + $opline =~ s@//.*@@; + +# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider +# the whole statement. +#print "APW <$lines[$realline_next - 1]>\n"; + if (defined $realline_next && + exists $lines[$realline_next - 1] && + !defined $suppress_export{$realline_next} && + ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || + $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { + # Handle definitions which produce identifiers with + # a prefix: + # XXX(foo); + # EXPORT_SYMBOL(something_foo); + my $name = $1; + if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ && + $name =~ /^${Ident}_$2/) { +#print "FOO C name<$name>\n"; + $suppress_export{$realline_next} = 1; + + } elsif ($stat !~ /(?: + \n.}\s*$| + ^.DEFINE_$Ident\(\Q$name\E\)| + ^.DECLARE_$Ident\(\Q$name\E\)| + ^.LIST_HEAD\(\Q$name\E\)| + ^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(| + \b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\() + )/x) { +#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n"; + $suppress_export{$realline_next} = 2; + } else { + $suppress_export{$realline_next} = 1; + } + } + if (!defined $suppress_export{$linenr} && + $prevline =~ /^.\s*$/ && + ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || + $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { +#print "FOO B <$lines[$linenr - 1]>\n"; + $suppress_export{$linenr} = 2; + } + if (defined $suppress_export{$linenr} && + $suppress_export{$linenr} == 2) { + WARN("EXPORT_SYMBOL", + "EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr); + } + +# check for global initialisers. + if ($line =~ /^\+(\s*$Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/) { + if (ERROR("GLOBAL_INITIALISERS", + "do not initialise globals to 0 or NULL\n" . + $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/($Type\s*$Ident\s*(?:\s+$Modifier))*\s*=\s*(0|NULL|false)\s*;/$1;/; + } + } +# check for static initialisers. + if ($line =~ /^\+.*\bstatic\s.*=\s*(0|NULL|false)\s*;/) { + if (ERROR("INITIALISED_STATIC", + "do not initialise statics to 0 or NULL\n" . + $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(\bstatic\s.*?)\s*=\s*(0|NULL|false)\s*;/$1;/; + } + } + +# check for misordered declarations of char/short/int/long with signed/unsigned + while ($sline =~ m{(\b$TypeMisordered\b)}g) { + my $tmp = trim($1); + WARN("MISORDERED_TYPE", + "type '$tmp' should be specified in [[un]signed] [short|int|long|long long] order\n" . $herecurr); + } + +# check for static const char * arrays. + if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) { + WARN("STATIC_CONST_CHAR_ARRAY", + "static const char * array should probably be static const char * const\n" . + $herecurr); + } + +# check for static char foo[] = "bar" declarations. + if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) { + WARN("STATIC_CONST_CHAR_ARRAY", + "static char array declaration should probably be static const char\n" . + $herecurr); + } + +# check for non-global char *foo[] = {"bar", ...} declarations. + if ($line =~ /^.\s+(?:static\s+|const\s+)?char\s+\*\s*\w+\s*\[\s*\]\s*=\s*\{/) { + WARN("STATIC_CONST_CHAR_ARRAY", + "char * array declaration might be better as static const\n" . + $herecurr); + } + +# check for function declarations without arguments like "int foo()" + if ($line =~ /(\b$Type\s+$Ident)\s*\(\s*\)/) { + if (ERROR("FUNCTION_WITHOUT_ARGS", + "Bad function definition - $1() should probably be $1(void)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(\b($Type)\s+($Ident))\s*\(\s*\)/$2 $3(void)/; + } + } + +# check for uses of DEFINE_PCI_DEVICE_TABLE + if ($line =~ /\bDEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=/) { + if (WARN("DEFINE_PCI_DEVICE_TABLE", + "Prefer struct pci_device_id over deprecated DEFINE_PCI_DEVICE_TABLE\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b(?:static\s+|)DEFINE_PCI_DEVICE_TABLE\s*\(\s*(\w+)\s*\)\s*=\s*/static const struct pci_device_id $1\[\] = /; + } + } + +# check for new typedefs, only function parameters and sparse annotations +# make sense. + if ($line =~ /\btypedef\s/ && + $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ && + $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ && + $line !~ /\b$typeTypedefs\b/ && + $line !~ /\b__bitwise(?:__|)\b/) { + WARN("NEW_TYPEDEFS", + "do not add new typedefs\n" . $herecurr); + } + +# * goes on variable not on type + # (char*[ const]) + while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) { + #print "AA<$1>\n"; + my ($ident, $from, $to) = ($1, $2, $2); + + # Should start with a space. + $to =~ s/^(\S)/ $1/; + # Should not end with a space. + $to =~ s/\s+$//; + # '*'s should not have spaces between. + while ($to =~ s/\*\s+\*/\*\*/) { + } + +## print "1: from<$from> to<$to> ident<$ident>\n"; + if ($from ne $to) { + if (ERROR("POINTER_LOCATION", + "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr) && + $fix) { + my $sub_from = $ident; + my $sub_to = $ident; + $sub_to =~ s/\Q$from\E/$to/; + $fixed[$fixlinenr] =~ + s@\Q$sub_from\E@$sub_to@; + } + } + } + while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) { + #print "BB<$1>\n"; + my ($match, $from, $to, $ident) = ($1, $2, $2, $3); + + # Should start with a space. + $to =~ s/^(\S)/ $1/; + # Should not end with a space. + $to =~ s/\s+$//; + # '*'s should not have spaces between. + while ($to =~ s/\*\s+\*/\*\*/) { + } + # Modifiers should have spaces. + $to =~ s/(\b$Modifier$)/$1 /; + +## print "2: from<$from> to<$to> ident<$ident>\n"; + if ($from ne $to && $ident !~ /^$Modifier$/) { + if (ERROR("POINTER_LOCATION", + "\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr) && + $fix) { + + my $sub_from = $match; + my $sub_to = $match; + $sub_to =~ s/\Q$from\E/$to/; + $fixed[$fixlinenr] =~ + s@\Q$sub_from\E@$sub_to@; + } + } + } + +# # no BUG() or BUG_ON() +# if ($line =~ /\b(BUG|BUG_ON)\b/) { +# print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n"; +# print "$herecurr"; +# $clean = 0; +# } + + if ($line =~ /\bLINUX_VERSION_CODE\b/) { + WARN("LINUX_VERSION_CODE", + "LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr); + } + +# check for uses of printk_ratelimit + if ($line =~ /\bprintk_ratelimit\s*\(/) { + WARN("PRINTK_RATELIMITED", +"Prefer printk_ratelimited or pr__ratelimited to printk_ratelimit\n" . $herecurr); + } + +# printk should use KERN_* levels. Note that follow on printk's on the +# same line do not need a level, so we use the current block context +# to try and find and validate the current printk. In summary the current +# printk includes all preceding printk's which have no newline on the end. +# we assume the first bad printk is the one to report. + if ($line =~ /\bprintk\((?!KERN_)\s*"/) { + my $ok = 0; + for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) { + #print "CHECK<$lines[$ln - 1]\n"; + # we have a preceding printk if it ends + # with "\n" ignore it, else it is to blame + if ($lines[$ln - 1] =~ m{\bprintk\(}) { + if ($rawlines[$ln - 1] !~ m{\\n"}) { + $ok = 1; + } + last; + } + } + if ($ok == 0) { + WARN("PRINTK_WITHOUT_KERN_LEVEL", + "printk() should include KERN_ facility level\n" . $herecurr); + } + } + + if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { + my $orig = $1; + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + my $level2 = $level; + $level2 = "dbg" if ($level eq "debug"); + WARN("PREFER_PR_LEVEL", + "Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr); + } + + if ($line =~ /\bpr_warning\s*\(/) { + if (WARN("PREFER_PR_LEVEL", + "Prefer pr_warn(... to pr_warning(...\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\bpr_warning\b/pr_warn/; + } + } + + if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { + my $orig = $1; + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + $level = "dbg" if ($level eq "debug"); + WARN("PREFER_DEV_LEVEL", + "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); + } + +# function brace can't be on same line, except for #defines of do while, +# or if closed on same line + if (($line=~/$Type\s*$Ident\(.*\).*\s*{/) and + !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) { + if (ERROR("OPEN_BRACE", + "open brace '{' following function declarations go on the next line\n" . $herecurr) && + $fix) { + fix_delete_line($fixlinenr, $rawline); + my $fixed_line = $rawline; + $fixed_line =~ /(^..*$Type\s*$Ident\(.*\)\s*){(.*)$/; + my $line1 = $1; + my $line2 = $2; + fix_insert_line($fixlinenr, ltrim($line1)); + fix_insert_line($fixlinenr, "\+{"); + if ($line2 !~ /^\s*$/) { + fix_insert_line($fixlinenr, "\+\t" . trim($line2)); + } + } + } + +# open braces for enum, union and struct go on the same line. + if ($line =~ /^.\s*{/ && + $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) { + if (ERROR("OPEN_BRACE", + "open brace '{' following $1 go on the same line\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = rtrim($prevrawline) . " {"; + fix_insert_line($fixlinenr, $fixedline); + $fixedline = $rawline; + $fixedline =~ s/^(.\s*){\s*/$1\t/; + if ($fixedline !~ /^\+\s*$/) { + fix_insert_line($fixlinenr, $fixedline); + } + } + } + +# missing space after union, struct or enum definition + if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident){1,2}[=\{]/) { + if (WARN("SPACING", + "missing space after $1 definition\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(.\s*(?:typedef\s+)?(?:enum|union|struct)(?:\s+$Ident){1,2})([=\{])/$1 $2/; + } + } + +# Function pointer declarations +# check spacing between type, funcptr, and args +# canonical declaration is "type (*funcptr)(args...)" + if ($line =~ /^.\s*($Declare)\((\s*)\*(\s*)($Ident)(\s*)\)(\s*)\(/) { + my $declare = $1; + my $pre_pointer_space = $2; + my $post_pointer_space = $3; + my $funcname = $4; + my $post_funcname_space = $5; + my $pre_args_space = $6; + +# the $Declare variable will capture all spaces after the type +# so check it for a missing trailing missing space but pointer return types +# don't need a space so don't warn for those. + my $post_declare_space = ""; + if ($declare =~ /(\s+)$/) { + $post_declare_space = $1; + $declare = rtrim($declare); + } + if ($declare !~ /\*$/ && $post_declare_space =~ /^$/) { + WARN("SPACING", + "missing space after return type\n" . $herecurr); + $post_declare_space = " "; + } + +# unnecessary space "type (*funcptr)(args...)" +# This test is not currently implemented because these declarations are +# equivalent to +# int foo(int bar, ...) +# and this is form shouldn't/doesn't generate a checkpatch warning. +# +# elsif ($declare =~ /\s{2,}$/) { +# WARN("SPACING", +# "Multiple spaces after return type\n" . $herecurr); +# } + +# unnecessary space "type ( *funcptr)(args...)" + if (defined $pre_pointer_space && + $pre_pointer_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space after function pointer open parenthesis\n" . $herecurr); + } + +# unnecessary space "type (* funcptr)(args...)" + if (defined $post_pointer_space && + $post_pointer_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space before function pointer name\n" . $herecurr); + } + +# unnecessary space "type (*funcptr )(args...)" + if (defined $post_funcname_space && + $post_funcname_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space after function pointer name\n" . $herecurr); + } + +# unnecessary space "type (*funcptr) (args...)" + if (defined $pre_args_space && + $pre_args_space =~ /^\s/) { + WARN("SPACING", + "Unnecessary space before function pointer arguments\n" . $herecurr); + } + + if (show_type("SPACING") && $fix) { + $fixed[$fixlinenr] =~ + s/^(.\s*)$Declare\s*\(\s*\*\s*$Ident\s*\)\s*\(/$1 . $declare . $post_declare_space . '(*' . $funcname . ')('/ex; + } + } + +# check for spacing round square brackets; allowed: +# 1. with a type on the left -- int [] a; +# 2. at the beginning of a line for slice initialisers -- [0...10] = 5, +# 3. inside a curly brace -- = { [0...10] = 5 } + while ($line =~ /(.*?\s)\[/g) { + my ($where, $prefix) = ($-[1], $1); + if ($prefix !~ /$Type\s+$/ && + ($where != 0 || $prefix !~ /^.\s+$/) && + $prefix !~ /[{,]\s+$/) { + if (ERROR("BRACKET_SPACE", + "space prohibited before open square bracket '['\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(\+.*?)\s+\[/$1\[/; + } + } + } + +# check for spaces between functions and their parentheses. + while ($line =~ /($Ident)\s+\(/g) { + my $name = $1; + my $ctx_before = substr($line, 0, $-[1]); + my $ctx = "$ctx_before$name"; + + # Ignore those directives where spaces _are_ permitted. + if ($name =~ /^(?: + if|for|while|switch|return|case| + volatile|__volatile__| + __attribute__|format|__extension__| + asm|__asm__)$/x) + { + # cpp #define statements have non-optional spaces, ie + # if there is a space between the name and the open + # parenthesis it is simply not a parameter group. + } elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) { + + # cpp #elif statement condition may start with a ( + } elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) { + + # If this whole things ends with a type its most + # likely a typedef for a function. + } elsif ($ctx =~ /$Type$/) { + + } else { + if (WARN("SPACING", + "space prohibited between function name and open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\b$name\s+\(/$name\(/; + } + } + } + +# Check operator spacing. + if (!($line=~/\#\s*include/)) { + my $fixed_line = ""; + my $line_fixed = 0; + + my $ops = qr{ + <<=|>>=|<=|>=|==|!=| + \+=|-=|\*=|\/=|%=|\^=|\|=|&=| + =>|->|<<|>>|<|>|=|!|~| + &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%| + \?:|\?|: + }x; + my @elements = split(/($ops|;)/, $opline); + +## print("element count: <" . $#elements . ">\n"); +## foreach my $el (@elements) { +## print("el: <$el>\n"); +## } + + my @fix_elements = (); + my $off = 0; + + foreach my $el (@elements) { + push(@fix_elements, substr($rawline, $off, length($el))); + $off += length($el); + } + + $off = 0; + + my $blank = copy_spacing($opline); + my $last_after = -1; + + for (my $n = 0; $n < $#elements; $n += 2) { + + my $good = $fix_elements[$n] . $fix_elements[$n + 1]; + +## print("n: <$n> good: <$good>\n"); + + $off += length($elements[$n]); + + # Pick up the preceding and succeeding characters. + my $ca = substr($opline, 0, $off); + my $cc = ''; + if (length($opline) >= ($off + length($elements[$n + 1]))) { + $cc = substr($opline, $off + length($elements[$n + 1])); + } + my $cb = "$ca$;$cc"; + + my $a = ''; + $a = 'V' if ($elements[$n] ne ''); + $a = 'W' if ($elements[$n] =~ /\s$/); + $a = 'C' if ($elements[$n] =~ /$;$/); + $a = 'B' if ($elements[$n] =~ /(\[|\()$/); + $a = 'O' if ($elements[$n] eq ''); + $a = 'E' if ($ca =~ /^\s*$/); + + my $op = $elements[$n + 1]; + + my $c = ''; + if (defined $elements[$n + 2]) { + $c = 'V' if ($elements[$n + 2] ne ''); + $c = 'W' if ($elements[$n + 2] =~ /^\s/); + $c = 'C' if ($elements[$n + 2] =~ /^$;/); + $c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/); + $c = 'O' if ($elements[$n + 2] eq ''); + $c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/); + } else { + $c = 'E'; + } + + my $ctx = "${a}x${c}"; + + my $at = "(ctx:$ctx)"; + + my $ptr = substr($blank, 0, $off) . "^"; + my $hereptr = "$hereline$ptr\n"; + + # Pull out the value of this operator. + my $op_type = substr($curr_values, $off + 1, 1); + + # Get the full operator variant. + my $opv = $op . substr($curr_vars, $off, 1); + + # Ignore operators passed as parameters. + if ($op_type ne 'V' && + $ca =~ /\s$/ && $cc =~ /^\s*,/) { + +# # Ignore comments +# } elsif ($op =~ /^$;+$/) { + + # ; should have either the end of line or a space or \ after it + } elsif ($op eq ';') { + if ($ctx !~ /.x[WEBC]/ && + $cc !~ /^\\/ && $cc !~ /^;/) { + if (ERROR("SPACING", + "space required after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + } + } + + # // is a comment + } elsif ($op eq '//') { + + # : when part of a bitfield + } elsif ($opv eq ':B') { + # skip the bitfield test for now + + # No spaces for: + # -> + } elsif ($op eq '->') { + if ($ctx =~ /Wx.|.xW/) { + if (ERROR("SPACING", + "spaces prohibited around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # , must have a space on the right. + } elsif ($op eq ',') { + if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) { + if (ERROR("SPACING", + "space required after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + $last_after = $n; + } + } + + # '*' as part of a type definition -- reported already. + } elsif ($opv eq '*_') { + #warn "'*' is part of type\n"; + + # unary operators should have a space before and + # none after. May be left adjacent to another + # unary operator, or a cast + } elsif ($op eq '!' || $op eq '~' || + $opv eq '*U' || $opv eq '-U' || + $opv eq '&U' || $opv eq '&&U') { + if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) { + if (ERROR("SPACING", + "space required before that '$op' $at\n" . $hereptr)) { + if ($n != $last_after + 2) { + $good = $fix_elements[$n] . " " . ltrim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + } + if ($op eq '*' && $cc =~/\s*$Modifier\b/) { + # A unary '*' may be const + + } elsif ($ctx =~ /.xW/) { + if (ERROR("SPACING", + "space prohibited after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . rtrim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # unary ++ and unary -- are allowed no space on one side. + } elsif ($op eq '++' or $op eq '--') { + if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) { + if (ERROR("SPACING", + "space required one side of that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . " "; + $line_fixed = 1; + } + } + if ($ctx =~ /Wx[BE]/ || + ($ctx =~ /Wx./ && $cc =~ /^;/)) { + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + if ($ctx =~ /ExW/) { + if (ERROR("SPACING", + "space prohibited after that '$op' $at\n" . $hereptr)) { + $good = $fix_elements[$n] . trim($fix_elements[$n + 1]); + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # << and >> may either have or not have spaces both sides + } elsif ($op eq '<<' or $op eq '>>' or + $op eq '&' or $op eq '^' or $op eq '|' or + $op eq '+' or $op eq '-' or + $op eq '*' or $op eq '/' or + $op eq '%') + { + if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { + if (ERROR("SPACING", + "need consistent spacing around '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + + # A colon needs no spaces before when it is + # terminating a case value or a label. + } elsif ($opv eq ':C' || $opv eq ':L') { + if ($ctx =~ /Wx./) { + if (ERROR("SPACING", + "space prohibited before that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]); + $line_fixed = 1; + } + } + + # All the others need spaces both sides. + } elsif ($ctx !~ /[EWC]x[CWE]/) { + my $ok = 0; + + # Ignore email addresses + if (($op eq '<' && + $cc =~ /^\S+\@\S+>/) || + ($op eq '>' && + $ca =~ /<\S+\@\S+$/)) + { + $ok = 1; + } + + # messages are ERROR, but ?: are CHK + if ($ok == 0) { + my $msg_type = \&ERROR; + $msg_type = \&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/); + + if (&{$msg_type}("SPACING", + "spaces required around that '$op' $at\n" . $hereptr)) { + $good = rtrim($fix_elements[$n]) . " " . trim($fix_elements[$n + 1]) . " "; + if (defined $fix_elements[$n + 2]) { + $fix_elements[$n + 2] =~ s/^\s+//; + } + $line_fixed = 1; + } + } + } + $off += length($elements[$n + 1]); + +## print("n: <$n> GOOD: <$good>\n"); + + $fixed_line = $fixed_line . $good; + } + + if (($#elements % 2) == 0) { + $fixed_line = $fixed_line . $fix_elements[$#elements]; + } + + if ($fix && $line_fixed && $fixed_line ne $fixed[$fixlinenr]) { + $fixed[$fixlinenr] = $fixed_line; + } + + + } + +# check for whitespace before a non-naked semicolon + if ($line =~ /^\+.*\S\s+;\s*$/) { + if (WARN("SPACING", + "space prohibited before semicolon\n" . $herecurr) && + $fix) { + 1 while $fixed[$fixlinenr] =~ + s/^(\+.*\S)\s+;/$1;/; + } + } + +# check for multiple assignments + if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) { + CHK("MULTIPLE_ASSIGNMENTS", + "multiple assignments should be avoided\n" . $herecurr); + } + +## # check for multiple declarations, allowing for a function declaration +## # continuation. +## if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ && +## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { +## +## # Remove any bracketed sections to ensure we do not +## # falsly report the parameters of functions. +## my $ln = $line; +## while ($ln =~ s/\([^\(\)]*\)//g) { +## } +## if ($ln =~ /,/) { +## WARN("MULTIPLE_DECLARATION", +## "declaring multiple variables together should be avoided\n" . $herecurr); +## } +## } + +#need space before brace following if, while, etc + if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) || + $line =~ /do{/) { + if (ERROR("SPACING", + "space required before the open brace '{'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/^(\+.*(?:do|\))){/$1 {/; + } + } + +## # check for blank lines before declarations +## if ($line =~ /^.\t+$Type\s+$Ident(?:\s*=.*)?;/ && +## $prevrawline =~ /^.\s*$/) { +## WARN("SPACING", +## "No blank lines before declarations\n" . $hereprev); +## } +## + +# closing brace should have a space following it when it has anything +# on the line + if ($line =~ /}(?!(?:,|;|\)))\S/) { + if (ERROR("SPACING", + "space required after that close brace '}'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/}((?!(?:,|;|\)))\S)/} $1/; + } + } + +# check spacing on square brackets + if ($line =~ /\[\s/ && $line !~ /\[\s*$/) { + if (ERROR("SPACING", + "space prohibited after that open square bracket '['\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\[\s+/\[/; + } + } + if ($line =~ /\s\]/) { + if (ERROR("SPACING", + "space prohibited before that close square bracket ']'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\s+\]/\]/; + } + } + +# check spacing on parentheses + if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ && + $line !~ /for\s*\(\s+;/) { + if (ERROR("SPACING", + "space prohibited after that open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\(\s+/\(/; + } + } + if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ && + $line !~ /for\s*\(.*;\s+\)/ && + $line !~ /:\s+\)/) { + if (ERROR("SPACING", + "space prohibited before that close parenthesis ')'\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\s+\)/\)/; + } + } + +# check unnecessary parentheses around addressof/dereference single $Lvals +# ie: &(foo->bar) should be &foo->bar and *(foo->bar) should be *foo->bar + + while ($line =~ /(?:[^&]&\s*|\*)\(\s*($Ident\s*(?:$Member\s*)+)\s*\)/g) { + CHK("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses around $1\n" . $herecurr); + } + +#goto labels aren't indented, allow a single space however + if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and + !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { + if (WARN("INDENTED_LABEL", + "labels should not be indented\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(.)\s+/$1/; + } + } + +# return is not a function + if (defined($stat) && $stat =~ /^.\s*return(\s*)\(/s) { + my $spacing = $1; + if ($^V && $^V ge 5.10.0 && + $stat =~ /^.\s*return\s*($balanced_parens)\s*;\s*$/) { + my $value = $1; + $value = deparenthesize($value); + if ($value =~ m/^\s*$FuncArg\s*(?:\?|$)/) { + ERROR("RETURN_PARENTHESES", + "return is not a function, parentheses are not required\n" . $herecurr); + } + } elsif ($spacing !~ /\s+/) { + ERROR("SPACING", + "space required before the open parenthesis '('\n" . $herecurr); + } + } + +# unnecessary return in a void function +# at end-of-function, with the previous line a single leading tab, then return; +# and the line before that not a goto label target like "out:" + if ($sline =~ /^[ \+]}\s*$/ && + $prevline =~ /^\+\treturn\s*;\s*$/ && + $linenr >= 3 && + $lines[$linenr - 3] =~ /^[ +]/ && + $lines[$linenr - 3] !~ /^[ +]\s*$Ident\s*:/) { + WARN("RETURN_VOID", + "void function return statements are not generally useful\n" . $hereprev); + } + +# if statements using unnecessary parentheses - ie: if ((foo == bar)) + if ($^V && $^V ge 5.10.0 && + $line =~ /\bif\s*((?:\(\s*){2,})/) { + my $openparens = $1; + my $count = $openparens =~ tr@\(@\(@; + my $msg = ""; + if ($line =~ /\bif\s*(?:\(\s*){$count,$count}$LvalOrFunc\s*($Compare)\s*$LvalOrFunc(?:\s*\)){$count,$count}/) { + my $comp = $4; #Not $1 because of $LvalOrFunc + $msg = " - maybe == should be = ?" if ($comp eq "=="); + WARN("UNNECESSARY_PARENTHESES", + "Unnecessary parentheses$msg\n" . $herecurr); + } + } + +# Return of what appears to be an errno should normally be -'ve + if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) { + my $name = $1; + if ($name ne 'EOF' && $name ne 'ERROR') { + WARN("USE_NEGATIVE_ERRNO", + "return of an errno should typically be -ve (return -$1)\n" . $herecurr); + } + } + +# Need a space before open parenthesis after if, while etc + if ($line =~ /\b(if|while|for|switch)\(/) { + if (ERROR("SPACING", + "space required before the open parenthesis '('\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/\b(if|while|for|switch)\(/$1 \(/; + } + } + +# Check for illegal assignment in if conditional -- and check for trailing +# statements after the conditional. + if ($line =~ /do\s*(?!{)/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0) + if (!defined $stat); + my ($stat_next) = ctx_statement_block($line_nr_next, + $remain_next, $off_next); + $stat_next =~ s/\n./\n /g; + ##print "stat<$stat> stat_next<$stat_next>\n"; + + if ($stat_next =~ /^\s*while\b/) { + # If the statement carries leading newlines, + # then count those as offsets. + my ($whitespace) = + ($stat_next =~ /^((?:\s*\n[+-])*\s*)/s); + my $offset = + statement_rawlines($whitespace) - 1; + + $suppress_whiletrailers{$line_nr_next + + $offset} = 1; + } + } + if (!defined $suppress_whiletrailers{$linenr} && + defined($stat) && defined($cond) && + $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) { + my ($s, $c) = ($stat, $cond); + + if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { + ERROR("ASSIGN_IN_IF", + "do not use assignment in if condition\n" . $herecurr); + } + + # Find out what is on the end of the line after the + # conditional. + substr($s, 0, length($c), ''); + $s =~ s/\n.*//g; + $s =~ s/$;//g; # Remove any comments + if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ && + $c !~ /}\s*while\s*/) + { + # Find out how long the conditional actually is. + my @newlines = ($c =~ /\n/gs); + my $cond_lines = 1 + $#newlines; + my $stat_real = ''; + + $stat_real = raw_line($linenr, $cond_lines) + . "\n" if ($cond_lines); + if (defined($stat_real) && $cond_lines > 1) { + $stat_real = "[...]\n$stat_real"; + } + + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . $herecurr . $stat_real); + } + } + +# Check for bitwise tests written as boolean + if ($line =~ / + (?: + (?:\[|\(|\&\&|\|\|) + \s*0[xX][0-9]+\s* + (?:\&\&|\|\|) + | + (?:\&\&|\|\|) + \s*0[xX][0-9]+\s* + (?:\&\&|\|\||\)|\]) + )/x) + { + WARN("HEXADECIMAL_BOOLEAN_TEST", + "boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr); + } + +# if and else should not have general statements after it + if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) { + my $s = $1; + $s =~ s/$;//g; # Remove any comments + if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) { + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . $herecurr); + } + } +# if should not continue a brace + if ($line =~ /}\s*if\b/) { + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line (or did you mean 'else if'?)\n" . + $herecurr); + } +# case and default should not have general statements after them + if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g && + $line !~ /\G(?: + (?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$| + \s*return\s+ + )/xg) + { + ERROR("TRAILING_STATEMENTS", + "trailing statements should be on next line\n" . $herecurr); + } + + # Check for }else {, these must be at the same + # indent level to be relevant to each other. + if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ && + $previndent == $indent) { + if (ERROR("ELSE_AFTER_BRACE", + "else should follow close brace '}'\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + $fixedline =~ s/}\s*$//; + if ($fixedline !~ /^\+\s*$/) { + fix_insert_line($fixlinenr, $fixedline); + } + $fixedline = $rawline; + $fixedline =~ s/^(.\s*)else/$1} else/; + fix_insert_line($fixlinenr, $fixedline); + } + } + + if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ && + $previndent == $indent) { + my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0); + + # Find out what is on the end of the line after the + # conditional. + substr($s, 0, length($c), ''); + $s =~ s/\n.*//g; + + if ($s =~ /^\s*;/) { + if (ERROR("WHILE_AFTER_BRACE", + "while should follow close brace '}'\n" . $hereprev) && + $fix && $prevline =~ /^\+/ && $line =~ /^\+/) { + fix_delete_line($fixlinenr - 1, $prevrawline); + fix_delete_line($fixlinenr, $rawline); + my $fixedline = $prevrawline; + my $trailing = $rawline; + $trailing =~ s/^\+//; + $trailing = trim($trailing); + $fixedline =~ s/}\s*$/} $trailing/; + fix_insert_line($fixlinenr, $fixedline); + } + } + } + +#Specific variable tests + while ($line =~ m{($Constant|$Lval)}g) { + my $var = $1; + +#gcc binary extension + if ($var =~ /^$Binary$/) { + if (WARN("GCC_BINARY_CONSTANT", + "Avoid gcc v4.3+ binary constant extension: <$var>\n" . $herecurr) && + $fix) { + my $hexval = sprintf("0x%x", oct($var)); + $fixed[$fixlinenr] =~ + s/\b$var\b/$hexval/; + } + } + +#CamelCase + if ($var !~ /^$Constant$/ && + $var =~ /[A-Z][a-z]|[a-z][A-Z]/ && +#Ignore Page variants + $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && +#Ignore SI style variants like nS, mV and dB (ie: max_uV, regulator_min_uA_show) + $var !~ /^(?:[a-z_]*?)_?[a-z][A-Z](?:_[a-z_]+)?$/) { + while ($var =~ m{($Ident)}g) { + my $word = $1; + next if ($word !~ /[A-Z][a-z]|[a-z][A-Z]/); + if ($check) { + seed_camelcase_includes(); + if (!$file && !$camelcase_file_seeded) { + seed_camelcase_file($realfile); + $camelcase_file_seeded = 1; + } + } + if (!defined $camelcase{$word}) { + $camelcase{$word} = 1; + CHK("CAMELCASE", + "Avoid CamelCase: <$word>\n" . $herecurr); + } + } + } + } + +#no spaces allowed after \ in define + if ($line =~ /\#\s*define.*\\\s+$/) { + if (WARN("WHITESPACE_AFTER_LINE_CONTINUATION", + "Whitespace after \\ makes next lines useless\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\s+$//; + } + } + +#warn if is #included and is available (uses RAW line) + if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\}) { + my $file = "$1.h"; + my $checkfile = "include/linux/$file"; + if (-f "$root/$checkfile" && + $realfile ne $checkfile && + $1 !~ /$allowed_asm_includes/) + { + if ($realfile =~ m{^arch/}) { + CHK("ARCH_INCLUDE_LINUX", + "Consider using #include instead of \n" . $herecurr); + } else { + WARN("INCLUDE_LINUX", + "Use #include instead of \n" . $herecurr); + } + } + } + +# multi-statement macros should be enclosed in a do while loop, grab the +# first statement and ensure its the whole macro if its not enclosed +# in a known good container + if ($realfile !~ m@/vmlinux.lds.h$@ && + $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) { + my $ln = $linenr; + my $cnt = $realcnt; + my ($off, $dstat, $dcond, $rest); + my $ctx = ''; + my $has_flow_statement = 0; + my $has_arg_concat = 0; + ($dstat, $dcond, $ln, $cnt, $off) = + ctx_statement_block($linenr, $realcnt, 0); + $ctx = $dstat; + #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n"; + #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n"; + + $has_flow_statement = 1 if ($ctx =~ /\b(goto|return)\b/); + $has_arg_concat = 1 if ($ctx =~ /\#\#/); + + $dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//; + $dstat =~ s/$;//g; + $dstat =~ s/\\\n.//g; + $dstat =~ s/^\s*//s; + $dstat =~ s/\s*$//s; + + # Flatten any parentheses and braces + while ($dstat =~ s/\([^\(\)]*\)/1/ || + $dstat =~ s/\{[^\{\}]*\}/1/ || + $dstat =~ s/\[[^\[\]]*\]/1/) + { + } + + # Flatten any obvious string concatentation. + while ($dstat =~ s/("X*")\s*$Ident/$1/ || + $dstat =~ s/$Ident\s*("X*")/$1/) + { + } + + my $exceptions = qr{ + $Declare| + module_param_named| + MODULE_PARM_DESC| + DECLARE_PER_CPU| + DEFINE_PER_CPU| + __typeof__\(| + union| + struct| + \.$Ident\s*=\s*| + ^\"|\"$ + }x; + #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; + if ($dstat ne '' && + $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), + $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo(); + $dstat !~ /^[!~-]?(?:$Lval|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo // foo->bar // foo.bar->baz + $dstat !~ /^'X'$/ && $dstat !~ /^'XX'$/ && # character constants + $dstat !~ /$exceptions/ && + $dstat !~ /^\.$Ident\s*=/ && # .foo = + $dstat !~ /^(?:\#\s*$Ident|\#\s*$Constant)\s*$/ && # stringification #foo + $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) + $dstat !~ /^for\s*$Constant$/ && # for (...) + $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() + $dstat !~ /^do\s*{/ && # do {... + $dstat !~ /^\({/ && # ({... + $ctx !~ /^.\s*#\s*define\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\b/) + { + $ctx =~ s/\n*$//; + my $herectx = $here . "\n"; + my $cnt = statement_rawlines($ctx); + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + if ($dstat =~ /;/) { + ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", + "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx"); + } else { + ERROR("COMPLEX_MACRO", + "Macros with complex values should be enclosed in parentheses\n" . "$herectx"); + } + } + +# check for macros with flow control, but without ## concatenation +# ## concatenation is commonly a macro that defines a function so ignore those + if ($has_flow_statement && !$has_arg_concat) { + my $herectx = $here . "\n"; + my $cnt = statement_rawlines($ctx); + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + WARN("MACRO_WITH_FLOW_CONTROL", + "Macros with flow control statements should be avoided\n" . "$herectx"); + } + +# check for line continuations outside of #defines, preprocessor #, and asm + + } else { + if ($prevline !~ /^..*\\$/ && + $line !~ /^\+\s*\#.*\\$/ && # preprocessor + $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm + $line =~ /^\+.*\\$/) { + WARN("LINE_CONTINUATIONS", + "Avoid unnecessary line continuations\n" . $herecurr); + } + } + +# do {} while (0) macro tests: +# single-statement macros do not need to be enclosed in do while (0) loop, +# macro should not end with a semicolon + if ($^V && $^V ge 5.10.0 && + $realfile !~ m@/vmlinux.lds.h$@ && + $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) { + my $ln = $linenr; + my $cnt = $realcnt; + my ($off, $dstat, $dcond, $rest); + my $ctx = ''; + ($dstat, $dcond, $ln, $cnt, $off) = + ctx_statement_block($linenr, $realcnt, 0); + $ctx = $dstat; + + $dstat =~ s/\\\n.//g; + + if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) { + my $stmts = $2; + my $semis = $3; + + $ctx =~ s/\n*$//; + my $cnt = statement_rawlines($ctx); + my $herectx = $here . "\n"; + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + if (($stmts =~ tr/;/;/) == 1 && + $stmts !~ /^\s*(if|while|for|switch)\b/) { + WARN("SINGLE_STATEMENT_DO_WHILE_MACRO", + "Single statement macros should not use a do {} while (0) loop\n" . "$herectx"); + } + if (defined $semis && $semis ne "") { + WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON", + "do {} while (0) macros should not be semicolon terminated\n" . "$herectx"); + } + } elsif ($dstat =~ /^\+\s*#\s*define\s+$Ident.*;\s*$/) { + $ctx =~ s/\n*$//; + my $cnt = statement_rawlines($ctx); + my $herectx = $here . "\n"; + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + WARN("TRAILING_SEMICOLON", + "macros should not use a trailing semicolon\n" . "$herectx"); + } + } + +# make sure symbols are always wrapped with VMLINUX_SYMBOL() ... +# all assignments may have only one of the following with an assignment: +# . +# ALIGN(...) +# VMLINUX_SYMBOL(...) + if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) { + WARN("MISSING_VMLINUX_SYMBOL", + "vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr); + } + +# check for redundant bracing round if etc + if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) { + my ($level, $endln, @chunks) = + ctx_statement_full($linenr, $realcnt, 1); + #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n"; + #print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n"; + if ($#chunks > 0 && $level == 0) { + my @allowed = (); + my $allow = 0; + my $seen = 0; + my $herectx = $here . "\n"; + my $ln = $linenr - 1; + for my $chunk (@chunks) { + my ($cond, $block) = @{$chunk}; + + # If the condition carries leading newlines, then count those as offsets. + my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s); + my $offset = statement_rawlines($whitespace) - 1; + + $allowed[$allow] = 0; + #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n"; + + # We have looked at and allowed this specific line. + $suppress_ifbraces{$ln + $offset} = 1; + + $herectx .= "$rawlines[$ln + $offset]\n[...]\n"; + $ln += statement_rawlines($block) - 1; + + substr($block, 0, length($cond), ''); + + $seen++ if ($block =~ /^\s*{/); + + #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n"; + if (statement_lines($cond) > 1) { + #print "APW: ALLOWED: cond<$cond>\n"; + $allowed[$allow] = 1; + } + if ($block =~/\b(?:if|for|while)\b/) { + #print "APW: ALLOWED: block<$block>\n"; + $allowed[$allow] = 1; + } + if (statement_block_size($block) > 1) { + #print "APW: ALLOWED: lines block<$block>\n"; + $allowed[$allow] = 1; + } + $allow++; + } + if ($seen) { + my $sum_allowed = 0; + foreach (@allowed) { + $sum_allowed += $_; + } + if ($sum_allowed == 0) { + WARN("BRACES", + "braces {} are not necessary for any arm of this statement\n" . $herectx); + } elsif ($sum_allowed != $allow && + $seen != $allow) { + CHK("BRACES", + "braces {} should be used on all arms of this statement\n" . $herectx); + } + } + } + } + if (!defined $suppress_ifbraces{$linenr - 1} && + $line =~ /\b(if|while|for|else)\b/) { + my $allowed = 0; + + # Check the pre-context. + if (substr($line, 0, $-[0]) =~ /(\}\s*)$/) { + #print "APW: ALLOWED: pre<$1>\n"; + $allowed = 1; + } + + my ($level, $endln, @chunks) = + ctx_statement_full($linenr, $realcnt, $-[0]); + + # Check the condition. + my ($cond, $block) = @{$chunks[0]}; + #print "CHECKING<$linenr> cond<$cond> block<$block>\n"; + if (defined $cond) { + substr($block, 0, length($cond), ''); + } + if (statement_lines($cond) > 1) { + #print "APW: ALLOWED: cond<$cond>\n"; + $allowed = 1; + } + if ($block =~/\b(?:if|for|while)\b/) { + #print "APW: ALLOWED: block<$block>\n"; + $allowed = 1; + } + if (statement_block_size($block) > 1) { + #print "APW: ALLOWED: lines block<$block>\n"; + $allowed = 1; + } + # Check the post-context. + if (defined $chunks[1]) { + my ($cond, $block) = @{$chunks[1]}; + if (defined $cond) { + substr($block, 0, length($cond), ''); + } + if ($block =~ /^\s*\{/) { + #print "APW: ALLOWED: chunk-1 block<$block>\n"; + $allowed = 1; + } + } + if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { + my $herectx = $here . "\n"; + my $cnt = statement_rawlines($block); + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + WARN("BRACES", + "braces {} are not necessary for single statement blocks\n" . $herectx); + } + } + +# check for unnecessary blank lines around braces + if (($line =~ /^.\s*}\s*$/ && $prevrawline =~ /^.\s*$/)) { + CHK("BRACES", + "Blank lines aren't necessary before a close brace '}'\n" . $hereprev); + } + if (($rawline =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { + CHK("BRACES", + "Blank lines aren't necessary after an open brace '{'\n" . $hereprev); + } + +# no volatiles please + my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b}; + if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) { + WARN("VOLATILE", + "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr); + } + +# concatenated string without spaces between elements + if ($line =~ /"X+"[A-Z_]+/ || $line =~ /[A-Z_]+"X+"/) { + CHK("CONCATENATED_STRING", + "Concatenated strings should use spaces between elements\n" . $herecurr); + } + +# warn about #if 0 + if ($line =~ /^.\s*\#\s*if\s+0\b/) { + CHK("REDUNDANT_CODE", + "if this code is redundant consider removing it\n" . + $herecurr); + } + +# check for needless "if () fn()" uses + if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) { + my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;'; + if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) { + WARN('NEEDLESS_IF', + "$1(NULL) is safe this check is probably not required\n" . $hereprev); + } + } + +# check for unnecessary "Out of Memory" messages + if ($line =~ /^\+.*\b$logFunctions\s*\(/ && + $prevline =~ /^[ \+]\s*if\s*\(\s*(\!\s*|NULL\s*==\s*)?($Lval)(\s*==\s*NULL\s*)?\s*\)/ && + (defined $1 || defined $3) && + $linenr > 3) { + my $testval = $2; + my $testline = $lines[$linenr - 3]; + + my ($s, $c) = ctx_statement_block($linenr - 3, $realcnt, 0); +# print("line: <$line>\nprevline: <$prevline>\ns: <$s>\nc: <$c>\n\n\n"); + + if ($c =~ /(?:^|\n)[ \+]\s*(?:$Type\s*)?\Q$testval\E\s*=\s*(?:\([^\)]*\)\s*)?\s*(?:devm_)?(?:[kv][czm]alloc(?:_node|_array)?\b|kstrdup|(?:dev_)?alloc_skb)/) { + WARN("OOM_MESSAGE", + "Possible unnecessary 'out of memory' message\n" . $hereprev); + } + } + +# check for logging functions with KERN_ + if ($line !~ /printk\s*\(/ && + $line =~ /\b$logFunctions\s*\(.*\b(KERN_[A-Z]+)\b/) { + my $level = $1; + if (WARN("UNNECESSARY_KERN_LEVEL", + "Possible unnecessary $level\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\s*$level\s*//; + } + } + +# check for bad placement of section $InitAttribute (e.g.: __initdata) + if ($line =~ /(\b$InitAttribute\b)/) { + my $attr = $1; + if ($line =~ /^\+\s*static\s+(?:const\s+)?(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*[=;]/) { + my $ptr = $1; + my $var = $2; + if ((($ptr =~ /\b(union|struct)\s+$attr\b/ && + ERROR("MISPLACED_INIT", + "$attr should be placed after $var\n" . $herecurr)) || + ($ptr !~ /\b(union|struct)\s+$attr\b/ && + WARN("MISPLACED_INIT", + "$attr should be placed after $var\n" . $herecurr))) && + $fix) { + $fixed[$fixlinenr] =~ s/(\bstatic\s+(?:const\s+)?)(?:$attr\s+)?($NonptrTypeWithAttr)\s+(?:$attr\s+)?($Ident(?:\[[^]]*\])?)\s*([=;])\s*/"$1" . trim(string_find_replace($2, "\\s*$attr\\s*", " ")) . " " . trim(string_find_replace($3, "\\s*$attr\\s*", "")) . " $attr" . ("$4" eq ";" ? ";" : " = ")/e; + } + } + } + +# check for $InitAttributeData (ie: __initdata) with const + if ($line =~ /\bconst\b/ && $line =~ /($InitAttributeData)/) { + my $attr = $1; + $attr =~ /($InitAttributePrefix)(.*)/; + my $attr_prefix = $1; + my $attr_type = $2; + if (ERROR("INIT_ATTRIBUTE", + "Use of const init definition must use ${attr_prefix}initconst\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/$InitAttributeData/${attr_prefix}initconst/; + } + } + +# check for $InitAttributeConst (ie: __initconst) without const + if ($line !~ /\bconst\b/ && $line =~ /($InitAttributeConst)/) { + my $attr = $1; + if (ERROR("INIT_ATTRIBUTE", + "Use of $attr requires a separate use of const\n" . $herecurr) && + $fix) { + my $lead = $fixed[$fixlinenr] =~ + /(^\+\s*(?:static\s+))/; + $lead = rtrim($1); + $lead = "$lead " if ($lead !~ /^\+$/); + $lead = "${lead}const "; + $fixed[$fixlinenr] =~ s/(^\+\s*(?:static\s+))/$lead/; + } + } + +# don't use __constant_ functions outside of include/uapi/ + if ($realfile !~ m@^include/uapi/@ && + $line =~ /(__constant_(?:htons|ntohs|[bl]e(?:16|32|64)_to_cpu|cpu_to_[bl]e(?:16|32|64)))\s*\(/) { + my $constant_func = $1; + my $func = $constant_func; + $func =~ s/^__constant_//; + if (WARN("CONSTANT_CONVERSION", + "$constant_func should be $func\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b$constant_func\b/$func/g; + } + } + +# prefer usleep_range over udelay + if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) { + my $delay = $1; + # ignore udelay's < 10, however + if (! ($delay < 10) ) { + CHK("USLEEP_RANGE", + "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $herecurr); + } + if ($delay > 2000) { + WARN("LONG_UDELAY", + "long udelay - prefer mdelay; see arch/arm/include/asm/delay.h\n" . $herecurr); + } + } + +# warn about unexpectedly long msleep's + if ($line =~ /\bmsleep\s*\((\d+)\);/) { + if ($1 < 20) { + WARN("MSLEEP", + "msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $herecurr); + } + } + +# check for comparisons of jiffies + if ($line =~ /\bjiffies\s*$Compare|$Compare\s*jiffies\b/) { + WARN("JIFFIES_COMPARISON", + "Comparing jiffies is almost always wrong; prefer time_after, time_before and friends\n" . $herecurr); + } + +# check for comparisons of get_jiffies_64() + if ($line =~ /\bget_jiffies_64\s*\(\s*\)\s*$Compare|$Compare\s*get_jiffies_64\s*\(\s*\)/) { + WARN("JIFFIES_COMPARISON", + "Comparing get_jiffies_64() is almost always wrong; prefer time_after64, time_before64 and friends\n" . $herecurr); + } + +# warn about #ifdefs in C files +# if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) { +# print "#ifdef in C files should be avoided\n"; +# print "$herecurr"; +# $clean = 0; +# } + +# warn about spacing in #ifdefs + if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) { + if (ERROR("SPACING", + "exactly one space required after that #$1\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ + s/^(.\s*\#\s*(ifdef|ifndef|elif))\s{2,}/$1 /; + } + + } + +# check for spinlock_t definitions without a comment. + if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ || + $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) { + my $which = $1; + if (!ctx_has_comment($first_line, $linenr)) { + CHK("UNCOMMENTED_DEFINITION", + "$1 definition without comment\n" . $herecurr); + } + } +# check for memory barriers without a comment. + if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { + if (!ctx_has_comment($first_line, $linenr)) { + WARN("MEMORY_BARRIER", + "memory barrier without comment\n" . $herecurr); + } + } +# check of hardware specific defines + if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) { + CHK("ARCH_DEFINES", + "architecture specific defines should be avoided\n" . $herecurr); + } + +# Check that the storage class is at the beginning of a declaration + if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) { + WARN("STORAGE_CLASS", + "storage class should be at the beginning of the declaration\n" . $herecurr) + } + +# check the location of the inline attribute, that it is between +# storage class and type. + if ($line =~ /\b$Type\s+$Inline\b/ || + $line =~ /\b$Inline\s+$Storage\b/) { + ERROR("INLINE_LOCATION", + "inline keyword should sit between storage class and type\n" . $herecurr); + } + +# Check for __inline__ and __inline, prefer inline + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b(__inline__|__inline)\b/) { + if (WARN("INLINE", + "plain inline is preferred over $1\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b(__inline__|__inline)\b/inline/; + + } + } + +# Check for __attribute__ packed, prefer __packed + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(.*\bpacked\b/) { + WARN("PREFER_PACKED", + "__packed is preferred over __attribute__((packed))\n" . $herecurr); + } + +# Check for __attribute__ aligned, prefer __aligned + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) { + WARN("PREFER_ALIGNED", + "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr); + } + +# Check for __attribute__ format(printf, prefer __printf + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { + if (WARN("PREFER_PRINTF", + "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf\s*,\s*(.*)\)\s*\)\s*\)/"__printf(" . trim($1) . ")"/ex; + + } + } + +# Check for __attribute__ format(scanf, prefer __scanf + if ($realfile !~ m@\binclude/uapi/@ && + $line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { + if (WARN("PREFER_SCANF", + "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\s*,\s*(.*)\)\s*\)\s*\)/"__scanf(" . trim($1) . ")"/ex; + } + } + +# check for sizeof(&) + if ($line =~ /\bsizeof\s*\(\s*\&/) { + WARN("SIZEOF_ADDRESS", + "sizeof(& should be avoided\n" . $herecurr); + } + +# check for sizeof without parenthesis + if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) { + if (WARN("SIZEOF_PARENTHESIS", + "sizeof $1 should be sizeof($1)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/"sizeof(" . trim($1) . ")"/ex; + } + } + +# check for line continuations in quoted strings with odd counts of " + if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) { + WARN("LINE_CONTINUATIONS", + "Avoid line continuations in quoted strings\n" . $herecurr); + } + +# check for struct spinlock declarations + if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) { + WARN("USE_SPINLOCK_T", + "struct spinlock should be spinlock_t\n" . $herecurr); + } + +# check for seq_printf uses that could be seq_puts + if ($sline =~ /\bseq_printf\s*\(.*"\s*\)\s*;\s*$/) { + my $fmt = get_quoted_string($line, $rawline); + if ($fmt ne "" && $fmt !~ /[^\\]\%/) { + if (WARN("PREFER_SEQ_PUTS", + "Prefer seq_puts to seq_printf\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bseq_printf\b/seq_puts/; + } + } + } + +# Check for misused memsets + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) { + + my $ms_addr = $2; + my $ms_val = $7; + my $ms_size = $12; + + if ($ms_size =~ /^(0x|)0$/i) { + ERROR("MEMSET", + "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n"); + } elsif ($ms_size =~ /^(0x|)1$/i) { + WARN("MEMSET", + "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n"); + } + } + +# Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar) + if ($^V && $^V ge 5.10.0 && + $line =~ /^\+(?:.*?)\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/s) { + if (WARN("PREFER_ETHER_ADDR_COPY", + "Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\bmemcpy\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*ETH_ALEN\s*\)/ether_addr_copy($2, $7)/; + } + } + +# typecasts on min/max could be min_t/max_t + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) { + if (defined $2 || defined $7) { + my $call = $1; + my $cast1 = deparenthesize($2); + my $arg1 = $3; + my $cast2 = deparenthesize($7); + my $arg2 = $8; + my $cast; + + if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) { + $cast = "$cast1 or $cast2"; + } elsif ($cast1 ne "") { + $cast = $cast1; + } else { + $cast = $cast2; + } + WARN("MINMAX", + "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n"); + } + } + +# check usleep_range arguments + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) { + my $min = $1; + my $max = $7; + if ($min eq $max) { + WARN("USLEEP_RANGE", + "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); + } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ && + $min > $max) { + WARN("USLEEP_RANGE", + "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); + } + } + +# check for naked sscanf + if ($^V && $^V ge 5.10.0 && + defined $stat && + $line =~ /\bsscanf\b/ && + ($stat !~ /$Ident\s*=\s*sscanf\s*$balanced_parens/ && + $stat !~ /\bsscanf\s*$balanced_parens\s*(?:$Compare)/ && + $stat !~ /(?:$Compare)\s*\bsscanf\s*$balanced_parens/)) { + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = raw_line($linenr, 0); + for (my $count = $linenr + 1; $count <= $lc; $count++) { + $stat_real = $stat_real . "\n" . raw_line($count, 0); + } + WARN("NAKED_SSCANF", + "unchecked sscanf return value\n" . "$here\n$stat_real\n"); + } + +# check for simple sscanf that should be kstrto + if ($^V && $^V ge 5.10.0 && + defined $stat && + $line =~ /\bsscanf\b/) { + my $lc = $stat =~ tr@\n@@; + $lc = $lc + $linenr; + my $stat_real = raw_line($linenr, 0); + for (my $count = $linenr + 1; $count <= $lc; $count++) { + $stat_real = $stat_real . "\n" . raw_line($count, 0); + } + if ($stat_real =~ /\bsscanf\b\s*\(\s*$FuncArg\s*,\s*("[^"]+")/) { + my $format = $6; + my $count = $format =~ tr@%@%@; + if ($count == 1 && + $format =~ /^"\%(?i:ll[udxi]|[udxi]ll|ll|[hl]h?[udxi]|[udxi][hl]h?|[hl]h?|[udxi])"$/) { + WARN("SSCANF_TO_KSTRTO", + "Prefer kstrto to single variable sscanf\n" . "$here\n$stat_real\n"); + } + } + } + +# check for new externs in .h files. + if ($realfile =~ /\.h$/ && + $line =~ /^\+\s*(extern\s+)$Type\s*$Ident\s*\(/s) { + if (CHK("AVOID_EXTERNS", + "extern prototypes should be avoided in .h files\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(.*)\bextern\b\s*(.*)/$1$2/; + } + } + +# check for new externs in .c files. + if ($realfile =~ /\.c$/ && defined $stat && + $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) + { + my $function_name = $1; + my $paren_space = $2; + + my $s = $stat; + if (defined $cond) { + substr($s, 0, length($cond), ''); + } + if ($s =~ /^\s*;/ && + $function_name ne 'uninitialized_var') + { + WARN("AVOID_EXTERNS", + "externs should be avoided in .c files\n" . $herecurr); + } + + if ($paren_space =~ /\n/) { + WARN("FUNCTION_ARGUMENTS", + "arguments for function declarations should follow identifier\n" . $herecurr); + } + + } elsif ($realfile =~ /\.c$/ && defined $stat && + $stat =~ /^.\s*extern\s+/) + { + WARN("AVOID_EXTERNS", + "externs should be avoided in .c files\n" . $herecurr); + } + +# checks for new __setup's + if ($rawline =~ /\b__setup\("([^"]*)"/) { + my $name = $1; + + if (!grep(/$name/, @setup_docs)) { + CHK("UNDOCUMENTED_SETUP", + "__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr); + } + } + +# check for pointless casting of kmalloc return + if ($line =~ /\*\s*\)\s*[kv][czm]alloc(_node){0,1}\b/) { + WARN("UNNECESSARY_CASTS", + "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); + } + +# alloc style +# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...) + if ($^V && $^V ge 5.10.0 && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*([kv][mz]alloc(?:_node)?)\s*\(\s*(sizeof\s*\(\s*struct\s+$Lval\s*\))/) { + CHK("ALLOC_SIZEOF_STRUCT", + "Prefer $3(sizeof(*$1)...) over $3($4...)\n" . $herecurr); + } + +# check for k[mz]alloc with multiplies that could be kmalloc_array/kcalloc + if ($^V && $^V ge 5.10.0 && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*(k[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)\s*,/) { + my $oldfunc = $3; + my $a1 = $4; + my $a2 = $10; + my $newfunc = "kmalloc_array"; + $newfunc = "kcalloc" if ($oldfunc eq "kzalloc"); + my $r1 = $a1; + my $r2 = $a2; + if ($a1 =~ /^sizeof\s*\S/) { + $r1 = $a2; + $r2 = $a1; + } + if ($r1 !~ /^sizeof\b/ && $r2 =~ /^sizeof\s*\S/ && + !($r1 =~ /^$Constant$/ || $r1 =~ /^[A-Z_][A-Z0-9_]*$/)) { + if (WARN("ALLOC_WITH_MULTIPLY", + "Prefer $newfunc over $oldfunc with multiply\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*(k[mz]alloc)\s*\(\s*($FuncArg)\s*\*\s*($FuncArg)/$1 . ' = ' . "$newfunc(" . trim($r1) . ', ' . trim($r2)/e; + + } + } + } + +# check for krealloc arg reuse + if ($^V && $^V ge 5.10.0 && + $line =~ /\b($Lval)\s*\=\s*(?:$balanced_parens)?\s*krealloc\s*\(\s*\1\s*,/) { + WARN("KREALLOC_ARG_REUSE", + "Reusing the krealloc arg is almost always a bug\n" . $herecurr); + } + +# check for alloc argument mismatch + if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { + WARN("ALLOC_ARRAY_ARGS", + "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); + } + +# check for multiple semicolons + if ($line =~ /;\s*;\s*$/) { + if (WARN("ONE_SEMICOLON", + "Statements terminations use 1 semicolon\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/(\s*;\s*){2,}$/;/g; + } + } + +# check for case / default statements not preceded by break/fallthrough/switch + if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) { + my $has_break = 0; + my $has_statement = 0; + my $count = 0; + my $prevline = $linenr; + while ($prevline > 1 && ($file || $count < 3) && !$has_break) { + $prevline--; + my $rline = $rawlines[$prevline - 1]; + my $fline = $lines[$prevline - 1]; + last if ($fline =~ /^\@\@/); + next if ($fline =~ /^\-/); + next if ($fline =~ /^.(?:\s*(?:case\s+(?:$Ident|$Constant)[\s$;]*|default):[\s$;]*)*$/); + $has_break = 1 if ($rline =~ /fall[\s_-]*(through|thru)/i); + next if ($fline =~ /^.[\s$;]*$/); + $has_statement = 1; + $count++; + $has_break = 1 if ($fline =~ /\bswitch\b|\b(?:break\s*;[\s$;]*$|return\b|goto\b|continue\b)/); + } + if (!$has_break && $has_statement) { + WARN("MISSING_BREAK", + "Possible switch case/default not preceeded by break or fallthrough comment\n" . $herecurr); + } + } + +# check for switch/default statements without a break; + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { + my $ctx = ''; + my $herectx = $here . "\n"; + my $cnt = statement_rawlines($stat); + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + WARN("DEFAULT_NO_BREAK", + "switch default: should use break\n" . $herectx); + } + +# check for gcc specific __FUNCTION__ + if ($line =~ /\b__FUNCTION__\b/) { + if (WARN("USE_FUNC", + "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr) && + $fix) { + $fixed[$fixlinenr] =~ s/\b__FUNCTION__\b/__func__/g; + } + } + +# check for use of yield() + if ($line =~ /\byield\s*\(\s*\)/) { + WARN("YIELD", + "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr); + } + +# check for comparisons against true and false + if ($line =~ /\+\s*(.*?)\b(true|false|$Lval)\s*(==|\!=)\s*(true|false|$Lval)\b(.*)$/i) { + my $lead = $1; + my $arg = $2; + my $test = $3; + my $otype = $4; + my $trail = $5; + my $op = "!"; + + ($arg, $otype) = ($otype, $arg) if ($arg =~ /^(?:true|false)$/i); + + my $type = lc($otype); + if ($type =~ /^(?:true|false)$/) { + if (("$test" eq "==" && "$type" eq "true") || + ("$test" eq "!=" && "$type" eq "false")) { + $op = ""; + } + + CHK("BOOL_COMPARISON", + "Using comparison to $otype is error prone\n" . $herecurr); + +## maybe suggesting a correct construct would better +## "Using comparison to $otype is error prone. Perhaps use '${lead}${op}${arg}${trail}'\n" . $herecurr); + + } + } + +# check for semaphores initialized locked + if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { + WARN("CONSIDER_COMPLETION", + "consider using a completion\n" . $herecurr); + } + +# recommend kstrto* over simple_strto* and strict_strto* + if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) { + WARN("CONSIDER_KSTRTO", + "$1 is obsolete, use k$3 instead\n" . $herecurr); + } + +# check for __initcall(), use device_initcall() explicitly or more appropriate function please + if ($line =~ /^.\s*__initcall\s*\(/) { + WARN("USE_DEVICE_INITCALL", + "please use device_initcall() or more appropriate function instead of __initcall() (see include/linux/init.h)\n" . $herecurr); + } + +# check for various ops structs, ensure they are const. + my $struct_ops = qr{acpi_dock_ops| + address_space_operations| + backlight_ops| + block_device_operations| + dentry_operations| + dev_pm_ops| + dma_map_ops| + extent_io_ops| + file_lock_operations| + file_operations| + hv_ops| + ide_dma_ops| + intel_dvo_dev_ops| + item_operations| + iwl_ops| + kgdb_arch| + kgdb_io| + kset_uevent_ops| + lock_manager_operations| + microcode_ops| + mtrr_ops| + neigh_ops| + nlmsvc_binding| + pci_raw_ops| + pipe_buf_operations| + platform_hibernation_ops| + platform_suspend_ops| + proto_ops| + rpc_pipe_ops| + seq_operations| + snd_ac97_build_ops| + soc_pcmcia_socket_ops| + stacktrace_ops| + sysfs_ops| + tty_operations| + usb_mon_operations| + wd_ops}x; + if ($line !~ /\bconst\b/ && + $line =~ /\bstruct\s+($struct_ops)\b/) { + WARN("CONST_STRUCT", + "struct $1 should normally be const\n" . + $herecurr); + } + +# use of NR_CPUS is usually wrong +# ignore definitions of NR_CPUS and usage to define arrays as likely right + if ($line =~ /\bNR_CPUS\b/ && + $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && + $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && + $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && + $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && + $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) + { + WARN("NR_CPUS", + "usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); + } + +# Use of __ARCH_HAS_ or ARCH_HAVE_ is wrong. + if ($line =~ /\+\s*#\s*define\s+((?:__)?ARCH_(?:HAS|HAVE)\w*)\b/) { + ERROR("DEFINE_ARCH_HAS", + "#define of '$1' is wrong - use Kconfig variables or standard guards instead\n" . $herecurr); + } + +# check for %L{u,d,i} in strings + my $string; + while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { + $string = substr($rawline, $-[1], $+[1] - $-[1]); + $string =~ s/%%/__/g; + if ($string =~ /(?mutex.\n" . $herecurr); + } + } + + if ($line =~ /debugfs_create_file.*S_IWUGO/ || + $line =~ /DEVICE_ATTR.*S_IWUGO/ ) { + WARN("EXPORTED_WORLD_WRITABLE", + "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr); + } + +# Mode permission misuses where it seems decimal should be octal +# This uses a shortcut match to avoid unnecessary uses of a slow foreach loop + if ($^V && $^V ge 5.10.0 && + $line =~ /$mode_perms_search/) { + foreach my $entry (@mode_permission_funcs) { + my $func = $entry->[0]; + my $arg_pos = $entry->[1]; + + my $skip_args = ""; + if ($arg_pos > 1) { + $arg_pos--; + $skip_args = "(?:\\s*$FuncArg\\s*,\\s*){$arg_pos,$arg_pos}"; + } + my $test = "\\b$func\\s*\\(${skip_args}([\\d]+)\\s*[,\\)]"; + if ($line =~ /$test/) { + my $val = $1; + $val = $6 if ($skip_args ne ""); + + if ($val !~ /^0$/ && + (($val =~ /^$Int$/ && $val !~ /^$Octal$/) || + length($val) ne 4)) { + ERROR("NON_OCTAL_PERMISSIONS", + "Use 4 digit octal (0777) not decimal permissions\n" . $herecurr); + } + } + } + } + } + + # If we have no input at all, then there is nothing to report on + # so just keep quiet. + if ($#rawlines == -1) { + exit(0); + } + + # In mailback mode only produce a report in the negative, for + # things that appear to be patches. + if ($mailback && ($clean == 1 || !$is_patch)) { + exit(0); + } + + # This is not a patch, and we are are in 'no-patch' mode so + # just keep quiet. + if (!$chk_patch && !$is_patch) { + exit(0); + } + + if (!$is_patch) { + ERROR("NOT_UNIFIED_DIFF", + "Does not appear to be a unified-diff format patch\n"); + } + if ($is_patch && $chk_signoff && $signoff == 0) { + ERROR("MISSING_SIGN_OFF", + "Missing Signed-off-by: line(s)\n"); + } + + print report_dump(); + if ($summary && !($clean == 1 && $quiet == 1)) { + print "$filename " if ($summary_file); + print "total: $cnt_error errors, $cnt_warn warnings, " . + (($check)? "$cnt_chk checks, " : "") . + "$cnt_lines lines checked\n"; + print "\n" if ($quiet == 0); + } + + if ($quiet == 0) { + + if ($^V lt 5.10.0) { + print("NOTE: perl $^V is not modern enough to detect all possible issues.\n"); + print("An upgrade to at least perl v5.10.0 is suggested.\n\n"); + } + + # If there were whitespace errors which cleanpatch can fix + # then suggest that. + if ($rpt_cleaners) { + print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n"; + print " scripts/cleanfile\n\n"; + $rpt_cleaners = 0; + } + } + + hash_show_words(\%use_type, "Used"); + hash_show_words(\%ignore_type, "Ignored"); + + if ($clean == 0 && $fix && + ("@rawlines" ne "@fixed" || + $#fixed_inserted >= 0 || $#fixed_deleted >= 0)) { + my $newfile = $filename; + $newfile .= ".EXPERIMENTAL-checkpatch-fixes" if (!$fix_inplace); + my $linecount = 0; + my $f; + + @fixed = fix_inserted_deleted_lines(\@fixed, \@fixed_inserted, \@fixed_deleted); + + open($f, '>', $newfile) + or die "$P: Can't open $newfile for write\n"; + foreach my $fixed_line (@fixed) { + $linecount++; + if ($file) { + if ($linecount > 3) { + $fixed_line =~ s/^\+//; + print $f $fixed_line . "\n"; + } + } else { + print $f $fixed_line . "\n"; + } + } + close($f); + + if (!$quiet) { + print << "EOM"; +Wrote EXPERIMENTAL --fix correction(s) to '$newfile' + +Do _NOT_ trust the results written to this file. +Do _NOT_ submit these changes without inspecting them for correctness. + +This EXPERIMENTAL file is simply a convenience to help rewrite patches. +No warranties, expressed or implied... + +EOM + } + } + + if ($clean == 1 && $quiet == 0) { + print "$vname has no obvious style problems and is ready for submission.\n" + } + if ($clean == 0 && $quiet == 0) { + print << "EOM"; +$vname has style problems, please review. + +If any of these errors are false positives, please report +them to the maintainer, see CHECKPATCH in MAINTAINERS. +EOM + } + + return $clean; +} diff --git a/scripts/spelling.txt b/scripts/spelling.txt new file mode 100644 index 00000000..fc7fd52b --- /dev/null +++ b/scripts/spelling.txt @@ -0,0 +1,1042 @@ +# Originally from Debian's Lintian tool. Various false positives have been +# removed, and various additions have been made as they've been discovered +# in the kernel source. +# +# License: GPLv2 +# +# The format of each line is: +# mistake||correction +# +abandonning||abandoning +abigious||ambiguous +abitrate||arbitrate +abov||above +abreviated||abbreviated +absense||absence +absolut||absolute +absoulte||absolute +acccess||access +acceleratoin||acceleration +accelleration||acceleration +accesing||accessing +accesnt||accent +accessable||accessible +accesss||access +accidentaly||accidentally +accidentually||accidentally +accoding||according +accomodate||accommodate +accomodates||accommodates +accordign||according +accoring||according +accout||account +accquire||acquire +accquired||acquired +acessable||accessible +acess||access +achitecture||architecture +acient||ancient +acitions||actions +acitve||active +acknowldegement||acknowldegement +acknowledgement||acknowledgment +ackowledge||acknowledge +ackowledged||acknowledged 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+shrinked||shrunk +siginificantly||significantly +signabl||signal +similary||similarly +similiar||similar +simlar||similar +simliar||similar +simpified||simplified +singaled||signaled +singal||signal +singed||signed +sleeped||slept +softwares||software +speach||speech +specfic||specific +speciefied||specified +specifc||specific +specifed||specified +specificatin||specification +specificaton||specification +specifing||specifying +specifiying||specifying +speficied||specified +speicify||specify +speling||spelling +spinlcok||spinlock +spinock||spinlock +splitted||split +spreaded||spread +sructure||structure +stablilization||stabilization +staically||statically +staion||station +standardss||standards +standartization||standardization +standart||standard +staticly||statically +stoped||stopped +stoppped||stopped +straming||streaming +struc||struct +structres||structures +stuct||struct +sturcture||structure +subdirectoires||subdirectories +suble||subtle +succesfully||successfully +succesful||successful +successfull||successful +sucessfully||successfully +sucess||success +superflous||superfluous +superseeded||superseded +suplied||supplied +suported||supported +suport||support +suppored||supported +supportin||supporting +suppoted||supported +suppported||supported +suppport||support +supress||suppress +surpresses||suppresses +susbsystem||subsystem +suspicously||suspiciously +swaping||swapping +switchs||switches +symetric||symmetric +synax||syntax +synchonized||synchronized +syncronize||synchronize +syncronizing||synchronizing +syncronus||synchronous +syste||system +sytem||system +sythesis||synthesis +taht||that +targetted||targeted +targetting||targeting +teh||the +temorary||temporary +temproarily||temporarily +thier||their +threds||threads +threshhold||threshold +throught||through +thses||these +tiggered||triggered +tipically||typically +tmis||this +torerable||tolerable +tramsmitted||transmitted +tramsmit||transmit +tranfer||transfer +transciever||transceiver +transferd||transferrd +transfered||transferred +transfering||transferring +transision||transition +transmittd||transmitted +transormed||transformed +trasmission||transmission +treshold||threshold +trigerring||triggering +trun||turn +ture||true +tyep||type +udpate||update +uesd||used +unconditionaly||unconditionally +underun||underrun +unecessary||unnecessary +unexecpted||unexpected +unexpectd||unexpected +unexpeted||unexpected +unfortunatelly||unfortunately +unifiy||unify +unknonw||unknown +unknow||unknown +unkown||unknown +unneedingly||unnecessarily +unresgister||unregister +unsinged||unsigned +unstabel||unstable +unsuccessfull||unsuccessful +unsuported||unsupported +untill||until +unuseful||useless +upate||update +usefule||useful +usefull||useful +usege||usage +usera||users +usualy||usually +utilites||utilities +utillities||utilities +utilties||utilities +utiltity||utility +utitity||utility +utitlty||utility +vaid||valid +vaild||valid +valide||valid +variantions||variations +varient||variant +vaule||value +verbse||verbose +verisons||versions +verison||version +verson||version +vicefersa||vice-versa +virtal||virtual +virtaul||virtual +virtiual||virtual +visiters||visitors +vitual||virtual +wating||waiting +whataver||whatever +whenver||whenever +wheter||whether +whe||when +wierd||weird +wiil||will +wirte||write +withing||within +wnat||want +workarould||workaround +writeing||writing +writting||writing +zombe||zombie +zomebie||zombie -- cgit v1.2.2 From e19ee13cc77c4770fabc6917b421f24cdaefec8c Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 19 Apr 2016 14:03:52 -0700 Subject: gpu: nvgpu: gv11b: set soc memory aperture type For gv11b, set platform data for soc memory aperture type to sysmem instead of vidmem. Bug 1749338 Change-Id: I6632e79e3ca68c437e5b04f6865f8f0b6f2943ce Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1129169 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 322bebc8..37b49106 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -76,6 +76,8 @@ static int gv11b_tegra_probe(struct device *dev) platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false; platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false; + /* soc memory accessed as system memory aperture */ + platform->g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem; gv11b_tegra_get_clocks(dev); @@ -146,4 +148,8 @@ struct gk20a_platform t19x_gpu_tegra_platform = { .default_big_page_size = SZ_64K, + .soc_name = "tegra19x", + + .vidmem_is_vidmem = true, + }; -- cgit v1.2.2 From c8b6a331d1e30595c5798fc3121575c1ab21e2ae Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 27 Apr 2016 18:25:57 +0530 Subject: gpu: nvgpu: use preemption modes defined in nvgpu-t18x.h Below definitions of preemption modes are deleted: NVGPU_GR_PREEMPTION_MODE_GFXP NVGPU_GR_PREEMPTION_MODE_CILP Use new definitions defined in nvgpu-t18x.h NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP NVGPU_COMPUTE_PREEMPTION_MODE_CILP Bug 1646259 Change-Id: Ieff51e41ef34eb61357f95778c400c8a3fa330c8 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1133597 Reviewed-by: Seshendra Gadagottu Reviewed-by: Ken Adams GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index f0736e19..5dee0921 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -320,7 +320,7 @@ static int gr_gv11b_commit_global_cb_manager(struct gk20a *g, gk20a_dbg_fn(""); - if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { + if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) { attrib_size_in_chunk = gr->attrib_cb_default_size + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); @@ -869,14 +869,14 @@ static int gr_gv11b_alloc_gr_ctx(struct gk20a *g, goto fail_free_betacb; } - (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP; + (*gr_ctx)->graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; } if (class == PASCAL_COMPUTE_A) { if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) - (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; + (*gr_ctx)->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP; else - (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; + (*gr_ctx)->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CTA; } gk20a_dbg_fn("done"); @@ -978,13 +978,13 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, gk20a_dbg_fn(""); - if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { + if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) { gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_graphics_preemption_options_o(), 0, gfxp_preempt_option); } - if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_CILP) { + if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) { gk20a_dbg_info("CILP: %x", cilp_preempt_option); gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_compute_preemption_options_o(), 0, cilp_preempt_option); @@ -1542,8 +1542,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, bool *early_exit, bool *ignore_debugger) { int ret; - bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->preempt_mode == - NVGPU_GR_PREEMPTION_MODE_CILP) ; + bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode == + NVGPU_COMPUTE_PREEMPTION_MODE_CILP) ; u32 global_mask = 0, dbgr_control0, global_esr_copy; u32 offset = proj_gpc_stride_v() * gpc + proj_tpc_in_gpc_stride_v() * tpc; -- cgit v1.2.2 From d089e402355f3533b18a50a4e9fe7423593762af Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Fri, 6 May 2016 14:34:07 +0300 Subject: gpu: nvgpu: refactor gk20a_mem_{wr,rd} for vidmem To support vidmem, pass g and mem_desc to the buffer memory accessor functions. This allows the functions to select the memory access method based on the buffer aperture instead of using the cpu pointer directly (like until now). The selection and aperture support will be in another patch; this patch only refactors these accessors, but keeps the underlying functionality as-is. JIRA DNVGPU-23 Change-Id: Ie2cc17c4a0315d03a66e92fb635c217840d5399e Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1128863 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 61 +++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 5dee0921..64bfa773 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -897,52 +897,51 @@ fail_free_gk20a_ctx: } static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, - struct gr_ctx_desc *gr_ctx) { - void *ctx_ptr = vmap(gr_ctx->mem.pages, - PAGE_ALIGN(gr_ctx->mem.size) >> PAGE_SHIFT, - 0, pgprot_writecombine(PAGE_KERNEL)); - if (!ctx_ptr) { + struct gr_ctx_desc *gr_ctx) +{ + struct mem_desc *mem = &gr_ctx->mem; + + if (gk20a_mem_begin(g, mem)) { WARN_ON("Cannot map context"); return; } gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_magic_value_o(), 0), + gk20a_mem_rd(g, mem, + ctxsw_prog_main_image_magic_value_o()), ctxsw_prog_main_image_magic_value_v_value_v()); gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(), 0)); + gk20a_mem_rd(g, mem, + ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o())); gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(), 0)); + gk20a_mem_rd(g, mem, + ctxsw_prog_main_image_context_timestamp_buffer_ptr_o())); gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_context_timestamp_buffer_control_o(), 0)); + gk20a_mem_rd(g, mem, + ctxsw_prog_main_image_context_timestamp_buffer_control_o())); gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_num_save_ops_o(), 0)); + gk20a_mem_rd(g, mem, + ctxsw_prog_main_image_num_save_ops_o())); gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_num_wfi_save_ops_o(), 0)); + gk20a_mem_rd(g, mem, + ctxsw_prog_main_image_num_wfi_save_ops_o())); gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_num_cta_save_ops_o(), 0)); + gk20a_mem_rd(g, mem, + ctxsw_prog_main_image_num_cta_save_ops_o())); gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_num_gfxp_save_ops_o(), 0)); + gk20a_mem_rd(g, mem, + ctxsw_prog_main_image_num_gfxp_save_ops_o())); gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_num_cilp_save_ops_o(), 0)); + gk20a_mem_rd(g, mem, + ctxsw_prog_main_image_num_cilp_save_ops_o())); gk20a_err(dev_from_gk20a(g), "image gfx preemption option (GFXP is 1) %x\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_graphics_preemption_options_o(), - 0)); - vunmap(ctx_ptr); + gk20a_mem_rd(g, mem, + ctxsw_prog_main_image_graphics_preemption_options_o())); + gk20a_mem_end(g, mem); } static void gr_gv11b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, @@ -967,7 +966,7 @@ static void gr_gv11b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, - void *ctx_ptr) + struct mem_desc *mem) { struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; u32 gfxp_preempt_option = @@ -980,13 +979,13 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) { gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); - gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_graphics_preemption_options_o(), 0, + gk20a_mem_wr(g, mem, ctxsw_prog_main_image_graphics_preemption_options_o(), gfxp_preempt_option); } if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) { gk20a_dbg_info("CILP: %x", cilp_preempt_option); - gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_compute_preemption_options_o(), 0, + gk20a_mem_wr(g, mem, ctxsw_prog_main_image_compute_preemption_options_o(), cilp_preempt_option); } @@ -995,7 +994,7 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, u32 size; u32 cbes_reserve; - gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_full_preemption_ptr_o(), 0, + gk20a_mem_wr(g, mem, ctxsw_prog_main_image_full_preemption_ptr_o(), gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8); err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); -- cgit v1.2.2 From 6863c08cc6c2ea1badfe23a536f6bf08d5d5431a Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 11 May 2016 16:55:23 +0530 Subject: gpu: nvgpu: Add support for multiple PBDMAs Added support for multiple PBDMAs handling during fifo_pbdma_isr and gk20a_init_fifo_reset_enable_hw use case. JIRA DNVGPU-26 Change-Id: I2e70c6f9a724899aaef179ae015149d7127f227b Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1145603 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index 500d2434..55960a4d 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h @@ -326,6 +326,10 @@ static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) { return (v & 0x1) << (0 + i*1); } +static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) { return 0x0000000e; -- cgit v1.2.2 From c3117bf337371d6e161a13849cadc8a4fc9c63b0 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 10 May 2016 13:47:17 -0700 Subject: gpu: nvgpu: gv11b: Use gp10b GR floorsweeping Use gp10b version of GR floorsweeping function. Change-Id: I5715672b5f94b779165f44c78aec14a2836928e7 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1144905 --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 64bfa773..cb9c1902 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1310,19 +1310,7 @@ static void gr_gv11b_commit_global_bundle_cb(struct gk20a *g, static int gr_gv11b_init_fs_state(struct gk20a *g) { - u32 data; - - data = gk20a_readl(g, gr_gpcs_tpcs_sm_texio_control_r()); - data = set_field(data, gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(), - gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); - gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); - - data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r()); - data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(), - gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); - gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); - - return gr_gm20b_ctx_state_floorsweep(g); + return gr_gp10b_init_fs_state(g); } static void gr_gv11b_init_cyclestats(struct gk20a *g) -- cgit v1.2.2 From a5274c2bc75f68b495f4bb7d7cd7d8352660ff9c Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Mon, 16 May 2016 20:09:33 +0300 Subject: gpu: nvgpu: gv11b: add PRAMIN support for mem accessors JIRA DNVGPU-23 Change-Id: I47c8d89e65b9bdb30b1399728d51bba77c3929ae Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1148389 Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h | 24 ++++++++++++++ drivers/gpu/nvgpu/gv11b/hw_pram_gv11b.h | 57 +++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/hw_pram_gv11b.h diff --git a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h index cb5d2dc0..b6efacf3 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h @@ -50,6 +50,30 @@ #ifndef _hw_bus_gv11b_h_ #define _hw_bus_gv11b_h_ +static inline u32 bus_bar0_window_r(void) +{ + return 0x00001700; +} +static inline u32 bus_bar0_window_base_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 bus_bar0_window_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) +{ + return 0x2000000; +} +static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) +{ + return 0x3000000; +} +static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) +{ + return 0x00000010; +} static inline u32 bus_bar1_block_r(void) { return 0x00001704; diff --git a/drivers/gpu/nvgpu/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pram_gv11b.h new file mode 100644 index 00000000..da2d4d2e --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_pram_gv11b.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pram_gv11b_h_ +#define _hw_pram_gv11b_h_ + +static inline u32 pram_data032_r(u32 i) +{ + return 0x00700000 + i*4; +} +#endif -- cgit v1.2.2 From eafba025b279fed658d03fd35b3877ef02797796 Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Mon, 9 May 2016 11:48:26 +0530 Subject: gpu: nvgpu: gv11b: change kernel path All kernel versions are getting moved inside $TOP/kernel folder. Changing kernel paths accordingly. Bug 200190733 Change-Id: I7dc6d1768151977fc60bacae34c2f8d839216351 Signed-off-by: Pritesh Raithatha Reviewed-on: http://git-master/r/1143388 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 9ff7b81e..4761ba6e 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -1,4 +1,4 @@ -nvgpu-t19x := ../../../../kernel-nvgpu-t19x/drivers/gpu/nvgpu +nvgpu-t19x := ../../../../nvgpu-t19x/drivers/gpu/nvgpu nvgpu-y += \ $(nvgpu-t19x)/gv11b/gv11b.o \ -- cgit v1.2.2 From 5d2a592383dcfef536b6d6169992f85c9d8bdaab Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Mon, 9 May 2016 11:48:26 +0530 Subject: gpu: nvgpu: gv11b: change kernel path All kernel versions are getting moved inside $TOP/kernel folder. Changing kernel paths accordingly. Bug 200190733 Change-Id: I7dc6d1768151977fc60bacae34c2f8d839216351 Signed-off-by: Pritesh Raithatha Reviewed-on: http://git-master/r/1145562 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani GVS: Gerrit_Virtual_Submit Reviewed-by: Varun Colbert Tested-by: Varun Colbert --- drivers/gpu/nvgpu/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 9ff7b81e..4761ba6e 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -1,4 +1,4 @@ -nvgpu-t19x := ../../../../kernel-nvgpu-t19x/drivers/gpu/nvgpu +nvgpu-t19x := ../../../../nvgpu-t19x/drivers/gpu/nvgpu nvgpu-y += \ $(nvgpu-t19x)/gv11b/gv11b.o \ -- cgit v1.2.2 From e7ee9c4b635b0f15e29a082adb2f7793bba59738 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Mon, 23 May 2016 12:48:15 +0530 Subject: gpu: nvgpu: Add device_info_data support Added device_info_data H/W register in Volta GPU hw_top_gv11b.h header. JIRA DNVGPU-26 Change-Id: I954a02df86ac7514c50ff72e71ea9b53e60c3354 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1151618 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h | 40 ++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h index ef81ce9d..65ffebb0 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h @@ -158,4 +158,44 @@ static inline u32 top_device_info_entry_enum_v(void) { return 0x00000002; } +static inline u32 top_device_info_entry_engine_type_v(void) +{ + return 0x00000002; +} +static inline u32 top_device_info_entry_data_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_data_type_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 top_device_info_data_type_enum2_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_data_inst_id_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_data_pri_base_v(u32 r) +{ + return (r >> 12) & 0xfff; +} +static inline u32 top_device_info_data_pri_base_align_v(void) +{ + return 0x0000000c; +} +static inline u32 top_device_info_data_fault_id_enum_v(u32 r) +{ + return (r >> 3) & 0x1f; +} +static inline u32 top_device_info_data_fault_id_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_data_fault_id_valid_v(void) +{ + return 0x00000001; +} #endif -- cgit v1.2.2 From 4dd4587f1734f06d1bc2173a282fcd7a10613d58 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 1 Jun 2016 08:47:30 -0700 Subject: gpu: t19x: config: Add t19x config file Add t19x config file to enable config for TEGRA_T19x_GPU. Bug 1757988 Change-Id: I0d1afd3f9a1d8f3b08963a07090583a2bb46dd69 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1157320 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 drivers/gpu/nvgpu/Kconfig diff --git a/drivers/gpu/nvgpu/Kconfig b/drivers/gpu/nvgpu/Kconfig new file mode 100644 index 00000000..6440472e --- /dev/null +++ b/drivers/gpu/nvgpu/Kconfig @@ -0,0 +1,6 @@ +config TEGRA_19x_GPU + bool "Tegra 19x family GPU" + depends on ARCH_TEGRA_19x_SOC + default y + help + Support for NVIDIA Tegra 19x family of GPU -- cgit v1.2.2 From 822b0dc53823e9c5bc3cbcdc78a62cc2c7f0647c Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Wed, 25 May 2016 13:24:37 +0300 Subject: gpu: nvgpu: fix patch write error check in update_ctxsw_preemption_mode Don't attempt to access memory if the patch context can't be mapped, but print an error message instead. Change-Id: I2d0ec22378ace0ef826f5a84a9ce4d35466f7832 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1157281 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index cb9c1902..ad8e4eff 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -998,6 +998,11 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8); err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); + if (err) { + gk20a_err(dev_from_gk20a(g), + "can't map patch context"); + goto out; + } addr = (u64_lo32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) >> gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) | @@ -1049,6 +1054,7 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, gr_gk20a_ctx_patch_write_end(g, ch_ctx); } +out: gk20a_dbg_fn("done"); } -- cgit v1.2.2 From 6f24a7666045b25072282d4c29ff190b7af33e59 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Thu, 2 Jun 2016 09:44:13 +0530 Subject: gpu: nvgpu: Add multiple engine and runlist support This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Volta GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ief3b586ff3d9f492f0277243b2a94952bab48786 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1156023 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 2 +- drivers/gpu/nvgpu/gv11b/ce2_gv11b.c | 28 ------------ drivers/gpu/nvgpu/gv11b/ce2_gv11b.h | 27 ------------ drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 27 ++++++++++++ drivers/gpu/nvgpu/gv11b/ce_gv11b.h | 26 +++++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 5 ++- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 +- drivers/gpu/nvgpu/gv11b/hw_ce2_gv11b.h | 81 ---------------------------------- drivers/gpu/nvgpu/gv11b/hw_ce_gv11b.h | 81 ++++++++++++++++++++++++++++++++++ 9 files changed, 141 insertions(+), 140 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gv11b/ce2_gv11b.c delete mode 100644 drivers/gpu/nvgpu/gv11b/ce2_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/ce_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/ce_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_ce2_gv11b.h create mode 100644 drivers/gpu/nvgpu/gv11b/hw_ce_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 4761ba6e..4ea56d8e 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -10,7 +10,7 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/fb_gv11b.o \ $(nvgpu-t19x)/gv11b/fifo_gv11b.o \ $(nvgpu-t19x)/gv11b/mm_gv11b.o \ - $(nvgpu-t19x)/gv11b/ce2_gv11b.o \ + $(nvgpu-t19x)/gv11b/ce_gv11b.o \ $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \ $(nvgpu-t19x)/gv11b/pmu_gv11b.o \ $(nvgpu-t19x)/gv11b/therm_gv11b.o diff --git a/drivers/gpu/nvgpu/gv11b/ce2_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce2_gv11b.c deleted file mode 100644 index d4ba4003..00000000 --- a/drivers/gpu/nvgpu/gv11b/ce2_gv11b.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * GV11B Graphics Copy Engine (gr host) - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ -#include "hw_ce2_gv11b.h" -#include "gp10b/ce2_gp10b.h" -#include "ce2_gv11b.h" - -void gv11b_init_ce2(struct gpu_ops *gops) -{ - gp10b_init_ce2(gops); -} diff --git a/drivers/gpu/nvgpu/gv11b/ce2_gv11b.h b/drivers/gpu/nvgpu/gv11b/ce2_gv11b.h deleted file mode 100644 index a7b2f99a..00000000 --- a/drivers/gpu/nvgpu/gv11b/ce2_gv11b.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * - * GV11B graphics copy engine - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - */ -#ifndef __CE2_GV11B_H__ -#define __CE2_GV11B_H__ - -struct gpu_ops; - -void gv11b_init_ce2(struct gpu_ops *gops); - -#endif /*__CE2_GV11B_H__*/ diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c new file mode 100644 index 00000000..961054e0 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -0,0 +1,27 @@ +/* + * Volta GPU series Copy Engine. + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. + */ + +#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ +#include "hw_ce_gv11b.h" +#include "gp10b/ce_gp10b.h" +#include "ce_gv11b.h" + +void gv11b_init_ce(struct gpu_ops *gops) +{ + gp10b_init_ce(gops); +} diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h new file mode 100644 index 00000000..27dffa5d --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h @@ -0,0 +1,26 @@ +/* + * + * Volta GPU series copy engine + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. + */ +#ifndef __CE_GV11B_H__ +#define __CE_GV11B_H__ + +struct gpu_ops; + +void gv11b_init_ce(struct gpu_ops *gops); + +#endif /*__CE2_GV11B_H__*/ diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index ad8e4eff..a4301fa9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1062,6 +1062,9 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, struct gk20a_debug_output *o) { struct gr_gk20a *gr = &g->gr; + u32 gr_engine_id; + + gr_engine_id = gk20a_fifo_get_gr_engine_id(g); gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n", gk20a_readl(g, gr_status_r())); @@ -1082,7 +1085,7 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR : 0x%x\n", gk20a_readl(g, gr_fecs_intr_r())); gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n", - gk20a_readl(g, fifo_engine_status_r(ENGINE_GR_GK20A))); + gk20a_readl(g, fifo_engine_status_r(gr_engine_id))); gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n", gk20a_readl(g, gr_activity_0_r())); gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n", diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e340c97e..876b5748 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -26,7 +26,7 @@ #include "gv11b/ltc_gv11b.h" #include "gv11b/fecs_trace_gv11b.h" #include "gv11b/gv11b.h" -#include "gv11b/ce2_gv11b.h" +#include "gv11b/ce_gv11b.h" #include "gv11b/gr_ctx_gv11b.h" #include "gv11b/mm_gv11b.h" #include "gv11b/pmu_gv11b.h" @@ -47,7 +47,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_ltc(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); - gv11b_init_ce2(gops); + gv11b_init_ce(gops); gv11b_init_mm(gops); gv11b_init_gr_ctx(gops); gv11b_init_pmu_ops(gops); diff --git a/drivers/gpu/nvgpu/gv11b/hw_ce2_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ce2_gv11b.h deleted file mode 100644 index e58bf271..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_ce2_gv11b.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce2_gv11b_h_ -#define _hw_ce2_gv11b_h_ - -static inline u32 ce2_intr_status_r(u32 i) -{ - return 0x00104410 + i*128; -} -static inline u32 ce2_intr_status_blockpipe_pending_f(void) -{ - return 0x1; -} -static inline u32 ce2_intr_status_blockpipe_reset_f(void) -{ - return 0x1; -} -static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2; -} -static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2; -} -static inline u32 ce2_intr_status_launcherr_pending_f(void) -{ - return 0x4; -} -static inline u32 ce2_intr_status_launcherr_reset_f(void) -{ - return 0x4; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ce_gv11b.h new file mode 100644 index 00000000..9f279207 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_ce_gv11b.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce_gv11b_h_ +#define _hw_ce_gv11b_h_ + +static inline u32 ce_intr_status_r(u32 i) +{ + return 0x00104410 + i*128; +} +static inline u32 ce_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +#endif -- cgit v1.2.2 From 973c2811ca584270da659fb01fa1facb5dd527fa Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Thu, 9 Jun 2016 18:55:12 +0530 Subject: gpu: nvgpu: Remove hard coded runlist_id mapping From this patch onwards, runlist_id is a member of struct channel_gk20a. So removed hard coded runlist_id mapping logic. JIRA DNVGPU-25 Change-Id: Ia02feffdc057b0dceab9721423feeed1cc7a1c12 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1161779 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index a4301fa9..59d5569c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1401,7 +1401,7 @@ static int gr_gv11b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a return ret; } - ret = g->ops.fifo.update_runlist(g, 0, ~0, true, false); + ret = g->ops.fifo.update_runlist(g, fault_ch->runlist_id, ~0, true, false); if (ret) { gk20a_err(dev_from_gk20a(g), "CILP: failed to restart runlist 0!"); -- cgit v1.2.2 From 4e476b2f9a4d877f105139b14bcc3f682a97df45 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Fri, 17 Jun 2016 16:33:28 +0530 Subject: gpu: nvgpu: update gr_gv11b_get_netlist_name method update gr_gv11b_get_netlist_name method as per ops get_netlist_name declaration Change-Id: Ide79d999564f489a80cff748ff61e42aabd5662a Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1166905 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c index 3fb0fa23..032e0c3e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c @@ -21,7 +21,7 @@ #include "gk20a/gk20a.h" #include "gr_ctx_gv11b.h" -static int gr_gv11b_get_netlist_name(int index, char *name) +static int gr_gv11b_get_netlist_name(struct gk20a *g, int index, char *name) { switch (index) { #ifdef GV11B_NETLIST_IMAGE_FW_NAME -- cgit v1.2.2 From ca9cb9715407d5e86228cf1b26e83b8dd6115385 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Fri, 17 Jun 2016 15:45:47 +0300 Subject: gpu: nvgpu: gv11x: support in-kernel vidmem mappings Propagate the buffer aperture flag in gk20a_locked_gmmu_map up so that buffers represented as a mem_desc and present in vidmem can be mapped to gpu. JIRA DNVGPU-18 JIRA DNVGPU-76 Change-Id: I67d476b2c1b84218217ef203e429fb5e8a33adc7 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1169297 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 59d5569c..a23c5e8c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -779,7 +779,8 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, size, NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none, - false); + false, + mem->aperture); if (!mem->gpu_va) { err = -ENOMEM; -- cgit v1.2.2 From f4035d17a39ac356f3cbf8aecc2ba4c679dd6fb3 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 5 Jul 2016 13:55:46 -0700 Subject: gpu: nvgpu: gv11b: update code to HW CL 36758735 Update headers and corresponding code to work with HW CL # 36758735 Bug 1735760 Change-Id: Ie26bfaa6377ab797c5ad978e4796a55334761b5d Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1175882 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 43 +- drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h | 76 ++- drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h | 4 +- drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h | 164 ------ drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | 8 + drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 20 +- drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h | 2 +- drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 42 +- drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 802 +++++++++++++++++++++----- drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h | 28 + drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h | 4 - drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 74 ++- drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h | 16 +- drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | 24 +- drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h | 4 + drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 42 +- drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h | 124 ++++ drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h | 36 +- 18 files changed, 1097 insertions(+), 416 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index a23c5e8c..c5d2aa56 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -911,17 +911,6 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, ctxsw_prog_main_image_magic_value_o()), ctxsw_prog_main_image_magic_value_v_value_v()); - gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n", - gk20a_mem_rd(g, mem, - ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o())); - - gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n", - gk20a_mem_rd(g, mem, - ctxsw_prog_main_image_context_timestamp_buffer_ptr_o())); - - gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n", - gk20a_mem_rd(g, mem, - ctxsw_prog_main_image_context_timestamp_buffer_control_o())); gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", gk20a_mem_rd(g, mem, @@ -1144,8 +1133,8 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n", gk20a_readl(g, gr_cwd_fs_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n", - gk20a_readl(g, gr_fe_tpc_fs_r(0))); - gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID(0): 0x%x\n", + gk20a_readl(g, gr_fe_tpc_fs_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n", gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0))); gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n", gk20a_readl(g, gr_cwd_sm_id_r(0))); @@ -1552,16 +1541,16 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, gpc, tpc, global_esr); if (cilp_enabled && sm_debugger_attached) { - if (global_esr & gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f()) - gk20a_writel(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset, - gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f()); + if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) + gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, + gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()); - if (global_esr & gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f()) - gk20a_writel(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset, - gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f()); + if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()) + gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, + gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()); - global_mask = gr_gpcs_tpcs_sm1_hww_global_esr_multiple_warp_errors_pending_f() | - gr_gpcs_tpcs_sm1_hww_global_esr_bpt_pause_pending_f(); + global_mask = gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() | + gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(); if (warp_esr != 0 || (global_esr & global_mask) != 0) { *ignore_debugger = true; @@ -1585,7 +1574,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, } /* reset the HWW errors after locking down */ - global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset); + global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: HWWs cleared for gpc %d tpc %d\n", @@ -1598,7 +1587,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, return ret; } - dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm1_dbgr_control0_r() + offset); + dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", @@ -1606,7 +1595,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, dbgr_control0 = set_field(dbgr_control0, gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(), gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f()); - gk20a_writel(g, gr_gpc0_tpc0_sm1_dbgr_control0_r() + offset, dbgr_control0); + gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); } gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, @@ -1720,10 +1709,10 @@ clean_up: static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) { - if (!(hww_warp_esr & gr_gpc0_tpc0_sm1_hww_warp_esr_addr_valid_m())) + if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) hww_warp_esr = set_field(hww_warp_esr, - gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_m(), - gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_none_f()); + gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), + gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f()); return hww_warp_esr; } diff --git a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h index b6efacf3..c06a106a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h @@ -50,30 +50,6 @@ #ifndef _hw_bus_gv11b_h_ #define _hw_bus_gv11b_h_ -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010; -} static inline u32 bus_bar1_block_r(void) { return 0x00001704; @@ -130,6 +106,58 @@ static inline u32 bus_bar2_block_ptr_shift_v(void) { return 0x0000000c; } +static inline u32 bus_bind_status_r(void) +{ + return 0x00001710; +} +static inline u32 bus_bind_status_bar1_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 bus_bind_status_bar1_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_outstanding_true_f(void) +{ + return 0x2; +} +static inline u32 bus_bind_status_bar2_pending_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 bus_bind_status_bar2_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_pending_busy_f(void) +{ + return 0x4; +} +static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 bus_bind_status_bar2_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_outstanding_true_f(void) +{ + return 0x8; +} static inline u32 bus_intr_0_r(void) { return 0x00001100; diff --git a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h index 04055b8c..ed1e657c 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h @@ -56,7 +56,7 @@ static inline u32 ccsr_channel_inst_r(u32 i) } static inline u32 ccsr_channel_inst__size_1_v(void) { - return 0x00001000; + return 0x00000200; } static inline u32 ccsr_channel_inst_ptr_f(u32 v) { @@ -88,7 +88,7 @@ static inline u32 ccsr_channel_r(u32 i) } static inline u32 ccsr_channel__size_1_v(void) { - return 0x00001000; + return 0x00000200; } static inline u32 ccsr_channel_enable_v(u32 r) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h index 5c60c30c..57a6b28d 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h @@ -290,168 +290,4 @@ static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_ { return 0x2; } -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) -{ - return 0x000000ac; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) -{ - return 0x000000b0; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) -{ - return 0x1ffff << 0; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) -{ - return 0x000000b4; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) -{ - return 0x00000080; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) -{ - return 0x00000020; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) -{ - return 0x00000000; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) -{ - return 0x00000000; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) -{ - return 0x00000004; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) -{ - return 0x600dbeef; -} -static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) -{ - return 0x00000008; -} -static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) -{ - return 0x0000000c; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) -{ - return 0x00000018; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) -{ - return 0x0000001c; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) -{ - return (r >> 0) & 0xffffff; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) -{ - return 0xff << 24; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) -{ - return (r >> 24) & 0xff; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) -{ - return 0x00000001; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) -{ - return 0x1000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) -{ - return 0x00000002; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) -{ - return 0x2000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) -{ - return 0x0000000a; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) -{ - return 0xa000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) -{ - return 0x0000000b; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) -{ - return 0xb000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) -{ - return 0x0000000c; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) -{ - return 0xc000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) -{ - return 0x0000000d; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) -{ - return 0xd000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) -{ - return 0x00000003; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) -{ - return 0x3000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) -{ - return 0x00000004; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) -{ - return 0x4000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) -{ - return 0x00000005; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) -{ - return 0x5000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) -{ - return 0x000000ff; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) -{ - return 0xff000000; -} #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h index 0a5622b4..900054aa 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h @@ -182,6 +182,10 @@ static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) { return 0x20; } +static inline u32 fb_mmu_invalidate_replay_cancel_f(void) +{ + return 0x20; +} static inline u32 fb_mmu_invalidate_sys_membar_s(void) { return 1; @@ -470,4 +474,8 @@ static inline u32 fb_mmu_vpr_info_fetch_true_v(void) { return 0x00000001; } +static inline u32 fb_niso_flush_sysmem_addr_r(void) +{ + return 0x00100c10; +} #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index 55960a4d..9c0f2483 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h @@ -104,7 +104,7 @@ static inline u32 fifo_eng_runlist_base_r(u32 i) } static inline u32 fifo_eng_runlist_base__size_1_v(void) { - return 0x0000000d; + return 0x00000001; } static inline u32 fifo_eng_runlist_r(u32 i) { @@ -112,7 +112,7 @@ static inline u32 fifo_eng_runlist_r(u32 i) } static inline u32 fifo_eng_runlist__size_1_v(void) { - return 0x0000000d; + return 0x00000001; } static inline u32 fifo_eng_runlist_length_f(u32 v) { @@ -268,7 +268,7 @@ static inline u32 fifo_intr_mmu_fault_id_r(void) } static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) { - return 0x00000040; + return 0x00000000; } static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) { @@ -332,7 +332,7 @@ static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) } static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) { - return 0x0000000e; + return 0x00000001; } static inline u32 fifo_intr_runlist_r(void) { @@ -412,7 +412,7 @@ static inline u32 fifo_engine_status_r(u32 i) } static inline u32 fifo_engine_status__size_1_v(void) { - return 0x0000000f; + return 0x00000002; } static inline u32 fifo_engine_status_id_v(u32 r) { @@ -500,7 +500,7 @@ static inline u32 fifo_pbdma_status_r(u32 i) } static inline u32 fifo_pbdma_status__size_1_v(void) { - return 0x0000000e; + return 0x00000001; } static inline u32 fifo_pbdma_status_id_v(u32 r) { @@ -600,11 +600,11 @@ static inline u32 fifo_replay_fault_buffer_size_r(void) } static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) { - return (v & 0x3fff) << 0; + return (v & 0x1ff) << 0; } static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) { - return 0x00002000; + return 0x000000c0; } static inline u32 fifo_replay_fault_buffer_get_r(void) { @@ -612,7 +612,7 @@ static inline u32 fifo_replay_fault_buffer_get_r(void) } static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) { - return (v & 0x3fff) << 0; + return (v & 0x1ff) << 0; } static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) { @@ -624,7 +624,7 @@ static inline u32 fifo_replay_fault_buffer_put_r(void) } static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) { - return (v & 0x3fff) << 0; + return (v & 0x1ff) << 0; } static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h index 75617e6e..280a048a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h @@ -124,7 +124,7 @@ static inline u32 fuse_status_opt_fbp_r(void) } static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) { - return (r >> (0 + i*0)) & 0x1; + return (r >> (0 + i*1)) & 0x1; } static inline u32 fuse_opt_ecc_en_r(void) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h index d54957eb..955626a6 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h @@ -70,9 +70,17 @@ static inline u32 gmmu_new_pde_aperture_video_memory_f(void) { return 0x2; } +static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} static inline u32 gmmu_new_pde_address_sys_f(u32 v) { - return (v & 0xfffffff) << 8; + return (v & 0xffffff) << 8; } static inline u32 gmmu_new_pde_address_sys_w(void) { @@ -118,6 +126,14 @@ static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) { return 0x2; } +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) +{ + return 0x6; +} static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) { return (v & 0xfffffff) << 4; @@ -138,6 +154,14 @@ static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) { return 0x2; } +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) +{ + return 0x6; +} static inline u32 gmmu_new_dual_pde_vol_small_w(void) { return 2; @@ -164,7 +188,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) } static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xfffffff) << 8; + return (v & 0xffffff) << 8; } static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { @@ -212,7 +236,7 @@ static inline u32 gmmu_new_pte_privilege_false_f(void) } static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xfffffff) << 8; + return (v & 0xffffff) << 8; } static inline u32 gmmu_new_pte_address_sys_w(void) { @@ -238,6 +262,14 @@ static inline u32 gmmu_new_pte_aperture_video_memory_f(void) { return 0x0; } +static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} static inline u32 gmmu_new_pte_read_only_w(void) { return 0; @@ -1078,7 +1110,7 @@ static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) { return 0x000000de; } -static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) +static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void) { return 0x000000cc; } @@ -1142,7 +1174,7 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) { return 0x000000ec; } -static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void) +static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void) { return 0x000000cd; } diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index 39b7074f..a37ce6e7 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -372,11 +372,11 @@ static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) } static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) { - return 0x0050433c; + return 0x005046a4; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) { - return 0x00419b3c; + return 0x00419ea4; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) { @@ -468,7 +468,7 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { - return 0x00504358; + return 0x005046b8; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) { @@ -504,7 +504,7 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_ } static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) { - return 0x0050436c; + return 0x005044a0; } static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) { @@ -532,15 +532,15 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pe } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) { - return 0x0050435c; + return 0x005046bc; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) { - return 0x00504360; + return 0x005046c0; } static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) { - return 0x00504370; + return 0x005044a4; } static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) { @@ -696,7 +696,7 @@ static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) } static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) { - return 0x1800; + return 0x7fffffff; } static inline u32 gr_fe_object_table_r(u32 i) { @@ -706,9 +706,9 @@ static inline u32 gr_fe_object_table_nvclass_v(u32 r) { return (r >> 0) & 0xffff; } -static inline u32 gr_fe_tpc_fs_r(u32 i) +static inline u32 gr_fe_tpc_fs_r(void) { - return 0x0040a200 + i*4; + return 0x004041c4; } static inline u32 gr_pri_mme_shadow_raw_index_r(void) { @@ -1530,9 +1530,29 @@ static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) { return 0x00502420; } -static inline u32 gr_rstr2d_gpc_map_r(u32 i) +static inline u32 gr_rstr2d_gpc_map0_r(void) { - return 0x0040780c + i*4; + return 0x0040780c; +} +static inline u32 gr_rstr2d_gpc_map1_r(void) +{ + return 0x00407810; +} +static inline u32 gr_rstr2d_gpc_map2_r(void) +{ + return 0x00407814; +} +static inline u32 gr_rstr2d_gpc_map3_r(void) +{ + return 0x00407818; +} +static inline u32 gr_rstr2d_gpc_map4_r(void) +{ + return 0x0040781c; +} +static inline u32 gr_rstr2d_gpc_map5_r(void) +{ + return 0x00407820; } static inline u32 gr_rstr2d_map_table_cfg_r(void) { @@ -1636,7 +1656,7 @@ static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) } static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) { - return 0x00001d80; + return 0x000001c0; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) { @@ -1648,7 +1668,7 @@ static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) } static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) { - return 0x00001d80; + return 0x00000182; } static inline u32 gr_pd_dist_skip_table_r(u32 i) { @@ -2032,7 +2052,7 @@ static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) } static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) { - return 0x00000030; + return 0x00000018; } static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) { @@ -2146,10 +2166,22 @@ static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) { return 0x00405b60 + i*4; } +static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) +{ + return 4; +} static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) { return (v & 0xf) << 0; } +static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) +{ + return (v & 0xf) << 4; +} static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) { return (v & 0xf) << 8; @@ -2158,6 +2190,10 @@ static inline u32 gr_cwd_sm_id_r(u32 i) { return 0x00405ba0 + i*4; } +static inline u32 gr_cwd_sm_id__size_1_v(void) +{ + return 0x00000010; +} static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) { return (v & 0xff) << 0; @@ -2316,7 +2352,7 @@ static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) } static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) { - return 0x00504608; + return 0x00504698; } static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) { @@ -2328,7 +2364,7 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) } static inline u32 gr_gpc0_tpc0_sm_arch_r(void) { - return 0x00504330; + return 0x0050469c; } static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) { @@ -2368,11 +2404,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { - return 0x00000480; + return 0x00030000; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) { - return 0x00000d10; + return 0x00030a00; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { @@ -2416,11 +2452,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) { - return 0x00000480; + return 0x00030000; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) { - return 0x00419e00; + return 0x00419b00; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) { @@ -2428,7 +2464,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) { - return 0x00419e04; + return 0x00419b04; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) { @@ -2672,11 +2708,11 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) { - return 0x00000030; + return 0x00000018; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) { - return 0x30; + return 0x18; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) { @@ -2712,7 +2748,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) { - return 0x005001dc; + return 0x00500ee4; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) { @@ -2720,7 +2756,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) { - return 0x00000de0; + return 0x00000250; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) { @@ -2728,7 +2764,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) { - return 0x005001d8; + return 0x00500ee0; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) { @@ -2740,7 +2776,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) { - return 0x004181e4; + return 0x00418eec; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) { @@ -2834,33 +2870,173 @@ static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) { return 0x80000000; } -static inline u32 gr_crstr_gpc_map_r(u32 i) +static inline u32 gr_crstr_gpc_map0_r(void) { - return 0x00418b08 + i*4; + return 0x00418b08; } -static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) +static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x7) << 0; } -static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) +static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) { - return (v & 0x1f) << 5; + return (v & 0x7) << 5; } -static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) +static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) { - return (v & 0x1f) << 10; + return (v & 0x7) << 10; } -static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) +static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) { - return (v & 0x1f) << 15; + return (v & 0x7) << 15; } -static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) +static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) { - return (v & 0x1f) << 20; + return (v & 0x7) << 20; } -static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) +static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) { - return (v & 0x1f) << 25; + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_gpc_map1_r(void) +{ + return 0x00418b0c; +} +static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) +{ + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_gpc_map2_r(void) +{ + return 0x00418b10; +} +static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) +{ + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_gpc_map3_r(void) +{ + return 0x00418b14; +} +static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) +{ + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_gpc_map4_r(void) +{ + return 0x00418b18; +} +static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) +{ + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_gpc_map5_r(void) +{ + return 0x00418b1c; +} +static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) +{ + return (v & 0x7) << 25; } static inline u32 gr_crstr_map_table_cfg_r(void) { @@ -2874,39 +3050,159 @@ static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) { return (v & 0xff) << 8; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) +{ + return 0x00418980; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) +{ + return 0x00418984; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) +{ + return 0x00418988; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) { - return 0x00418980 + i*4; + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) +{ + return 3; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) +{ + return (v & 0x7) << 28; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) +{ + return 0x7 << 28; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) +{ + return (r >> 28) & 0x7; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) +{ + return 0x0041898c; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) { return (v & 0x7) << 0; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) { return (v & 0x7) << 4; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) { return (v & 0x7) << 8; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) { return (v & 0x7) << 12; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) { return (v & 0x7) << 16; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) { return (v & 0x7) << 20; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) { return (v & 0x7) << 24; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) { return (v & 0x7) << 28; } @@ -2990,87 +3286,135 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { return 0x10000000; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_r(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) { - return 0x00419fa8; + return 0x00419e44; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_stack_error_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) { return 0x2; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_api_stack_error_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) { return 0x4; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_pc_wrap_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) { return 0x10; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) { return 0x20; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_pc_overflow_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) { return 0x40; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) +{ + return 0x80; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) { return 0x100; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) { return 0x200; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) +{ + return 0x400; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) { return 0x800; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_oor_reg_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) +{ + return 0x1000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) { return 0x2000; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_oor_addr_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) { return 0x4000; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) { return 0x8000; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) { return 0x10000; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) +{ + return 0x20000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) { return 0x40000; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_mmu_fault_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) { return 0x800000; } -static inline u32 gr_gpcs_tpcs_sm1_hww_warp_esr_report_mask_stack_overflow_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) { return 0x400000; } -static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_r(void) +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) { - return 0x00419fac; + return 0x80000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) +{ + return 0x100000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) +{ + return 0x00419e4c; } -static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) +{ + return 0x1; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) { return 0x4; } -static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_bpt_int_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) { return 0x10; } -static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_bpt_pause_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void) +{ + return 0x20000000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) { return 0x20; } -static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_report_mask_single_step_complete_report_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) { return 0x40; } @@ -3138,118 +3482,190 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { return 0x00000001; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_r(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) { - return 0x00504784; + return 0x00504610; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_m(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) { return 0x1 << 0; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_v(u32 r) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) { return (r >> 0) & 0x1; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_on_v(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) { return 0x00000001; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_debugger_mode_off_v(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) { return 0x00000000; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_stop_trigger_enable_f(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_stop_trigger_disable_f(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) { return 0x0; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_single_step_mode_enable_f(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) { return 0x8; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_single_step_mode_disable_f(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) { return 0x0; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_control0_run_trigger_task_f(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; } -static inline u32 gr_gpc0_tpc0_sm1_warp_valid_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) { - return 0x00504788; + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) +{ + return 0x00504614; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) { - return 0x00504790; + return 0x00504624; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_bpt_trap_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) { - return 0x00504798; + return 0x00504634; } -static inline u32 gr_gpcs_tpcs_sm1_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) { - return 0x00419f90; + return 0x00419e24; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_r(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) { - return 0x00504780; + return 0x0050460c; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_sm_in_trap_mode_v(u32 r) +static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) { return (r >> 0) & 0x1; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_locked_down_v(u32 r) +static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) { return (r >> 4) & 0x1; } -static inline u32 gr_gpc0_tpc0_sm1_dbgr_status0_locked_down_true_v(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) { return 0x00000001; } -static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_r(void) +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) { - return 0x00419fb4; + return 0x00419e50; } -static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_bpt_int_pending_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) { return 0x10; } -static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_bpt_pause_pending_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) { return 0x20; } -static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_single_step_complete_pending_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) { return 0x40; } -static inline u32 gr_gpcs_tpcs_sm1_hww_global_esr_multiple_warp_errors_pending_f(void) +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) { return 0x4; } -static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_r(void) +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) { - return 0x005047b4; + return 0x00504650; } -static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f(void) +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) { return 0x10; } -static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_bpt_pause_pending_f(void) +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void) +{ + return 0x20000000; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) { return 0x20; } -static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f(void) +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) { return 0x40; } -static inline u32 gr_gpc0_tpc0_sm1_hww_global_esr_multiple_warp_errors_pending_f(void) +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) { return 0x4; } +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) +{ + return 0x8; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) +{ + return 0x80000000; +} static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) { return 0x00504224; @@ -3266,45 +3682,45 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) { return 0x100; } -static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_r(void) +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) { - return 0x005047b0; + return 0x00504648; } -static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_v(u32 r) +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) { return (r >> 0) & 0xffff; } -static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_none_v(void) +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) { return 0x00000000; } -static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_error_none_f(void) +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) { return 0x0; } -static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_valid_m(void) +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void) { return 0x1 << 24; } -static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_m(void) +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void) { return 0x7 << 25; } -static inline u32 gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_none_f(void) +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void) { return 0x0; } static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) { - return 0x005047b8; + return 0x00504654; } static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) { - return 0x005043a0; + return 0x00504770; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) { - return 0x00419ba0; + return 0x00419f70; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) { @@ -3316,11 +3732,11 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) } static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) { - return 0x005043b0; + return 0x0050477c; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) { - return 0x00419bb0; + return 0x00419f7c; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) { @@ -3338,9 +3754,29 @@ static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) { return 0x4; } -static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) +static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) +{ + return 0x0041bf00; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) +{ + return 0x0041bf04; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) +{ + return 0x0041bf08; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) +{ + return 0x0041bf0c; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) +{ + return 0x0041bf10; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) { - return 0x0041bf00 + i*4; + return 0x0041bf14; } static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) { @@ -3362,6 +3798,10 @@ static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) { return (v & 0x7) << 21; } +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) +{ + return (v & 0x1f) << 24; +} static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) { return 0x0041bfd4; @@ -3370,6 +3810,34 @@ static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) { return (v & 0xffffff) << 0; } +static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) +{ + return 0x0041bfe4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) +{ + return (v & 0x1f) << 5; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) +{ + return (v & 0x1f) << 10; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) +{ + return (v & 0x1f) << 20; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) +{ + return (v & 0x1f) << 25; +} static inline u32 gr_bes_zrop_settings_r(void) { return 0x00408850; @@ -3416,75 +3884,107 @@ static inline u32 gr_zcull_subregion_qty_v(void) } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) { - return 0x00504308; + return 0x00504604; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) { - return 0x0050430c; + return 0x00504608; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) { - return 0x00504318; + return 0x0050465c; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) { - return 0x00504320; + return 0x00504660; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) { - return 0x00504324; + return 0x00504664; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) { - return 0x00504328; + return 0x00504668; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) { - return 0x0050432c; + return 0x0050466c; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) { - return 0x0050431c; + return 0x00504658; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) { - return 0x00504378; + return 0x00504730; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) { - return 0x0050437c; + return 0x00504734; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) { - return 0x00504380; + return 0x00504738; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) { - return 0x00504384; + return 0x0050473c; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) { - return 0x00504388; + return 0x00504740; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) { - return 0x0050438c; + return 0x00504744; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) { - return 0x00504390; + return 0x00504748; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) { - return 0x00504394; + return 0x0050474c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) +{ + return 0x00504678; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) +{ + return 0x00504694; } -static inline u32 gr_pri_gpc0_tpc0_sm1_dsm_perf_counter_status_s1_r(void) +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) { - return 0x005047c4; + return 0x005046f0; } -static inline u32 gr_pri_gpc0_tpc0_sm1_dsm_perf_counter_status1_r(void) +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) { - return 0x005047d0; + return 0x00504700; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) +{ + return 0x005046f4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) +{ + return 0x00504704; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) +{ + return 0x005046f8; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) +{ + return 0x00504708; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) +{ + return 0x005046fc; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) +{ + return 0x0050470c; } static inline u32 gr_fe_pwr_mode_r(void) { @@ -3584,7 +4084,7 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) } static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) { - return 0x00419f84; + return 0x00419e10; } static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) { @@ -3648,7 +4148,7 @@ static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) } static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) { - return 0x00419bd8; + return 0x00419c84; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) { @@ -3664,7 +4164,7 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_ma } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) { - return 0x00419ba4; + return 0x00419f78; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) { @@ -3680,10 +4180,10 @@ static inline u32 gr_gpcs_tc_debug0_r(void) } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0xff) << 0; } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { - return 0x1ff << 0; + return 0xff << 0; } #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h index 02db6af6..2dbd759f 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h @@ -50,6 +50,26 @@ #ifndef _hw_ltc_gv11b_h_ #define _hw_ltc_gv11b_h_ +static inline u32 ltc_pltcg_base_v(void) +{ + return 0x00140000; +} +static inline u32 ltc_pltcg_extent_v(void) +{ + return 0x0017ffff; +} +static inline u32 ltc_ltc0_ltss_v(void) +{ + return 0x00140200; +} +static inline u32 ltc_ltc0_lts0_v(void) +{ + return 0x00140400; +} +static inline u32 ltc_ltcs_ltss_v(void) +{ + return 0x0017e200; +} static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) { return 0x0014046c; @@ -550,4 +570,12 @@ static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) { return (r >> 16) & 0x1f; } +static inline u32 ltc_ltca_g_axi_pctrl_r(void) +{ + return 0x00160000; +} +static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v) +{ + return (v & 0xff) << 2; +} #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h index 98bec43a..7fe4d158 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h @@ -78,10 +78,6 @@ static inline u32 mc_intr_pfifo_pending_f(void) { return 0x100; } -static inline u32 mc_intr_hub_pending_f(void) -{ - return 0x200; -} static inline u32 mc_intr_pgraph_pending_f(void) { return 0x1000; diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h index 3863c6d6..b3aaa7e6 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h @@ -72,7 +72,7 @@ static inline u32 pbdma_gp_base_r(u32 i) } static inline u32 pbdma_gp_base__size_1_v(void) { - return 0x0000000e; + return 0x00000001; } static inline u32 pbdma_gp_base_offset_f(u32 v) { @@ -334,6 +334,38 @@ static inline u32 pbdma_userd_addr_f(u32 v) { return (v & 0x7fffff) << 9; } +static inline u32 pbdma_config_r(u32 i) +{ + return 0x000400f4 + i*8192; +} +static inline u32 pbdma_config_l2_evict_first_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_l2_evict_normal_f(void) +{ + return 0x1; +} +static inline u32 pbdma_config_l2_evict_last_f(void) +{ + return 0x2; +} +static inline u32 pbdma_config_ce_split_enable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_ce_split_disable_f(void) +{ + return 0x10; +} +static inline u32 pbdma_config_auth_level_non_privileged_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_auth_level_privileged_f(void) +{ + return 0x100; +} static inline u32 pbdma_userd_hi_r(u32 i) { return 0x0004000c + i*8192; @@ -478,6 +510,14 @@ static inline u32 pbdma_intr_0_signature_pending_f(void) { return 0x80000000; } +static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_intr_1_r(u32 i) +{ + return 0x00040148 + i*8192; +} static inline u32 pbdma_intr_en_0_r(u32 i) { return 0x0004010c + i*8192; @@ -526,6 +566,38 @@ static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) { return (v & 0x7fff) << 0; } +static inline u32 pbdma_syncpointa_r(u32 i) +{ + return 0x000400a4 + i*8192; +} +static inline u32 pbdma_syncpointa_payload_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pbdma_syncpointb_r(u32 i) +{ + return 0x000400a8 + i*8192; +} +static inline u32 pbdma_syncpointb_op_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pbdma_syncpointb_op_wait_v(void) +{ + return 0x00000000; +} +static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 pbdma_syncpointb_wait_switch_en_v(void) +{ + return 0x00000001; +} +static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) +{ + return (r >> 8) & 0xfff; +} static inline u32 pbdma_runlist_timeslice_r(u32 i) { return 0x000400f8 + i*8192; diff --git a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h index 836c014b..4d11fef4 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h @@ -52,7 +52,7 @@ static inline u32 perf_pmasys_control_r(void) { - return 0x0024a000; + return 0x001b4000; } static inline u32 perf_pmasys_control_membuf_status_v(u32 r) { @@ -84,7 +84,7 @@ static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) } static inline u32 perf_pmasys_mem_block_r(void) { - return 0x0024a070; + return 0x001b4070; } static inline u32 perf_pmasys_mem_block_base_f(u32 v) { @@ -148,7 +148,7 @@ static inline u32 perf_pmasys_mem_block_valid_false_f(void) } static inline u32 perf_pmasys_outbase_r(void) { - return 0x0024a074; + return 0x001b4074; } static inline u32 perf_pmasys_outbase_ptr_f(u32 v) { @@ -156,7 +156,7 @@ static inline u32 perf_pmasys_outbase_ptr_f(u32 v) } static inline u32 perf_pmasys_outbaseupper_r(void) { - return 0x0024a078; + return 0x001b4078; } static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) { @@ -164,7 +164,7 @@ static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) } static inline u32 perf_pmasys_outsize_r(void) { - return 0x0024a07c; + return 0x001b407c; } static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) { @@ -172,7 +172,7 @@ static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) } static inline u32 perf_pmasys_mem_bytes_r(void) { - return 0x0024a084; + return 0x001b4084; } static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) { @@ -180,7 +180,7 @@ static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) } static inline u32 perf_pmasys_mem_bump_r(void) { - return 0x0024a088; + return 0x001b4088; } static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) { @@ -188,7 +188,7 @@ static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) } static inline u32 perf_pmasys_enginestatus_r(void) { - return 0x0024a0a4; + return 0x001b40a4; } static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h index f107300e..e08c6854 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h @@ -70,6 +70,10 @@ static inline u32 proj_lts_stride_v(void) { return 0x00000200; } +static inline u32 proj_fbpa_stride_v(void) +{ + return 0x00004000; +} static inline u32 proj_ppc_in_gpc_base_v(void) { return 0x00003000; @@ -102,29 +106,37 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) { return 0x00001800; } +static inline u32 proj_host_num_engines_v(void) +{ + return 0x00000002; +} static inline u32 proj_host_num_pbdma_v(void) { - return 0x0000000e; + return 0x00000001; } static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) { - return 0x00000007; + return 0x00000002; } static inline u32 proj_scal_litter_num_fbps_v(void) { - return 0x00000008; + return 0x00000001; +} +static inline u32 proj_scal_litter_num_fbpas_v(void) +{ + return 0x00000001; } static inline u32 proj_scal_litter_num_gpcs_v(void) { - return 0x00000008; + return 0x00000001; } static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) { - return 0x00000003; + return 0x00000001; } static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) { - return 0x00000003; + return 0x00000002; } static inline u32 proj_scal_litter_num_zcull_banks_v(void) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h index bb8b5dea..27ea4246 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h @@ -542,6 +542,10 @@ static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) { return 0x20000000; } +static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) +{ + return 0x30000000; +} static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) { return (v & 0x1) << 30; diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index a19e5251..6ccbc266 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -148,7 +148,7 @@ static inline u32 ram_in_page_dir_base_lo_w(void) } static inline u32 ram_in_page_dir_base_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xff) << 0; } static inline u32 ram_in_page_dir_base_hi_w(void) { @@ -354,6 +354,14 @@ static inline u32 ram_fc_allowed_syncpoints_w(void) { return 58; } +static inline u32 ram_fc_syncpointa_w(void) +{ + return 41; +} +static inline u32 ram_fc_syncpointb_w(void) +{ + return 42; +} static inline u32 ram_fc_target_w(void) { return 43; @@ -436,7 +444,11 @@ static inline u32 ram_userd_gp_top_level_get_hi_w(void) } static inline u32 ram_rl_entry_size_v(void) { - return 0x00000010; + return 0x00000008; +} +static inline u32 ram_rl_entry_chid_f(u32 v) +{ + return (v & 0xfff) << 0; } static inline u32 ram_rl_entry_id_f(u32 v) { @@ -444,14 +456,34 @@ static inline u32 ram_rl_entry_id_f(u32 v) } static inline u32 ram_rl_entry_type_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1) << 13; +} +static inline u32 ram_rl_entry_type_chid_f(void) +{ + return 0x0; } static inline u32 ram_rl_entry_type_tsg_f(void) { - return 0x1; + return 0x2000; +} +static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) +{ + return (v & 0xf) << 14; +} +static inline u32 ram_rl_entry_timeslice_scale_3_f(void) +{ + return 0xc000; +} +static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) +{ + return (v & 0xff) << 18; +} +static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) +{ + return 0x2000000; } static inline u32 ram_rl_entry_tsg_length_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0x3f) << 26; } #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h index ee3dbc0e..2c464d2c 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h @@ -54,6 +54,114 @@ static inline u32 therm_use_a_r(void) { return 0x00020798; } +static inline u32 therm_use_a_ext_therm_0_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_use_a_ext_therm_1_enable_f(void) +{ + return 0x2; +} +static inline u32 therm_use_a_ext_therm_2_enable_f(void) +{ + return 0x4; +} +static inline u32 therm_evt_ext_therm_0_r(void) +{ + return 0x00020700; +} +static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_1_r(void) +{ + return 0x00020704; +} +static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_2_r(void) +{ + return 0x00020708; +} +static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) +{ + return 0x00000003; +} static inline u32 therm_weight_1_r(void) { return 0x00020024; @@ -106,6 +214,22 @@ static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) { return 0x4; } +static inline u32 therm_gate_ctrl_eng_pwr_m(void) +{ + return 0x3 << 4; +} +static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) +{ + return 0x10; +} +static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) +{ + return 0x00000002; +} +static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) +{ + return 0x20; +} static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) { return (v & 0x1f) << 8; diff --git a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h index 65ffebb0..cb65cad8 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h @@ -138,13 +138,37 @@ static inline u32 top_device_info_type_enum_graphics_f(void) { return 0x0; } -static inline u32 top_device_info_type_enum_copy0_v(void) +static inline u32 top_device_info_type_enum_copy2_v(void) { - return 0x00000001; + return 0x00000003; +} +static inline u32 top_device_info_type_enum_copy2_f(void) +{ + return 0xc; +} +static inline u32 top_device_info_type_enum_lce_v(void) +{ + return 0x00000013; +} +static inline u32 top_device_info_type_enum_lce_f(void) +{ + return 0x4c; +} +static inline u32 top_device_info_engine_v(u32 r) +{ + return (r >> 5) & 0x1; } -static inline u32 top_device_info_type_enum_copy0_f(void) +static inline u32 top_device_info_runlist_v(u32 r) { - return 0x4; + return (r >> 4) & 0x1; +} +static inline u32 top_device_info_intr_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 top_device_info_reset_v(u32 r) +{ + return (r >> 2) & 0x1; } static inline u32 top_device_info_entry_v(u32 r) { @@ -158,10 +182,6 @@ static inline u32 top_device_info_entry_enum_v(void) { return 0x00000002; } -static inline u32 top_device_info_entry_engine_type_v(void) -{ - return 0x00000002; -} static inline u32 top_device_info_entry_data_v(void) { return 0x00000001; -- cgit v1.2.2 From 27b8b2a633a3a85c6ada7310ac81cebe519b950d Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Thu, 7 Jul 2016 11:09:32 +0300 Subject: gpu: nvgpu: use vidmem by default in gmmu_alloc variants For devices that have vidmem available, use the vidmem allocator in gk20a_gmmu_alloc{,attr,_map,_map_attr}. For others, use sysmem. Because all of the buffers haven't been tested to work in vidmem yet, rename calls to gk20a_gmmu_alloc{,attr,_map,_map_attr} to have _sys at the end to declare explicitly that vidmem is used. Enabling vidmem for each now is a matter of removing "_sys" from the function call. Jira DNVGPU-18 Change-Id: Ieb13c21c774380ac0be9987e177b4adc0a647abb Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1176810 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index c5d2aa56..831b92f5 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -770,7 +770,7 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, gk20a_dbg_fn(""); - err = gk20a_gmmu_alloc_attr(vm->mm->g, 0, size, mem); + err = gk20a_gmmu_alloc_sys(vm->mm->g, size, mem); if (err) return err; -- cgit v1.2.2 From b551c5effb6bb47ee21c04d9a78b195c201e92bd Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 29 Jun 2016 16:16:31 +0530 Subject: gpu: nvgpu: Add control flag to allow kernel to create privileged CE channels Added control flag for nvgpu infra to allow kernel to create privileged CE channels for page migration and clearing support between sysmem and videmem. JIRA DNVGPU-53 Change-Id: I2d1faf034e194b7a850ac33aec4f6c315c7e552b Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1173093 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 37b49106..d9754a81 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -148,6 +148,8 @@ struct gk20a_platform t19x_gpu_tegra_platform = { .default_big_page_size = SZ_64K, + .has_ce = true, + .soc_name = "tegra19x", .vidmem_is_vidmem = true, -- cgit v1.2.2 From 4f9b90da4cf62c7aa9884fcbe7184e44571a8008 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 29 Jun 2016 14:09:33 -0700 Subject: gpu: nvgpu: gv11b: update NVGPU_COMPAT_TEGRA_GV11B Bug 1735760 Change-Id: I16acfe7f911fdfdd7c2a1715fecb22b9689a0796 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1173333 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Adeel Raza --- drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h index d376f3dd..63901445 100644 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h +++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h @@ -18,7 +18,7 @@ #define NVGPU_GPUID_GV11B \ GK20A_GPUID(NVGPU_GPU_ARCH_GV110, NVGPU_GPU_IMPL_GV11B) -#define NVGPU_COMPAT_TEGRA_GV11B "nvidia,g11b" +#define NVGPU_COMPAT_TEGRA_GV11B "nvidia,gv11b" #define NVGPU_COMPAT_GENERIC_GV11B "nvidia,generic-gv11b" #define TEGRA_19x_GPUID NVGPU_GPUID_GV11B -- cgit v1.2.2 From 32fe739f68e6307062a8a3f535be41208c97766d Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 7 Jul 2016 13:47:48 -0700 Subject: gpu: nvgpu: gv11b: updated hal and gpu_ops Added init_fb, init_fifo and get_litter_values. Also initialized read_ptimer Bug 1735760 Change-Id: Ia1665d60392e9cc58db4cc3f292597aeaea0c718 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1177174 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Adeel Raza --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 88 ++++++++++++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 876b5748..33b0d955 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -31,14 +31,96 @@ #include "gv11b/mm_gv11b.h" #include "gv11b/pmu_gv11b.h" #include "gv11b/therm_gv11b.h" +#include "gv11b/fb_gv11b.h" +#include "gv11b/fifo_gv11b.h" +#include "gv11b/hw_proj_gv11b.h" #include "gm20b/gr_gm20b.h" +static struct gpu_ops gv11b_ops; + +static int gv11b_get_litter_value(struct gk20a *g, + enum nvgpu_litter_value value) +{ + int ret = EINVAL; + switch (value) { + case GPU_LIT_NUM_GPCS: + ret = proj_scal_litter_num_gpcs_v(); + break; + case GPU_LIT_NUM_PES_PER_GPC: + ret = proj_scal_litter_num_pes_per_gpc_v(); + break; + case GPU_LIT_NUM_ZCULL_BANKS: + ret = proj_scal_litter_num_zcull_banks_v(); + break; + case GPU_LIT_NUM_TPC_PER_GPC: + ret = proj_scal_litter_num_tpc_per_gpc_v(); + break; + case GPU_LIT_NUM_FBPS: + ret = proj_scal_litter_num_fbps_v(); + break; + case GPU_LIT_GPC_BASE: + ret = proj_gpc_base_v(); + break; + case GPU_LIT_GPC_STRIDE: + ret = proj_gpc_stride_v(); + break; + case GPU_LIT_GPC_SHARED_BASE: + ret = proj_gpc_shared_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_BASE: + ret = proj_tpc_in_gpc_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_STRIDE: + ret = proj_tpc_in_gpc_stride_v(); + break; + case GPU_LIT_TPC_IN_GPC_SHARED_BASE: + ret = proj_tpc_in_gpc_shared_base_v(); + break; + case GPU_LIT_PPC_IN_GPC_STRIDE: + ret = proj_ppc_in_gpc_stride_v(); + break; + case GPU_LIT_ROP_BASE: + ret = proj_rop_base_v(); + break; + case GPU_LIT_ROP_STRIDE: + ret = proj_rop_stride_v(); + break; + case GPU_LIT_ROP_SHARED_BASE: + ret = proj_rop_shared_base_v(); + break; + case GPU_LIT_HOST_NUM_ENGINES: + ret = proj_host_num_engines_v(); + break; + case GPU_LIT_HOST_NUM_PBDMA: + ret = proj_host_num_pbdma_v(); + break; + case GPU_LIT_LTC_STRIDE: + ret = proj_ltc_stride_v(); + break; + case GPU_LIT_LTS_STRIDE: + ret = proj_lts_stride_v(); + break; + case GPU_LIT_NUM_FBPAS: + ret = proj_scal_litter_num_fbpas_v(); + break; + case GPU_LIT_FBPA_STRIDE: + ret = proj_fbpa_stride_v(); + break; + default: + break; + } + + return ret; +} + int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + *gops = gv11b_ops; + /* boot in non-secure modes for time beeing */ gops->privsecurity = 0; gops->securegpccs = 0; @@ -47,14 +129,18 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_ltc(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); + gv11b_init_fb(gops); + gv11b_init_fifo(gops); gv11b_init_ce(gops); gv11b_init_mm(gops); gv11b_init_gr_ctx(gops); gv11b_init_pmu_ops(gops); - gk20a_init_debug_ops(gops); + gk20a_init_debug_ops(gops); gv11b_init_therm_ops(gops); gops->name = "gv11b"; gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; + gops->get_litter_value = gv11b_get_litter_value; + gops->read_ptimer = gk20a_read_ptimer; c->twod_class = FERMI_TWOD_A; c->threed_class = VOLTA_A; -- cgit v1.2.2 From 7297e1401962af075b14db2fec2f95b6a80d97f6 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 1 Aug 2016 14:27:54 +0530 Subject: gpu: nvgpu: post bpt events after processing Receive hww_global_esr in gr_gv11b_handle_sm_exception() and pass it to gr_gk20a_handle_sm_exception() Bug 200209410 Change-Id: I57a701a1f1fa560367f78db212c06d4ce361c7f0 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1194987 GVS: Gerrit_Virtual_Submit Reviewed-by: Cory Perry Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 831b92f5..12b07d11 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -61,14 +61,15 @@ static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) } static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event, struct channel_gk20a *fault_ch) + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr) { int ret = 0; u32 offset = proj_gpc_stride_v() * gpc + proj_tpc_in_gpc_stride_v() * tpc; u32 lrf_ecc_status, shm_ecc_status; - gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch); + gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); /* Check for LRF ECC errors. */ lrf_ecc_status = gk20a_readl(g, -- cgit v1.2.2 From 2c6652f182d84dc7ec4218576b65ad582f05d4a6 Mon Sep 17 00:00:00 2001 From: Cory Perry Date: Thu, 28 Jul 2016 22:37:09 -0700 Subject: gpu: nvgpu: send only one event to the debugger Event notifications on TSGs should only be sent to the channel that caused the event to happen in the first place, not evey channel in the tsg. Any more and the debugger will not be able to tell what channel actually got the event. Worse yet, if all the channels in a tsg are bound to the same debug session (as is the case with cuda-gdb), then multiple nvgpu events for the same gpu event will be triggered, causing events to be buffered and the client to get out of sync. One gpu exception, one nvgpu event per tsg. Bug 1793988 Change-Id: Ifb33b65f09f67b0e323917c7e7ea016fc3676f18 Signed-off-by: Cory Perry Reviewed-on: http://git-master/r/1194207 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 12b07d11..9d0b4ade 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1680,21 +1680,14 @@ static int gr_gv11b_handle_fecs_error(struct gk20a *g, } if (gk20a_gr_sm_debugger_attached(g)) { + gk20a_dbg_gpu_post_events(ch); + if (gk20a_is_channel_marked_as_tsg(ch)) { struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; - struct channel_gk20a *__ch; - - mutex_lock(&tsg->ch_list_lock); - list_for_each_entry(__ch, &tsg->ch_list, ch_entry) { - gk20a_dbg_gpu_post_events(__ch); - } - mutex_unlock(&tsg->ch_list_lock); gk20a_tsg_event_id_post_event(tsg, NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); } else { - gk20a_dbg_gpu_post_events(ch); - gk20a_channel_event_id_post_event(ch, NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); } -- cgit v1.2.2 From 51b5ec852096c0eeb1eaca48ae132d7bf9ac7a9d Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 22 Aug 2016 13:20:05 -0700 Subject: gpu: nvgpu: gv11b: hw header update Updated hw headers to CL#37001916. Some of important changes include new door bell user mode mechanism and new runlist structure. Bug 1735765 Change-Id: Icf01156dd3e7d94466f553ffc53267e4043e1188 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1205888 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 63 ++- drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h | 24 + drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | 12 - drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 20 +- drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 12 +- drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 830 ++++++---------------------- drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h | 8 - drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 42 +- drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h | 16 +- drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | 12 +- drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h | 8 +- drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 128 ++++- drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h | 356 ------------ drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h | 2 +- drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h | 89 +++ 15 files changed, 465 insertions(+), 1157 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 9d0b4ade..088ec040 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -72,16 +72,16 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); /* Check for LRF ECC errors. */ - lrf_ecc_status = gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); - if ( (lrf_ecc_status & + lrf_ecc_status = gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); + if ((lrf_ecc_status & gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) || (lrf_ecc_status & gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) || (lrf_ecc_status & gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) || (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f()) ) { + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f())) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, "Single bit error detected in SM LRF!"); @@ -93,14 +93,14 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset, 0); } - if ( (lrf_ecc_status & + if ((lrf_ecc_status & gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) || (lrf_ecc_status & gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) || (lrf_ecc_status & gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) || (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f()) ) { + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f())) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, "Double bit error detected in SM LRF!"); @@ -109,14 +109,13 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, gk20a_readl(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset); gk20a_writel(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, - 0); + gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, 0); } gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, lrf_ecc_status); /* Check for SHM ECC errors. */ - shm_ecc_status = gk20a_readl(g, + shm_ecc_status = gk20a_readl(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset); if ((shm_ecc_status & gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) || @@ -125,7 +124,7 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, (shm_ecc_status & gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) || (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) { + gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f())) { u32 ecc_stats_reg_val; gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, @@ -144,10 +143,10 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, ecc_stats_reg_val); } - if ( (shm_ecc_status & + if ((shm_ecc_status & gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) || (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) { + gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f())) { u32 ecc_stats_reg_val; gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, @@ -1133,8 +1132,8 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, gk20a_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n", gk20a_readl(g, gr_cwd_fs_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n", - gk20a_readl(g, gr_fe_tpc_fs_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS(0): 0x%x\n", + gk20a_readl(g, gr_fe_tpc_fs_r(0))); gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n", gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0))); gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n", @@ -1184,7 +1183,7 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, static bool gr_activity_empty_or_preempted(u32 val) { - while(val) { + while (val) { u32 v = val & 7; if (v != gr_activity_4_gpc0_empty_v() && v != gr_activity_4_gpc0_preempted_v()) @@ -1542,16 +1541,16 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, gpc, tpc, global_esr); if (cilp_enabled && sm_debugger_attached) { - if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) - gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, - gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()); + if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()) + gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, + gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()); - if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()) - gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, - gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()); + if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f()) + gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, + gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f()); - global_mask = gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() | - gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(); + global_mask = gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f() | + gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(); if (warp_esr != 0 || (global_esr & global_mask) != 0) { *ignore_debugger = true; @@ -1575,7 +1574,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, } /* reset the HWW errors after locking down */ - global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); + global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: HWWs cleared for gpc %d tpc %d\n", @@ -1588,15 +1587,15 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, return ret; } - dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); - if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) { + dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); + if (dbgr_control0 & gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f()) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", gpc, tpc); dbgr_control0 = set_field(dbgr_control0, - gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(), - gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f()); - gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); + gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(), + gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f()); + gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset, dbgr_control0); } gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, @@ -1703,10 +1702,10 @@ clean_up: static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) { - if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) + if (!(hww_warp_esr & gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m())) hww_warp_esr = set_field(hww_warp_esr, - gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), - gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f()); + gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(), + gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f()); return hww_warp_esr; } diff --git a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h index c06a106a..66571ae7 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h @@ -50,6 +50,30 @@ #ifndef _hw_bus_gv11b_h_ #define _hw_bus_gv11b_h_ +static inline u32 bus_bar0_window_r(void) +{ + return 0x00001700; +} +static inline u32 bus_bar0_window_base_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 bus_bar0_window_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) +{ + return 0x2000000; +} +static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) +{ + return 0x3000000; +} +static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) +{ + return 0x00000010; +} static inline u32 bus_bar1_block_r(void) { return 0x00001704; diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h index 900054aa..9e4bab8b 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h @@ -174,18 +174,6 @@ static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) { return 0x10; } -static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void) -{ - return 0x18; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20; -} -static inline u32 fb_mmu_invalidate_replay_cancel_f(void) -{ - return 0x20; -} static inline u32 fb_mmu_invalidate_sys_membar_s(void) { return 1; diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index 9c0f2483..8af66362 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h @@ -104,7 +104,7 @@ static inline u32 fifo_eng_runlist_base_r(u32 i) } static inline u32 fifo_eng_runlist_base__size_1_v(void) { - return 0x00000001; + return 0x00000002; } static inline u32 fifo_eng_runlist_r(u32 i) { @@ -112,7 +112,7 @@ static inline u32 fifo_eng_runlist_r(u32 i) } static inline u32 fifo_eng_runlist__size_1_v(void) { - return 0x00000001; + return 0x00000002; } static inline u32 fifo_eng_runlist_length_f(u32 v) { @@ -268,7 +268,7 @@ static inline u32 fifo_intr_mmu_fault_id_r(void) } static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) { - return 0x00000000; + return 0x00000040; } static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) { @@ -332,7 +332,7 @@ static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) } static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) { - return 0x00000001; + return 0x00000003; } static inline u32 fifo_intr_runlist_r(void) { @@ -412,7 +412,7 @@ static inline u32 fifo_engine_status_r(u32 i) } static inline u32 fifo_engine_status__size_1_v(void) { - return 0x00000002; + return 0x00000004; } static inline u32 fifo_engine_status_id_v(u32 r) { @@ -500,7 +500,7 @@ static inline u32 fifo_pbdma_status_r(u32 i) } static inline u32 fifo_pbdma_status__size_1_v(void) { - return 0x00000001; + return 0x00000003; } static inline u32 fifo_pbdma_status_id_v(u32 r) { @@ -600,11 +600,11 @@ static inline u32 fifo_replay_fault_buffer_size_r(void) } static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x3ff) << 0; } static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) { - return 0x000000c0; + return 0x00000140; } static inline u32 fifo_replay_fault_buffer_get_r(void) { @@ -612,7 +612,7 @@ static inline u32 fifo_replay_fault_buffer_get_r(void) } static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x3ff) << 0; } static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) { @@ -624,7 +624,7 @@ static inline u32 fifo_replay_fault_buffer_put_r(void) } static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x3ff) << 0; } static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h index 955626a6..8c324225 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h @@ -242,6 +242,14 @@ static inline u32 gmmu_new_pte_address_sys_w(void) { return 0; } +static inline u32 gmmu_new_pte_address_vid_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_vid_w(void) +{ + return 0; +} static inline u32 gmmu_new_pte_vol_w(void) { return 0; @@ -1110,7 +1118,7 @@ static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) { return 0x000000de; } -static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void) +static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) { return 0x000000cc; } @@ -1174,7 +1182,7 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) { return 0x000000ec; } -static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void) +static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void) { return 0x000000cd; } diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index a37ce6e7..6cfa33ea 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -372,11 +372,11 @@ static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) } static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) { - return 0x005046a4; + return 0x0050433c; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) { - return 0x00419ea4; + return 0x00419b3c; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) { @@ -468,7 +468,7 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { - return 0x005046b8; + return 0x00504358; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) { @@ -504,7 +504,7 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_ } static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) { - return 0x005044a0; + return 0x0050436c; } static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) { @@ -532,15 +532,15 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pe } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) { - return 0x005046bc; + return 0x0050435c; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) { - return 0x005046c0; + return 0x00504360; } static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) { - return 0x005044a4; + return 0x00504370; } static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) { @@ -696,7 +696,7 @@ static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) } static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) { - return 0x7fffffff; + return 0x1800; } static inline u32 gr_fe_object_table_r(u32 i) { @@ -706,9 +706,9 @@ static inline u32 gr_fe_object_table_nvclass_v(u32 r) { return (r >> 0) & 0xffff; } -static inline u32 gr_fe_tpc_fs_r(void) +static inline u32 gr_fe_tpc_fs_r(u32 i) { - return 0x004041c4; + return 0x0040a200 + i*4; } static inline u32 gr_pri_mme_shadow_raw_index_r(void) { @@ -1530,29 +1530,9 @@ static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) { return 0x00502420; } -static inline u32 gr_rstr2d_gpc_map0_r(void) +static inline u32 gr_rstr2d_gpc_map_r(u32 i) { - return 0x0040780c; -} -static inline u32 gr_rstr2d_gpc_map1_r(void) -{ - return 0x00407810; -} -static inline u32 gr_rstr2d_gpc_map2_r(void) -{ - return 0x00407814; -} -static inline u32 gr_rstr2d_gpc_map3_r(void) -{ - return 0x00407818; -} -static inline u32 gr_rstr2d_gpc_map4_r(void) -{ - return 0x0040781c; -} -static inline u32 gr_rstr2d_gpc_map5_r(void) -{ - return 0x00407820; + return 0x0040780c + i*4; } static inline u32 gr_rstr2d_map_table_cfg_r(void) { @@ -1656,7 +1636,7 @@ static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) } static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) { - return 0x000001c0; + return 0x00000380; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) { @@ -1668,7 +1648,7 @@ static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) } static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) { - return 0x00000182; + return 0x00000302; } static inline u32 gr_pd_dist_skip_table_r(u32 i) { @@ -2052,7 +2032,7 @@ static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) } static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) { - return 0x00000018; + return 0x00000030; } static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) { @@ -2352,19 +2332,19 @@ static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) } static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) { - return 0x00504698; + return 0x00504608; } -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) { return (v & 0xffff) << 0; } -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) { return (r >> 0) & 0xffff; } static inline u32 gr_gpc0_tpc0_sm_arch_r(void) { - return 0x0050469c; + return 0x00504330; } static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) { @@ -2404,11 +2384,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { - return 0x00030000; + return 0x00001000; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) { - return 0x00030a00; + return 0x00001900; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { @@ -2452,11 +2432,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) { - return 0x00030000; + return 0x00001000; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) { - return 0x00419b00; + return 0x00419e00; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) { @@ -2464,7 +2444,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) { - return 0x00419b04; + return 0x00419e04; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) { @@ -2708,11 +2688,11 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) { - return 0x00000018; + return 0x00000030; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) { - return 0x18; + return 0x30; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) { @@ -2748,7 +2728,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) { - return 0x00500ee4; + return 0x005001dc; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) { @@ -2756,7 +2736,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) { - return 0x00000250; + return 0x00000170; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) { @@ -2764,7 +2744,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) { - return 0x00500ee0; + return 0x005001d8; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) { @@ -2776,7 +2756,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) { - return 0x00418eec; + return 0x004181e4; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) { @@ -2870,173 +2850,33 @@ static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) { return 0x80000000; } -static inline u32 gr_crstr_gpc_map0_r(void) -{ - return 0x00418b08; -} -static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) -{ - return (v & 0x7) << 15; -} -static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_gpc_map1_r(void) -{ - return 0x00418b0c; -} -static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) -{ - return (v & 0x7) << 15; -} -static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_gpc_map2_r(void) -{ - return 0x00418b10; -} -static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) -{ - return (v & 0x7) << 15; -} -static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_gpc_map3_r(void) -{ - return 0x00418b14; -} -static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) -{ - return (v & 0x7) << 15; -} -static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_gpc_map4_r(void) -{ - return 0x00418b18; -} -static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) +static inline u32 gr_crstr_gpc_map_r(u32 i) { - return (v & 0x7) << 15; + return 0x00418b08 + i*4; } -static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) +static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) { - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_gpc_map5_r(void) -{ - return 0x00418b1c; -} -static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) -{ - return (v & 0x7) << 0; + return (v & 0x1f) << 0; } -static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) +static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) { - return (v & 0x7) << 5; + return (v & 0x1f) << 5; } -static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) +static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) { - return (v & 0x7) << 10; + return (v & 0x1f) << 10; } -static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) +static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) { - return (v & 0x7) << 15; + return (v & 0x1f) << 15; } -static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) +static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) { - return (v & 0x7) << 20; + return (v & 0x1f) << 20; } -static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) +static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) { - return (v & 0x7) << 25; + return (v & 0x1f) << 25; } static inline u32 gr_crstr_map_table_cfg_r(void) { @@ -3050,159 +2890,39 @@ static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) { return (v & 0xff) << 8; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) -{ - return 0x00418980; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) -{ - return (v & 0x7) << 4; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) -{ - return (v & 0x7) << 16; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) -{ - return (v & 0x7) << 28; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) -{ - return 0x00418984; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) -{ - return (v & 0x7) << 4; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) -{ - return (v & 0x7) << 16; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) -{ - return (v & 0x7) << 28; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) -{ - return 0x00418988; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) -{ - return (v & 0x7) << 4; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) -{ - return (v & 0x7) << 16; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) -{ - return 3; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) -{ - return (v & 0x7) << 28; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) -{ - return 0x7 << 28; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) -{ - return (r >> 28) & 0x7; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) { - return 0x0041898c; + return 0x00418980 + i*4; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) { return (v & 0x7) << 0; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) { return (v & 0x7) << 4; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) { return (v & 0x7) << 8; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) { return (v & 0x7) << 12; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) { return (v & 0x7) << 16; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) { return (v & 0x7) << 20; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) { return (v & 0x7) << 24; } -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) { return (v & 0x7) << 28; } @@ -3210,14 +2930,6 @@ static inline u32 gr_gpcs_gpm_pd_cfg_r(void) { return 0x00418c6c; } -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) -{ - return 0x1; -} static inline u32 gr_gpcs_gcc_pagepool_base_r(void) { return 0x00419004; @@ -3286,135 +2998,87 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { return 0x10000000; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_r(void) { - return 0x00419e44; + return 0x00419f28; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) { return 0x2; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) { return 0x4; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) { return 0x10; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) { return 0x20; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) { return 0x40; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) -{ - return 0x80; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) { return 0x100; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) { return 0x200; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) -{ - return 0x400; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) { return 0x800; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) -{ - return 0x1000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) { return 0x2000; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) { return 0x4000; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) { return 0x8000; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) { return 0x10000; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) -{ - return 0x20000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) { return 0x40000; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) { return 0x800000; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) { return 0x400000; } -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) -{ - return 0x80000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) -{ - return 0x100000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) -{ - return 0x00419e4c; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_r(void) { - return 0x1; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) -{ - return 0x2; + return 0x00419f2c; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) { return 0x4; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) { return 0x10; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void) -{ - return 0x20000000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void) -{ - return 0x40000000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) { return 0x20; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) { return 0x40; } @@ -3482,190 +3146,118 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { return 0x00000001; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) { - return 0x00504610; + return 0x00504704; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) { return 0x1 << 0; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) { return (r >> 0) & 0x1; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) { return 0x00000001; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) { return 0x00000000; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) { return 0x0; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) { return 0x8; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) { return 0x0; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) { - return (r >> 1) & 0x1; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) -{ - return 0x1 << 2; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614; + return 0x00504708; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) { - return 0x00504624; + return 0x00504710; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) { - return 0x00504634; + return 0x00504718; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_bpt_pause_mask_r(void) { - return 0x00419e24; + return 0x00419f10; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) { - return 0x0050460c; + return 0x00504700; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) { return (r >> 0) & 0x1; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) { return (r >> 4) & 0x1; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) { return 0x00000001; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_r(void) { - return 0x00419e50; + return 0x00419f34; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_int_pending_f(void) { return 0x10; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(void) { return 0x20; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_single_step_complete_pending_f(void) { return 0x40; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) { return 0x4; } -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) { - return 0x80000000; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) -{ - return 0x00504650; + return 0x00504734; } -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) { return 0x10; } -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void) -{ - return 0x20000000; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void) -{ - return 0x40000000; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) { return 0x20; } -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) { return 0x40; } -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) { return 0x4; } -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000; -} static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) { return 0x00504224; @@ -3682,45 +3274,45 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) { return 0x100; } -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) { - return 0x00504648; + return 0x00504730; } -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) { return (r >> 0) & 0xffff; } -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) { return 0x00000000; } -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) { return 0x0; } -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) { - return 0x1 << 24; + return 0xff << 16; } -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) { - return 0x7 << 25; + return 0xf << 24; } -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) { return 0x0; } -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) { - return 0x00504654; + return 0x00504738; } static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) { - return 0x00504770; + return 0x005043a0; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) { - return 0x00419f70; + return 0x00419ba0; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) { @@ -3732,11 +3324,11 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) } static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) { - return 0x0050477c; + return 0x005043b0; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) { - return 0x00419f7c; + return 0x00419bb0; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) { @@ -3754,29 +3346,9 @@ static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) { return 0x4; } -static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) +static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) { - return 0x0041bf00; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) -{ - return 0x0041bf04; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) -{ - return 0x0041bf08; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) -{ - return 0x0041bf0c; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) -{ - return 0x0041bf10; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) -{ - return 0x0041bf14; + return 0x0041bf00 + i*4; } static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) { @@ -3798,10 +3370,6 @@ static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) { return (v & 0x7) << 21; } -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) -{ - return (v & 0x1f) << 24; -} static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) { return 0x0041bfd4; @@ -3810,33 +3378,25 @@ static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) { return (v & 0xffffff) << 0; } -static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) -{ - return 0x0041bfe4; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) { - return (v & 0x1f) << 0; + return 0x0041bfb0 + i*4; } -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) { - return (v & 0x1f) << 5; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) -{ - return (v & 0x1f) << 10; + return (v & 0xff) << 0; } -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) { - return (v & 0x1f) << 15; + return (v & 0xff) << 8; } -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) { - return (v & 0x1f) << 20; + return (v & 0xff) << 16; } -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) { - return (v & 0x1f) << 25; + return (v & 0xff) << 24; } static inline u32 gr_bes_zrop_settings_r(void) { @@ -3884,107 +3444,75 @@ static inline u32 gr_zcull_subregion_qty_v(void) } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) { - return 0x00504604; + return 0x00504308; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) { - return 0x00504608; + return 0x0050430c; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) { - return 0x0050465c; + return 0x00504318; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) { - return 0x00504660; + return 0x00504320; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) { - return 0x00504664; + return 0x00504324; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) { - return 0x00504668; + return 0x00504328; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) { - return 0x0050466c; + return 0x0050432c; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) { - return 0x00504658; + return 0x0050431c; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) { - return 0x00504730; + return 0x00504378; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) { - return 0x00504734; + return 0x0050437c; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) { - return 0x00504738; + return 0x00504380; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) { - return 0x0050473c; + return 0x00504384; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) { - return 0x00504740; + return 0x00504388; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) { - return 0x00504744; + return 0x0050438c; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) { - return 0x00504748; + return 0x00504390; } static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) { - return 0x0050474c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) -{ - return 0x00504678; + return 0x00504394; } -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) +static inline u32 gr_pri_gpc0_tpc0_sm0_dsm_perf_counter_status_s1_r(void) { - return 0x00504694; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) -{ - return 0x005046f0; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) -{ - return 0x00504700; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) -{ - return 0x005046f4; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) -{ - return 0x00504704; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) -{ - return 0x005046f8; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) -{ - return 0x00504708; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) -{ - return 0x005046fc; + return 0x00504744; } -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) +static inline u32 gr_pri_gpc0_tpc0_sm0_dsm_perf_counter_status1_r(void) { - return 0x0050470c; + return 0x00504750; } static inline u32 gr_fe_pwr_mode_r(void) { @@ -4082,55 +3610,55 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) { return 0x004188ac; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_r(void) { - return 0x00419e10; + return 0x00419f04; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_f(u32 v) { return (v & 0x1) << 0; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_on_v(void) { return 0x00000001; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_m(void) { return 0x1 << 31; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_v(u32 r) { return (r >> 31) & 0x1; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_disable_f(void) { return 0x0; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(void) { return 0x1 << 3; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f(void) { return 0x8; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f(void) { return 0x0; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_m(void) { return 0x1 << 30; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_v(u32 r) { return (r >> 30) & 0x1; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; } @@ -4148,7 +3676,7 @@ static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) } static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) { - return 0x00419c84; + return 0x00419bd8; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) { @@ -4164,7 +3692,7 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_ma } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) { - return 0x00419f78; + return 0x00419ba4; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) { @@ -4180,10 +3708,10 @@ static inline u32 gr_gpcs_tc_debug0_r(void) } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0x1ff) << 0; } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { - return 0xff << 0; + return 0x1ff << 0; } #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h index 2dbd759f..4c10852e 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h @@ -570,12 +570,4 @@ static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) { return (r >> 16) & 0x1f; } -static inline u32 ltc_ltca_g_axi_pctrl_r(void) -{ - return 0x00160000; -} -static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v) -{ - return (v & 0xff) << 2; -} #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h index b3aaa7e6..259d366d 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h @@ -72,7 +72,7 @@ static inline u32 pbdma_gp_base_r(u32 i) } static inline u32 pbdma_gp_base__size_1_v(void) { - return 0x00000001; + return 0x00000003; } static inline u32 pbdma_gp_base_offset_f(u32 v) { @@ -470,10 +470,6 @@ static inline u32 pbdma_intr_0_pbcrc_pending_f(void) { return 0x80000; } -static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) -{ - return 0x100000; -} static inline u32 pbdma_intr_0_method_pending_f(void) { return 0x200000; @@ -510,10 +506,6 @@ static inline u32 pbdma_intr_0_signature_pending_f(void) { return 0x80000000; } -static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void) -{ - return 0x10000000; -} static inline u32 pbdma_intr_1_r(u32 i) { return 0x00040148 + i*8192; @@ -566,38 +558,6 @@ static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) { return (v & 0x7fff) << 0; } -static inline u32 pbdma_syncpointa_r(u32 i) -{ - return 0x000400a4 + i*8192; -} -static inline u32 pbdma_syncpointa_payload_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 pbdma_syncpointb_r(u32 i) -{ - return 0x000400a8 + i*8192; -} -static inline u32 pbdma_syncpointb_op_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 pbdma_syncpointb_op_wait_v(void) -{ - return 0x00000000; -} -static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 pbdma_syncpointb_wait_switch_en_v(void) -{ - return 0x00000001; -} -static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) -{ - return (r >> 8) & 0xfff; -} static inline u32 pbdma_runlist_timeslice_r(u32 i) { return 0x000400f8 + i*8192; diff --git a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h index 4d11fef4..836c014b 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h @@ -52,7 +52,7 @@ static inline u32 perf_pmasys_control_r(void) { - return 0x001b4000; + return 0x0024a000; } static inline u32 perf_pmasys_control_membuf_status_v(u32 r) { @@ -84,7 +84,7 @@ static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) } static inline u32 perf_pmasys_mem_block_r(void) { - return 0x001b4070; + return 0x0024a070; } static inline u32 perf_pmasys_mem_block_base_f(u32 v) { @@ -148,7 +148,7 @@ static inline u32 perf_pmasys_mem_block_valid_false_f(void) } static inline u32 perf_pmasys_outbase_r(void) { - return 0x001b4074; + return 0x0024a074; } static inline u32 perf_pmasys_outbase_ptr_f(u32 v) { @@ -156,7 +156,7 @@ static inline u32 perf_pmasys_outbase_ptr_f(u32 v) } static inline u32 perf_pmasys_outbaseupper_r(void) { - return 0x001b4078; + return 0x0024a078; } static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) { @@ -164,7 +164,7 @@ static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) } static inline u32 perf_pmasys_outsize_r(void) { - return 0x001b407c; + return 0x0024a07c; } static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) { @@ -172,7 +172,7 @@ static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) } static inline u32 perf_pmasys_mem_bytes_r(void) { - return 0x001b4084; + return 0x0024a084; } static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) { @@ -180,7 +180,7 @@ static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) } static inline u32 perf_pmasys_mem_bump_r(void) { - return 0x001b4088; + return 0x0024a088; } static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) { @@ -188,7 +188,7 @@ static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) } static inline u32 perf_pmasys_enginestatus_r(void) { - return 0x001b40a4; + return 0x0024a0a4; } static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h index e08c6854..3477c03e 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h @@ -108,23 +108,23 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) } static inline u32 proj_host_num_engines_v(void) { - return 0x00000002; + return 0x00000004; } static inline u32 proj_host_num_pbdma_v(void) { - return 0x00000001; + return 0x00000003; } static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) { - return 0x00000002; + return 0x00000004; } static inline u32 proj_scal_litter_num_fbps_v(void) { - return 0x00000001; + return 0x00000002; } static inline u32 proj_scal_litter_num_fbpas_v(void) { - return 0x00000001; + return 0x00000004; } static inline u32 proj_scal_litter_num_gpcs_v(void) { @@ -132,7 +132,7 @@ static inline u32 proj_scal_litter_num_gpcs_v(void) } static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) { - return 0x00000001; + return 0x00000002; } static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h index 27ea4246..965f8663 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h @@ -608,11 +608,11 @@ static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) } static inline u32 pwr_pmu_queue_head_r(u32 i) { - return 0x0010a4a0 + i*4; + return 0x0010a800 + i*4; } static inline u32 pwr_pmu_queue_head__size_1_v(void) { - return 0x00000004; + return 0x00000008; } static inline u32 pwr_pmu_queue_head_address_f(u32 v) { @@ -624,11 +624,11 @@ static inline u32 pwr_pmu_queue_head_address_v(u32 r) } static inline u32 pwr_pmu_queue_tail_r(u32 i) { - return 0x0010a4b0 + i*4; + return 0x0010a820 + i*4; } static inline u32 pwr_pmu_queue_tail__size_1_v(void) { - return 0x00000004; + return 0x00000008; } static inline u32 pwr_pmu_queue_tail_address_f(u32 v) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index 6ccbc266..c6f51acb 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -148,7 +148,7 @@ static inline u32 ram_in_page_dir_base_lo_w(void) } static inline u32 ram_in_page_dir_base_hi_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffffffff) << 0; } static inline u32 ram_in_page_dir_base_hi_w(void) { @@ -354,14 +354,6 @@ static inline u32 ram_fc_allowed_syncpoints_w(void) { return 58; } -static inline u32 ram_fc_syncpointa_w(void) -{ - return 41; -} -static inline u32 ram_fc_syncpointb_w(void) -{ - return 42; -} static inline u32 ram_fc_target_w(void) { return 43; @@ -443,6 +435,74 @@ static inline u32 ram_userd_gp_top_level_get_hi_w(void) return 23; } static inline u32 ram_rl_entry_size_v(void) +{ + return 0x00000010; +} +static inline u32 ram_rl_entry_type_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 ram_rl_entry_type_channel_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_type_tsg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) +{ + return (v & 0x3) << 4; +} +static inline u32 ram_rl_entry_chan_inst_target_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) +{ + return (v & 0x3) << 6; +} +static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_nvlink_coh_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_ptr_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_align_shift_v(void) { return 0x00000008; } @@ -450,40 +510,56 @@ static inline u32 ram_rl_entry_chid_f(u32 v) { return (v & 0xfff) << 0; } -static inline u32 ram_rl_entry_id_f(u32 v) +static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffff) << 12; } -static inline u32 ram_rl_entry_type_f(u32 v) +static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0xffffffff) << 0; } -static inline u32 ram_rl_entry_type_chid_f(void) +static inline u32 ram_rl_entry_tsg_vmid_f(u32 v) { - return 0x0; + return (v & 0xff) << 4; } -static inline u32 ram_rl_entry_type_tsg_f(void) +static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) { - return 0x2000; + return (v & 0xf) << 16; } -static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) +static inline u32 ram_rl_entry_tsg_timeslice_scale_entry_tsg_timeslice_scale_3_v(void) { - return (v & 0xf) << 14; + return 0x00000003; } -static inline u32 ram_rl_entry_timeslice_scale_3_f(void) +static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) { - return 0xc000; + return (v & 0xff) << 24; } -static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) +static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_128_v(void) { - return (v & 0xff) << 18; + return 0x00000080; } -static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) +static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_disable_v(void) { - return 0x2000000; + return 0x00000000; } static inline u32 ram_rl_entry_tsg_length_f(u32 v) { - return (v & 0x3f) << 26; + return (v & 0xff) << 0; +} +static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_init_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_min_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_max_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) +{ + return (v & 0xfff) << 0; } #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h index 2c464d2c..a3cfcf91 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h @@ -50,360 +50,4 @@ #ifndef _hw_therm_gv11b_h_ #define _hw_therm_gv11b_h_ -static inline u32 therm_use_a_r(void) -{ - return 0x00020798; -} -static inline u32 therm_use_a_ext_therm_0_enable_f(void) -{ - return 0x1; -} -static inline u32 therm_use_a_ext_therm_1_enable_f(void) -{ - return 0x2; -} -static inline u32 therm_use_a_ext_therm_2_enable_f(void) -{ - return 0x4; -} -static inline u32 therm_evt_ext_therm_0_r(void) -{ - return 0x00020700; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) -{ - return (v & 0x3f) << 24; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) -{ - return 0x00000001; -} -static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) -{ - return (v & 0x3) << 30; -} -static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) -{ - return 0x00000000; -} -static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) -{ - return 0x00000001; -} -static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) -{ - return 0x00000002; -} -static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) -{ - return 0x00000003; -} -static inline u32 therm_evt_ext_therm_1_r(void) -{ - return 0x00020704; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) -{ - return (v & 0x3f) << 24; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) -{ - return 0x00000002; -} -static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) -{ - return (v & 0x3) << 30; -} -static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) -{ - return 0x00000000; -} -static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) -{ - return 0x00000001; -} -static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) -{ - return 0x00000002; -} -static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) -{ - return 0x00000003; -} -static inline u32 therm_evt_ext_therm_2_r(void) -{ - return 0x00020708; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) -{ - return (v & 0x3f) << 24; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) -{ - return 0x00000003; -} -static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) -{ - return (v & 0x3) << 30; -} -static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) -{ - return 0x00000000; -} -static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) -{ - return 0x00000001; -} -static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) -{ - return 0x00000002; -} -static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) -{ - return 0x00000003; -} -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return 0x00020200 + i*4; -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return 0x3 << 0; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return 0x3 << 2; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4; -} -static inline u32 therm_gate_ctrl_eng_pwr_m(void) -{ - return 0x3 << 4; -} -static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) -{ - return 0x10; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) -{ - return 0x00000002; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) -{ - return 0x20; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1f) << 8; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return 0x1f << 8; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7) << 13; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return 0x7 << 13; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xf) << 16; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return 0xf << 16; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xf) << 20; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return 0xf << 20; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return 0xffffffff << 0; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028c; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return 0xffffffff << 0; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return 0x00020160 + i*4; -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3f) << 16; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return 0x3f << 16; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16) & 0x3f; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return 0x000202c8 + i*4; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return 0x3f << 0; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xe; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3f) << 6; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return 0x3f << 6; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3f) << 12; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return 0x3f << 12; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3f) << 18; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return 0x3f << 18; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3f) << 24; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return 0x3f << 24; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return 0x1 << 0; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return 0x000203c0 + i*4; -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1) << 16; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return 0x1 << 16; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000; -} #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h index cb65cad8..2e2ff6ba 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h @@ -208,7 +208,7 @@ static inline u32 top_device_info_data_pri_base_align_v(void) } static inline u32 top_device_info_data_fault_id_enum_v(u32 r) { - return (r >> 3) & 0x1f; + return (r >> 3) & 0x7f; } static inline u32 top_device_info_data_fault_id_v(u32 r) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h new file mode 100644 index 00000000..8bcf163f --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_usermode_gv11b_h_ +#define _hw_usermode_gv11b_h_ + +static inline u32 usermode_cfg0_r(void) +{ + return 0x00810000; +} +static inline u32 usermode_cfg0_usermode_class_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 usermode_cfg0_usermode_class_id_value_v(void) +{ + return 0x0000c361; +} +static inline u32 usermode_time_0_r(void) +{ + return 0x00810080; +} +static inline u32 usermode_time_0_nsec_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 usermode_time_1_r(void) +{ + return 0x00810084; +} +static inline u32 usermode_time_1_nsec_f(u32 v) +{ + return (v & 0x1fffffff) << 0; +} +static inline u32 usermode_notify_channel_pending_r(void) +{ + return 0x00810090; +} +static inline u32 usermode_notify_channel_pending_id_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +#endif -- cgit v1.2.2 From f1f9e2a3e6957470f479de6de7802c32c78888bd Mon Sep 17 00:00:00 2001 From: Bharat Nihalani Date: Tue, 13 Sep 2016 17:56:10 +0530 Subject: Add NVIDIA-REVIEWERS file for nvgpu-t19x module This is done to designate nvgpu-t19x module owners so as to help with tools like Coverity and Code Coverage. bug 200195707 Change-Id: I1f75c11392c74372112018ed3f8fc882dd676bc4 Signed-off-by: Bharat Nihalani Reviewed-on: http://git-master/r/1220031 Reviewed-by: Deepak Nibade --- NVIDIA-REVIEWERS | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 NVIDIA-REVIEWERS diff --git a/NVIDIA-REVIEWERS b/NVIDIA-REVIEWERS new file mode 100644 index 00000000..d5de0d05 --- /dev/null +++ b/NVIDIA-REVIEWERS @@ -0,0 +1,59 @@ +This is a reviewers file that can be parsed by get_nv_reviewers.py that +internally uses scripts/get_maintainer.pl from kernel. + +See the MAINTAINERS file in the Linux kernel source tree for details of the +file format. The file format is defined by the upstream Linux kernel community, +so don't modify it without upstreaming any changes to get_maintainer.pl. + +Descriptions of section entries (copied from MAINTAINERS): + + P: Person (obsolete) + M: Mail patches to: FullName + L: Mailing list that is relevant to this area + W: Web-page with status/info + Q: Patchwork web based patch tracking system site + T: SCM tree type and location. Type is one of: git, hg, quilt, stgit, topgit. + S: Status, one of the following: + Supported: Someone is actually paid to look after this. + Maintained: Someone actually looks after it. + Odd Fixes: It has a maintainer but they don't have time to do + much other than throw the odd patch in. See below.. + Orphan: No current maintainer [but maybe you could take the + role as you write your new code]. + Obsolete: Old code. Something tagged obsolete generally means + it has been replaced by a better system and you + should be using that. + F: Files and directories with wildcard patterns. + A trailing slash includes all files and subdirectory files. + F: drivers/net/ all files in and below drivers/net + F: drivers/net/* all files in drivers/net, but not below + F: */net/* all files in "any top level directory"/net + One pattern per line. Multiple F: lines acceptable. + X: Files and directories that are NOT maintained, same rules as F: + Files exclusions are tested before file matches. + Can be useful for excluding a specific subdirectory, for instance: + F: net/ + X: net/ipv6/ + matches all files in and below net excluding net/ipv6/ + K: Keyword perl extended regex pattern to match content in a + patch or file. For instance: + K: of_get_profile + matches patches or files that contain "of_get_profile" + K: \b(printk|pr_(info|err))\b + matches patches or files that contain one or more of the words + printk, pr_info or pr_err + One regex pattern per line. Multiple K: lines acceptable. + +Note: For the hard of thinking, this list is meant to remain in alphabetical +order. If you could add yourselves to it in alphabetical order that would be +so much easier [Ed] + +Maintainers List (try to look for most precise areas first) + + ----------------------------------- +GPU +M: Terje Bergstrom +L: sw-mobile-nvgpu-core@exchange.nvidia.com +S: Supported +F: drivers/* +F: include/* -- cgit v1.2.2 From 8fdf40a849f19dc2f00aacce976ed2e22dbb08f4 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 13 Sep 2016 13:08:01 -0700 Subject: gpu: gv11b: create modified runlist Create gv11b runlist for channel and tsg in the new specified way. Also set runlist entry size for gv11b. Bug 1735760 Change-Id: Ifd421cd71180e9d02303f4cfc92a59fd74d6d893 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1220258 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru Reviewed-by: Seema Khowala Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 63 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 46 ++++++++++++------------- 2 files changed, 86 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index af5f094d..35b36ec5 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -21,8 +21,71 @@ #include "hw_pbdma_gv11b.h" #include "fifo_gv11b.h" #include "hw_fifo_gv11b.h" +#include "hw_ram_gv11b.h" +#include "hw_ccsr_gv11b.h" + +static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) +{ + + u32 runlist_entry_0 = ram_rl_entry_type_tsg_v(); + + if (tsg->timeslice_timeout) + runlist_entry_0 |= + ram_rl_entry_tsg_timeslice_scale_f(tsg->timeslice_scale) | + ram_rl_entry_tsg_timeslice_timeout_f(tsg->timeslice_timeout); + else + runlist_entry_0 |= + ram_rl_entry_tsg_timeslice_scale_f( + ram_rl_entry_tsg_timeslice_scale_3_v()) | + ram_rl_entry_tsg_timeslice_timeout_f( + ram_rl_entry_tsg_timeslice_timeout_128_v()); + + runlist[0] = runlist_entry_0; + runlist[1] = ram_rl_entry_tsg_length_f(tsg->num_active_channels); + runlist[2] = ram_rl_entry_tsg_tsgid_f(tsg->tsgid); + runlist[3] = 0; + + gk20a_dbg_info("gv11b tsg runlist [0] %x [1] %x [2] %x [3] %x\n", + runlist[0], runlist[1], runlist[2], runlist[3]); + +} + +static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) +{ + struct gk20a *g = c->g; + u32 addr_lo, addr_hi; + u32 runlist_entry; + + /* Time being use 0 pbdma sequencer */ + runlist_entry = ram_rl_entry_type_channel_v() | + ram_rl_entry_chan_runqueue_selector_f(0) | + ram_rl_entry_chan_userd_target_f( + ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | + ram_rl_entry_chan_inst_target_f( + ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()); + + addr_lo = u64_lo32(c->userd_iova) >> + ram_rl_entry_chan_userd_ptr_align_shift_v(); + addr_hi = u64_hi32(c->userd_iova); + runlist[0] = runlist_entry | ram_rl_entry_chan_userd_ptr_lo_f(addr_lo); + runlist[1] = ram_rl_entry_chan_userd_ptr_hi_f(addr_hi); + + addr_lo = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)) >> + ram_rl_entry_chan_inst_ptr_align_shift_v(); + addr_hi = u64_hi32(gk20a_mm_inst_block_addr(g, &c->inst_block)); + + runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) | + ram_rl_entry_chid_f(c->hw_chid); + runlist[3] = ram_rl_entry_chan_inst_ptr_hi_f(addr_hi); + + gk20a_dbg_info("gv11b channel runlist [0] %x [1] %x [2] %x [3] %x\n", + runlist[0], runlist[1], runlist[2], runlist[3]); +} void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); + gops->fifo.runlist_entry_size = ram_rl_entry_size_v; + gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry; + gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry; } diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index c6f51acb..9cd2096a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -462,7 +462,7 @@ static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) { return (v & 0x3) << 4; } -static inline u32 ram_rl_entry_chan_inst_target_target_sys_mem_ncoh_v(void) +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) { return 0x00000003; } @@ -470,19 +470,19 @@ static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) { return (v & 0x3) << 6; } -static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_v(void) +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) { return 0x00000000; } -static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_nvlink_coh_v(void) +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) { return 0x00000001; } -static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_coh_v(void) +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) { return 0x00000002; } -static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_ncoh_v(void) +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) { return 0x00000003; } @@ -494,18 +494,6 @@ static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) { return (v & 0xffffffff) << 0; } -static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_inst_ptr_align_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_ptr_align_shift_v(void) -{ - return 0x00000008; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_align_shift_v(void) -{ - return 0x00000008; -} static inline u32 ram_rl_entry_chid_f(u32 v) { return (v & 0xfff) << 0; @@ -526,7 +514,7 @@ static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) { return (v & 0xf) << 16; } -static inline u32 ram_rl_entry_tsg_timeslice_scale_entry_tsg_timeslice_scale_3_v(void) +static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) { return 0x00000003; } @@ -534,11 +522,11 @@ static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) { return (v & 0xff) << 24; } -static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_128_v(void) +static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) { return 0x00000080; } -static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_disable_v(void) +static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) { return 0x00000000; } @@ -546,15 +534,15 @@ static inline u32 ram_rl_entry_tsg_length_f(u32 v) { return (v & 0xff) << 0; } -static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_init_v(void) +static inline u32 ram_rl_entry_tsg_length_init_v(void) { return 0x00000000; } -static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_min_v(void) +static inline u32 ram_rl_entry_tsg_length_min_v(void) { return 0x00000001; } -static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_max_v(void) +static inline u32 ram_rl_entry_tsg_length_max_v(void) { return 0x00000080; } @@ -562,4 +550,16 @@ static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) { return (v & 0xfff) << 0; } +static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) +{ + return 0x00000008; +} #endif -- cgit v1.2.2 From 09168aac40b22ba264de6a7fc1e5264528b1fe9f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Sep 2016 14:41:31 -0700 Subject: gpu: nvgpu: gv11b: header updates for CL#37119043 Bug 1735760 Change-Id: I5216863a25338f14498ae0be58b86993104d4e99 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1222031 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 207 +------------------- drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 88 +-------- drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 174 ++--------------- drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 16 ++ drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | 8 +- drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 312 ++++++++++++++++++++++++------- 6 files changed, 283 insertions(+), 522 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 088ec040..02044df6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -67,105 +67,16 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, int ret = 0; u32 offset = proj_gpc_stride_v() * gpc + proj_tpc_in_gpc_stride_v() * tpc; - u32 lrf_ecc_status, shm_ecc_status; + u32 lrf_ecc_status; gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); /* Check for LRF ECC errors. */ lrf_ecc_status = gk20a_readl(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); - if ((lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f())) { - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Single bit error detected in SM LRF!"); - - g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] += - gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset); - gk20a_writel(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset, - 0); - } - if ((lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f())) { - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Double bit error detected in SM LRF!"); - - g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] += - gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset); - gk20a_writel(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, 0); - } + gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, lrf_ecc_status); - - /* Check for SHM ECC errors. */ - shm_ecc_status = gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset); - if ((shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) || - (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f()) || - (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) || - (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f())) { - u32 ecc_stats_reg_val; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Single bit error detected in SM SHM!"); - - ecc_stats_reg_val = - gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); - g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] += - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); - g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] += - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); - gk20a_writel(g, - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, - ecc_stats_reg_val); - } - if ((shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) || - (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f())) { - u32 ecc_stats_reg_val; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Double bit error detected in SM SHM!"); - - ecc_stats_reg_val = - gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); - g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] += - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); - gk20a_writel(g, - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, - ecc_stats_reg_val); - } - gk20a_writel(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset, - shm_ecc_status); - - return ret; } @@ -176,7 +87,6 @@ static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 offset = proj_gpc_stride_v() * gpc + proj_tpc_in_gpc_stride_v() * tpc; u32 esr; - u32 ecc_stats_reg_val; gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); @@ -184,119 +94,6 @@ static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, gr_gpc0_tpc0_tex_m_hww_esr_r() + offset); gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr); - if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Single bit error detected in TEX!"); - - /* Pipe 0 counters */ - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); - g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, - ecc_stats_reg_val); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); - g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, - ecc_stats_reg_val); - - - /* Pipe 1 counters */ - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); - g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, - ecc_stats_reg_val); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); - g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, - ecc_stats_reg_val); - - - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); - } - if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f()) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Double bit error detected in TEX!"); - - /* Pipe 0 counters */ - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); - g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, - ecc_stats_reg_val); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); - g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, - ecc_stats_reg_val); - - - /* Pipe 1 counters */ - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); - g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, - ecc_stats_reg_val); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); - g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, - ecc_stats_reg_val); - - - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); - } - gk20a_writel(g, gr_gpc0_tpc0_tex_m_hww_esr_r() + offset, esr); diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index 8af66362..7e9e2743 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h @@ -190,22 +190,6 @@ static inline u32 fifo_intr_0_lb_error_reset_f(void) { return 0x1000000; } -static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void) -{ - return 0x2000000; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) -{ - return 0x8000000; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) -{ - return 0x8000000; -} -static inline u32 fifo_intr_0_mmu_fault_pending_f(void) -{ - return 0x10000000; -} static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) { return 0x20000000; @@ -230,14 +214,6 @@ static inline u32 fifo_intr_en_0_sched_error_m(void) { return 0x1 << 8; } -static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 fifo_intr_en_0_mmu_fault_m(void) -{ - return 0x1 << 28; -} static inline u32 fifo_intr_en_1_r(void) { return 0x00002528; @@ -262,62 +238,14 @@ static inline u32 fifo_intr_chsw_error_r(void) { return 0x0000256c; } -static inline u32 fifo_intr_mmu_fault_id_r(void) -{ - return 0x0000259c; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) -{ - return 0x00000040; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) -{ - return 0x0; -} -static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) -{ - return 0x00002800 + i*16; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) -{ - return (r >> 0) & 0xfffffff; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) -{ - return 0x00002804 + i*16; -} -static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) -{ - return 0x00002808 + i*16; -} -static inline u32 fifo_intr_mmu_fault_info_r(u32 i) -{ - return 0x0000280c + i*16; -} -static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20) & 0x1; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void) +static inline u32 fifo_gpc_v(void) { return 0x00000000; } -static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void) +static inline u32 fifo_hub_v(void) { return 0x00000001; } -static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8) & 0x7f; -} static inline u32 fifo_intr_pbdma_id_r(void) { return 0x000025a0; @@ -394,18 +322,6 @@ static inline u32 fifo_preempt_id_f(u32 v) { return (v & 0xfff) << 0; } -static inline u32 fifo_trigger_mmu_fault_r(u32 i) -{ - return 0x00002a30 + i*4; -} -static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) -{ - return (v & 0x1f) << 0; -} -static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) -{ - return (v & 0x1) << 8; -} static inline u32 fifo_engine_status_r(u32 i) { return 0x00002640 + i*8; diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index 6cfa33ea..e8394215 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -470,102 +470,6 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { return 0x00504358; } -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void) -{ - return 0x80; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void) -{ - return 0x100; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void) -{ - return 0x200; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void) -{ - return 0x400; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void) -{ - return 0x800; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) -{ - return 0x0050436c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void) -{ - return 0x2; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void) -{ - return 0x100; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void) -{ - return 0x200; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) -{ - return 0x0050435c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) -{ - return 0x00504360; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) -{ - return 0x00504370; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) -{ - return 0xff << 0; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void) -{ - return 0xff << 8; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r) -{ - return (r >> 8) & 0xff; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void) -{ - return 0xff << 16; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r) -{ - return (r >> 16) & 0xff; -} static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) { return 0x005042c4; @@ -582,46 +486,6 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) { return 0x2; } -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void) -{ - return 0x00504218; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void) -{ - return 0xffff << 0; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void) -{ - return 0xffff << 16; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r) -{ - return (r >> 16) & 0xffff; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void) -{ - return 0x005042ec; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void) -{ - return 0xffff << 0; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void) -{ - return 0xffff << 16; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r) -{ - return (r >> 16) & 0xffff; -} static inline u32 gr_pri_be0_crop_status1_r(void) { return 0x00410134; @@ -654,6 +518,14 @@ static inline u32 gr_pipe_bundle_address_value_v(u32 r) { return (r >> 0) & 0xffff; } +static inline u32 gr_pipe_bundle_address_veid_f(u32 v) +{ + return (v & 0x3f) << 20; +} +static inline u32 gr_pipe_bundle_address_veid_v(u32 r) +{ + return (r >> 20) & 0x3f; +} static inline u32 gr_pipe_bundle_data_r(void) { return 0x00400204; @@ -1498,14 +1370,6 @@ static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) { return (r >> 3) & 0x1; } -static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r) -{ - return (r >> 7) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r) -{ - return (r >> 11) & 0x1; -} static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) { return (r >> 15) & 0x1; @@ -1514,14 +1378,6 @@ static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) { return (r >> 0) & 0x1; } -static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r) -{ - return (r >> 8) & 0x1; -} static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) { return (r >> 12) & 0x1; @@ -2384,11 +2240,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { - return 0x00001000; + return 0x00000800; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) { - return 0x00001900; + return 0x00001100; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { @@ -2432,7 +2288,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) { - return 0x00001000; + return 0x00000800; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) { @@ -3266,14 +3122,6 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) { return 0x1; } -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void) -{ - return 0x80; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) -{ - return 0x100; -} static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) { return 0x00504730; diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h index 259d366d..38d63487 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h @@ -574,4 +574,20 @@ static inline u32 pbdma_runlist_timeslice_enable_true_f(void) { return 0x10000000; } +static inline u32 pbdma_set_channel_info_r(u32 i) +{ + return 0x000400fc + i*8192; +} +static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) +{ + return 0x1; +} +static inline u32 pbdma_set_channel_info_veid_f(u32 v) +{ + return (v & 0x3f) << 8; +} #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h index 3477c03e..f57e0263 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h @@ -114,17 +114,21 @@ static inline u32 proj_host_num_pbdma_v(void) { return 0x00000003; } +static inline u32 proj_litter_num_subctx_v(void) +{ + return 0x00000040; +} static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) { return 0x00000004; } static inline u32 proj_scal_litter_num_fbps_v(void) { - return 0x00000002; + return 0x00000001; } static inline u32 proj_scal_litter_num_fbpas_v(void) { - return 0x00000004; + return 0x00000002; } static inline u32 proj_scal_litter_num_gpcs_v(void) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index 9cd2096a..7c89db4d 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -86,37 +86,9 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +static inline u32 ram_in_page_dir_base_vol_false_f(void) { - return (v & 0x1) << 4; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return 0x1 << 4; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return 0x1 << 5; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20; + return 0x0; } static inline u32 ram_in_big_page_size_f(u32 v) { @@ -154,89 +126,293 @@ static inline u32 ram_in_page_dir_base_hi_w(void) { return 129; } -static inline u32 ram_in_adr_limit_lo_f(u32 v) +static inline u32 ram_in_engine_cs_w(void) { - return (v & 0xfffff) << 12; + return 132; +} +static inline u32 ram_in_engine_cs_wfi_v(void) +{ + return 0x00000000; } -static inline u32 ram_in_adr_limit_lo_w(void) +static inline u32 ram_in_engine_cs_wfi_f(void) { - return 130; + return 0x0; } -static inline u32 ram_in_adr_limit_hi_f(u32 v) +static inline u32 ram_in_engine_cs_fg_v(void) { - return (v & 0xffffffff) << 0; + return 0x00000001; } -static inline u32 ram_in_adr_limit_hi_w(void) +static inline u32 ram_in_engine_cs_fg_f(void) { - return 131; + return 0x8; } -static inline u32 ram_in_engine_cs_w(void) +static inline u32 ram_in_engine_wfi_mode_w(void) { return 132; } -static inline u32 ram_in_engine_cs_wfi_v(void) +static inline u32 ram_in_engine_wfi_mode_physical_v(void) { return 0x00000000; } -static inline u32 ram_in_engine_cs_wfi_f(void) +static inline u32 ram_in_engine_wfi_mode_physical_f(void) { return 0x0; } -static inline u32 ram_in_engine_cs_fg_v(void) +static inline u32 ram_in_engine_wfi_mode_virtual_v(void) { return 0x00000001; } -static inline u32 ram_in_engine_cs_fg_f(void) +static inline u32 ram_in_engine_wfi_mode_virtual_f(void) { - return 0x8; + return 0x4; } -static inline u32 ram_in_gr_cs_w(void) +static inline u32 ram_in_engine_wfi_target_w(void) { return 132; } -static inline u32 ram_in_gr_cs_wfi_f(void) +static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_nocoh_f(void) +{ + return 0x3; +} +static inline u32 ram_in_engine_wfi_target_local_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_target_local_mem_f(void) { return 0x0; } -static inline u32 ram_in_gr_wfi_target_w(void) +static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) { - return 132; + return (v & 0xfffff) << 12; } -static inline u32 ram_in_gr_wfi_mode_w(void) +static inline u32 ram_in_engine_wfi_ptr_lo_w(void) { return 132; } -static inline u32 ram_in_gr_wfi_mode_physical_v(void) +static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_engine_wfi_ptr_hi_w(void) +{ + return 133; +} +static inline u32 ram_in_engine_wfi_veid_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ram_in_engine_wfi_veid_w(void) +{ + return 134; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) +{ + return 136; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) +{ + return 137; +} +static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) +{ + return (v & 0x3) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) { return 0x00000000; } -static inline u32 ram_in_gr_wfi_mode_physical_f(void) +static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) { - return 0x0; + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) +{ + return 0x00000002; } -static inline u32 ram_in_gr_wfi_mode_virtual_v(void) +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) +{ + return (v & 0x1) << (2 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) { return 0x00000001; } -static inline u32 ram_in_gr_wfi_mode_virtual_f(void) +static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) { - return 0x4; + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) +{ + return (v & 0x1) << (4 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) +{ + return (v & 0x1) << (5 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) +{ + return (v & 0x1) << (10 + i*0); +} +static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) +{ + return (v & 0x1) << (11 + i*0); +} +static inline u32 ram_in_sc_big_page_size__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_big_page_size_64kb_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) +{ + return (v & 0xfffff) << (12 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) +{ + return (v & 0xffffffff) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_sc_page_dir_base_target_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) +{ + return 168; } -static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_big_page_size_0_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_sc_big_page_size_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) { return (v & 0xfffff) << 12; } -static inline u32 ram_in_gr_wfi_ptr_lo_w(void) +static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) { - return 132; + return 168; } -static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) +static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffffffff) << 0; } -static inline u32 ram_in_gr_wfi_ptr_hi_w(void) +static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) { - return 133; + return 169; } static inline u32 ram_in_base_shift_v(void) { @@ -378,6 +554,10 @@ static inline u32 ram_fc_runlist_timeslice_w(void) { return 62; } +static inline u32 ram_fc_set_channel_info_w(void) +{ + return 63; +} static inline u32 ram_userd_base_shift_v(void) { return 0x00000009; @@ -550,10 +730,6 @@ static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) { return (v & 0xfff) << 0; } -static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) -{ - return 0x0000000c; -} static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) { return 0x00000008; @@ -562,4 +738,8 @@ static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) { return 0x00000008; } +static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} #endif -- cgit v1.2.2 From 507081b2eae666f9c3e713fd7d9d97fdc8b6c56f Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 28 Sep 2016 16:55:36 -0700 Subject: gpu: nvgpu: gv11b: kernel hw header update Kernel hardware headers updtae related to ctxsw, ramfc and pbdma. JIRA GV11B-21 Change-Id: I99588b420a814068eaf894e999a8ad8e6234e26c Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1228760 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h | 96 +++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 4 ++ drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 80 +++++++++++++++------- drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 32 +++++++++ 4 files changed, 184 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h index 57a6b28d..4ca83ea4 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h @@ -58,6 +58,42 @@ static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) { return 0x00000008; } +static inline u32 ctxsw_prog_main_image_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) +{ + return 0x00000011; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) +{ + return 0x00000012; +} +static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) +{ + return 0x00000021; +} static inline u32 ctxsw_prog_main_image_patch_count_o(void) { return 0x00000010; @@ -142,6 +178,62 @@ static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) { return 0x000000f8; } +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) +{ + return 0x00000060; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) +{ + return 0x00000064; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) +{ + return 0x00000068; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) +{ + return 0x00000070; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) +{ + return 0x00000074; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) +{ + return 0x00000078; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) +{ + return 0x0000007c; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} static inline u32 ctxsw_prog_main_image_magic_value_o(void) { return 0x000000fc; @@ -270,10 +362,6 @@ static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp { return 0x1; } -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068; -} static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) { return 0x00000084; diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index e8394215..c58ee6ba 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -3230,6 +3230,10 @@ static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) { return 0x0041bfb0 + i*4; } +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) +{ + return 0x00000005; +} static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) { return (v & 0xff) << 0; diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h index 38d63487..be8089d8 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h @@ -130,22 +130,6 @@ static inline u32 pbdma_put_hi_r(u32 i) { return 0x00040060 + i*8192; } -static inline u32 pbdma_formats_r(u32 i) -{ - return 0x0004009c + i*8192; -} -static inline u32 pbdma_formats_gp_fermi0_f(void) -{ - return 0x0; -} -static inline u32 pbdma_formats_pb_fermi1_f(void) -{ - return 0x100; -} -static inline u32 pbdma_formats_mp_fermi0_f(void) -{ - return 0x0; -} static inline u32 pbdma_pb_header_r(u32 i) { return 0x00040084 + i*8192; @@ -242,14 +226,6 @@ static inline u32 pbdma_data0_r(u32 i) { return 0x000400c4 + i*8192; } -static inline u32 pbdma_target_r(u32 i) -{ - return 0x000400ac + i*8192; -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1f; -} static inline u32 pbdma_acquire_r(u32 i) { return 0x00040030 + i*8192; @@ -574,6 +550,62 @@ static inline u32 pbdma_runlist_timeslice_enable_true_f(void) { return 0x10000000; } +static inline u32 pbdma_target_r(u32 i) +{ + return 0x000400ac + i*8192; +} +static inline u32 pbdma_target_engine_sw_f(void) +{ + return 0x1f; +} +static inline u32 pbdma_target_eng_ctx_valid_true_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_target_eng_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_ce_ctx_valid_true_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_target_ce_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) +{ + return 0x1000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) +{ + return 0x3000000; +} +static inline u32 pbdma_target_should_send_tsg_event_true_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_target_should_send_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) +{ + return 0x0; +} static inline u32 pbdma_set_channel_info_r(u32 i) { return 0x000400fc + i*8192; diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index 7c89db4d..868e4ad9 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -90,6 +90,38 @@ static inline u32 ram_in_page_dir_base_vol_false_f(void) { return 0x0; } +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) +{ + return 0x10; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) +{ + return 0x20; +} static inline u32 ram_in_big_page_size_f(u32 v) { return (v & 0x1) << 11; -- cgit v1.2.2 From 1a36091fb9e31578c2e01c60cbe0a9b01b64bc9e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Sat, 24 Sep 2016 11:20:37 -0700 Subject: gpu: nvgpu: gv11b: sysmem userd support For gv11b, userd is allocated from sysmem. Updated gp_get and gp_put functions to read or write from sysmem instead of bar1 memory. In gv11b, after updating gp_put, it is required to notify pending work to host through channel doorbell. JIRA GV11B-1 Change-Id: Iebc52e6ccfc8b9ca0c57b227190e0ce1161076f1 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1226613 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 47 ++++++++++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 8 ++++++ 2 files changed, 53 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 35b36ec5..c6e0f0a2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -12,17 +12,17 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ - #include #include - #include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" #include "gp10b/fifo_gp10b.h" #include "hw_pbdma_gv11b.h" #include "fifo_gv11b.h" #include "hw_fifo_gv11b.h" #include "hw_ram_gv11b.h" #include "hw_ccsr_gv11b.h" +#include "hw_usermode_gv11b.h" static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { @@ -82,10 +82,53 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) runlist[0], runlist[1], runlist[2], runlist[3]); } +static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) +{ + gk20a_dbg_info("channel ring door bell %d\n", c->hw_chid); + + gk20a_writel(c->g, usermode_notify_channel_pending_r(), + usermode_notify_channel_pending_id_f(c->hw_chid)); +} + +static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) +{ + struct mem_desc *userd_mem = &g->fifo.userd; + u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + + return gk20a_mem_rd32(g, userd_mem, + offset + ram_userd_gp_get_w()); + +} + +static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) +{ + struct mem_desc *userd_mem = &g->fifo.userd; + u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + + gk20a_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), + c->gpfifo.put); + /* commit everything to cpu */ + smp_mb(); + + gv11b_ring_channel_doorbell(c); + +} + + +static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) +{ + return ccsr_channel__size_1_v(); +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); + /* for gv11b no need to do any thing special for fifo hw setup */ + gops->fifo.init_fifo_setup_hw = NULL; gops->fifo.runlist_entry_size = ram_rl_entry_size_v; gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry; gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry; + gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos; + gops->fifo.userd_gp_get = gv11b_userd_gp_get; + gops->fifo.userd_gp_put = gv11b_userd_gp_put; } diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 0ac18a91..54df6745 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -18,8 +18,16 @@ #include "gk20a/gk20a.h" #include "gp10b/mm_gp10b.h" #include "mm_gv11b.h" +#include "hw_fb_gv11b.h" + +bool gv11b_mm_is_bar1_supported(struct gk20a *g) +{ + return false; +} void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); + gops->mm.bar1_bind = NULL; + gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; } -- cgit v1.2.2 From 6f29d0d8cd81f3b964fff975b917569b865b26d3 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 7 Sep 2016 10:22:28 -0700 Subject: gpu: nvgpu: gv11b: setup rop mappings JIRA GV11B-21 Change-Id: I7695936bdac4502ceb0bdad4fc029e249eb2f05d Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1224783 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 61 +++++++++++++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 02044df6..3488a03a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -22,13 +22,13 @@ #include "gk20a/dbg_gpu_gk20a.h" #include "gm20b/gr_gm20b.h" -#include "gp10b/gr_gp10b.h" #include "gv11b/gr_gv11b.h" #include "hw_gr_gv11b.h" #include "hw_fifo_gv11b.h" #include "hw_proj_gv11b.h" #include "hw_ctxsw_prog_gv11b.h" #include "hw_mc_gv11b.h" +#include "hw_gr_gv11b.h" #include static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) @@ -1507,6 +1507,64 @@ static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) return hww_warp_esr; } +int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) +{ + u32 map; + u32 i, j, mapregs; + u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); + u32 num_tpc_per_gpc = nvgpu_get_litter_value(g, + GPU_LIT_NUM_TPC_PER_GPC); + + gk20a_dbg_fn(""); + + if (!gr->map_tiles) + return -1; + + gk20a_writel(g, gr_crstr_map_table_cfg_r(), + gr_crstr_map_table_cfg_row_offset_f(gr->map_row_offset) | + gr_crstr_map_table_cfg_num_entries_f(gr->tpc_count)); + + /* 6 tpc can be stored in one map register */ + mapregs = (num_gpcs * num_tpc_per_gpc + 5) / 6; + + for (i = 0, j = 0; i < mapregs; i++, j = j + 6) { + map = gr_crstr_gpc_map_tile0_f(gr->map_tiles[j]) | + gr_crstr_gpc_map_tile1_f(gr->map_tiles[j + 1]) | + gr_crstr_gpc_map_tile2_f(gr->map_tiles[j + 2]) | + gr_crstr_gpc_map_tile3_f(gr->map_tiles[j + 3]) | + gr_crstr_gpc_map_tile4_f(gr->map_tiles[j + 4]) | + gr_crstr_gpc_map_tile5_f(gr->map_tiles[j + 5]); + + gk20a_writel(g, gr_crstr_gpc_map_r(i), map); + gk20a_writel(g, gr_ppcs_wwdx_map_gpc_map_r(i), map); + gk20a_writel(g, gr_rstr2d_gpc_map_r(i), map); + } + + gk20a_writel(g, gr_ppcs_wwdx_map_table_cfg_r(), + gr_ppcs_wwdx_map_table_cfg_row_offset_f(gr->map_row_offset) | + gr_ppcs_wwdx_map_table_cfg_num_entries_f(gr->tpc_count)); + + for (i = 0, j = 1; i < gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(); + i++, j = j + 4) { + gk20a_writel(g, gr_ppcs_wwdx_map_table_cfg_coeff_r(i), + gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f( + ((1 << j) % gr->tpc_count)) | + gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f( + ((1 << (j + 1)) % gr->tpc_count)) | + gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f( + ((1 << (j + 2)) % gr->tpc_count)) | + gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f( + ((1 << (j + 3)) % gr->tpc_count))); + } + + gk20a_writel(g, gr_rstr2d_map_table_cfg_r(), + gr_rstr2d_map_table_cfg_row_offset_f(gr->map_row_offset) | + gr_rstr2d_map_table_cfg_num_entries_f(gr->tpc_count)); + + return 0; +} + + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -1543,4 +1601,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception; gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error; + gops->gr.setup_rop_mapping = gr_gv11b_setup_rop_mapping; } -- cgit v1.2.2 From 0b05d33d8af2dc602ffc78de4c16432b083ec80f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 24 Aug 2016 09:18:14 -0700 Subject: gpu: nvgpu: gv11b : add mm and tsg init Bug 1735760 Change-Id: I6b33b38ed555759a57ad170e7f75839df51da228 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1207273 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 33b0d955..af87636a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -132,11 +132,12 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_fb(gops); gv11b_init_fifo(gops); gv11b_init_ce(gops); - gv11b_init_mm(gops); gv11b_init_gr_ctx(gops); + gv11b_init_mm(gops); gv11b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); gv11b_init_therm_ops(gops); + gk20a_init_tsg_ops(gops); gops->name = "gv11b"; gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; gops->get_litter_value = gv11b_get_litter_value; -- cgit v1.2.2 From 20d4f2052a25053c716201e708b4caddda1c9a16 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 4 Oct 2016 15:24:46 -0700 Subject: gpu: nvgpu: gv11b: program sw veid bundles Program hw state with relevant sw veid bundles. JIRA GV11B-11 Change-Id: I2c5e02016ed41db9c9b7f85cc0b401abaa003d37 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1231598 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 58 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 ++ 2 files changed, 61 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 3488a03a..d8b251c6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1565,6 +1565,63 @@ int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) } +static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) +{ + struct av_list_gk20a *sw_veid_bundle_init = + &g->gr.ctx_vars.sw_veid_bundle_init; + u32 j; + u32 num_subctx = nvgpu_get_litter_value(g, GPU_LIT_NUM_SUBCTX); + u32 err = 0; + unsigned long end_jiffies = jiffies + + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); + + for (j = 0; j < num_subctx; j++) { + + gk20a_writel(g, gr_pipe_bundle_address_r(), + sw_veid_bundle_init->l[index].addr | + gr_pipe_bundle_address_veid_f(j)); + + err = gr_gk20a_wait_fe_idle(g, end_jiffies, + GR_IDLE_CHECK_DEFAULT); + } +} + +static int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) +{ + struct av_list_gk20a *sw_veid_bundle_init = + &g->gr.ctx_vars.sw_veid_bundle_init; + u32 i; + u32 last_bundle_data = 0; + u32 err = 0; + unsigned long end_jiffies = jiffies + + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); + + gk20a_dbg_fn(""); + for (i = 0; i < sw_veid_bundle_init->count; i++) { + + if (i == 0 || last_bundle_data != + sw_veid_bundle_init->l[i].value) { + gk20a_writel(g, gr_pipe_bundle_data_r(), + sw_veid_bundle_init->l[i].value); + last_bundle_data = sw_veid_bundle_init->l[i].value; + } + + if (gr_pipe_bundle_address_value_v( + sw_veid_bundle_init->l[i].addr) == GR_GO_IDLE_BUNDLE) { + gk20a_writel(g, gr_pipe_bundle_address_r(), + sw_veid_bundle_init->l[i].addr); + err |= gr_gk20a_wait_idle(g, end_jiffies, + GR_IDLE_CHECK_DEFAULT); + } else + gv11b_write_bundle_veid_state(g, i); + + if (err) + break; + } + gk20a_dbg_fn("done"); + return err; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -1602,4 +1659,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gr_gv11b_pre_process_sm_exception; gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error; gops->gr.setup_rop_mapping = gr_gv11b_setup_rop_mapping; + gops->gr.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 11f5fb47..5f13aa5c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -25,6 +25,9 @@ enum { VOLTA_DMA_COPY_A = 0xC3B5, }; +/* use magic number 99 for subctx litter value */ +#define GPU_LIT_NUM_SUBCTX 99 + void gv11b_init_gr(struct gpu_ops *ops); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct mem_desc *mem); -- cgit v1.2.2 From 37f317a3c4033b54ab4bf47286fb9ebd48edb021 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 15 Sep 2016 14:43:55 -0700 Subject: gpu: nvgpu: gv11b: zcull programming Bug 1735760 Change-Id: Id801efb613b5740389bde5dc2cfff47232d0a0f3 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1221582 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 32 ++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 5 +++-- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index d8b251c6..78ffd3d4 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1622,6 +1622,37 @@ static int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) return err; } +void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, + u32 *zcull_map_tiles) +{ + u32 val, i, j; + + gk20a_dbg_fn(""); + + for (i = 0, j = 0; i < (zcull_num_entries / 8); i++, j += 8) { + val = + gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f( + zcull_map_tiles[j+0]) | + gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f( + zcull_map_tiles[j+1]) | + gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f( + zcull_map_tiles[j+2]) | + gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f( + zcull_map_tiles[j+3]) | + gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f( + zcull_map_tiles[j+4]) | + gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f( + zcull_map_tiles[j+5]) | + gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f( + zcull_map_tiles[j+6]) | + gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f( + zcull_map_tiles[j+7]); + + gk20a_writel(g, gr_gpcs_zcull_sm_in_gpc_number_map_r(i), val); + } +} + + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -1660,4 +1691,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error; gops->gr.setup_rop_mapping = gr_gv11b_setup_rop_mapping; gops->gr.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle; + gops->gr.program_zcull_mapping = gr_gv11b_program_zcull_mapping; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 5f13aa5c..df03cd8a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -31,6 +31,7 @@ enum { void gv11b_init_gr(struct gpu_ops *ops); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct mem_desc *mem); - - +/*zcull*/ +void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, + u32 *zcull_map_tiles); #endif -- cgit v1.2.2 From 8b34e4c6a8c2e8d162833e943f67ff072b0b7ecb Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 13 Oct 2016 15:17:01 -0700 Subject: gpu: nvgpu: gv11b: header update for CL#37320141 Hardware header updates for CL#37320141 JIRA GV11B-27 JIRA GV11B-7 JIRA GV11B-8 JIRA GV11B-9 Change-Id: I54d467f42d4074d1d9ae912f6d46ab2e323f69bc Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1236263 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 2 +- drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 96 +++++---------------------------- drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h | 20 +++++++ drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h | 4 ++ drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 16 +++--- 5 files changed, 47 insertions(+), 91 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h index 8c324225..f5e146c4 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h @@ -1182,7 +1182,7 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) { return 0x000000ec; } -static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void) +static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) { return 0x000000cd; } diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index c58ee6ba..a5e93058 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -2676,7 +2676,7 @@ static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) } static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) { - return 0x00500100; + return 0x00418100; } static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) { @@ -2688,7 +2688,19 @@ static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) } static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) { - return 0x0050014c; + return 0x0041814c; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) +{ + return 0x0041815c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) +{ + return 0x00418198; } static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) { @@ -3114,14 +3126,6 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f { return 0x4; } -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) -{ - return 0x00504224; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) -{ - return 0x1; -} static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) { return 0x00504730; @@ -3294,78 +3298,6 @@ static inline u32 gr_zcull_subregion_qty_v(void) { return 0x00000010; } -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00504308; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x0050430c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x00504318; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00504320; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00504324; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00504328; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0050432c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x0050431c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00504378; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x0050437c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00504380; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x00504384; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00504388; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x0050438c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00504390; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x00504394; -} -static inline u32 gr_pri_gpc0_tpc0_sm0_dsm_perf_counter_status_s1_r(void) -{ - return 0x00504744; -} -static inline u32 gr_pri_gpc0_tpc0_sm0_dsm_perf_counter_status1_r(void) -{ - return 0x00504750; -} static inline u32 gr_fe_pwr_mode_r(void) { return 0x00404170; diff --git a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h index 4c10852e..6968c699 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h @@ -246,6 +246,26 @@ static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) { return (r >> 0) & 0xffffffff; } +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) +{ + return 0x0017e204; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) +{ + return 8; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xff; +} static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) { return 0x0017e2b0; diff --git a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h index 7fe4d158..98bec43a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h @@ -78,6 +78,10 @@ static inline u32 mc_intr_pfifo_pending_f(void) { return 0x100; } +static inline u32 mc_intr_hub_pending_f(void) +{ + return 0x200; +} static inline u32 mc_intr_pgraph_pending_f(void) { return 0x1000; diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index 868e4ad9..46772ff4 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -498,19 +498,23 @@ static inline u32 ram_fc_acquire_w(void) { return 12; } -static inline u32 ram_fc_semaphorea_w(void) +static inline u32 ram_fc_sem_addr_hi_w(void) { return 14; } -static inline u32 ram_fc_semaphoreb_w(void) +static inline u32 ram_fc_sem_addr_lo_w(void) { return 15; } -static inline u32 ram_fc_semaphorec_w(void) +static inline u32 ram_fc_sem_payload_lo_w(void) { return 16; } -static inline u32 ram_fc_semaphored_w(void) +static inline u32 ram_fc_sem_payload_hi_w(void) +{ + return 39; +} +static inline u32 ram_fc_sem_execute_w(void) { return 17; } @@ -554,10 +558,6 @@ static inline u32 ram_fc_subdevice_w(void) { return 37; } -static inline u32 ram_fc_formats_w(void) -{ - return 39; -} static inline u32 ram_fc_allowed_syncpoints_w(void) { return 58; -- cgit v1.2.2 From ac5383e76e2a2629d4bb1573ed080b89f1e2040f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 13 Oct 2016 15:48:44 -0700 Subject: gpu: nvgpu: gv11b: remove tex exception update for CL#37320141 JIRA GV11B-27 Change-Id: I095af59ac419b44b3a1e3abc489857d6f533874a Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1236274 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 78ffd3d4..89be2563 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -83,22 +83,7 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event) { - int ret = 0; - u32 offset = proj_gpc_stride_v() * gpc + - proj_tpc_in_gpc_stride_v() * tpc; - u32 esr; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); - - esr = gk20a_readl(g, - gr_gpc0_tpc0_tex_m_hww_esr_r() + offset); - gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr); - - gk20a_writel(g, - gr_gpc0_tpc0_tex_m_hww_esr_r() + offset, - esr); - - return ret; + return 0; } static int gr_gv11b_commit_global_cb_manager(struct gk20a *g, -- cgit v1.2.2 From 2de62a6083075451318c2ef6b5323f50bf5ebc3f Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 14 Oct 2016 05:05:16 -0700 Subject: gpu: nvgpu: gv11b: fix sparse warning Fix following sparse warning my making funtion as static: $TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/mm_gv11b.c:23:6: warning: symbol 'gv11b_mm_is_bar1_supported' was not declared. Should it be static? Bug 200088648 Change-Id: I4af7ed1ae112813887a14a11b8fcea0b72c90e39 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1236689 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 54df6745..80ac21e6 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -20,7 +20,7 @@ #include "mm_gv11b.h" #include "hw_fb_gv11b.h" -bool gv11b_mm_is_bar1_supported(struct gk20a *g) +static bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; } -- cgit v1.2.2 From 742156225248816acba9955b14fc43fc9fe737bc Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 14 Oct 2016 13:37:41 -0700 Subject: gpu: nvgpu: gv11b: enable gpc exceptions Add function ptr and function for enabling gpc exceptions. Disable Tex exceptions. JIRA GV11B-28 JIRA GV11B-27 Change-Id: Ife8fe22c24da00ae14f68fd977d84d208831eb45 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1236899 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 89be2563..d8b79bac 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -80,6 +80,20 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, return ret; } +static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + u32 tpc_mask; + + gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), + gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); + + tpc_mask = + gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); + + gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), tpc_mask); +} + static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event) { @@ -1670,6 +1684,7 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.get_access_map = gr_gv11b_get_access_map; gops->gr.handle_sm_exception = gr_gv11b_handle_sm_exception; gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; + gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; gops->gr.mask_hww_warp_esr = gv11b_mask_hww_warp_esr; gops->gr.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception; -- cgit v1.2.2 From e5b96a827301a4ebdff45425722281de9d500d01 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 17 Oct 2016 16:38:21 -0700 Subject: gpu: nvgpu: gv11b: update sm arch info Use updated register offset for gr_gpc0_tpc0_sm_arch_r() to read and update correct sm arch info. JIRA GV11B-21 Change-Id: I34af2d4a7665d7848bd74bc56a92ff2c861ceac9 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1237916 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index d8b79bac..4274a800 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1651,11 +1651,24 @@ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, } } +static void gr_gv11b_detect_sm_arch(struct gk20a *g) +{ + u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r()); + + g->gpu_characteristics.sm_arch_spa_version = + gr_gpc0_tpc0_sm_arch_spa_version_v(v); + g->gpu_characteristics.sm_arch_sm_version = + gr_gpc0_tpc0_sm_arch_sm_version_v(v); + g->gpu_characteristics.sm_arch_warp_count = + gr_gpc0_tpc0_sm_arch_warp_count_v(v); + +} void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); gops->gr.init_fs_state = gr_gv11b_init_fs_state; + gops->gr.detect_sm_arch = gr_gv11b_detect_sm_arch; gops->gr.is_valid_class = gr_gv11b_is_valid_class; gops->gr.commit_global_cb_manager = gr_gv11b_commit_global_cb_manager; gops->gr.commit_global_pagepool = gr_gv11b_commit_global_pagepool; -- cgit v1.2.2 From da1695ae5c1319e19afe8e7890b51de67ec8c052 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 13 Jul 2016 18:29:17 -0700 Subject: gpu: nvgpu: gv11b: avoid host1x device dependency gpu is completely out from host1x block and no need to create device nodes under host1x. Bug 1735760 Change-Id: I2df861b07b38ce6931a86a928184ad164095948a Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1181063 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index d9754a81..1f36e59c 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -46,25 +46,7 @@ static int gv11b_tegra_get_clocks(struct device *dev) static int gv11b_tegra_probe(struct device *dev) { struct gk20a_platform *platform = dev_get_drvdata(dev); - struct device_node *np = dev->of_node; - struct device_node *host1x_node; - struct platform_device *host1x_pdev; - const __be32 *host1x_ptr; - - host1x_ptr = of_get_property(np, "nvidia,host1x", NULL); - if (!host1x_ptr) { - gk20a_err(dev, "host1x device not available"); - return -ENOSYS; - } - - host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr)); - host1x_pdev = of_find_device_by_node(host1x_node); - if (!host1x_pdev) { - gk20a_err(dev, "host1x device not available"); - return -ENOSYS; - } - - platform->g->host1x_dev = host1x_pdev; + platform->bypass_smmu = !device_is_iommuable(dev); platform->disable_bigpage = platform->bypass_smmu; -- cgit v1.2.2 From 35d2db64e28df6d65fed381c793f0954eed5eb7b Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 17 Oct 2016 10:39:18 -0700 Subject: gpu: nvgpu: gv11b: update gr cb callbacks Update gr cb callbacks with gv11b default sizes. Also updated sw method ids for volta. JIRA GV11B-11 Change-Id: I77cccedb7a017f378e2194cef98ea4b0bf7acd6b Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1237786 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 28 +++++++++++++++++++++------- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 5 +++++ 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 4274a800..94fd8058 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -364,7 +364,7 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, { gk20a_dbg_fn(""); - if (class_num == PASCAL_COMPUTE_A) { + if (class_num == VOLTA_COMPUTE_A) { switch (offset << 2) { case NVC0C0_SET_SHADER_EXCEPTIONS: gk20a_gr_set_shader_exceptions(g, data); @@ -374,18 +374,18 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, } } - if (class_num == PASCAL_A) { + if (class_num == VOLTA_A) { switch (offset << 2) { - case NVC097_SET_SHADER_EXCEPTIONS: + case NVC397_SET_SHADER_EXCEPTIONS: gk20a_gr_set_shader_exceptions(g, data); break; - case NVC097_SET_CIRCULAR_BUFFER_SIZE: + case NVC397_SET_CIRCULAR_BUFFER_SIZE: g->ops.gr.set_circular_buffer_size(g, data); break; - case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE: + case NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE: g->ops.gr.set_alpha_circular_buffer_size(g, data); break; - case NVC097_SET_GO_IDLE_TIMEOUT: + case NVC397_SET_GO_IDLE_TIMEOUT: gr_gv11b_set_go_idle_timeout(g, data); break; case NVC097_SET_COALESCE_BUFFER_SIZE: @@ -401,12 +401,25 @@ fail: return -EINVAL; } +static void gr_gv11b_bundle_cb_defaults(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + + gr->bundle_cb_default_size = + gr_scc_bundle_cb_size_div_256b__prod_v(); + gr->min_gpm_fifo_depth = + gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(); + gr->bundle_cb_token_limit = + gr_pd_ab_dist_cfg2_token_limit_init_v(); +} + static void gr_gv11b_cb_size_default(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; if (!gr->attrib_cb_default_size) - gr->attrib_cb_default_size = 0x800; + gr->attrib_cb_default_size = + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); gr->alpha_cb_default_size = gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); } @@ -1680,6 +1693,7 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb; gops->gr.commit_global_bundle_cb = gr_gv11b_commit_global_bundle_cb; gops->gr.handle_sw_method = gr_gv11b_handle_sw_method; + gops->gr.bundle_cb_defaults = gr_gv11b_bundle_cb_defaults; gops->gr.cb_size_default = gr_gv11b_cb_size_default; gops->gr.set_alpha_circular_buffer_size = gr_gv11b_set_alpha_circular_buffer_size; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index df03cd8a..fe5445d9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -28,6 +28,11 @@ enum { /* use magic number 99 for subctx litter value */ #define GPU_LIT_NUM_SUBCTX 99 +#define NVC397_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC397_SET_GO_IDLE_TIMEOUT 0x022c + void gv11b_init_gr(struct gpu_ops *ops); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct mem_desc *mem); -- cgit v1.2.2 From 2fd1ee0ca784e4235766601d6a7ef52ba1f0c519 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 17 Oct 2016 10:26:25 -0700 Subject: gpu: nvgpu: gv11b: update ramfc Updated ramfc: - To include channel veid info - Set valid context bit - Enabled userd writeback JIRA GV11B-11 Change-Id: I0e8c62fe0dee02071b0ca60f157151038ab5c09b Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1237764 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 86 ++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 28 +++++++++++ drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 8 +++ drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 30 ++++------- 4 files changed, 133 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index c6e0f0a2..0e1c1999 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -24,6 +24,9 @@ #include "hw_ccsr_gv11b.h" #include "hw_usermode_gv11b.h" +#define CHANNEL_INFO_VEID0 0 +#define PBDMA_SUBDEVICE_ID 1 + static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { @@ -82,6 +85,88 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) runlist[0], runlist[1], runlist[2], runlist[3]); } +static void gv11b_userd_writeback_config(struct gk20a *g) +{ + gk20a_writel(g, fifo_userd_writeback_r(), fifo_userd_writeback_timer_f( + fifo_userd_writeback_timer_100us_v())); + + +} + +static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, + u64 gpfifo_base, u32 gpfifo_entries, u32 flags) +{ + struct gk20a *g = c->g; + struct mem_desc *mem = &c->inst_block; + u32 data; + + gk20a_dbg_fn(""); + + gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v()); + + gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(), + pbdma_gp_base_offset_f( + u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); + + gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), + pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | + pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); + + gk20a_mem_wr32(g, mem, ram_fc_signature_w(), + c->g->ops.fifo.get_pbdma_signature(c->g)); + + gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(), + pbdma_pb_header_priv_user_f() | + pbdma_pb_header_method_zero_f() | + pbdma_pb_header_subchannel_zero_f() | + pbdma_pb_header_level_main_f() | + pbdma_pb_header_first_true_f() | + pbdma_pb_header_type_inc_f()); + + gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(), + pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) | + pbdma_subdevice_status_active_f() | + pbdma_subdevice_channel_dma_enable_f()); + + gk20a_mem_wr32(g, mem, ram_fc_target_w(), + pbdma_target_eng_ctx_valid_true_f() | + pbdma_target_engine_sw_f()); + + gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), + channel_gk20a_pbdma_acquire_val(c)); + + gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), + pbdma_runlist_timeslice_timeout_128_f() | + pbdma_runlist_timeslice_timescale_3_f() | + pbdma_runlist_timeslice_enable_true_f()); + + + gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + + /* Until full subcontext is supported, always use VEID0 */ + gk20a_mem_wr32(g, mem, ram_fc_set_channel_info_w(), + pbdma_set_channel_info_scg_type_graphics_compute0_f() | + pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); + + if (c->is_privileged_channel) { + /* Set privilege level for channel */ + gk20a_mem_wr32(g, mem, ram_fc_config_w(), + pbdma_config_auth_level_privileged_f()); + + gk20a_channel_setup_ramfc_for_privileged_channel(c); + } + + /* Enable userd writeback */ + data = gk20a_mem_rd32(g, mem, ram_fc_config_w()); + data = data | pbdma_config_userd_writeback_enable_f(); + gk20a_mem_wr32(g, mem, ram_fc_config_w(),data); + + gv11b_userd_writeback_config(g); + + return channel_gp10b_commit_userd(c); +} + + static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) { gk20a_dbg_info("channel ring door bell %d\n", c->hw_chid); @@ -131,4 +216,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos; gops->fifo.userd_gp_get = gv11b_userd_gp_get; gops->fifo.userd_gp_put = gv11b_userd_gp_put; + gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; } diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index 7e9e2743..8ea2e06a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h @@ -70,6 +70,34 @@ static inline u32 fifo_bar1_base_valid_true_f(void) { return 0x10000000; } +static inline u32 fifo_userd_writeback_r(void) +{ + return 0x0000225c; +} +static inline u32 fifo_userd_writeback_timer_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_userd_writeback_timer_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_userd_writeback_timer_shorter_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_userd_writeback_timer_100us_v(void) +{ + return 0x00000064; +} +static inline u32 fifo_userd_writeback_timescale_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 fifo_userd_writeback_timescale_0_v(void) +{ + return 0x00000000; +} static inline u32 fifo_runlist_base_r(void) { return 0x00002270; diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h index be8089d8..c4d3a631 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h @@ -342,6 +342,14 @@ static inline u32 pbdma_config_auth_level_privileged_f(void) { return 0x100; } +static inline u32 pbdma_config_userd_writeback_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_userd_writeback_enable_f(void) +{ + return 0x1000; +} static inline u32 pbdma_userd_hi_r(u32 i) { return 0x0004000c + i*8192; diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index 46772ff4..11874209 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -178,6 +178,10 @@ static inline u32 ram_in_engine_cs_fg_f(void) { return 0x8; } +static inline u32 ram_in_engine_wfi_mode_f(u32 v) +{ + return (v & 0x1) << 2; +} static inline u32 ram_in_engine_wfi_mode_w(void) { return 132; @@ -186,17 +190,13 @@ static inline u32 ram_in_engine_wfi_mode_physical_v(void) { return 0x00000000; } -static inline u32 ram_in_engine_wfi_mode_physical_f(void) -{ - return 0x0; -} static inline u32 ram_in_engine_wfi_mode_virtual_v(void) { return 0x00000001; } -static inline u32 ram_in_engine_wfi_mode_virtual_f(void) +static inline u32 ram_in_engine_wfi_target_f(u32 v) { - return 0x4; + return (v & 0x3) << 0; } static inline u32 ram_in_engine_wfi_target_w(void) { @@ -206,26 +206,14 @@ static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) { return 0x00000002; } -static inline u32 ram_in_engine_wfi_target_sys_mem_coh_f(void) -{ - return 0x2; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_nocoh_v(void) +static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) { return 0x00000003; } -static inline u32 ram_in_engine_wfi_target_sys_mem_nocoh_f(void) -{ - return 0x3; -} static inline u32 ram_in_engine_wfi_target_local_mem_v(void) { return 0x00000000; } -static inline u32 ram_in_engine_wfi_target_local_mem_f(void) -{ - return 0x0; -} static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) { return (v & 0xfffff) << 12; @@ -582,6 +570,10 @@ static inline u32 ram_fc_chid_id_w(void) { return 0; } +static inline u32 ram_fc_config_w(void) +{ + return 61; +} static inline u32 ram_fc_runlist_timeslice_w(void) { return 62; -- cgit v1.2.2 From f00a98154ecaddf849b283dd5b7cbda0f6c8f90f Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 19 Oct 2016 11:24:32 -0700 Subject: gpu: nvgpu: gv11b: enable correct interrupts Enable stall and non-stall interupts for gv11b. Support for replayable interrupts will be added later. Hub interrupts are not enabled and they will be enabled after non-replayabale fault handling is in place. JIRA GV11B-11 Change-Id: I99cc470dae9d02f92e9fb3cb49186dabfed78875 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1239337 Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index bc0aee2e..0111d6b3 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -20,7 +20,32 @@ #include "gv11b/mc_gv11b.h" #include "hw_mc_gv11b.h" +static void mc_gv11b_intr_enable(struct gk20a *g) +{ + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), + 0xffffffff); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = + mc_intr_pfifo_pending_f() + | eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffff); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = + mc_intr_pfifo_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f() + | eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); +} + void gv11b_init_mc(struct gpu_ops *gops) { gp10b_init_mc(gops); + gops->mc.intr_enable = mc_gv11b_intr_enable; } -- cgit v1.2.2 From 06bad79189543d5402baaa9ae6bb9d8319cd0908 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 11 Oct 2016 11:16:30 -0700 Subject: gpu: nvgpu: gv11b: bl compression updated mmu pte kind JIRA GV11B-8 Change-Id: I2baff42e077411a9c72b0d10739f4a45d4bd79a7 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1234567 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 53 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 097bc21d..fb31d6a8 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -22,7 +22,60 @@ #include "hw_gmmu_gv11b.h" +static void gv11b_init_uncompressed_kind_map(void) +{ + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms2_4cbra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms2_4cbra_v()] = + gmmu_pte_kind_generic_16bx2_v(); +} + +static bool gv11b_kind_supported(u8 k) +{ + return (k == gmmu_pte_kind_c32_ms2_4cbra_v() + || k == gmmu_pte_kind_c64_ms2_4cbra_v()); +} + +static bool gv11b_kind_z(u8 k) +{ + return (k == gmmu_pte_kind_c32_ms2_4cbra_v() + || k == gmmu_pte_kind_c64_ms2_4cbra_v()); +} + +static bool gv11b_kind_compressible(u8 k) +{ + + return (k == gmmu_pte_kind_c32_ms2_4cbra_v() + || k == gmmu_pte_kind_c64_ms2_4cbra_v()); +} + +static bool gv11b_kind_zbc(u8 k) +{ + + return (k == gmmu_pte_kind_c32_ms2_4cbra_v() + || k == gmmu_pte_kind_c64_ms2_4cbra_v()); +} + +static void gv11b_init_kind_attr(void) +{ + u16 k; + + for (k = 0; k < 256; k++) { + if (gv11b_kind_supported((u8)k)) + gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED; + if (gv11b_kind_compressible((u8)k)) + gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE; + if (gv11b_kind_z((u8)k)) + gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z; + if (gv11b_kind_zbc((u8)k)) + gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC; + } +} + void gv11b_init_fb(struct gpu_ops *gops) { gp10b_init_fb(gops); + + gv11b_init_uncompressed_kind_map(); + gv11b_init_kind_attr(); + } -- cgit v1.2.2 From 56fcce12e00187438529d44f2e70cd28df9288bc Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 27 Oct 2016 11:16:30 -0700 Subject: gpu: nvgpu: gv11b: pmu HAL update Update pmu HAL to have function for is_pmu_supported(). At this moment pmu support is disabled for gv11b. JIRA GV11B-21 Change-Id: I1790e6e4dc80e0761df78e6092da2b6ca0e39d64 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1243919 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: Alex Waterman Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 0b0144ce..62e42c31 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -21,7 +21,13 @@ #include "pmu_gv11b.h" #include "hw_pwr_gv11b.h" +static bool gv11b_is_pmu_supported(struct gk20a *g) +{ + return false; +} + void gv11b_init_pmu_ops(struct gpu_ops *gops) { gp10b_init_pmu_ops(gops); + gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; } -- cgit v1.2.2 From e38542cc1e7cf4eb22cfa4089600a787ece0e189 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 27 Oct 2016 12:29:46 -0700 Subject: gpu: nvgpu: gv11b: commit global timeslice Implement chip specific commit_global_timeslice function. JIRA GV11B-21 Change-Id: I4f852913cb181f62063084c4e118d97148f99056 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1243947 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 54 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 94fd8058..cc4bbb21 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1677,6 +1677,59 @@ static void gr_gv11b_detect_sm_arch(struct gk20a *g) } +static int gr_gv11b_commit_global_timeslice(struct gk20a *g, + struct channel_gk20a *c, bool patch) +{ + struct channel_ctx_gk20a *ch_ctx = NULL; + u32 pd_ab_dist_cfg0; + u32 ds_debug; + u32 mpc_vtg_debug; + u32 pe_vaf; + u32 pe_vsc_vpc; + + gk20a_dbg_fn(""); + + pd_ab_dist_cfg0 = gk20a_readl(g, gr_pd_ab_dist_cfg0_r()); + ds_debug = gk20a_readl(g, gr_ds_debug_r()); + mpc_vtg_debug = gk20a_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r()); + + if (patch) { + int err; + + ch_ctx = &c->ch_ctx; + err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); + if (err) + return err; + } + + pe_vaf = gk20a_readl(g, gr_gpcs_tpcs_pe_vaf_r()); + pe_vsc_vpc = gk20a_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); + + pe_vaf = gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f() | pe_vaf; + pe_vsc_vpc = gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f() | + pe_vsc_vpc; + pd_ab_dist_cfg0 = gr_pd_ab_dist_cfg0_timeslice_enable_en_f() | + pd_ab_dist_cfg0; + ds_debug = gr_ds_debug_timeslice_mode_enable_f() | ds_debug; + mpc_vtg_debug = gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f() | + mpc_vtg_debug; + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, + patch); + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pes_vsc_vpc_r(), + pe_vsc_vpc, patch); + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg0_r(), + pd_ab_dist_cfg0, patch); + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_debug_r(), ds_debug, patch); + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(), + mpc_vtg_debug, patch); + + if (patch) + gr_gk20a_ctx_patch_write_end(g, ch_ctx); + + return 0; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -1719,4 +1772,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.setup_rop_mapping = gr_gv11b_setup_rop_mapping; gops->gr.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle; gops->gr.program_zcull_mapping = gr_gv11b_program_zcull_mapping; + gops->gr.commit_global_timeslice = gr_gv11b_commit_global_timeslice; } -- cgit v1.2.2 From e1bcaa33abd46fd7e2b66ad09a02f7f30d6a0dfe Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 28 Oct 2016 17:11:21 -0700 Subject: gpu: nvgpu: gv11b: add dbg_session_ops JIRA GV11B-21 Change-Id: Ib9c099fb0f9cf910bd5abfc9fd6010803b52c9f8 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1244768 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index af87636a..a11d6a71 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -36,6 +36,7 @@ #include "gv11b/hw_proj_gv11b.h" #include "gm20b/gr_gm20b.h" +#include "gk20a/dbg_gpu_gk20a.h" static struct gpu_ops gv11b_ops; @@ -136,6 +137,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_mm(gops); gv11b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); + gk20a_init_dbg_session_ops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); gops->name = "gv11b"; -- cgit v1.2.2 From 2c23fd19ad62a58fc35ac4c08760915abc74dc63 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 26 Sep 2016 08:49:39 -0700 Subject: gpu: nvgpu: gv11b: smid programming gv11b specific smid table init, smid numbering and smid programing. JIRA GV11B-21 Change-Id: I3a0f8355f2cd90ab1518cd8a5642a0e84202bdf8 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1227096 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 92 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index cc4bbb21..e6050359 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1674,7 +1674,95 @@ static void gr_gv11b_detect_sm_arch(struct gk20a *g) gr_gpc0_tpc0_sm_arch_sm_version_v(v); g->gpu_characteristics.sm_arch_warp_count = gr_gpc0_tpc0_sm_arch_warp_count_v(v); +} + +static void gr_gv11b_init_sm_id_table(struct gk20a *g) +{ + u32 gpc, tpc; + u32 sm_id = 0; + + /* TODO populate smids based on power efficiency */ + for (tpc = 0; tpc < g->gr.max_tpc_per_gpc_count; tpc++) { + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + + if (tpc < g->gr.gpc_tpc_count[gpc]) { + g->gr.sm_to_cluster[sm_id].tpc_index = tpc; + g->gr.sm_to_cluster[sm_id].gpc_index = gpc; + g->gr.sm_to_cluster[sm_id].sm_index = sm_id % 2; + g->gr.sm_to_cluster[sm_id].global_tpc_index = + sm_id; + sm_id++; + } + } + } + g->gr.no_of_sm = sm_id; +} + +static void gr_gv11b_program_sm_id_numbering(struct gk20a *g, + u32 gpc, u32 tpc, u32 smid) +{ + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, + GPU_LIT_TPC_IN_GPC_STRIDE); + u32 gpc_offset = gpc_stride * gpc; + u32 tpc_offset = tpc_in_gpc_stride * tpc; + u32 global_tpc_index = g->gr.sm_to_cluster[smid].global_tpc_index; + + gk20a_writel(g, gr_gpc0_tpc0_sm_cfg_r() + gpc_offset + tpc_offset, + gr_gpc0_tpc0_sm_cfg_tpc_id_f(global_tpc_index)); + gk20a_writel(g, gr_gpc0_gpm_pd_sm_id_r(tpc) + gpc_offset, + gr_gpc0_gpm_pd_sm_id_id_f(global_tpc_index)); + gk20a_writel(g, gr_gpc0_tpc0_pe_cfg_smid_r() + gpc_offset + tpc_offset, + gr_gpc0_tpc0_pe_cfg_smid_value_f(global_tpc_index)); +} + +static int gr_gv11b_load_smid_config(struct gk20a *g) +{ + u32 *tpc_sm_id; + u32 i, j; + u32 tpc_index, gpc_index, tpc_id; + u32 sms_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); + int num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); + + tpc_sm_id = kcalloc(gr_cwd_sm_id__size_1_v(), sizeof(u32), GFP_KERNEL); + if (!tpc_sm_id) + return -ENOMEM; + /* Each NV_PGRAPH_PRI_CWD_GPC_TPC_ID can store 4 TPCs.*/ + for (i = 0; i <= ((g->gr.tpc_count-1) / 4); i++) { + u32 reg = 0; + u32 bit_stride = gr_cwd_gpc_tpc_id_gpc0_s() + + gr_cwd_gpc_tpc_id_tpc0_s(); + + for (j = 0; j < 4; j++) { + u32 sm_id; + u32 bits; + + tpc_id = (i << 2) + j; + sm_id = tpc_id * sms_per_tpc; + + if (sm_id >= g->gr.no_of_sm) + break; + + gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index; + tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index; + + bits = gr_cwd_gpc_tpc_id_gpc0_f(gpc_index) | + gr_cwd_gpc_tpc_id_tpc0_f(tpc_index); + reg |= bits << (j * bit_stride); + + tpc_sm_id[gpc_index + (num_gpcs * ((tpc_index & 4) + >> 2))] |= tpc_id << tpc_index * bit_stride; + } + gk20a_writel(g, gr_cwd_gpc_tpc_id_r(i), reg); + } + + for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++) + gk20a_writel(g, gr_cwd_sm_id_r(i), tpc_sm_id[i]); + + kfree(tpc_sm_id); + + return 0; } static int gr_gv11b_commit_global_timeslice(struct gk20a *g, @@ -1773,4 +1861,8 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle; gops->gr.program_zcull_mapping = gr_gv11b_program_zcull_mapping; gops->gr.commit_global_timeslice = gr_gv11b_commit_global_timeslice; + gops->gr.init_sm_id_table = gr_gv11b_init_sm_id_table; + gops->gr.load_smid_config = gr_gv11b_load_smid_config; + gops->gr.program_sm_id_numbering = + gr_gv11b_program_sm_id_numbering; } -- cgit v1.2.2 From df91b07944196556c7245c4e05f8de737f47ff1d Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 2 Nov 2016 10:22:45 -0700 Subject: gpu: nvgpu: gv11b: hw headers for mmu fault JIRA GV11B-7 Change-Id: I9d1a530c668cc3b9e27a6efb4761f68916e85b43 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1246513 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Alex Waterman Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h | 64 ++ drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | 940 ++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 4 +- drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | 4 + 4 files changed, 1010 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h index 4ca83ea4..228bf5f2 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h @@ -250,6 +250,70 @@ static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) { return (r >> 0) & 0xffff; } +static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) +{ + return 0x000000b8; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) +{ + return 0x000000bc; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) +{ + return 0x000000c0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) +{ + return 0x000000c4; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) +{ + return 0x000000c8; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) +{ + return 0x000000cc; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) +{ + return 0x000000e0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) +{ + return 0x000000e4; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} static inline u32 ctxsw_prog_local_image_ppc_info_o(void) { return 0x000000f4; diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h index 9e4bab8b..781dc0c1 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h @@ -466,4 +466,944 @@ static inline u32 fb_niso_flush_sysmem_addr_r(void) { return 0x00100c10; } +static inline u32 fb_niso_intr_r(void) +{ + return 0x00100a20; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_r(u32 i) +{ + return 0x00100a24 + i*4; +} +static inline u32 fb_niso_intr_en__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_set_r(u32 i) +{ + return 0x00100a2c + i*4; +} +static inline u32 fb_niso_intr_en_set__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_r(u32 i) +{ + return 0x00100a34 + i*4; +} +static inline u32 fb_niso_intr_en_clr__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) +{ + return 0x00000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) +{ + return 0x00100e24 + i*20; +} +static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) +{ + return (r >> 1) & 0x3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x6; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) +{ + return 0x00100e28 + i*20; +} +static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_buffer_get_r(u32 i) +{ + return 0x00100e2c + i*20; +} +static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_yes_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_put_r(u32 i) +{ + return 0x00100e30 + i*20; +} +static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_size_r(u32 i) +{ + return 0x00100e34 + i*20; +} +static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) +{ + return 0x20000000; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_addr_lo_r(void) +{ + return 0x00100e4c; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_addr_hi_r(void) +{ + return 0x00100e50; +} +static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_inst_lo_r(void) +{ + return 0x00100e54; +} +static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) +{ + return (r >> 10) & 0x3; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_inst_hi_r(void) +{ + return 0x00100e58; +} +static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_info_r(void) +{ + return 0x00100e5c; +} +static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 fb_mmu_fault_info_client_v(u32 r) +{ + return (r >> 8) & 0x7f; +} +static inline u32 fb_mmu_fault_info_access_type_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 fb_mmu_fault_info_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_info_info_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_status_r(void) +{ + return 0x00100e60; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_replayable_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fb_mmu_fault_status_replayable_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 fb_mmu_fault_status_non_replayable_v(u32 r) +{ + return (r >> 9) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 fb_mmu_fault_status_replayable_error_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_v(u32 r) +{ + return (r >> 13) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_v(u32 r) +{ + return (r >> 14) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 15; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fb_mmu_fault_status_busy_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_status_busy_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_status_busy_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_busy_true_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_status_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_status_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_status_valid_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_set_f(void) +{ + return 0x80000000; +} #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index a5e93058..99da5f73 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -522,9 +522,9 @@ static inline u32 gr_pipe_bundle_address_veid_f(u32 v) { return (v & 0x3f) << 20; } -static inline u32 gr_pipe_bundle_address_veid_v(u32 r) +static inline u32 gr_pipe_bundle_address_veid_w(void) { - return (r >> 20) & 0x3f; + return 0; } static inline u32 gr_pipe_bundle_data_r(void) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h index f57e0263..2022f87e 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h @@ -146,6 +146,10 @@ static inline u32 proj_scal_litter_num_zcull_banks_v(void) { return 0x00000004; } +static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) +{ + return 0x00000002; +} static inline u32 proj_scal_max_gpcs_v(void) { return 0x00000020; -- cgit v1.2.2 From a42d3072fba8085d6d86f9c5ce5352d0684745e7 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 7 Nov 2016 09:33:04 -0800 Subject: gpu: nvgpu: gv11b: hw headers for mmu fault JIRA GV11B-7 Change-Id: Ib50c4266a1a9d05b98bf4cbef663b534289055ed Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1249156 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | 74 ++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h index 781dc0c1..0dc52fa0 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h @@ -1110,7 +1110,7 @@ static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) { return (r >> 30) & 0x1; } -static inline u32 fb_mmu_fault_info_info_valid_v(u32 r) +static inline u32 fb_mmu_fault_info_valid_v(u32 r) { return (r >> 31) & 0x1; } @@ -1318,6 +1318,14 @@ static inline u32 fb_mmu_fault_status_replayable_v(u32 r) { return (r >> 8) & 0x1; } +static inline u32 fb_mmu_fault_status_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_set_f(void) +{ + return 0x100; +} static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) { return (v & 0x1) << 9; @@ -1326,6 +1334,14 @@ static inline u32 fb_mmu_fault_status_non_replayable_v(u32 r) { return (r >> 9) & 0x1; } +static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) +{ + return 0x200; +} static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) { return (v & 0x1) << 10; @@ -1334,6 +1350,14 @@ static inline u32 fb_mmu_fault_status_replayable_error_v(u32 r) { return (r >> 10) & 0x1; } +static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) +{ + return 0x400; +} static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) { return (v & 0x1) << 11; @@ -1342,6 +1366,14 @@ static inline u32 fb_mmu_fault_status_non_replayable_error_v(u32 r) { return (r >> 11) & 0x1; } +static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) +{ + return 0x800; +} static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) { return (v & 0x1) << 12; @@ -1350,6 +1382,14 @@ static inline u32 fb_mmu_fault_status_replayable_overflow_v(u32 r) { return (r >> 12) & 0x1; } +static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) +{ + return 0x1000; +} static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) { return (v & 0x1) << 13; @@ -1358,6 +1398,14 @@ static inline u32 fb_mmu_fault_status_non_replayable_overflow_v(u32 r) { return (r >> 13) & 0x1; } +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) +{ + return 0x2000; +} static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) { return (v & 0x1) << 14; @@ -1366,6 +1414,14 @@ static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_v(u32 r) { return (r >> 14) & 0x1; } +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) +{ + return 0x4000; +} static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_f(u32 v) { return (v & 0x1) << 15; @@ -1374,6 +1430,14 @@ static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_v(u32 r) { return (r >> 15) & 0x1; } +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) +{ + return 0x8000; +} static inline u32 fb_mmu_fault_status_busy_f(u32 v) { return (v & 0x1) << 30; @@ -1406,4 +1470,12 @@ static inline u32 fb_mmu_fault_status_valid_set_f(void) { return 0x80000000; } +static inline u32 fb_mmu_fault_status_valid_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_clear_f(void) +{ + return 0x80000000; +} #endif -- cgit v1.2.2 From 68ff0c8f309e79266682f96994cf83c921061f77 Mon Sep 17 00:00:00 2001 From: Shardar Shariff Md Date: Tue, 1 Nov 2016 19:13:34 +0530 Subject: gpu: nvgpu: gv11b: use fuse control read/write APIs for K4.4 Use fuse control read/write APIs when accessing fuse control registers for Kernel version 4.4 Bug 200243956 Change-Id: I3d78ec2733b5f56615fa0b588664570c85557e63 Signed-off-by: Shardar Shariff Md Reviewed-on: http://git-master/r/1245826 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index e6050359..ca5e8dc0 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -16,6 +16,7 @@ #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ #include #include +#include #include "gk20a/gr_gk20a.h" #include "gk20a/semaphore_gk20a.h" @@ -1135,8 +1136,13 @@ static void gr_gv11b_init_cyclestats(struct gk20a *g) static void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0); +#else + tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); + tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); +#endif if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) tegra_fuse_writel(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); -- cgit v1.2.2 From 7b67abb2edb606b9ad0d0ecf0d94a333770974b1 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 16 Nov 2016 09:33:43 -0800 Subject: gpu: nvgpu: gv11b: support for new littler values Add support for new litter values: GPU_LIT_NUM_SUBCTX GPU_LIT_NUM_SM_PER_TPC Also updated get_litter_value api to use int instead of enum type. JIRA GV11B-21 Change-Id: Ide06245d03743e2d757d27d045701beb25b6707b Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1254857 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 11 ++++++++--- include/linux/tegra_gpu_t19x.h | 24 ++++++++++++++++++++++++ 3 files changed, 33 insertions(+), 3 deletions(-) create mode 100644 include/linux/tegra_gpu_t19x.h diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index ca5e8dc0..f60337e2 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -31,6 +31,7 @@ #include "hw_mc_gv11b.h" #include "hw_gr_gv11b.h" #include +#include static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) { diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a11d6a71..3124f540 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -17,7 +17,7 @@ #include #include - +#include #include "gk20a/gk20a.h" #include "gv11b/hal_gv11b.h" @@ -40,8 +40,7 @@ static struct gpu_ops gv11b_ops; -static int gv11b_get_litter_value(struct gk20a *g, - enum nvgpu_litter_value value) +static int gv11b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; switch (value) { @@ -57,6 +56,9 @@ static int gv11b_get_litter_value(struct gk20a *g, case GPU_LIT_NUM_TPC_PER_GPC: ret = proj_scal_litter_num_tpc_per_gpc_v(); break; + case GPU_LIT_NUM_SM_PER_TPC: + ret = proj_scal_litter_num_sm_per_tpc_v(); + break; case GPU_LIT_NUM_FBPS: ret = proj_scal_litter_num_fbps_v(); break; @@ -108,6 +110,9 @@ static int gv11b_get_litter_value(struct gk20a *g, case GPU_LIT_FBPA_STRIDE: ret = proj_fbpa_stride_v(); break; + case GPU_LIT_NUM_SUBCTX: + ret = proj_litter_num_subctx_v(); + break; default: break; } diff --git a/include/linux/tegra_gpu_t19x.h b/include/linux/tegra_gpu_t19x.h new file mode 100644 index 00000000..f6157c12 --- /dev/null +++ b/include/linux/tegra_gpu_t19x.h @@ -0,0 +1,24 @@ +/* + * Tegra GPU Virtualization Interfaces to Server + * + * Copyright (c) 2016, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __TEGRA_GPU_T19X_H +#define __TEGRA_GPU_T19X_H + +#define GPU_LIT_NUM_SUBCTX 99 + +#endif -- cgit v1.2.2 From 1eb564a27946305e164269a4f6e2005aa797f7e5 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 16 Nov 2016 10:43:29 -0800 Subject: gpu: nvgpu: gv11b: chip specific init_inst_block Remove va limits for inst block in gv11b. JIRA GV11B-21 Change-Id: I5338e2d64b3bbebeb5e309d63db3e8360ae05723 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1254880 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 80ac21e6..ff4e3b06 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -25,9 +25,25 @@ static bool gv11b_mm_is_bar1_supported(struct gk20a *g) return false; } +static void gv11b_init_inst_block(struct mem_desc *inst_block, + struct vm_gk20a *vm, u32 big_page_size) +{ + struct gk20a *g = gk20a_from_vm(vm); + + gk20a_dbg_info("inst block phys = 0x%llx, kv = 0x%p", + gk20a_mm_inst_block_addr(g, inst_block), inst_block->cpu_va); + + g->ops.mm.init_pdb(g, inst_block, vm); + + if (big_page_size && g->ops.mm.set_big_page_size) + g->ops.mm.set_big_page_size(g, inst_block, big_page_size); +} + + void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); gops->mm.bar1_bind = NULL; gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; + gops->mm.init_inst_block = gv11b_init_inst_block; } -- cgit v1.2.2 From 4bac40b5b3a89054f53b2a608841d84d4262a8a7 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 16 Nov 2016 11:44:40 -0800 Subject: gpu: nvgpu: gv11b: set ce context valid Set copy engine context valid for channel loaded on pbdma. JIRA GV11B-21 Change-Id: I74445dcefe38b52723705c185e6a37c9f56ac2bf Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1254916 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 0e1c1999..bc413a9e 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -130,6 +130,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, gk20a_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_eng_ctx_valid_true_f() | + pbdma_target_ce_ctx_valid_true_f() | pbdma_target_engine_sw_f()); gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), -- cgit v1.2.2 From 331762a7e78924296dacb4c1465e67679d4b57f7 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 22 Nov 2016 10:31:42 -0800 Subject: gpu: nvgpu: gv11b: implement mm_setup_hw Reuse gk20a_mm_setup_hw for gv11b. JIRA GV11B-21 Change-Id: I5141dbb8088799a8bd5df55469bc371b63497e96 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1254939 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index ff4e3b06..7f104a6d 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -46,4 +46,5 @@ void gv11b_init_mm(struct gpu_ops *gops) gops->mm.bar1_bind = NULL; gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; + gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; } -- cgit v1.2.2 From 903df9b59705f7ebbb66fb2912c1419a0c992368 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 29 Nov 2016 16:14:19 -0800 Subject: gpu: nvgpu: gv11b: fix sparse warning Fix following sparse warning by making function as static: $TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/gr_gv11b.c:1529:5: warning: symbol 'gr_gv11b_setup_rop_mapping' was not declared. Should it be static? Bug 200088648 Change-Id: Idd388170f35e7e6cd7559d8aab8968f7e8e545c6 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1261891 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index f60337e2..7f5b8d3f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1526,7 +1526,7 @@ static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) return hww_warp_esr; } -int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) +static int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) { u32 map; u32 i, j, mapregs; -- cgit v1.2.2 From 26199ffdf5bb5cf1d5a810c63904cc950314fe7b Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 1 Dec 2016 15:12:29 -0800 Subject: gpu: nvgpu: gv11b: hw header update for CL37510769 Change-Id: Ie25197e9bc08088ff837677d72fa8c28828f0bf4 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1263414 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 6 +++--- drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index 99da5f73..02bb120b 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -2240,11 +2240,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { - return 0x00000800; + return 0x00000400; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) { - return 0x00001100; + return 0x00000d00; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { @@ -2288,7 +2288,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) { - return 0x00000800; + return 0x00000400; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) { diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h index 2022f87e..4e30447c 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h @@ -128,7 +128,7 @@ static inline u32 proj_scal_litter_num_fbps_v(void) } static inline u32 proj_scal_litter_num_fbpas_v(void) { - return 0x00000002; + return 0x00000001; } static inline u32 proj_scal_litter_num_gpcs_v(void) { -- cgit v1.2.2 From 67b54c3c76cfa488e1d102e5c74a32b3aaba9287 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 16 Nov 2016 12:25:08 -0800 Subject: gpu: nvgpu: legacy support with subcontext gv11b needs atleast one subcontext to submit work. To support legacy in gv11b, currently main context is always copied into subcontext0 (veid0) during channel commit instance. As part of channel commit instance, veid0 for that channel is created and relevant pdb and context info copied to vedi0. JIRA GV11B-21 Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1231169 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 3 +- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 12 +++ drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 42 +++++++++- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 147 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/subctx_gv11b.h | 27 ++++++ 5 files changed, 228 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv11b/subctx_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/subctx_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 4ea56d8e..c059e464 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -13,6 +13,7 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/ce_gv11b.o \ $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \ $(nvgpu-t19x)/gv11b/pmu_gv11b.o \ - $(nvgpu-t19x)/gv11b/therm_gv11b.o + $(nvgpu-t19x)/gv11b/therm_gv11b.o \ + $(nvgpu-t19x)/gv11b/subctx_gv11b.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index bc413a9e..b9276e09 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -19,6 +19,8 @@ #include "gp10b/fifo_gp10b.h" #include "hw_pbdma_gv11b.h" #include "fifo_gv11b.h" +#include "subctx_gv11b.h" +#include "gr_gv11b.h" #include "hw_fifo_gv11b.h" #include "hw_ram_gv11b.h" #include "hw_ccsr_gv11b.h" @@ -200,6 +202,15 @@ static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) } +static void channel_gv11b_unbind(struct channel_gk20a *ch) +{ + gk20a_dbg_fn(""); + + gv11b_free_subctx_header(ch); + + channel_gk20a_unbind(ch); + +} static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) { @@ -218,4 +229,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.userd_gp_get = gv11b_userd_gp_get; gops->fifo.userd_gp_put = gv11b_userd_gp_put; gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; + gops->fifo.unbind_channel = channel_gv11b_unbind; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 7f5b8d3f..bdb96329 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -13,6 +13,7 @@ * more details. */ +#include #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ #include #include @@ -24,12 +25,16 @@ #include "gm20b/gr_gm20b.h" #include "gv11b/gr_gv11b.h" +#include "gv11b/mm_gv11b.h" +#include "gv11b/subctx_gv11b.h" #include "hw_gr_gv11b.h" #include "hw_fifo_gv11b.h" #include "hw_proj_gv11b.h" #include "hw_ctxsw_prog_gv11b.h" #include "hw_mc_gv11b.h" #include "hw_gr_gv11b.h" +#include "hw_ram_gv11b.h" +#include "hw_pbdma_gv11b.h" #include #include @@ -1583,7 +1588,6 @@ static int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) return 0; } - static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) { struct av_list_gk20a *sw_veid_bundle_init = @@ -1766,12 +1770,43 @@ static int gr_gv11b_load_smid_config(struct gk20a *g) for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++) gk20a_writel(g, gr_cwd_sm_id_r(i), tpc_sm_id[i]); - kfree(tpc_sm_id); return 0; } +static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) +{ + u32 addr_lo; + u32 addr_hi; + struct ctx_header_desc *ctx; + + gk20a_dbg_fn(""); + + gv11b_alloc_subctx_header(c); + + gv11b_update_subctx_header(c, gpu_va); + + ctx = &c->ch_ctx.ctx_header; + addr_lo = u64_lo32(ctx->mem.gpu_va) >> ram_in_base_shift_v(); + addr_hi = u64_hi32(ctx->mem.gpu_va); + + /* point this address to engine_wfi_ptr */ + gk20a_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(), + ram_in_engine_cs_wfi_v() | + ram_in_engine_wfi_target_f( + ram_in_engine_wfi_target_sys_mem_ncoh_v()) | + ram_in_engine_wfi_mode_f(ram_in_engine_wfi_mode_virtual_v()) | + ram_in_engine_wfi_ptr_lo_f(addr_lo)); + + gk20a_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_ptr_hi_w(), + ram_in_engine_wfi_ptr_hi_f(addr_hi)); + + return 0; +} + + + static int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c, bool patch) { @@ -1828,6 +1863,7 @@ static int gr_gv11b_commit_global_timeslice(struct gk20a *g, void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); + gops->gr.init_preemption_state = NULL; gops->gr.init_fs_state = gr_gv11b_init_fs_state; gops->gr.detect_sm_arch = gr_gv11b_detect_sm_arch; gops->gr.is_valid_class = gr_gv11b_is_valid_class; @@ -1872,4 +1908,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.load_smid_config = gr_gv11b_load_smid_config; gops->gr.program_sm_id_numbering = gr_gv11b_program_sm_id_numbering; + gops->gr.commit_inst = gr_gv11b_commit_inst; + } diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c new file mode 100644 index 00000000..3acc53f6 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -0,0 +1,147 @@ +/* + * Volta GPU series Subcontext + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. + */ + +#include "gk20a/gk20a.h" +#include "gk20a/semaphore_gk20a.h" +#include "gv11b/subctx_gv11b.h" +#include "gv11b/hw_ram_gv11b.h" +#include "gv11b/hw_ctxsw_prog_gv11b.h" + +static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, + struct mem_desc *inst_block); + +void gv11b_free_subctx_header(struct channel_gk20a *c) +{ + struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; + struct gk20a *g = c->g; + + gk20a_dbg_fn(""); + + if (ctx->mem.gpu_va) { + gk20a_gmmu_unmap(c->vm, ctx->mem.gpu_va, + ctx->mem.size, gk20a_mem_flag_none); + + gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, &ctx->mem); + } +} + +int gv11b_alloc_subctx_header(struct channel_gk20a *c) +{ + struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; + struct gk20a *g = c->g; + int ret = 0; + + gk20a_dbg_fn(""); + + if (ctx->mem.gpu_va == 0) { + ret = gk20a_gmmu_alloc_attr_sys(g, + DMA_ATTR_NO_KERNEL_MAPPING, + ctxsw_prog_fecs_header_v(), + &ctx->mem); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "failed to allocate sub ctx header"); + return ret; + } + ctx->mem.gpu_va = gk20a_gmmu_map(c->vm, + &ctx->mem.sgt, + ctx->mem.size, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + gk20a_mem_flag_none, true, + ctx->mem.aperture); + if (!ctx->mem.gpu_va) { + gk20a_err(dev_from_gk20a(g), + "failed to map ctx header"); + gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, + &ctx->mem); + return -ENOMEM; + } + /* Now clear the buffer */ + if (gk20a_mem_begin(g, &ctx->mem)) + return -ENOMEM; + + gk20a_memset(g, &ctx->mem, 0, 0, ctx->mem.size); + gk20a_mem_end(g, &ctx->mem); + + gv11b_init_subcontext_pdb(c, &c->inst_block); + + } + return ret; +} + +static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, + struct mem_desc *inst_block) +{ + struct gk20a *g = c->g; + struct vm_gk20a *vm; + u64 pdb_addr, pdb_addr_lo, pdb_addr_hi; + u32 format_word; + u32 lo, hi; + + gk20a_dbg_fn(""); + /* load main pdb as veid0 pdb also */ + vm = c->vm; + pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.sgt->sgl, 0); + pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); + pdb_addr_hi = u64_hi32(pdb_addr); + format_word = ram_in_sc_page_dir_base_target_f( + ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | + ram_in_sc_page_dir_base_vol_f( + ram_in_sc_page_dir_base_vol_true_v(), 0) | + ram_in_sc_page_dir_base_fault_replay_tex_f(0, 0) | + ram_in_sc_page_dir_base_fault_replay_gcc_f(0, 0) | + ram_in_sc_use_ver2_pt_format_f(1, 0) | + ram_in_sc_big_page_size_f(1, 0) | + ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); + lo = ram_in_sc_page_dir_base_vol_0_w(); + hi = ram_in_sc_page_dir_base_hi_0_w(); + gk20a_mem_wr32(g, inst_block, lo, format_word); + gk20a_mem_wr32(g, inst_block, hi, pdb_addr_hi); + + /* make subcontext0 address space to valid */ + /* TODO fix proper hw register definations */ + gk20a_mem_wr32(g, inst_block, 166, 0x1); + gk20a_mem_wr32(g, inst_block, 167, 0); + gk20a_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), + ram_in_engine_wfi_veid_f(0)); + +} + +int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) +{ + struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; + struct mem_desc *gr_mem; + struct gk20a *g = c->g; + int ret = 0; + u32 addr_lo, addr_hi; + + addr_lo = u64_lo32(gpu_va); + addr_hi = u64_hi32(gpu_va); + + gr_mem = &ctx->mem; + g->ops.mm.l2_flush(g, true); + if (gk20a_mem_begin(g, gr_mem)) + return -ENOMEM; + + gk20a_mem_wr(g, gr_mem, + ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi); + gk20a_mem_wr(g, gr_mem, + ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo); + gk20a_mem_end(g, gr_mem); + return ret; +} diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h new file mode 100644 index 00000000..357cd254 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h @@ -0,0 +1,27 @@ +/* + * + * Volta GPU series Subcontext + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. + */ +#ifndef __SUBCONTEXT_GV11B_H__ +#define __SUBCONTEXT_GV11B_H__ + +int gv11b_alloc_subctx_header(struct channel_gk20a *c); + +void gv11b_free_subctx_header(struct channel_gk20a *c); + +int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va); +#endif /* __SUBCONTEXT_GV11B_H__ */ -- cgit v1.2.2 From 35969806d2c763d4a5662ba6a9233a63aa00352d Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 2 Dec 2016 10:45:09 -0800 Subject: gpu: nvgpu: gv11b: add clock gating prod settings JIRA GV11B-15 Change-Id: I38d8cbda33f9c4e8b44ca227cd5ea5fef346bfbd Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1266705 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 648 +++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h | 93 ++++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 54 +++ 4 files changed, 796 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c create mode 100644 drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index c059e464..4f7b5422 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -5,6 +5,7 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/mc_gv11b.o \ $(nvgpu-t19x)/gv11b/ltc_gv11b.o \ $(nvgpu-t19x)/gv11b/hal_gv11b.o \ + $(nvgpu-t19x)/gv11b/gv11b_gating_reglist.o \ $(nvgpu-t19x)/gv11b/gr_gv11b.o \ $(nvgpu-t19x)/gv11b/fecs_trace_gv11b.o \ $(nvgpu-t19x)/gv11b/fb_gv11b.o \ diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c new file mode 100644 index 00000000..9bd40eff --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c @@ -0,0 +1,648 @@ +/* + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * This file is autogenerated. Do not edit. + */ + +#ifndef __gv11b_gating_reglist_h__ +#define __gv11b_gating_reglist_h__ + +#include +#include "gv11b_gating_reglist.h" + +struct gating_desc { + u32 addr; + u32 prod; + u32 disable; +}; +/* slcg bus */ +static const struct gating_desc gv11b_slcg_bus[] = { + {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, +}; + +/* slcg ce2 */ +static const struct gating_desc gv11b_slcg_ce2[] = { + {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, +}; + +/* slcg chiplet */ +static const struct gating_desc gv11b_slcg_chiplet[] = { + {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, +}; + +/* slcg fb */ +static const struct gating_desc gv11b_slcg_fb[] = { + {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x001facb4, .prod = 0x00000000, .disable = 0x000001fe}, +}; + +/* slcg fifo */ +static const struct gating_desc gv11b_slcg_fifo[] = { + {.addr = 0x000026ec, .prod = 0x00000000, .disable = 0x0001fffe}, +}; + +/* slcg gr */ +static const struct gating_desc gv11b_slcg_gr[] = { + {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, + {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, + {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, + {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002}, + {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, + {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, + {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, + {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, + {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, + {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, + {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, + {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, + {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, + {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, + {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, + {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, + {.addr = 0x00419c84, .prod = 0x0003fffe, .disable = 0x0003fffe}, + {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, + {.addr = 0x00419c94, .prod = 0x00007ffe, .disable = 0x00007ffe}, + {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, + {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, + {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, + {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, + {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000000ff}, +}; + +/* slcg ltc */ +static const struct gating_desc gv11b_slcg_ltc[] = { + {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, +}; + +/* slcg perf */ +static const struct gating_desc gv11b_slcg_perf[] = { + {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00248018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00246018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x00244018, .prod = 0xffffffff, .disable = 0x00000000}, + {.addr = 0x0024a124, .prod = 0x00000001, .disable = 0x00000000}, +}; + +/* slcg PriRing */ +static const struct gating_desc gv11b_slcg_priring[] = { + {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, +}; + +/* slcg pwr_csb */ +static const struct gating_desc gv11b_slcg_pwr_csb[] = { + {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, + {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* slcg pmu */ +static const struct gating_desc gv11b_slcg_pmu[] = { + {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* therm gr */ +static const struct gating_desc gv11b_slcg_therm[] = { + {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* slcg Xbar */ +static const struct gating_desc gv11b_slcg_xbar[] = { + {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, + {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, + {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, +}; + +/* blcg bus */ +static const struct gating_desc gv11b_blcg_bus[] = { + {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* blcg ce */ +static const struct gating_desc gv11b_blcg_ce[] = { + {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg ctxsw prog */ +static const struct gating_desc gv11b_blcg_ctxsw_prog[] = { +}; + +/* blcg fb */ +static const struct gating_desc gv11b_blcg_fb[] = { + {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x001facb0, .prod = 0x00004242, .disable = 0x00000000}, +}; + +/* blcg fifo */ +static const struct gating_desc gv11b_blcg_fifo[] = { + {.addr = 0x000026e0, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg gr */ +static const struct gating_desc gv11b_blcg_gr[] = { + {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, + {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, + {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, + {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, + {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, + {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00419c80, .prod = 0x00000003, .disable = 0x00000000}, + {.addr = 0x00419c88, .prod = 0x00000003, .disable = 0x00000000}, + {.addr = 0x00419c90, .prod = 0x00000003, .disable = 0x00000000}, + {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, + {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, + {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419a40, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a48, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a50, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a58, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a60, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a68, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a78, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a80, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg ltc */ +static const struct gating_desc gv11b_blcg_ltc[] = { + {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, +}; + +/* blcg pwr_csb */ +static const struct gating_desc gv11b_blcg_pwr_csb[] = { + {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg pmu */ +static const struct gating_desc gv11b_blcg_pmu[] = { + {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg Xbar */ +static const struct gating_desc gv11b_blcg_xbar[] = { + {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, + {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, + {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, + {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* pg gr */ +static const struct gating_desc gv11b_pg_gr[] = { +}; + +/* inline functions */ +void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_bus) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_bus[i].addr, + gv11b_slcg_bus[i].prod); + else + gk20a_writel(g, gv11b_slcg_bus[i].addr, + gv11b_slcg_bus[i].disable); + } +} + +void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_ce2) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_ce2[i].addr, + gv11b_slcg_ce2[i].prod); + else + gk20a_writel(g, gv11b_slcg_ce2[i].addr, + gv11b_slcg_ce2[i].disable); + } +} + +void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_chiplet) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_chiplet[i].addr, + gv11b_slcg_chiplet[i].prod); + else + gk20a_writel(g, gv11b_slcg_chiplet[i].addr, + gv11b_slcg_chiplet[i].disable); + } +} + +void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ +} + +void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_fb) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_fb[i].addr, + gv11b_slcg_fb[i].prod); + else + gk20a_writel(g, gv11b_slcg_fb[i].addr, + gv11b_slcg_fb[i].disable); + } +} + +void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_fifo) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_fifo[i].addr, + gv11b_slcg_fifo[i].prod); + else + gk20a_writel(g, gv11b_slcg_fifo[i].addr, + gv11b_slcg_fifo[i].disable); + } +} + +void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_gr) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_gr[i].addr, + gv11b_slcg_gr[i].prod); + else + gk20a_writel(g, gv11b_slcg_gr[i].addr, + gv11b_slcg_gr[i].disable); + } +} + +void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_ltc) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_ltc[i].addr, + gv11b_slcg_ltc[i].prod); + else + gk20a_writel(g, gv11b_slcg_ltc[i].addr, + gv11b_slcg_ltc[i].disable); + } +} + +void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_perf) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_perf[i].addr, + gv11b_slcg_perf[i].prod); + else + gk20a_writel(g, gv11b_slcg_perf[i].addr, + gv11b_slcg_perf[i].disable); + } +} + +void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_priring) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_priring[i].addr, + gv11b_slcg_priring[i].prod); + else + gk20a_writel(g, gv11b_slcg_priring[i].addr, + gv11b_slcg_priring[i].disable); + } +} + +void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_pwr_csb) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, + gv11b_slcg_pwr_csb[i].prod); + else + gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, + gv11b_slcg_pwr_csb[i].disable); + } +} + +void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_pmu) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_pmu[i].addr, + gv11b_slcg_pmu[i].prod); + else + gk20a_writel(g, gv11b_slcg_pmu[i].addr, + gv11b_slcg_pmu[i].disable); + } +} + +void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_therm) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_therm[i].addr, + gv11b_slcg_therm[i].prod); + else + gk20a_writel(g, gv11b_slcg_therm[i].addr, + gv11b_slcg_therm[i].disable); + } +} + +void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_slcg_xbar) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_slcg_xbar[i].addr, + gv11b_slcg_xbar[i].prod); + else + gk20a_writel(g, gv11b_slcg_xbar[i].addr, + gv11b_slcg_xbar[i].disable); + } +} + +void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_bus) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_bus[i].addr, + gv11b_blcg_bus[i].prod); + else + gk20a_writel(g, gv11b_blcg_bus[i].addr, + gv11b_blcg_bus[i].disable); + } +} + +void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_ce) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_ce[i].addr, + gv11b_blcg_ce[i].prod); + else + gk20a_writel(g, gv11b_blcg_ce[i].addr, + gv11b_blcg_ce[i].disable); + } +} + +void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_ctxsw_prog) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, + gv11b_blcg_ctxsw_prog[i].prod); + else + gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, + gv11b_blcg_ctxsw_prog[i].disable); + } +} + +void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_fb) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_fb[i].addr, + gv11b_blcg_fb[i].prod); + else + gk20a_writel(g, gv11b_blcg_fb[i].addr, + gv11b_blcg_fb[i].disable); + } +} + +void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_fifo) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_fifo[i].addr, + gv11b_blcg_fifo[i].prod); + else + gk20a_writel(g, gv11b_blcg_fifo[i].addr, + gv11b_blcg_fifo[i].disable); + } +} + +void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_gr) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_gr[i].addr, + gv11b_blcg_gr[i].prod); + else + gk20a_writel(g, gv11b_blcg_gr[i].addr, + gv11b_blcg_gr[i].disable); + } +} + +void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_ltc) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_ltc[i].addr, + gv11b_blcg_ltc[i].prod); + else + gk20a_writel(g, gv11b_blcg_ltc[i].addr, + gv11b_blcg_ltc[i].disable); + } +} + +void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_pwr_csb) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, + gv11b_blcg_pwr_csb[i].prod); + else + gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, + gv11b_blcg_pwr_csb[i].disable); + } +} + +void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_pmu) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_pmu[i].addr, + gv11b_blcg_pmu[i].prod); + else + gk20a_writel(g, gv11b_blcg_pmu[i].addr, + gv11b_blcg_pmu[i].disable); + } +} + +void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_blcg_xbar) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_blcg_xbar[i].addr, + gv11b_blcg_xbar[i].prod); + else + gk20a_writel(g, gv11b_blcg_xbar[i].addr, + gv11b_blcg_xbar[i].disable); + } +} + +void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gv11b_pg_gr) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gv11b_pg_gr[i].addr, + gv11b_pg_gr[i].prod); + else + gk20a_writel(g, gv11b_pg_gr[i].addr, + gv11b_pg_gr[i].disable); + } +} + +#endif /* __gv11b_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h new file mode 100644 index 00000000..ba91a2a7 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2016, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "gk20a/gk20a.h" + +void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, + bool prod); + diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 3124f540..ccaa570c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -34,12 +34,66 @@ #include "gv11b/fb_gv11b.h" #include "gv11b/fifo_gv11b.h" #include "gv11b/hw_proj_gv11b.h" +#include "gv11b/gv11b_gating_reglist.h" #include "gm20b/gr_gm20b.h" #include "gk20a/dbg_gpu_gk20a.h" static struct gpu_ops gv11b_ops; +static struct gpu_ops gv11b_ops = { + .clock_gating = { + .slcg_bus_load_gating_prod = + gv11b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gv11b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gv11b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gv11b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gv11b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gv11b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gv11b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gv11b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gv11b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gv11b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gv11b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gv11b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gv11b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gv11b_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gv11b_blcg_ce_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gv11b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gv11b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gv11b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gv11b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gv11b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gv11b_blcg_pwr_csb_load_gating_prod, + .blcg_pmu_load_gating_prod = + gv11b_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gv11b_blcg_xbar_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gv11b_pg_gr_load_gating_prod, + } +}; + static int gv11b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; -- cgit v1.2.2 From 609260d3d6c50045703ef3fea49ef414e6d58e82 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 28 Dec 2016 11:11:12 -0800 Subject: gpu: nvgpu: gv11b: hw header update for CL37750038 Change-Id: I7ca3d9968dc37b6514a08d3f49b6d2353e11671d Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1277786 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 124 -------------------------------- drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 6 +- 2 files changed, 3 insertions(+), 127 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index 8ea2e06a..d3e82e55 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h @@ -502,128 +502,4 @@ static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) { return 0x00000001; } -static inline u32 fifo_replay_fault_buffer_lo_r(void) -{ - return 0x00002a70; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_hi_r(void) -{ - return 0x00002a74; -} -static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_size_r(void) -{ - return 0x00002a78; -} -static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) -{ - return (v & 0x3ff) << 0; -} -static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) -{ - return 0x00000140; -} -static inline u32 fifo_replay_fault_buffer_get_r(void) -{ - return 0x00002a7c; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) -{ - return (v & 0x3ff) << 0; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_put_r(void) -{ - return 0x00002a80; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) -{ - return (v & 0x3ff) << 0; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_info_r(void) -{ - return 0x00002a84; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void) -{ - return 0x00000001; -} #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index 02bb120b..99da5f73 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -2240,11 +2240,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { - return 0x00000400; + return 0x00000800; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) { - return 0x00000d00; + return 0x00001100; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { @@ -2288,7 +2288,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) { - return 0x00000400; + return 0x00000800; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) { -- cgit v1.2.2 From ea1330f2ede5302301af95ff4af7ff49f87fd3e5 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Thu, 24 Nov 2016 09:46:13 +0530 Subject: nvgpu: gv11b: Add non secure PMU bootstrap(). pmu_bootstrap() does not support gv11b PMU non-secure boot. gv11b_pmu_bootstrap function is added with the updated/new args. JIRA GV11B-30 Change-Id: I42c1a7bd77d75c6e59ee4cc695cc879ce7cec095 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1259271 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 121 +++++++++++++++++++++++++++++++++++- 1 file changed, 120 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 62e42c31..e235e39b 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B PMU * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,19 +15,138 @@ #include /* for udelay */ #include +#include #include "gk20a/gk20a.h" #include "gp10b/pmu_gp10b.h" #include "pmu_gv11b.h" #include "hw_pwr_gv11b.h" +#define ALIGN_4KB 12 + static bool gv11b_is_pmu_supported(struct gk20a *g) { return false; } +static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu) +{ + struct gk20a *g = gk20a_from_pmu(pmu); + struct gk20a_platform *platform = dev_get_drvdata(g->dev); + struct mm_gk20a *mm = &g->mm; + struct pmu_ucode_desc *desc = pmu->desc; + u64 addr_code_lo, addr_data_lo, addr_load_lo; + u64 addr_code_hi, addr_data_hi, addr_load_hi; + u32 i, blocks, addr_args; + + gk20a_dbg_fn(""); + + gk20a_writel(g, pwr_falcon_itfen_r(), + gk20a_readl(g, pwr_falcon_itfen_r()) | + pwr_falcon_itfen_ctxen_enable_f()); + + gk20a_writel(g, pwr_pmu_new_instblk_r(), + pwr_pmu_new_instblk_ptr_f( + gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB) + | pwr_pmu_new_instblk_valid_f(1) + | pwr_pmu_new_instblk_target_sys_ncoh_f()); + + /* TBD: load all other surfaces */ + g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( + pmu, GK20A_PMU_TRACE_BUFSIZE); + g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); + g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( + pmu, GK20A_PMU_DMAIDX_VIRT); + + g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, + clk_get_rate(platform->clk[1])); + + addr_args = (pwr_falcon_hwcfg_dmem_size_v( + gk20a_readl(g, pwr_falcon_hwcfg_r())) + << GK20A_PMU_DMEM_BLKSIZE2) - + g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); + + pmu_copy_to_dmem(pmu, addr_args, + (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), + g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); + + gk20a_writel(g, pwr_falcon_dmemc_r(0), + pwr_falcon_dmemc_offs_f(0) | + pwr_falcon_dmemc_blk_f(0) | + pwr_falcon_dmemc_aincw_f(1)); + + addr_code_lo = u64_lo32((pmu->ucode.gpu_va + + desc->app_start_offset + + desc->app_resident_code_offset) >> 8); + + addr_code_hi = u64_hi32((pmu->ucode.gpu_va + + desc->app_start_offset + + desc->app_resident_code_offset) >> 8); + addr_data_lo = u64_lo32((pmu->ucode.gpu_va + + desc->app_start_offset + + desc->app_resident_data_offset) >> 8); + addr_data_hi = u64_hi32((pmu->ucode.gpu_va + + desc->app_start_offset + + desc->app_resident_data_offset) >> 8); + addr_load_lo = u64_lo32((pmu->ucode.gpu_va + + desc->bootloader_start_offset) >> 8); + addr_load_hi = u64_hi32((pmu->ucode.gpu_va + + desc->bootloader_start_offset) >> 8); + + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), GK20A_PMU_DMAIDX_UCODE); + gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_code_lo << 8); + gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_code_hi); + gk20a_writel(g, pwr_falcon_dmemd_r(0), desc->app_resident_code_offset); + gk20a_writel(g, pwr_falcon_dmemd_r(0), desc->app_resident_code_size); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); + gk20a_writel(g, pwr_falcon_dmemd_r(0), desc->app_imem_entry); + gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_data_lo << 8); + gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_data_hi); + gk20a_writel(g, pwr_falcon_dmemd_r(0), desc->app_resident_data_size); + gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x1); + gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_args); + + g->ops.pmu.write_dmatrfbase(g, + addr_load_lo - (desc->bootloader_imem_offset >> 8)); + + blocks = ((desc->bootloader_size + 0xFF) & ~0xFF) >> 8; + + for (i = 0; i < blocks; i++) { + gk20a_writel(g, pwr_falcon_dmatrfmoffs_r(), + desc->bootloader_imem_offset + (i << 8)); + gk20a_writel(g, pwr_falcon_dmatrffboffs_r(), + desc->bootloader_imem_offset + (i << 8)); + gk20a_writel(g, pwr_falcon_dmatrfcmd_r(), + pwr_falcon_dmatrfcmd_imem_f(1) | + pwr_falcon_dmatrfcmd_write_f(0) | + pwr_falcon_dmatrfcmd_size_f(6) | + pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE)); + } + + gk20a_writel(g, pwr_falcon_bootvec_r(), + pwr_falcon_bootvec_vec_f(desc->bootloader_entry_point)); + + gk20a_writel(g, pwr_falcon_cpuctl_r(), + pwr_falcon_cpuctl_startcpu_f(1)); + + gk20a_writel(g, pwr_falcon_os_r(), desc->app_version); + + return 0; +} + + void gv11b_init_pmu_ops(struct gpu_ops *gops) { gp10b_init_pmu_ops(gops); + gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; } -- cgit v1.2.2 From 209f4eadde89f8678221ab187763ac03b23543e7 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 29 Dec 2016 13:25:28 -0800 Subject: gpu: nvgpu: gv11b: hw header for CL 37750038 and mmu fault JIRA GV11B-7 Change-Id: I32428e6b91050ad3f697eb80e2aabda2cc1bfda4 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1249339 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h | 16 +++ drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | 4 + drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 12 ++ drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 200 ++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 6 +- 5 files changed, 233 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h index ed1e657c..618c4806 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h @@ -110,6 +110,22 @@ static inline u32 ccsr_channel_status_v(u32 r) { return (r >> 24) & 0xf; } +static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) +{ + return 0x400000; +} +static inline u32 ccsr_channel_eng_faulted_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 ccsr_channel_eng_faulted_reset_f(void) +{ + return 0x800000; +} static inline u32 ccsr_channel_busy_v(u32 r) { return (r >> 28) & 0x1; diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h index 0dc52fa0..d2f22afa 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h @@ -1062,6 +1062,10 @@ static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) { return 0x00000003; } +static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) { return (r >> 12) & 0xfffff; diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index d3e82e55..d68c823a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h @@ -502,4 +502,16 @@ static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) { return 0x00000001; } +static inline u32 fifo_cfg0_r(void) +{ + return 0x00002004; +} +static inline u32 fifo_cfg0_num_pbdma_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) +{ + return (r >> 16) & 0xff; +} #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h index f5e146c4..1c523f87 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h @@ -1274,4 +1274,204 @@ static inline u32 gmmu_pte_kind_s8_2s_v(void) { return 0x0000002b; } +static inline u32 gmmu_fault_buf_size_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r) +{ + return (r >> 8) & 0x3; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) +{ + return 0; +} +static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_inst_hi_w(void) +{ + return 1; +} +static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void) +{ + return 2; +} +static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) +{ + return 2; +} +static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_addr_hi_w(void) +{ + return 3; +} +static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void) +{ + return 4; +} +static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void) +{ + return 5; +} +static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 gmmu_fault_buf_entry_engine_id_w(void) +{ + return 6; +} +static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gmmu_fault_buf_entry_fault_type_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void) +{ + return 0x80; +} +static inline u32 gmmu_fault_buf_entry_client_v(u32 r) +{ + return (r >> 8) & 0x7f; +} +static inline u32 gmmu_fault_buf_entry_client_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 gmmu_fault_buf_entry_access_type_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 gmmu_fault_buf_entry_gpc_id_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void) +{ + return 0x20000000; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) +{ + return 0x40000000; +} +static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_valid_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_valid_true_f(void) +{ + return 0x80000000; +} #endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index 11874209..bcbb7b81 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -710,10 +710,6 @@ static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) { return (v & 0xffffffff) << 0; } -static inline u32 ram_rl_entry_tsg_vmid_f(u32 v) -{ - return (v & 0xff) << 4; -} static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) { return (v & 0xf) << 16; -- cgit v1.2.2 From 4ad2d3aebc4137d350efaff8072d60441572bcf2 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 13 Jan 2017 13:32:09 -0800 Subject: gpu: nvgpu: gv11b: support for multiple runlists Add support for multiple runlists in gv11b. Bug 1834201 Change-Id: I5a4cb92643626675314b4b61df330cde06e22c9f Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1285044 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b9276e09..4929f4d1 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B fifo * - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -230,4 +230,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.userd_gp_put = gv11b_userd_gp_put; gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; gops->fifo.unbind_channel = channel_gv11b_unbind; + gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; } -- cgit v1.2.2 From a674eeee419a68e27bec63e46200036f5f33c8ff Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 13 Jan 2017 14:24:36 -0800 Subject: gpu: nvgpu: gv11b: Support Stencil ZBC Pre-GP10X All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds). Clears for these kinds typically happen in two phases, depth phase and stencil phase. The depth clears can be compressed or ZBC-ed, whereas the stencil part is always uncompressed. Stencil ZBC in GP10X For GP10X both the depth and the stencil data for these packed kinds can be ZBC cleared. A given tile will be a cross product of the following states for depth and stencil. Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0, ZBC index 1 Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2 JIRA GV11B-9 Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1235520 Reviewed-by: Terje Bergstrom Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 190 ++++++++++++++++++++++-------------- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 12 ++- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 21 +++- 3 files changed, 147 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index bdb96329..4c23455d 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1,7 +1,7 @@ /* * GV11b GPU GR * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -223,96 +223,135 @@ static void gr_gv11b_commit_global_pagepool(struct gk20a *g, gr_gpcs_gcc_pagepool_total_pages_f(size), patch); } -static int gr_gv11b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *color_val, u32 index) +static int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_query_params *query_params) { + u32 index = query_params->index_size; + + if (index >= GK20A_ZBC_TABLE_SIZE) { + gk20a_err(dev_from_gk20a(g), + "invalid zbc stencil table index\n"); + return -EINVAL; + } + query_params->depth = gr->zbc_s_tbl[index].stencil; + query_params->format = gr->zbc_s_tbl[index].format; + query_params->ref_cnt = gr->zbc_s_tbl[index].ref_cnt; + + return 0; +} + +static bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *zbc_val, int *ret_val) +{ + struct zbc_s_table *s_tbl; u32 i; - u32 zbc_c; + bool added = false; + + *ret_val = -ENOMEM; + + /* search existing tables */ + for (i = 0; i < gr->max_used_s_index; i++) { + + s_tbl = &gr->zbc_s_tbl[i]; + + if (s_tbl->ref_cnt && + s_tbl->stencil == zbc_val->depth && + s_tbl->format == zbc_val->format) { + added = true; + s_tbl->ref_cnt++; + *ret_val = 0; + break; + } + } + /* add new table */ + if (!added && + gr->max_used_s_index < GK20A_ZBC_TABLE_SIZE) { + + s_tbl = &gr->zbc_s_tbl[gr->max_used_s_index]; + WARN_ON(s_tbl->ref_cnt != 0); + + *ret_val = g->ops.gr.add_zbc_s(g, gr, + zbc_val, gr->max_used_s_index); + + if (!(*ret_val)) + gr->max_used_s_index++; + } + return added; +} + +static int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *stencil_val, u32 index) +{ + u32 zbc_s; /* update l2 table */ - g->ops.ltc.set_zbc_color_entry(g, color_val, index); - - /* update ds table */ - gk20a_writel(g, gr_ds_zbc_color_r_r(), - gr_ds_zbc_color_r_val_f(color_val->color_ds[0])); - gk20a_writel(g, gr_ds_zbc_color_g_r(), - gr_ds_zbc_color_g_val_f(color_val->color_ds[1])); - gk20a_writel(g, gr_ds_zbc_color_b_r(), - gr_ds_zbc_color_b_val_f(color_val->color_ds[2])); - gk20a_writel(g, gr_ds_zbc_color_a_r(), - gr_ds_zbc_color_a_val_f(color_val->color_ds[3])); - - gk20a_writel(g, gr_ds_zbc_color_fmt_r(), - gr_ds_zbc_color_fmt_val_f(color_val->format)); - - gk20a_writel(g, gr_ds_zbc_tbl_index_r(), - gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE)); - - /* trigger the write */ - gk20a_writel(g, gr_ds_zbc_tbl_ld_r(), - gr_ds_zbc_tbl_ld_select_c_f() | - gr_ds_zbc_tbl_ld_action_write_f() | - gr_ds_zbc_tbl_ld_trigger_active_f()); + g->ops.ltc.set_zbc_s_entry(g, stencil_val, index); /* update local copy */ - for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { - gr->zbc_col_tbl[index].color_l2[i] = color_val->color_l2[i]; - gr->zbc_col_tbl[index].color_ds[i] = color_val->color_ds[i]; - } - gr->zbc_col_tbl[index].format = color_val->format; - gr->zbc_col_tbl[index].ref_cnt++; - - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), - color_val->color_ds[0]); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), - color_val->color_ds[1]); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), - color_val->color_ds[2]); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), - color_val->color_ds[3]); - zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3)); - zbc_c &= ~(0x7f << ((index % 4) * 7)); - zbc_c |= color_val->format << ((index % 4) * 7); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); + gr->zbc_s_tbl[index].stencil = stencil_val->depth; + gr->zbc_s_tbl[index].format = stencil_val->format; + gr->zbc_s_tbl[index].ref_cnt++; + + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_s_r(index), stencil_val->depth); + zbc_s = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() + + (index & ~3)); + zbc_s &= ~(0x7f << (index % 4) * 7); + zbc_s |= stencil_val->format << (index % 4) * 7; + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r() + + (index & ~3), zbc_s); return 0; } -static int gr_gv11b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *depth_val, u32 index) +static int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, + struct gr_gk20a *gr) { - u32 zbc_z; + struct zbc_entry zbc_val; + u32 err; - /* update l2 table */ - g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); + /* load default stencil table */ + zbc_val.type = GV11B_ZBC_TYPE_STENCIL; - /* update ds table */ - gk20a_writel(g, gr_ds_zbc_z_r(), - gr_ds_zbc_z_val_f(depth_val->depth)); + zbc_val.depth = 0x0; + zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8; + err = gr_gk20a_add_zbc(g, gr, &zbc_val); - gk20a_writel(g, gr_ds_zbc_z_fmt_r(), - gr_ds_zbc_z_fmt_val_f(depth_val->format)); + zbc_val.depth = 0x1; + zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8; + err |= gr_gk20a_add_zbc(g, gr, &zbc_val); - gk20a_writel(g, gr_ds_zbc_tbl_index_r(), - gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE)); + zbc_val.depth = 0xff; + zbc_val.format = ZBC_STENCIL_CLEAR_FMT_U8; + err |= gr_gk20a_add_zbc(g, gr, &zbc_val); - /* trigger the write */ - gk20a_writel(g, gr_ds_zbc_tbl_ld_r(), - gr_ds_zbc_tbl_ld_select_z_f() | - gr_ds_zbc_tbl_ld_action_write_f() | - gr_ds_zbc_tbl_ld_trigger_active_f()); + if (!err) { + gr->max_default_s_index = 3; + } else { + gk20a_err(dev_from_gk20a(g), + "fail to load default zbc stencil table\n"); + return err; + } - /* update local copy */ - gr->zbc_dep_tbl[index].depth = depth_val->depth; - gr->zbc_dep_tbl[index].format = depth_val->format; - gr->zbc_dep_tbl[index].ref_cnt++; + return 0; +} + +static int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr) +{ + int ret; + u32 i; + + for (i = 0; i < gr->max_used_s_index; i++) { + struct zbc_s_table *s_tbl = &gr->zbc_s_tbl[i]; + struct zbc_entry zbc_val; - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); - zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3)); - zbc_z &= ~(0x7f << (index % 4) * 7); - zbc_z |= depth_val->format << (index % 4) * 7; - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z); + zbc_val.type = GV11B_ZBC_TYPE_STENCIL; + zbc_val.depth = s_tbl->stencil; + zbc_val.format = s_tbl->format; + ret = g->ops.gr.add_zbc_s(g, gr, &zbc_val, i); + if (ret) + return ret; + } return 0; } @@ -1869,8 +1908,11 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.is_valid_class = gr_gv11b_is_valid_class; gops->gr.commit_global_cb_manager = gr_gv11b_commit_global_cb_manager; gops->gr.commit_global_pagepool = gr_gv11b_commit_global_pagepool; - gops->gr.add_zbc_color = gr_gv11b_add_zbc_color; - gops->gr.add_zbc_depth = gr_gv11b_add_zbc_depth; + gops->gr.add_zbc_s = gr_gv11b_add_zbc_stencil; + gops->gr.load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl; + gops->gr.load_zbc_s_tbl = gr_gv11b_load_stencil_tbl; + gops->gr.zbc_s_query_table = gr_gv11b_zbc_s_query_table; + gops->gr.add_zbc_type_s = gr_gv11b_add_zbc_type_s; gops->gr.pagepool_default_size = gr_gv11b_pagepool_default_size; gops->gr.calc_global_ctx_buffer_size = gr_gv11b_calc_global_ctx_buffer_size; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index fe5445d9..d31c92ca 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -1,7 +1,7 @@ /* * GV11B GPU GR * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,6 +16,16 @@ #ifndef _NVGPU_GR_GV11B_H_ #define _NVGPU_GR_GV11B_H_ +#define GV11B_ZBC_TYPE_STENCIL T19X_ZBC +#define ZBC_STENCIL_CLEAR_FMT_INVAILD 0 +#define ZBC_STENCIL_CLEAR_FMT_U8 1 + +struct zbc_s_table { + u32 stencil; + u32 format; + u32 ref_cnt; +}; + struct gpu_ops; enum { diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index df2b0f68..c0e46be3 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B LTC * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -20,7 +20,26 @@ #include "gv11b/ltc_gv11b.h" #include "hw_ltc_gv11b.h" +/* + * Sets the ZBC stencil for the passed index. + */ +static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, + struct zbc_entry *stencil_val, + u32 index) +{ + u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; + + gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), + ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); + + gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(), + stencil_val->depth); + + gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); +} + void gv11b_init_ltc(struct gpu_ops *gops) { gp10b_init_ltc(gops); + gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; } -- cgit v1.2.2 From 3f0e08da43a448d8a1a85529b03d4c073f8c11c5 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 4 Jan 2017 17:18:11 -0800 Subject: gpu: nvgpu: Use timer API in gv11b's wait_idle() The interface for wait_idle() was changed for gk20a, etc, so this change is necessary to update the wait_idle function for gv11b. Similarly for wait_fe() - this needs to no longer use an end_jiffie argument. Bug 1799159 Change-Id: I192159feffda5476269194e7d6ef15b5fe3055bd Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1280459 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 4c23455d..4984af46 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -19,6 +19,8 @@ #include #include +#include + #include "gk20a/gr_gk20a.h" #include "gk20a/semaphore_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" @@ -1049,7 +1051,7 @@ static bool gr_activity_empty_or_preempted(u32 val) return true; } -static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long end_jiffies, +static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, u32 expect_delay) { u32 delay = expect_delay; @@ -1058,9 +1060,12 @@ static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long end_jiffies, bool gr_busy; u32 gr_status; u32 activity0, activity1, activity2, activity4; + struct nvgpu_timeout timeout; gk20a_dbg_fn(""); + nvgpu_timeout_init(g, &timeout, duration_ms, NVGPU_TIMER_CPU_TIMER); + do { /* fmodel: host gets fifo_engine_status(gr) from gr only when gr_status is read */ @@ -1089,8 +1094,7 @@ static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long end_jiffies, usleep_range(delay, delay * 2); delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); - } while (time_before(jiffies, end_jiffies) - || !tegra_platform_is_silicon()); + } while (!nvgpu_timeout_expired(&timeout)); gk20a_err(dev_from_gk20a(g), "timeout, ctxsw busy : %d, gr busy : %d, %08x, %08x, %08x, %08x", @@ -1634,8 +1638,6 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) u32 j; u32 num_subctx = nvgpu_get_litter_value(g, GPU_LIT_NUM_SUBCTX); u32 err = 0; - unsigned long end_jiffies = jiffies + - msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); for (j = 0; j < num_subctx; j++) { @@ -1643,8 +1645,8 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) sw_veid_bundle_init->l[index].addr | gr_pipe_bundle_address_veid_f(j)); - err = gr_gk20a_wait_fe_idle(g, end_jiffies, - GR_IDLE_CHECK_DEFAULT); + err = gr_gk20a_wait_fe_idle(g, gk20a_get_gr_idle_timeout(g), + GR_IDLE_CHECK_DEFAULT); } } @@ -1655,8 +1657,6 @@ static int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) u32 i; u32 last_bundle_data = 0; u32 err = 0; - unsigned long end_jiffies = jiffies + - msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); gk20a_dbg_fn(""); for (i = 0; i < sw_veid_bundle_init->count; i++) { @@ -1672,8 +1672,9 @@ static int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) sw_veid_bundle_init->l[i].addr) == GR_GO_IDLE_BUNDLE) { gk20a_writel(g, gr_pipe_bundle_address_r(), sw_veid_bundle_init->l[i].addr); - err |= gr_gk20a_wait_idle(g, end_jiffies, - GR_IDLE_CHECK_DEFAULT); + err |= gr_gk20a_wait_idle(g, + gk20a_get_gr_idle_timeout(g), + GR_IDLE_CHECK_DEFAULT); } else gv11b_write_bundle_veid_state(g, i); -- cgit v1.2.2 From 64ab12979590564db19c820ff8cdd71579a9b317 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 11 Jan 2017 14:28:32 -0800 Subject: gpu: nvgpu: gv11b: sw methods for shader exception Added proper sw methods handling of shader execptions for gv11b. Bug 1834201 Change-Id: I3f3a45beed777cc4af59368dccd9dc7bb8181c37 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1283729 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 23 +++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 ++ drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 10 +++++++++- 3 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 4984af46..79eee0e5 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -407,6 +407,25 @@ static void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data) gk20a_dbg_fn("done"); } + +static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) +{ + u32 val; + + gk20a_dbg_fn(""); + + if (data == NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE) + val = 0; + else + val = 0xffffffff; + + /* setup sm warp esr report masks */ + gk20a_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(), val); + + /* setup sm global esr report mask */ + gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(), val); +} + static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data) { @@ -415,7 +434,7 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, if (class_num == VOLTA_COMPUTE_A) { switch (offset << 2) { case NVC0C0_SET_SHADER_EXCEPTIONS: - gk20a_gr_set_shader_exceptions(g, data); + gv11b_gr_set_shader_exceptions(g, data); break; default: goto fail; @@ -425,7 +444,7 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, if (class_num == VOLTA_A) { switch (offset << 2) { case NVC397_SET_SHADER_EXCEPTIONS: - gk20a_gr_set_shader_exceptions(g, data); + gv11b_gr_set_shader_exceptions(g, data); break; case NVC397_SET_CIRCULAR_BUFFER_SIZE: g->ops.gr.set_circular_buffer_size(g, data); diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index d31c92ca..b2549edd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -43,6 +43,8 @@ enum { #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c +#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 + void gv11b_init_gr(struct gpu_ops *ops); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct mem_desc *mem); diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index 99da5f73..656597ba 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -554,6 +554,14 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void) { return 0x80000000; } +static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) +{ + return 0x00419ea8; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) +{ + return 0x00419eac; +} static inline u32 gr_fe_go_idle_timeout_r(void) { return 0x00404154; -- cgit v1.2.2 From 3a4a7d196a6a7fd256052cded45d6763c20dd3f6 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Wed, 18 Jan 2017 18:32:09 +0530 Subject: drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse header The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Ied87164ea1de793d97a4cc6a754150164af04698 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/1287500 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 79eee0e5..10b1aebb 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -16,8 +16,8 @@ #include #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ #include -#include #include +#include #include diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index e235e39b..9ee1ed30 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -14,8 +14,8 @@ */ #include /* for udelay */ -#include #include +#include #include "gk20a/gk20a.h" #include "gp10b/pmu_gp10b.h" -- cgit v1.2.2 From 4f3871309d5216b50179feed8f8024193b2224cf Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 13 Jan 2017 13:34:24 -0800 Subject: gpu: nvgpu: gv11b: restore golden context Restore golden context correctly with subcontext header. Increase subctx header size to hold complete golden context. Also fill function pointer for freeing context header. Bug 1834201 Change-Id: Id8a3437bc437fef02ee15333c1163290217d34d1 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1282440 Reviewed-by: Alex Waterman Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 6 +----- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 26 ++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 3 ++- 3 files changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 4929f4d1..7f2f5a65 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -185,7 +185,6 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) return gk20a_mem_rd32(g, userd_mem, offset + ram_userd_gp_get_w()); - } static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) @@ -199,17 +198,13 @@ static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) smp_mb(); gv11b_ring_channel_doorbell(c); - } static void channel_gv11b_unbind(struct channel_gk20a *ch) { gk20a_dbg_fn(""); - gv11b_free_subctx_header(ch); - channel_gk20a_unbind(ch); - } static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) @@ -231,4 +226,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; gops->fifo.unbind_channel = channel_gv11b_unbind; gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; + gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 10b1aebb..dfb46701 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1853,8 +1853,6 @@ static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) /* point this address to engine_wfi_ptr */ gk20a_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(), ram_in_engine_cs_wfi_v() | - ram_in_engine_wfi_target_f( - ram_in_engine_wfi_target_sys_mem_ncoh_v()) | ram_in_engine_wfi_mode_f(ram_in_engine_wfi_mode_virtual_v()) | ram_in_engine_wfi_ptr_lo_f(addr_lo)); @@ -1919,6 +1917,29 @@ static int gr_gv11b_commit_global_timeslice(struct gk20a *g, return 0; } +static void gv11b_restore_context_header(struct gk20a *g, + struct mem_desc *ctxheader) +{ + u32 va_lo, va_hi; + struct gr_gk20a *gr = &g->gr; + + va_hi = gk20a_mem_rd(g, ctxheader, + ctxsw_prog_main_image_context_buffer_ptr_hi_o()); + va_lo = gk20a_mem_rd(g, ctxheader, + ctxsw_prog_main_image_context_buffer_ptr_o()); + gk20a_mem_wr_n(g, ctxheader, 0, + gr->ctx_vars.local_golden_image, + gr->ctx_vars.golden_image_size); + gk20a_mem_wr(g, ctxheader, + ctxsw_prog_main_image_context_buffer_ptr_hi_o(), va_hi); + gk20a_mem_wr(g, ctxheader, + ctxsw_prog_main_image_context_buffer_ptr_o(), va_lo); + gk20a_mem_wr(g, ctxheader, + ctxsw_prog_main_image_num_restore_ops_o(), 0); + gk20a_mem_wr(g, ctxheader, + ctxsw_prog_main_image_num_save_ops_o(), 0); +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -1971,5 +1992,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.program_sm_id_numbering = gr_gv11b_program_sm_id_numbering; gops->gr.commit_inst = gr_gv11b_commit_inst; + gops->gr.restore_context_header = gv11b_restore_context_header; } diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 3acc53f6..b0d0a192 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -44,6 +44,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) { struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; struct gk20a *g = c->g; + struct gr_gk20a *gr = &g->gr; int ret = 0; gk20a_dbg_fn(""); @@ -51,7 +52,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) if (ctx->mem.gpu_va == 0) { ret = gk20a_gmmu_alloc_attr_sys(g, DMA_ATTR_NO_KERNEL_MAPPING, - ctxsw_prog_fecs_header_v(), + gr->ctx_vars.golden_image_size, &ctx->mem); if (ret) { gk20a_err(dev_from_gk20a(g), -- cgit v1.2.2 From 4b09997772f406d16945016ff4581c7c992faeab Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 13:01:36 -0800 Subject: nvgpu: gpu: HW header update for Volta Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 7 +- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 10 +- drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c | 1 + drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 14 +- drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c | 1 + drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 26 +- drivers/gpu/nvgpu/gv11b/gv11b.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 38 +- drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h | 217 -- drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h | 133 - drivers/gpu/nvgpu/gv11b/hw_ce_gv11b.h | 81 - drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h | 445 --- drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | 1485 --------- drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 517 --- drivers/gpu/nvgpu/gv11b/hw_flush_gv11b.h | 181 - drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h | 137 - drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 1477 -------- drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 3509 -------------------- drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h | 593 ---- drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h | 245 -- drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 633 ---- drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h | 205 -- drivers/gpu/nvgpu/gv11b/hw_pram_gv11b.h | 57 - drivers/gpu/nvgpu/gv11b/hw_pri_ringmaster_gv11b.h | 145 - .../gpu/nvgpu/gv11b/hw_pri_ringstation_sys_gv11b.h | 69 - drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | 161 - drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h | 825 ----- drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 765 ----- drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h | 53 - drivers/gpu/nvgpu/gv11b/hw_timer_gv11b.h | 109 - drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h | 221 -- drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h | 89 - drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 9 +- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 9 +- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 8 +- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 8 +- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 6 +- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 8 +- drivers/gpu/nvgpu/gv11b/therm_gv11b.c | 6 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h | 217 ++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 133 + .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 81 + .../include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | 445 +++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 1485 +++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 517 +++ .../nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h | 181 + .../nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | 137 + .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 1477 ++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 3509 ++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 593 ++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 245 ++ .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 633 ++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h | 205 ++ .../nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h | 57 + .../nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | 145 + .../nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | 69 + .../nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 161 + .../nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 825 +++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 765 +++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 53 + .../nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h | 109 + .../nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h | 221 ++ .../include/nvgpu/hw/gv11b/hw_usermode_gv11b.h | 89 + 63 files changed, 12443 insertions(+), 12413 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_ce_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_flush_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_pram_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_pri_ringmaster_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_pri_ringstation_sys_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_timer_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h delete mode 100644 drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 961054e0..efe443cc 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -1,7 +1,7 @@ /* * Volta GPU series Copy Engine. * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,9 +16,10 @@ * this program. */ -#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ -#include "hw_ce_gv11b.h" +#include "gk20a/gk20a.h" + #include "gp10b/ce_gp10b.h" + #include "ce_gv11b.h" void gv11b_init_ce(struct gpu_ops *gops) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index fb31d6a8..9588287f 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -1,8 +1,8 @@ /* * GV11B FB * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. -* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. @@ -16,11 +16,13 @@ #include #include "gk20a/gk20a.h" +#include "gk20a/kind_gk20a.h" + #include "gp10b/fb_gp10b.h" + #include "gv11b/fb_gv11b.h" -#include "gk20a/kind_gk20a.h" -#include "hw_gmmu_gv11b.h" +#include static void gv11b_init_uncompressed_kind_map(void) { diff --git a/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c b/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c index f3f8b797..92357980 100644 --- a/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c @@ -14,6 +14,7 @@ */ #include "gp10b/fecs_trace_gp10b.h" + #include "gv11b/fecs_trace_gv11b.h" #ifdef CONFIG_GK20A_CTXSW_TRACE diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 7f2f5a65..ab32016e 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -14,17 +14,21 @@ */ #include #include + #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" + #include "gp10b/fifo_gp10b.h" -#include "hw_pbdma_gv11b.h" + +#include +#include +#include +#include +#include + #include "fifo_gv11b.h" #include "subctx_gv11b.h" #include "gr_gv11b.h" -#include "hw_fifo_gv11b.h" -#include "hw_ram_gv11b.h" -#include "hw_ccsr_gv11b.h" -#include "hw_usermode_gv11b.h" #define CHANNEL_INFO_VEID0 0 #define PBDMA_SUBDEVICE_ID 1 diff --git a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c index 032e0c3e..6cb42baa 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c @@ -19,6 +19,7 @@ */ #include "gk20a/gk20a.h" + #include "gr_ctx_gv11b.h" static int gr_gv11b_get_netlist_name(struct gk20a *g, int index, char *name) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index dfb46701..31c1a420 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -13,32 +13,34 @@ * more details. */ -#include -#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ #include #include +#include +#include + #include #include +#include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" #include "gk20a/semaphore_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gm20b/gr_gm20b.h" + #include "gv11b/gr_gv11b.h" #include "gv11b/mm_gv11b.h" #include "gv11b/subctx_gv11b.h" -#include "hw_gr_gv11b.h" -#include "hw_fifo_gv11b.h" -#include "hw_proj_gv11b.h" -#include "hw_ctxsw_prog_gv11b.h" -#include "hw_mc_gv11b.h" -#include "hw_gr_gv11b.h" -#include "hw_ram_gv11b.h" -#include "hw_pbdma_gv11b.h" -#include -#include + +#include +#include +#include +#include +#include +#include +#include +#include static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) { diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index c1809f95..09628940 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c @@ -17,6 +17,7 @@ */ #include "gk20a/gk20a.h" + #include "gv11b/gv11b.h" int gv11b_init_gpu_characteristics(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ccaa570c..07f386e8 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B Tegra HAL interface * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,26 +18,28 @@ #include #include -#include "gk20a/gk20a.h" -#include "gv11b/hal_gv11b.h" -#include "gv11b/gr_gv11b.h" -#include "gv11b/mc_gv11b.h" -#include "gv11b/ltc_gv11b.h" -#include "gv11b/fecs_trace_gv11b.h" -#include "gv11b/gv11b.h" -#include "gv11b/ce_gv11b.h" -#include "gv11b/gr_ctx_gv11b.h" -#include "gv11b/mm_gv11b.h" -#include "gv11b/pmu_gv11b.h" -#include "gv11b/therm_gv11b.h" -#include "gv11b/fb_gv11b.h" -#include "gv11b/fifo_gv11b.h" -#include "gv11b/hw_proj_gv11b.h" -#include "gv11b/gv11b_gating_reglist.h" +#include "gk20a/gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" #include "gm20b/gr_gm20b.h" -#include "gk20a/dbg_gpu_gk20a.h" + +#include "hal_gv11b.h" +#include "gr_gv11b.h" +#include "mc_gv11b.h" +#include "ltc_gv11b.h" +#include "fecs_trace_gv11b.h" +#include "gv11b.h" +#include "ce_gv11b.h" +#include "gr_ctx_gv11b.h" +#include "mm_gv11b.h" +#include "pmu_gv11b.h" +#include "therm_gv11b.h" +#include "fb_gv11b.h" +#include "fifo_gv11b.h" +#include "gv11b_gating_reglist.h" + +#include static struct gpu_ops gv11b_ops; diff --git a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h deleted file mode 100644 index 66571ae7..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_bus_gv11b_h_ -#define _hw_bus_gv11b_h_ - -static inline u32 bus_bar0_window_r(void) -{ - return 0x00001700; -} -static inline u32 bus_bar0_window_base_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 bus_bar0_window_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) -{ - return 0x2000000; -} -static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) -{ - return 0x3000000; -} -static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) -{ - return 0x00000010; -} -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) -{ - return 0x20000000; -} -static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) -{ - return 0x20000000; -} -static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) -{ - return 0x30000000; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 bus_bind_status_r(void) -{ - return 0x00001710; -} -static inline u32 bus_bind_status_bar1_pending_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 bus_bind_status_bar1_pending_empty_f(void) -{ - return 0x0; -} -static inline u32 bus_bind_status_bar1_pending_busy_f(void) -{ - return 0x1; -} -static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 bus_bind_status_bar1_outstanding_false_f(void) -{ - return 0x0; -} -static inline u32 bus_bind_status_bar1_outstanding_true_f(void) -{ - return 0x2; -} -static inline u32 bus_bind_status_bar2_pending_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 bus_bind_status_bar2_pending_empty_f(void) -{ - return 0x0; -} -static inline u32 bus_bind_status_bar2_pending_busy_f(void) -{ - return 0x4; -} -static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 bus_bind_status_bar2_outstanding_false_f(void) -{ - return 0x0; -} -static inline u32 bus_bind_status_bar2_outstanding_true_f(void) -{ - return 0x8; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return 0x1 << 1; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return 0x1 << 2; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return 0x1 << 3; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return 0x1 << 1; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return 0x1 << 2; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return 0x1 << 3; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h deleted file mode 100644 index 618c4806..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ccsr_gv11b_h_ -#define _hw_ccsr_gv11b_h_ - -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return 0x00800000 + i*8; -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000200; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) -{ - return 0x20000000; -} -static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) -{ - return 0x30000000; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return 0x00800004 + i*8; -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000200; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1) << 10; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24) & 0xf; -} -static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) -{ - return (v & 0x1) << 22; -} -static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) -{ - return 0x400000; -} -static inline u32 ccsr_channel_eng_faulted_f(u32 v) -{ - return (v & 0x1) << 23; -} -static inline u32 ccsr_channel_eng_faulted_reset_f(void) -{ - return 0x800000; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28) & 0x1; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ce_gv11b.h deleted file mode 100644 index 9f279207..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_ce_gv11b.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce_gv11b_h_ -#define _hw_ce_gv11b_h_ - -static inline u32 ce_intr_status_r(u32 i) -{ - return 0x00104410 + i*128; -} -static inline u32 ce_intr_status_blockpipe_pending_f(void) -{ - return 0x1; -} -static inline u32 ce_intr_status_blockpipe_reset_f(void) -{ - return 0x1; -} -static inline u32 ce_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2; -} -static inline u32 ce_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2; -} -static inline u32 ce_intr_status_launcherr_pending_f(void) -{ - return 0x4; -} -static inline u32 ce_intr_status_launcherr_reset_f(void) -{ - return 0x4; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h deleted file mode 100644 index 228bf5f2..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h +++ /dev/null @@ -1,445 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctxsw_prog_gv11b_h_ -#define _hw_ctxsw_prog_gv11b_h_ - -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008; -} -static inline u32 ctxsw_prog_main_image_ctl_o(void) -{ - return 0x0000000c; -} -static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) -{ - return 0x00000000; -} -static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) -{ - return 0x00000008; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) -{ - return 0x00000010; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) -{ - return 0x00000011; -} -static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) -{ - return 0x00000012; -} -static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) -{ - return 0x00000020; -} -static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) -{ - return 0x00000021; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001c; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return 0x7 << 0; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return 0x7 << 3; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002c; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dc; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) -{ - return 0x00000060; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) -{ - return 0x00000064; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) -{ - return 0x00000070; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) -{ - return 0x00000074; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) -{ - return 0x00000078; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) -{ - return 0x0000007c; -} -static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fc; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0de; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000c; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) -{ - return 0x000000b8; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) -{ - return 0x000000bc; -} -static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) -{ - return 0x000000c0; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) -{ - return 0x000000c4; -} -static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) -{ - return 0x000000c8; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) -{ - return 0x000000cc; -} -static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) -{ - return 0x000000e0; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) -{ - return 0x000000e4; -} -static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16) & 0xffff; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fc; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becab; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ec; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16) & 0xff; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return 0x3 << 0; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003c; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return 0x1 << 3; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h deleted file mode 100644 index d2f22afa..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h +++ /dev/null @@ -1,1485 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fb_gv11b_h_ -#define _hw_fb_gv11b_h_ - -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) -{ - return 0x1; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15) & 0x1; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16) & 0xff; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) -{ - return (r >> 11) & 0x1; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) -{ - return 0x800; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) -{ - return 0x0; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) -{ - return 0x2; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbc; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return 0x1 << 2; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7) << 3; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return 0x7 << 3; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3) & 0x7; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return 0x1 << 6; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6) & 0x1; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3) << 7; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return 0x3 << 7; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7) & 0x3; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3f) << 9; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return 0x3f << 9; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9) & 0x3f; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1f) << 15; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return 0x1f << 15; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15) & 0x1f; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1) << 20; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return 0x1 << 20; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20) & 0x1; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return 0x7 << 24; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24) & 0x7; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return 0x1 << 31; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return 0x3 << 0; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) -{ - return 0x2; -} -static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) -{ - return 0x3; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000c; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100ccc; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) -{ - return 0x2; -} -static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) -{ - return 0x3; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000c; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16) & 0x1; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return 0x1 << 16; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001; -} -static inline u32 fb_niso_flush_sysmem_addr_r(void) -{ - return 0x00100c10; -} -static inline u32 fb_niso_intr_r(void) -{ - return 0x00100a20; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) -{ - return 0x1; -} -static inline u32 fb_niso_intr_hub_access_counter_error_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) -{ - return 0x2; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_f(u32 v) -{ - return (v & 0x1) << 27; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) -{ - return 0x8000000; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) -{ - return 0x10000000; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_f(u32 v) -{ - return (v & 0x1) << 29; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) -{ - return 0x20000000; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) -{ - return 0x40000000; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) -{ - return 0x80000000; -} -static inline u32 fb_niso_intr_en_r(u32 i) -{ - return 0x00100a24 + i*4; -} -static inline u32 fb_niso_intr_en__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) -{ - return 0x1; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) -{ - return 0x2; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) -{ - return (v & 0x1) << 27; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) -{ - return 0x8000000; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) -{ - return 0x10000000; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) -{ - return (v & 0x1) << 29; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) -{ - return 0x20000000; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) -{ - return 0x40000000; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 fb_niso_intr_en_set_r(u32 i) -{ - return 0x00100a2c + i*4; -} -static inline u32 fb_niso_intr_en_set__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) -{ - return 0x1; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) -{ - return 0x2; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_f(u32 v) -{ - return (v & 0x1) << 27; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_f(u32 v) -{ - return (v & 0x1) << 29; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000; -} -static inline u32 fb_niso_intr_en_clr_r(u32 i) -{ - return 0x00100a34 + i*4; -} -static inline u32 fb_niso_intr_en_clr__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) -{ - return 0x1; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) -{ - return 0x2; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_f(u32 v) -{ - return (v & 0x1) << 27; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) -{ - return 0x8000000; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) -{ - return 0x10000000; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_f(u32 v) -{ - return (v & 0x1) << 29; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) -{ - return 0x20000000; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) -{ - return 0x40000000; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) -{ - return 0x80000000; -} -static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) -{ - return 0x00000000; -} -static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) -{ - return 0x00100e24 + i*20; -} -static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) -{ - return 0x00000000; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) -{ - return 0x1; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3) << 1; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) -{ - return (r >> 1) & 0x3; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) -{ - return 0x4; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x6; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) -{ - return (r >> 12) & 0xfffff; -} -static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) -{ - return 0x00100e28 + i*20; -} -static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 fb_mmu_fault_buffer_get_r(u32 i) -{ - return 0x00100e2c + i*20; -} -static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) -{ - return (v & 0xfffff) << 0; -} -static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) -{ - return (r >> 0) & 0xfffff; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_yes_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) -{ - return 0x40000000; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_yes_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_yes_f(void) -{ - return 0x80000000; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) -{ - return 0x80000000; -} -static inline u32 fb_mmu_fault_buffer_put_r(u32 i) -{ - return 0x00100e30 + i*20; -} -static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) -{ - return (v & 0xfffff) << 0; -} -static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) -{ - return (r >> 0) & 0xfffff; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) -{ - return 0x40000000; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) -{ - return 0x00000000; -} -static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) -{ - return 0x80000000; -} -static inline u32 fb_mmu_fault_buffer_size_r(u32 i) -{ - return 0x00100e34 + i*20; -} -static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) -{ - return (v & 0xfffff) << 0; -} -static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) -{ - return (r >> 0) & 0xfffff; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) -{ - return (v & 0x1) << 29; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) -{ - return (r >> 29) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) -{ - return 0x20000000; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) -{ - return 0x40000000; -} -static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) -{ - return 0x80000000; -} -static inline u32 fb_mmu_fault_addr_lo_r(void) -{ - return 0x00100e4c; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) -{ - return 0x00000002; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) -{ - return 0x2; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) -{ - return 0x00000003; -} -static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) -{ - return 0x3; -} -static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) -{ - return (r >> 12) & 0xfffff; -} -static inline u32 fb_mmu_fault_addr_hi_r(void) -{ - return 0x00100e50; -} -static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 fb_mmu_fault_inst_lo_r(void) -{ - return 0x00100e54; -} -static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) -{ - return (r >> 0) & 0x1ff; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) -{ - return (r >> 10) & 0x3; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) -{ - return 0x00000002; -} -static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) -{ - return 0x00000003; -} -static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) -{ - return (r >> 12) & 0xfffff; -} -static inline u32 fb_mmu_fault_inst_hi_r(void) -{ - return 0x00100e58; -} -static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 fb_mmu_fault_info_r(void) -{ - return 0x00100e5c; -} -static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) -{ - return (r >> 7) & 0x1; -} -static inline u32 fb_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8) & 0x7f; -} -static inline u32 fb_mmu_fault_info_access_type_v(u32 r) -{ - return (r >> 16) & 0xf; -} -static inline u32 fb_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20) & 0x1; -} -static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) -{ - return (r >> 24) & 0x1f; -} -static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) -{ - return (r >> 29) & 0x1; -} -static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 fb_mmu_fault_info_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 fb_mmu_fault_status_r(void) -{ - return 0x00100e60; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) -{ - return 0x1; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) -{ - return 0x1; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) -{ - return 0x2; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) -{ - return 0x2; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) -{ - return 0x4; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) -{ - return 0x4; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) -{ - return 0x8; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) -{ - return 0x8; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) -{ - return 0x10; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) -{ - return 0x10; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_v(u32 r) -{ - return (r >> 5) & 0x1; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) -{ - return 0x20; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) -{ - return 0x20; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_v(u32 r) -{ - return (r >> 6) & 0x1; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) -{ - return 0x40; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) -{ - return 0x40; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_f(u32 v) -{ - return (v & 0x1) << 7; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_v(u32 r) -{ - return (r >> 7) & 0x1; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) -{ - return 0x80; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) -{ - return 0x80; -} -static inline u32 fb_mmu_fault_status_replayable_f(u32 v) -{ - return (v & 0x1) << 8; -} -static inline u32 fb_mmu_fault_status_replayable_v(u32 r) -{ - return (r >> 8) & 0x1; -} -static inline u32 fb_mmu_fault_status_replayable_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_replayable_set_f(void) -{ - return 0x100; -} -static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) -{ - return (v & 0x1) << 9; -} -static inline u32 fb_mmu_fault_status_non_replayable_v(u32 r) -{ - return (r >> 9) & 0x1; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) -{ - return 0x200; -} -static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) -{ - return (v & 0x1) << 10; -} -static inline u32 fb_mmu_fault_status_replayable_error_v(u32 r) -{ - return (r >> 10) & 0x1; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) -{ - return 0x400; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) -{ - return (v & 0x1) << 11; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_v(u32 r) -{ - return (r >> 11) & 0x1; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) -{ - return 0x800; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) -{ - return (v & 0x1) << 12; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_v(u32 r) -{ - return (r >> 12) & 0x1; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) -{ - return 0x1000; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) -{ - return (v & 0x1) << 13; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_v(u32 r) -{ - return (r >> 13) & 0x1; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) -{ - return 0x2000; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) -{ - return (v & 0x1) << 14; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_v(u32 r) -{ - return (r >> 14) & 0x1; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) -{ - return 0x4000; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_f(u32 v) -{ - return (v & 0x1) << 15; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_v(u32 r) -{ - return (r >> 15) & 0x1; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) -{ - return 0x8000; -} -static inline u32 fb_mmu_fault_status_busy_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 fb_mmu_fault_status_busy_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 fb_mmu_fault_status_busy_true_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_busy_true_f(void) -{ - return 0x40000000; -} -static inline u32 fb_mmu_fault_status_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_mmu_fault_status_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 fb_mmu_fault_status_valid_set_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_valid_set_f(void) -{ - return 0x80000000; -} -static inline u32 fb_mmu_fault_status_valid_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_status_valid_clear_f(void) -{ - return 0x80000000; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h deleted file mode 100644 index d68c823a..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fifo_gv11b_h_ -#define _hw_fifo_gv11b_h_ - -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000; -} -static inline u32 fifo_userd_writeback_r(void) -{ - return 0x0000225c; -} -static inline u32 fifo_userd_writeback_timer_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 fifo_userd_writeback_timer_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_userd_writeback_timer_shorter_v(void) -{ - return 0x00000003; -} -static inline u32 fifo_userd_writeback_timer_100us_v(void) -{ - return 0x00000064; -} -static inline u32 fifo_userd_writeback_timescale_f(u32 v) -{ - return (v & 0xf) << 12; -} -static inline u32 fifo_userd_writeback_timescale_0_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) -{ - return 0x20000000; -} -static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) -{ - return 0x30000000; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xf) << 20; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return 0x00002280 + i*8; -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return 0x00002284 + i*8; -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 fifo_eng_runlist_length_max_v(void) -{ - return 0x0000ffff; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return 0x00002350 + i*4; -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return 0x00002390 + i*4; -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000; -} -static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) -{ - return 0x800000; -} -static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) -{ - return 0x800000; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1) << 8; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return 0x1 << 8; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252c; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254c; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000a; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256c; -} -static inline u32 fifo_gpc_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_hub_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1) << (0 + i*1); -} -static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) -{ - return (r >> (0 + i*1)) & 0x1; -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000003; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return 0x3fffffff << 0; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffff; -} -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262c; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1) << (0 + i*1); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return 0x1 << (0 + i*1); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return 0x00002640 + i*8; -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0) & 0xfff; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12) & 0x1; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13) & 0x7; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16) & 0xfff; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28) & 0x1; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15) & 0x1; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return 0x00003080 + i*4; -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000003; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0) & 0xfff; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12) & 0x1; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13) & 0x7; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16) & 0xfff; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28) & 0x1; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15) & 0x1; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_cfg0_r(void) -{ - return 0x00002004; -} -static inline u32 fifo_cfg0_num_pbdma_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) -{ - return (r >> 16) & 0xff; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_flush_gv11b.h deleted file mode 100644 index 380f8824..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_flush_gv11b.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_flush_gv11b_h_ -#define _hw_flush_gv11b_h_ - -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000c; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h deleted file mode 100644 index 280a048a..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fuse_gv11b_h_ -#define _hw_fuse_gv11b_h_ - -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return 0x00021c38 + i*4; -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return 0x00021838 + i*4; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return 0xff << 0; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return 0x1 << 0; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return 0xffff << 0; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return 0x00021d70 + i*4; -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0 + i*1)) & 0x1; -} -static inline u32 fuse_opt_ecc_en_r(void) -{ - return 0x00021228; -} -static inline u32 fuse_opt_feature_fuses_override_disable_r(void) -{ - return 0x000213f0; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h deleted file mode 100644 index 1c523f87..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h +++ /dev/null @@ -1,1477 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gmmu_gv11b_h_ -#define _hw_gmmu_gv11b_h_ - -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) -{ - return 0x4; -} -static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) -{ - return 0x6; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xffffff) << 8; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) -{ - return 0x4; -} -static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) -{ - return 0x6; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) -{ - return 0x4; -} -static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) -{ - return 0x6; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xffffff) << 8; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xffffff) << 8; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_address_vid_f(u32 v) -{ - return (v & 0xffffff) << 8; -} -static inline u32 gmmu_new_pte_address_vid_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) -{ - return 0x4; -} -static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) -{ - return 0x6; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0x3ffff) << 4; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xff) << 4; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ff; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000; -} -static inline u32 gmmu_pte_kind_z16_v(void) -{ - return 0x00000001; -} -static inline u32 gmmu_pte_kind_z16_2c_v(void) -{ - return 0x00000002; -} -static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) -{ - return 0x00000003; -} -static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) -{ - return 0x00000004; -} -static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) -{ - return 0x00000005; -} -static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) -{ - return 0x00000006; -} -static inline u32 gmmu_pte_kind_z16_2z_v(void) -{ - return 0x00000007; -} -static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) -{ - return 0x00000008; -} -static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) -{ - return 0x00000009; -} -static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) -{ - return 0x0000000a; -} -static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) -{ - return 0x0000000b; -} -static inline u32 gmmu_pte_kind_z16_2cz_v(void) -{ - return 0x00000036; -} -static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) -{ - return 0x00000037; -} -static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) -{ - return 0x00000038; -} -static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) -{ - return 0x00000039; -} -static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) -{ - return 0x0000005f; -} -static inline u32 gmmu_pte_kind_z16_4cz_v(void) -{ - return 0x0000000c; -} -static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) -{ - return 0x0000000d; -} -static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) -{ - return 0x0000000e; -} -static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) -{ - return 0x0000000f; -} -static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) -{ - return 0x00000010; -} -static inline u32 gmmu_pte_kind_s8z24_v(void) -{ - return 0x00000011; -} -static inline u32 gmmu_pte_kind_s8z24_1z_v(void) -{ - return 0x00000012; -} -static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) -{ - return 0x00000013; -} -static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) -{ - return 0x00000014; -} -static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) -{ - return 0x00000015; -} -static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) -{ - return 0x00000016; -} -static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) -{ - return 0x00000017; -} -static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) -{ - return 0x00000018; -} -static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) -{ - return 0x00000019; -} -static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) -{ - return 0x0000001a; -} -static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) -{ - return 0x0000001b; -} -static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) -{ - return 0x0000001c; -} -static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) -{ - return 0x0000001d; -} -static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) -{ - return 0x0000001e; -} -static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) -{ - return 0x0000001f; -} -static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) -{ - return 0x00000020; -} -static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) -{ - return 0x00000021; -} -static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) -{ - return 0x00000022; -} -static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) -{ - return 0x00000023; -} -static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) -{ - return 0x00000024; -} -static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) -{ - return 0x00000025; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) -{ - return 0x00000026; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) -{ - return 0x00000027; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) -{ - return 0x00000028; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) -{ - return 0x00000029; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) -{ - return 0x0000002e; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) -{ - return 0x0000002f; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) -{ - return 0x00000030; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) -{ - return 0x00000031; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) -{ - return 0x00000032; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) -{ - return 0x00000033; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) -{ - return 0x00000034; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) -{ - return 0x00000035; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) -{ - return 0x0000003a; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) -{ - return 0x0000003b; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) -{ - return 0x0000003c; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) -{ - return 0x0000003d; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) -{ - return 0x0000003e; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) -{ - return 0x0000003f; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) -{ - return 0x00000040; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) -{ - return 0x00000041; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) -{ - return 0x00000042; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) -{ - return 0x00000043; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) -{ - return 0x00000044; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) -{ - return 0x00000045; -} -static inline u32 gmmu_pte_kind_z24s8_v(void) -{ - return 0x00000046; -} -static inline u32 gmmu_pte_kind_z24s8_1z_v(void) -{ - return 0x00000047; -} -static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) -{ - return 0x00000048; -} -static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) -{ - return 0x00000049; -} -static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) -{ - return 0x0000004a; -} -static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) -{ - return 0x0000004b; -} -static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) -{ - return 0x0000004c; -} -static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) -{ - return 0x0000004d; -} -static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) -{ - return 0x0000004e; -} -static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) -{ - return 0x0000004f; -} -static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) -{ - return 0x00000050; -} -static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) -{ - return 0x00000051; -} -static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) -{ - return 0x00000052; -} -static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) -{ - return 0x00000053; -} -static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) -{ - return 0x00000054; -} -static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) -{ - return 0x00000055; -} -static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) -{ - return 0x00000056; -} -static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) -{ - return 0x00000057; -} -static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) -{ - return 0x00000058; -} -static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) -{ - return 0x00000059; -} -static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) -{ - return 0x0000005a; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) -{ - return 0x0000005b; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) -{ - return 0x0000005c; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) -{ - return 0x0000005d; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) -{ - return 0x0000005e; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) -{ - return 0x00000063; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) -{ - return 0x00000064; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) -{ - return 0x00000065; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) -{ - return 0x00000066; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) -{ - return 0x00000067; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) -{ - return 0x00000068; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) -{ - return 0x00000069; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) -{ - return 0x0000006a; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) -{ - return 0x0000006f; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) -{ - return 0x00000070; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) -{ - return 0x00000071; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) -{ - return 0x00000072; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) -{ - return 0x00000073; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) -{ - return 0x00000074; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) -{ - return 0x00000075; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) -{ - return 0x00000076; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) -{ - return 0x00000077; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) -{ - return 0x00000078; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) -{ - return 0x00000079; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) -{ - return 0x0000007a; -} -static inline u32 gmmu_pte_kind_zf32_v(void) -{ - return 0x0000007b; -} -static inline u32 gmmu_pte_kind_zf32_1z_v(void) -{ - return 0x0000007c; -} -static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) -{ - return 0x0000007d; -} -static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) -{ - return 0x0000007e; -} -static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) -{ - return 0x0000007f; -} -static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) -{ - return 0x00000080; -} -static inline u32 gmmu_pte_kind_zf32_2cs_v(void) -{ - return 0x00000081; -} -static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) -{ - return 0x00000082; -} -static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) -{ - return 0x00000083; -} -static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) -{ - return 0x00000084; -} -static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) -{ - return 0x00000085; -} -static inline u32 gmmu_pte_kind_zf32_2cz_v(void) -{ - return 0x00000086; -} -static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) -{ - return 0x00000087; -} -static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) -{ - return 0x00000088; -} -static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) -{ - return 0x00000089; -} -static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) -{ - return 0x0000008a; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) -{ - return 0x0000008b; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) -{ - return 0x0000008c; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) -{ - return 0x0000008d; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) -{ - return 0x0000008e; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) -{ - return 0x0000008f; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) -{ - return 0x00000090; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) -{ - return 0x00000091; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) -{ - return 0x00000092; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) -{ - return 0x00000097; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) -{ - return 0x00000098; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) -{ - return 0x00000099; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) -{ - return 0x0000009a; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) -{ - return 0x0000009b; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) -{ - return 0x0000009c; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) -{ - return 0x0000009d; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) -{ - return 0x0000009e; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) -{ - return 0x0000009f; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) -{ - return 0x000000a0; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) -{ - return 0x000000a1; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) -{ - return 0x000000a2; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) -{ - return 0x000000a3; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) -{ - return 0x000000a4; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) -{ - return 0x000000a5; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) -{ - return 0x000000a6; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) -{ - return 0x000000a7; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) -{ - return 0x000000a8; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) -{ - return 0x000000a9; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) -{ - return 0x000000aa; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) -{ - return 0x000000ab; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) -{ - return 0x000000ac; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) -{ - return 0x000000ad; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) -{ - return 0x000000ae; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) -{ - return 0x000000b3; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) -{ - return 0x000000b4; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) -{ - return 0x000000b5; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) -{ - return 0x000000b6; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) -{ - return 0x000000b7; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) -{ - return 0x000000b8; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) -{ - return 0x000000b9; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) -{ - return 0x000000ba; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) -{ - return 0x000000bb; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) -{ - return 0x000000bc; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) -{ - return 0x000000bd; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) -{ - return 0x000000be; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) -{ - return 0x000000bf; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) -{ - return 0x000000c0; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) -{ - return 0x000000c1; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) -{ - return 0x000000c2; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) -{ - return 0x000000c3; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) -{ - return 0x000000c4; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) -{ - return 0x000000c5; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) -{ - return 0x000000c6; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) -{ - return 0x000000c7; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) -{ - return 0x000000c8; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) -{ - return 0x000000ce; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) -{ - return 0x000000cf; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) -{ - return 0x000000d0; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) -{ - return 0x000000d1; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) -{ - return 0x000000d2; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) -{ - return 0x000000d3; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) -{ - return 0x000000d4; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) -{ - return 0x000000d5; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) -{ - return 0x000000d6; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) -{ - return 0x000000d7; -} -static inline u32 gmmu_pte_kind_generic_16bx2_v(void) -{ - return 0x000000fe; -} -static inline u32 gmmu_pte_kind_c32_2c_v(void) -{ - return 0x000000d8; -} -static inline u32 gmmu_pte_kind_c32_2cbr_v(void) -{ - return 0x000000d9; -} -static inline u32 gmmu_pte_kind_c32_2cba_v(void) -{ - return 0x000000da; -} -static inline u32 gmmu_pte_kind_c32_2cra_v(void) -{ - return 0x000000db; -} -static inline u32 gmmu_pte_kind_c32_2bra_v(void) -{ - return 0x000000dc; -} -static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) -{ - return 0x000000dd; -} -static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) -{ - return 0x000000de; -} -static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) -{ - return 0x000000cc; -} -static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) -{ - return 0x000000df; -} -static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) -{ - return 0x000000e0; -} -static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) -{ - return 0x000000e1; -} -static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) -{ - return 0x000000e2; -} -static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) -{ - return 0x000000e3; -} -static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) -{ - return 0x0000002c; -} -static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) -{ - return 0x000000e4; -} -static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) -{ - return 0x000000e5; -} -static inline u32 gmmu_pte_kind_c64_2c_v(void) -{ - return 0x000000e6; -} -static inline u32 gmmu_pte_kind_c64_2cbr_v(void) -{ - return 0x000000e7; -} -static inline u32 gmmu_pte_kind_c64_2cba_v(void) -{ - return 0x000000e8; -} -static inline u32 gmmu_pte_kind_c64_2cra_v(void) -{ - return 0x000000e9; -} -static inline u32 gmmu_pte_kind_c64_2bra_v(void) -{ - return 0x000000ea; -} -static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) -{ - return 0x000000eb; -} -static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) -{ - return 0x000000ec; -} -static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) -{ - return 0x000000cd; -} -static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) -{ - return 0x000000ed; -} -static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) -{ - return 0x000000ee; -} -static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) -{ - return 0x000000ef; -} -static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) -{ - return 0x000000f0; -} -static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) -{ - return 0x000000f1; -} -static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) -{ - return 0x0000002d; -} -static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) -{ - return 0x000000f2; -} -static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) -{ - return 0x000000f3; -} -static inline u32 gmmu_pte_kind_c128_2c_v(void) -{ - return 0x000000f4; -} -static inline u32 gmmu_pte_kind_c128_2cr_v(void) -{ - return 0x000000f5; -} -static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) -{ - return 0x000000f6; -} -static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) -{ - return 0x000000f7; -} -static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) -{ - return 0x000000f8; -} -static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) -{ - return 0x000000f9; -} -static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) -{ - return 0x000000fa; -} -static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) -{ - return 0x000000fb; -} -static inline u32 gmmu_pte_kind_x8c24_v(void) -{ - return 0x000000fc; -} -static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) -{ - return 0x000000fd; -} -static inline u32 gmmu_pte_kind_smsked_message_v(void) -{ - return 0x000000ca; -} -static inline u32 gmmu_pte_kind_smhost_message_v(void) -{ - return 0x000000cb; -} -static inline u32 gmmu_pte_kind_s8_v(void) -{ - return 0x0000002a; -} -static inline u32 gmmu_pte_kind_s8_2s_v(void) -{ - return 0x0000002b; -} -static inline u32 gmmu_fault_buf_size_v(void) -{ - return 0x00000020; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r) -{ - return (r >> 8) & 0x3; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void) -{ - return 0; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void) -{ - return 0x00000000; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void) -{ - return 0x00000002; -} -static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void) -{ - return 0x00000003; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r) -{ - return (r >> 12) & 0xfffff; -} -static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) -{ - return 0; -} -static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 gmmu_fault_buf_entry_inst_hi_w(void) -{ - return 1; -} -static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void) -{ - return 2; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r) -{ - return (r >> 12) & 0xfffff; -} -static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) -{ - return 2; -} -static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 gmmu_fault_buf_entry_addr_hi_w(void) -{ - return 3; -} -static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void) -{ - return 4; -} -static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void) -{ - return 5; -} -static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r) -{ - return (r >> 0) & 0x1ff; -} -static inline u32 gmmu_fault_buf_entry_engine_id_w(void) -{ - return 6; -} -static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 gmmu_fault_buf_entry_fault_type_w(void) -{ - return 7; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r) -{ - return (r >> 7) & 0x1; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void) -{ - return 7; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void) -{ - return 0x00000001; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void) -{ - return 0x80; -} -static inline u32 gmmu_fault_buf_entry_client_v(u32 r) -{ - return (r >> 8) & 0x7f; -} -static inline u32 gmmu_fault_buf_entry_client_w(void) -{ - return 7; -} -static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r) -{ - return (r >> 16) & 0xf; -} -static inline u32 gmmu_fault_buf_entry_access_type_w(void) -{ - return 7; -} -static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r) -{ - return (r >> 20) & 0x1; -} -static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void) -{ - return 7; -} -static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r) -{ - return (r >> 24) & 0x1f; -} -static inline u32 gmmu_fault_buf_entry_gpc_id_w(void) -{ - return 7; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r) -{ - return (r >> 29) & 0x1; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_w(void) -{ - return 7; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void) -{ - return 0x00000001; -} -static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void) -{ - return 0x20000000; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void) -{ - return 7; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void) -{ - return 0x00000001; -} -static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) -{ - return 0x40000000; -} -static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gmmu_fault_buf_entry_valid_w(void) -{ - return 7; -} -static inline u32 gmmu_fault_buf_entry_valid_true_v(void) -{ - return 0x00000001; -} -static inline u32 gmmu_fault_buf_entry_valid_true_f(void) -{ - return 0x80000000; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h deleted file mode 100644 index 656597ba..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ /dev/null @@ -1,3509 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gr_gv11b_h_ -#define _hw_gr_gv11b_h_ - -static inline u32 gr_intr_r(void) -{ - return 0x00400100; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1) << 8; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013c; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108; -} -static inline u32 gr_exception_fe_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_exception_gpc_m(void) -{ - return 0x1 << 24; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_exception_ds_m(void) -{ - return 0x1 << 4; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011c; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1) << 16; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2) & 0xfff; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16) & 0x7; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070c; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21) & 0x1; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060c; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450c; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return 0x7 << 0; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0) & 0x7; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x0050433c; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419b3c; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8c; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500; -} -static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x00504d00; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8c; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500; -} -static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x0041cd00; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200; -} -static inline u32 gr_pri_be1_becs_be_activity0_r(void) -{ - return 0x00410600; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x00504358; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004c; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884c; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_pipe_bundle_address_veid_f(u32 v) -{ - return (v & 0x3f) << 20; -} -static inline u32 gr_pipe_bundle_address_veid_w(void) -{ - return 0; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) -{ - return 0x00419ea8; -} -static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) -{ - return 0x00419eac; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x1800; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return 0x00404200 + i*4; -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_fe_tpc_fs_r(u32 i) -{ - return 0x0040a200 + i*4; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448c; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910c; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return 0x1 << 2; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904c; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900c; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901c; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return 0xf << 0; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0) & 0xf; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xe; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1f) << 8; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920c; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return 0x00409180 + i*16; -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return 0x00409184 + i*16; -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return 0x00409188 + i*16; -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return 0x004091c0 + i*8; -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return 0x3f << 2; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2) & 0x3f; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return 0x004091c4 + i*8; -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911c; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0) & 0xfffffff; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3) << 28; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return 0x3 << 28; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28) & 0x3; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) -{ - return 0x20000000; -} -static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) -{ - return 0x30000000; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001a; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004; -} -static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) -{ - return 0x0000003a; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18; -} -static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) -{ - return (v & 0x1) << 16; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1) << 17; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1) << 18; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1) << 10; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return 0x1 << 10; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10) & 0x1; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960c; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return 0x00409800 + i*4; -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return 0x004098c0 + i*4; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return 0x00409840 + i*4; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1f) << 0; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return 0x1f << 0; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1f) << 16; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return 0x1f << 16; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16) & 0x1f; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return 0x3f << 0; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0) & 0x3f; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1) << 12; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return 0x1 << 12; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12) & 0x1; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return 0xfffffff << 0; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0) & 0xfffffff; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3) << 28; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return 0x3 << 28; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28) & 0x3; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0c; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return 0xfffffff << 0; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0) & 0xfffffff; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3) << 28; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return 0x3 << 28; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28) & 0x3; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1f) << 0; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return 0x1f << 0; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) -{ - return (r >> 15) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) -{ - return (r >> 12) & 0x1; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420; -} -static inline u32 gr_rstr2d_gpc_map_r(u32 i) -{ - return 0x0040780c + i*4; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bc; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return 0x00406028 + i*4; -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xf) << 4; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xf) << 8; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xf) << 12; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xf) << 16; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xf) << 20; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xf) << 24; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xf) << 28; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffff; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffff) << 16; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fff) << 0; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x00000380; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fff) << 16; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000302; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return 0x004064d0 + i*4; -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xff) << 16; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580c; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7f) << 0; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return 0xffffffff << 0; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581c; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffff) << 0; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585c; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584c; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return 0x00405870 + i*4; -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ff) << 0; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000030; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800c; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ff) << 0; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ff) << 10; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return 0x3ff << 10; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10) & 0x3ff; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 gr_scc_init_r(void) -{ - return 0x0040802c; -} -static inline u32 gr_scc_init_ram_trigger_f(void) -{ - return 0x1; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return 0x00405b60 + i*4; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) -{ - return 4; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) -{ - return 4; -} -static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) -{ - return (v & 0xf) << 4; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xf) << 8; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return 0x00405ba0 + i*4; -} -static inline u32 gr_cwd_sm_id__size_1_v(void) -{ - return 0x00000010; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16) & 0x1f; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return 0x3f << 0; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0) & 0x3f; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return 0xffffff << 0; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0) & 0xffffff; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ff) << 0; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xf) << 16; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xf) << 8; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return 0x00500a04 + i*32; -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return 0x00500c10 + i*4; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return 0x00500c30 + i*4; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504608; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x00504330; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8) & 0xfff; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20) & 0xfff; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffff) << 0; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return 0x3fffff << 0; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00000800; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00001100; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return 0xffff << 0; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffff) << 0; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00000800; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419e00; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419e04; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffff) << 0; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return 0x1fffff << 0; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0) & 0x1fffff; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0ac; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return 0x3f << 0; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0) & 0x3f; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3f) << 6; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return 0x3f << 6; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6) & 0x3f; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return 0xfff << 0; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0) & 0xfff; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10c; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return 0x1 << 2; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return 0x0041a180 + i*16; -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return 0x0041a184 + i*16; -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return 0x0041a188 + i*16; -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return 0x0041a1c0 + i*8; -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return 0x0041a1c4 + i*8; -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return 0x0041a800 + i*4; -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return 0xffffffff << 0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ff) << 0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return 0x7ff << 0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0) & 0x7ff; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000030; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x30; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x005001dc; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x00000170; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x005001d8; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x004181e4; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befc; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return 0x00418ea0 + i*4; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffff) << 0; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return 0x3fffff << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return 0x00418010 + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return 0x0041804c + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return 0x00418088 + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return 0x004180c4 + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00418100; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return 0x00418110 + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0041814c; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) -{ - return 0x0041815c + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) -{ - return 0x00418198; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000c; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 gr_crstr_gpc_map_r(u32 i) -{ - return 0x00418b08 + i*4; -} -static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) -{ - return (v & 0x1f) << 0; -} -static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) -{ - return (v & 0x1f) << 5; -} -static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) -{ - return (v & 0x1f) << 10; -} -static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) -{ - return (v & 0x1f) << 15; -} -static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) -{ - return (v & 0x1f) << 20; -} -static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) -{ - return (v & 0x1f) << 25; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) -{ - return 0x00418980 + i*4; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) -{ - return (v & 0x7) << 4; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) -{ - return (v & 0x7) << 16; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) -{ - return (v & 0x7) << 28; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6c; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ff) << 0; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980c; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2c; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_r(void) -{ - return 0x00419f28; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_r(void) -{ - return 0x00419f2c; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0c; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450c; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xff) << 16; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16) & 0xff; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) -{ - return 0x00504704; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000; -} -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) -{ - return 0x00504708; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504710; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504718; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_bpt_pause_mask_r(void) -{ - return 0x00419f10; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) -{ - return 0x00504700; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_r(void) -{ - return 0x00419f34; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) -{ - return 0x00504734; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) -{ - return 0x00504730; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) -{ - return 0xff << 16; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) -{ - return 0xf << 24; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) -{ - return 0x00504738; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x005043a0; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419ba0; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return 0x1 << 4; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x005043b0; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419bb0; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) -{ - return 0x0041bf00 + i*4; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1f) << 16; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7) << 21; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) -{ - return 0x0041bfb0 + i*4; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) -{ - return 0x00000005; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) -{ - return (v & 0xff) << 16; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return 0x1 << 11; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return 0x1 << 2; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return 0x3 << 3; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return 0x3 << 5; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return 0x3 << 28; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16) & 0x1; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188ac; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_r(void) -{ - return 0x00419f04; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(void) -{ - return 0x1 << 3; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419bd8; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return 0x7 << 8; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419ba4; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return 0x3 << 11; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0x1ff) << 0; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return 0x1ff << 0; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h deleted file mode 100644 index 6968c699..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h +++ /dev/null @@ -1,593 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ltc_gv11b_h_ -#define _hw_ltc_gv11b_h_ - -static inline u32 ltc_pltcg_base_v(void) -{ - return 0x00140000; -} -static inline u32 ltc_pltcg_extent_v(void) -{ - return 0x0017ffff; -} -static inline u32 ltc_ltc0_ltss_v(void) -{ - return 0x00140200; -} -static inline u32 ltc_ltc0_lts0_v(void) -{ - return 0x00140400; -} -static inline u32 ltc_ltcs_ltss_v(void) -{ - return 0x0017e200; -} -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046c; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return 0x1 << 15; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16) & 0x3; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26c; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046c; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x3ffff) << 0; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x3ffff) << 0; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0003ffff; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000b; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0) & 0x3ffffff; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27c; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24) & 0xf; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28) & 0xf; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2ac; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1f) << 16; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return 0x0017e33c + i*4; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34c; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return 0xffffffff << 0; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) -{ - return 0x0017e204; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) -{ - return 8; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) -{ - return 0xff << 0; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc1_ltss_g_elpg_r(void) -{ - return 0x00142214; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20c; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return 0x1 << 20; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return 0x1 << 30; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040c; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051c; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return 0xff << 0; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return 0xff << 16; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16) & 0xff; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8) & 0xf; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8) & 0xf; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0x001422a0; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0x001422a4; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058c; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16) & 0x1f; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h deleted file mode 100644 index 98bec43a..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_mc_gv11b_h_ -#define _hw_mc_gv11b_h_ - -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24) & 0x1f; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20) & 0xf; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4) & 0xf; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0) & 0xf; -} -static inline u32 mc_intr_r(u32 i) -{ - return 0x00000100 + i*4; -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100; -} -static inline u32 mc_intr_hub_pending_f(void) -{ - return 0x200; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return 0x00000140 + i*4; -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return 0x00000160 + i*4; -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return 0x00000180 + i*4; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return 0x1 << 4; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20; -} -static inline u32 mc_enable_ce0_m(void) -{ - return 0x1 << 6; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13) & 0x1; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000; -} -static inline u32 mc_enable_ce2_m(void) -{ - return 0x1 << 21; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return 0x1 << 0; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1) << (0 + i*1); -} -static inline u32 mc_elpg_enable_r(void) -{ - return 0x0000020c; -} -static inline u32 mc_elpg_enable_xbar_enabled_f(void) -{ - return 0x4; -} -static inline u32 mc_elpg_enable_pfb_enabled_f(void) -{ - return 0x100000; -} -static inline u32 mc_elpg_enable_hub_enabled_f(void) -{ - return 0x20000000; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h deleted file mode 100644 index c4d3a631..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h +++ /dev/null @@ -1,633 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pbdma_gv11b_h_ -#define _hw_pbdma_gv11b_h_ - -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffff) << 10; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10) & 0x1fffff; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return 0x00040048 + i*8192; -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000003; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffff) << 3; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return 0x0004004c + i*8192; -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1f) << 16; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return 0x00040050 + i*8192; -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return 0x00040014 + i*8192; -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return 0x00040000 + i*8192; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return 0x00040054 + i*8192; -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return 0x00040058 + i*8192; -} -static inline u32 pbdma_get_r(u32 i) -{ - return 0x00040018 + i*8192; -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return 0x0004001c + i*8192; -} -static inline u32 pbdma_put_r(u32 i) -{ - return 0x0004005c + i*8192; -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return 0x00040060 + i*8192; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return 0x00040084 + i*8192; -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return 0x00040118 + i*8192; -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return 0x00040094 + i*8192; -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return 0x000400c0 + i*8192; -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfff) << 2; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2) & 0xfff; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16) & 0x7; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return 0x000400c8 + i*8192; -} -static inline u32 pbdma_method2_r(u32 i) -{ - return 0x000400d0 + i*8192; -} -static inline u32 pbdma_method3_r(u32 i) -{ - return 0x000400d8 + i*8192; -} -static inline u32 pbdma_data0_r(u32 i) -{ - return 0x000400c4 + i*8192; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return 0x00040030 + i*8192; -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xf) << 11; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000f; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffff) << 15; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffff; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0; -} -static inline u32 pbdma_status_r(u32 i) -{ - return 0x00040100 + i*8192; -} -static inline u32 pbdma_channel_r(u32 i) -{ - return 0x00040120 + i*8192; -} -static inline u32 pbdma_signature_r(u32 i) -{ - return 0x00040010 + i*8192; -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xface; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return 0x00040008 + i*8192; -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 pbdma_userd_target_sys_mem_coh_f(void) -{ - return 0x2; -} -static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) -{ - return 0x3; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffff) << 9; -} -static inline u32 pbdma_config_r(u32 i) -{ - return 0x000400f4 + i*8192; -} -static inline u32 pbdma_config_l2_evict_first_f(void) -{ - return 0x0; -} -static inline u32 pbdma_config_l2_evict_normal_f(void) -{ - return 0x1; -} -static inline u32 pbdma_config_l2_evict_last_f(void) -{ - return 0x2; -} -static inline u32 pbdma_config_ce_split_enable_f(void) -{ - return 0x0; -} -static inline u32 pbdma_config_ce_split_disable_f(void) -{ - return 0x10; -} -static inline u32 pbdma_config_auth_level_non_privileged_f(void) -{ - return 0x0; -} -static inline u32 pbdma_config_auth_level_privileged_f(void) -{ - return 0x100; -} -static inline u32 pbdma_config_userd_writeback_disable_f(void) -{ - return 0x0; -} -static inline u32 pbdma_config_userd_writeback_enable_f(void) -{ - return 0x1000; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return 0x0004000c + i*8192; -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return 0x000400e4 + i*8192; -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return 0x00040108 + i*8192; -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return 0x00040148 + i*8192; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return 0x0004010c + i*8192; -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return 0x0004014c + i*8192; -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return 0x0004013c + i*8192; -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008; -} -static inline u32 pbdma_allowed_syncpoints_r(u32 i) -{ - return 0x000400e8 + i*8192; -} -static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) -{ - return (v & 0x7fff) << 16; -} -static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r) -{ - return (r >> 16) & 0x7fff; -} -static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) -{ - return (v & 0x1) << 15; -} -static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) -{ - return (v & 0x7fff) << 0; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return 0x000400f8 + i*8192; -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000; -} -static inline u32 pbdma_target_r(u32 i) -{ - return 0x000400ac + i*8192; -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1f; -} -static inline u32 pbdma_target_eng_ctx_valid_true_f(void) -{ - return 0x10000; -} -static inline u32 pbdma_target_eng_ctx_valid_false_f(void) -{ - return 0x0; -} -static inline u32 pbdma_target_ce_ctx_valid_true_f(void) -{ - return 0x20000; -} -static inline u32 pbdma_target_ce_ctx_valid_false_f(void) -{ - return 0x0; -} -static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) -{ - return 0x0; -} -static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) -{ - return 0x1000000; -} -static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) -{ - return 0x2000000; -} -static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) -{ - return 0x3000000; -} -static inline u32 pbdma_target_should_send_tsg_event_true_f(void) -{ - return 0x20000000; -} -static inline u32 pbdma_target_should_send_tsg_event_false_f(void) -{ - return 0x0; -} -static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) -{ - return 0x80000000; -} -static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) -{ - return 0x0; -} -static inline u32 pbdma_set_channel_info_r(u32 i) -{ - return 0x000400fc + i*8192; -} -static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) -{ - return 0x0; -} -static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) -{ - return 0x1; -} -static inline u32 pbdma_set_channel_info_veid_f(u32 v) -{ - return (v & 0x3f) << 8; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h deleted file mode 100644 index 836c014b..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_perf_gv11b_h_ -#define _hw_perf_gv11b_h_ - -static inline u32 perf_pmasys_control_r(void) -{ - return 0x0024a000; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5) & 0x1; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x0024a070; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3) << 28; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28) & 0x3; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x0024a074; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffff) << 5; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x0024a078; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x0024a07c; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffff) << 5; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x0024a084; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x0024a088; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x0024a0a4; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pram_gv11b.h deleted file mode 100644 index da2d4d2e..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_pram_gv11b.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pram_gv11b_h_ -#define _hw_pram_gv11b_h_ - -static inline u32 pram_data032_r(u32 i) -{ - return 0x00700000 + i*4; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pri_ringmaster_gv11b.h deleted file mode 100644 index 835366c1..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_pri_ringmaster_gv11b.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringmaster_gv11b_h_ -#define _hw_pri_ringmaster_gv11b_h_ - -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004c; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return 0x3f << 0; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0) & 0x3f; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005c; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006c; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pri_ringstation_sys_gv11b.h deleted file mode 100644 index e192bd13..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_pri_ringstation_sys_gv11b.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_sys_gv11b_h_ -#define _hw_pri_ringstation_sys_gv11b_h_ - -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return 0x00122300 + i*4; -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return 0x7 << 0; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h deleted file mode 100644 index 4e30447c..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_proj_gv11b_h_ -#define _hw_proj_gv11b_h_ - -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200; -} -static inline u32 proj_fbpa_stride_v(void) -{ - return 0x00004000; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800; -} -static inline u32 proj_host_num_engines_v(void) -{ - return 0x00000004; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000003; -} -static inline u32 proj_litter_num_subctx_v(void) -{ - return 0x00000040; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000004; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000001; -} -static inline u32 proj_scal_litter_num_fbpas_v(void) -{ - return 0x00000001; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000001; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000002; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004; -} -static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) -{ - return 0x00000002; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h deleted file mode 100644 index 965f8663..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h +++ /dev/null @@ -1,825 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pwr_gv11b_h_ -#define _hw_pwr_gv11b_h_ - -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00c; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1) << 7; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1) << 7; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01c; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1) << 7; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1) << 16; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1) << 17; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1) << 18; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1) << 19; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1) << 20; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1) << 21; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1) << 22; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1) << 23; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04c; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1) & 0x7fff; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1 << 4; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1 << 6; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6) & 0x1; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1) << 20; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return 0x1 << 20; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20) & 0x1; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return 0x0010a180 + i*16; -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return 0x0010a184 + i*16; -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return 0x0010a188 + i*16; -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10c; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1 << 1; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1 << 2; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0) & 0x1ff; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9) & 0x1ff; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11c; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16c; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return 0x1 << 31; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return 0xf << 0; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0) & 0xf; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xe; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1f) << 8; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20c; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return 0x0010a1c0 + i*8; -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return 0x3f << 2; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return 0xff << 8; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1) << 25; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return 0x0010a1c4 + i*8; -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000; -} -static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) -{ - return 0x30000000; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ff; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48c; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return 0xff << 0; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return 0x0010a580 + i*4; -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return 0x0010a800 + i*4; -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000008; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return 0x0010a820 + i*4; -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000008; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4cc; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return 0x0010a504 + i*16; -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return 0x0010a508 + i*16; -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffff) << 0; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0) & 0x7fffffff; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return 0x0010a50c + i*16; -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return 0x3 << 0; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return 0x1 << 2; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return 0x0010a9f0 + i*8; -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return 0x0010a9f4 + i*8; -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return 0x0010aa30 + i*8; -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return 0x0010a5c0 + i*4; -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return 0x0010a450 + i*4; -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000c; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7ac; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return 0x0010a6c0 + i*4; -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return 0x0010a6e8 + i*4; -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return 0x0010a710 + i*4; -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return 0x0010a760 + i*4; -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return 0x0010ae00 + i*4; -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return 0x1 << 2; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h deleted file mode 100644 index bcbb7b81..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ /dev/null @@ -1,765 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ram_gv11b_h_ -#define _hw_ram_gv11b_h_ - -static inline u32 ram_in_ramfc_s(void) -{ - return 4096; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) -{ - return 0x2; -} -static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) -{ - return 0x3; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4; -} -static inline u32 ram_in_page_dir_base_vol_false_f(void) -{ - return 0x0; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return 0x1 << 4; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return 0x1 << 5; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1) << 11; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return 0x1 << 11; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8; -} -static inline u32 ram_in_engine_wfi_mode_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 ram_in_engine_wfi_mode_w(void) -{ - return 132; -} -static inline u32 ram_in_engine_wfi_mode_physical_v(void) -{ - return 0x00000000; -} -static inline u32 ram_in_engine_wfi_mode_virtual_v(void) -{ - return 0x00000001; -} -static inline u32 ram_in_engine_wfi_target_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 ram_in_engine_wfi_target_w(void) -{ - return 132; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) -{ - return 0x00000002; -} -static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) -{ - return 0x00000003; -} -static inline u32 ram_in_engine_wfi_target_local_mem_v(void) -{ - return 0x00000000; -} -static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 ram_in_engine_wfi_ptr_lo_w(void) -{ - return 132; -} -static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 ram_in_engine_wfi_ptr_hi_w(void) -{ - return 133; -} -static inline u32 ram_in_engine_wfi_veid_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 ram_in_engine_wfi_veid_w(void) -{ - return 134; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) -{ - return 136; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) -{ - return 137; -} -static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) -{ - return (v & 0x3) << (0 + i*0); -} -static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) -{ - return 0x00000040; -} -static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) -{ - return 0x00000000; -} -static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) -{ - return 0x00000001; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) -{ - return 0x00000002; -} -static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) -{ - return 0x00000003; -} -static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) -{ - return (v & 0x1) << (2 + i*0); -} -static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) -{ - return 0x00000040; -} -static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) -{ - return 0x00000001; -} -static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) -{ - return 0x00000000; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) -{ - return (v & 0x1) << (4 + i*0); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) -{ - return 0x00000040; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) -{ - return (v & 0x1) << (5 + i*0); -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) -{ - return 0x00000040; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) -{ - return (v & 0x1) << (10 + i*0); -} -static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) -{ - return 0x00000040; -} -static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) -{ - return 0x00000000; -} -static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) -{ - return 0x00000001; -} -static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) -{ - return (v & 0x1) << (11 + i*0); -} -static inline u32 ram_in_sc_big_page_size__size_1_v(void) -{ - return 0x00000040; -} -static inline u32 ram_in_sc_big_page_size_64kb_v(void) -{ - return 0x00000001; -} -static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) -{ - return (v & 0xfffff) << (12 + i*0); -} -static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) -{ - return 0x00000040; -} -static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) -{ - return (v & 0xffffffff) << (0 + i*0); -} -static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) -{ - return 0x00000040; -} -static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 ram_in_sc_page_dir_base_target_0_w(void) -{ - return 168; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) -{ - return 168; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) -{ - return 168; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) -{ - return 168; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) -{ - return (v & 0x1) << 10; -} -static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) -{ - return 168; -} -static inline u32 ram_in_sc_big_page_size_0_f(u32 v) -{ - return (v & 0x1) << 11; -} -static inline u32 ram_in_sc_big_page_size_0_w(void) -{ - return 168; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) -{ - return 168; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) -{ - return 169; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12; -} -static inline u32 ram_fc_sem_addr_hi_w(void) -{ - return 14; -} -static inline u32 ram_fc_sem_addr_lo_w(void) -{ - return 15; -} -static inline u32 ram_fc_sem_payload_lo_w(void) -{ - return 16; -} -static inline u32 ram_fc_sem_payload_hi_w(void) -{ - return 39; -} -static inline u32 ram_fc_sem_execute_w(void) -{ - return 17; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37; -} -static inline u32 ram_fc_allowed_syncpoints_w(void) -{ - return 58; -} -static inline u32 ram_fc_target_w(void) -{ - return 43; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0; -} -static inline u32 ram_fc_config_w(void) -{ - return 61; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62; -} -static inline u32 ram_fc_set_channel_info_w(void) -{ - return 63; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200; -} -static inline u32 ram_userd_put_w(void) -{ - return 16; -} -static inline u32 ram_userd_get_w(void) -{ - return 17; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19; -} -static inline u32 ram_userd_ref_threshold_w(void) -{ - return 20; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000010; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 ram_rl_entry_type_channel_v(void) -{ - return 0x00000000; -} -static inline u32 ram_rl_entry_type_tsg_v(void) -{ - return 0x00000001; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) -{ - return (v & 0x3) << 4; -} -static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) -{ - return 0x00000003; -} -static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) -{ - return (v & 0x3) << 6; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) -{ - return 0x00000000; -} -static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) -{ - return 0x00000001; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) -{ - return 0x00000002; -} -static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) -{ - return 0x00000003; -} -static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) -{ - return (v & 0xffffff) << 8; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) -{ - return (v & 0xf) << 16; -} -static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) -{ - return 0x00000003; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) -{ - return 0x00000080; -} -static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) -{ - return 0x00000000; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 ram_rl_entry_tsg_length_init_v(void) -{ - return 0x00000000; -} -static inline u32 ram_rl_entry_tsg_length_min_v(void) -{ - return 0x00000001; -} -static inline u32 ram_rl_entry_tsg_length_max_v(void) -{ - return 0x00000080; -} -static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) -{ - return 0x00000008; -} -static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) -{ - return 0x00000008; -} -static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) -{ - return 0x0000000c; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h deleted file mode 100644 index a3cfcf91..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_therm_gv11b_h_ -#define _hw_therm_gv11b_h_ - -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_timer_gv11b.h deleted file mode 100644 index 7d5750c2..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_timer_gv11b.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_timer_gv11b_h_ -#define _hw_timer_gv11b_h_ - -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return 0xffffff << 0; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0) & 0xffffff; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return 0x1 << 31; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908c; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h deleted file mode 100644 index 2e2ff6ba..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_top_gv11b_h_ -#define _hw_top_gv11b_h_ - -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245c; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454; -} -static inline u32 top_device_info_r(u32 i) -{ - return 0x00022700 + i*4; -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26) & 0xf; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21) & 0xf; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15) & 0x1f; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9) & 0x1f; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2) & 0x1fffffff; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0; -} -static inline u32 top_device_info_type_enum_copy2_v(void) -{ - return 0x00000003; -} -static inline u32 top_device_info_type_enum_copy2_f(void) -{ - return 0xc; -} -static inline u32 top_device_info_type_enum_lce_v(void) -{ - return 0x00000013; -} -static inline u32 top_device_info_type_enum_lce_f(void) -{ - return 0x4c; -} -static inline u32 top_device_info_engine_v(u32 r) -{ - return (r >> 5) & 0x1; -} -static inline u32 top_device_info_runlist_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 top_device_info_intr_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 top_device_info_reset_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002; -} -static inline u32 top_device_info_entry_data_v(void) -{ - return 0x00000001; -} -static inline u32 top_device_info_data_type_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 top_device_info_data_type_enum2_v(void) -{ - return 0x00000000; -} -static inline u32 top_device_info_data_inst_id_v(u32 r) -{ - return (r >> 26) & 0xf; -} -static inline u32 top_device_info_data_pri_base_v(u32 r) -{ - return (r >> 12) & 0xfff; -} -static inline u32 top_device_info_data_pri_base_align_v(void) -{ - return 0x0000000c; -} -static inline u32 top_device_info_data_fault_id_enum_v(u32 r) -{ - return (r >> 3) & 0x7f; -} -static inline u32 top_device_info_data_fault_id_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 top_device_info_data_fault_id_valid_v(void) -{ - return 0x00000001; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h deleted file mode 100644 index 8bcf163f..00000000 --- a/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_usermode_gv11b_h_ -#define _hw_usermode_gv11b_h_ - -static inline u32 usermode_cfg0_r(void) -{ - return 0x00810000; -} -static inline u32 usermode_cfg0_usermode_class_id_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 usermode_cfg0_usermode_class_id_value_v(void) -{ - return 0x0000c361; -} -static inline u32 usermode_time_0_r(void) -{ - return 0x00810080; -} -static inline u32 usermode_time_0_nsec_f(u32 v) -{ - return (v & 0x7ffffff) << 5; -} -static inline u32 usermode_time_1_r(void) -{ - return 0x00810084; -} -static inline u32 usermode_time_1_nsec_f(u32 v) -{ - return (v & 0x1fffffff) << 0; -} -static inline u32 usermode_notify_channel_pending_r(void) -{ - return 0x00810090; -} -static inline u32 usermode_notify_channel_pending_id_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -#endif diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index c0e46be3..85ff33d2 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -13,12 +13,13 @@ * more details. */ -#include - #include "gk20a/gk20a.h" + #include "gp10b/ltc_gp10b.h" -#include "gv11b/ltc_gv11b.h" -#include "hw_ltc_gv11b.h" + +#include "ltc_gv11b.h" + +#include /* * Sets the ZBC stencil for the passed index. diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 0111d6b3..65aad786 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B master * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,9 +16,12 @@ #include #include "gk20a/gk20a.h" + #include "gp10b/mc_gp10b.h" -#include "gv11b/mc_gv11b.h" -#include "hw_mc_gv11b.h" + +#include "mc_gv11b.h" + +#include static void mc_gv11b_intr_enable(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 7f104a6d..404ee921 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B MMU * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,10 +15,14 @@ #include #include + #include "gk20a/gk20a.h" + #include "gp10b/mm_gp10b.h" + #include "mm_gv11b.h" -#include "hw_fb_gv11b.h" + +#include static bool gv11b_mm_is_bar1_supported(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 1f36e59c..8fd6583e 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -1,7 +1,7 @@ /* * GV11B Tegra Platform Interface * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,17 +18,19 @@ #include #include #include -#include #include #include #include #include #include + +#include + #include "gk20a/platform_gk20a.h" #include "gk20a/gk20a.h" #include "platform_tegra.h" + #include "gr_gv11b.h" -#include "hw_gr_gv11b.h" /* * gv11b_tegra_get_clocks() diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 9ee1ed30..6b56dd21 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -15,12 +15,16 @@ #include /* for udelay */ #include + #include + #include "gk20a/gk20a.h" + #include "gp10b/pmu_gp10b.h" #include "pmu_gv11b.h" -#include "hw_pwr_gv11b.h" + +#include #define ALIGN_4KB 12 diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index b0d0a192..02683d8b 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -1,7 +1,7 @@ /* * Volta GPU series Subcontext * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,9 +18,11 @@ #include "gk20a/gk20a.h" #include "gk20a/semaphore_gk20a.h" + #include "gv11b/subctx_gv11b.h" -#include "gv11b/hw_ram_gv11b.h" -#include "gv11b/hw_ctxsw_prog_gv11b.h" + +#include +#include static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, struct mem_desc *inst_block); diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.c b/drivers/gpu/nvgpu/gv11b/therm_gv11b.c index 69d2a1fe..89520ead 100644 --- a/drivers/gpu/nvgpu/gv11b/therm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/therm_gv11b.c @@ -1,8 +1,7 @@ /* - * * GV11B Therm * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,8 +14,9 @@ */ #include "gk20a/gk20a.h" + #include "gp10b/therm_gp10b.h" -#include "hw_therm_gv11b.h" + #include "therm_gv11b.h" void gv11b_init_therm_ops(struct gpu_ops *gops) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h new file mode 100644 index 00000000..66571ae7 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_bus_gv11b_h_ +#define _hw_bus_gv11b_h_ + +static inline u32 bus_bar0_window_r(void) +{ + return 0x00001700; +} +static inline u32 bus_bar0_window_base_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 bus_bar0_window_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) +{ + return 0x2000000; +} +static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) +{ + return 0x3000000; +} +static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) +{ + return 0x00000010; +} +static inline u32 bus_bar1_block_r(void) +{ + return 0x00001704; +} +static inline u32 bus_bar1_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar1_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 bus_bar1_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar2_block_r(void) +{ + return 0x00001714; +} +static inline u32 bus_bar2_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar2_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 bus_bar2_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar1_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bar2_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bind_status_r(void) +{ + return 0x00001710; +} +static inline u32 bus_bind_status_bar1_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 bus_bind_status_bar1_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_outstanding_true_f(void) +{ + return 0x2; +} +static inline u32 bus_bind_status_bar2_pending_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 bus_bind_status_bar2_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_pending_busy_f(void) +{ + return 0x4; +} +static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 bus_bind_status_bar2_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_outstanding_true_f(void) +{ + return 0x8; +} +static inline u32 bus_intr_0_r(void) +{ + return 0x00001100; +} +static inline u32 bus_intr_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +static inline u32 bus_intr_en_0_r(void) +{ + return 0x00001140; +} +static inline u32 bus_intr_en_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_en_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_en_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h new file mode 100644 index 00000000..618c4806 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ccsr_gv11b_h_ +#define _hw_ccsr_gv11b_h_ + +static inline u32 ccsr_channel_inst_r(u32 i) +{ + return 0x00800000 + i*8; +} +static inline u32 ccsr_channel_inst__size_1_v(void) +{ + return 0x00000200; +} +static inline u32 ccsr_channel_inst_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 ccsr_channel_inst_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 ccsr_channel_inst_bind_false_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_bind_true_f(void) +{ + return 0x80000000; +} +static inline u32 ccsr_channel_r(u32 i) +{ + return 0x00800004 + i*8; +} +static inline u32 ccsr_channel__size_1_v(void) +{ + return 0x00000200; +} +static inline u32 ccsr_channel_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ccsr_channel_enable_set_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ccsr_channel_enable_set_true_f(void) +{ + return 0x400; +} +static inline u32 ccsr_channel_enable_clr_true_f(void) +{ + return 0x800; +} +static inline u32 ccsr_channel_status_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) +{ + return 0x400000; +} +static inline u32 ccsr_channel_eng_faulted_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 ccsr_channel_eng_faulted_reset_f(void) +{ + return 0x800000; +} +static inline u32 ccsr_channel_busy_v(u32 r) +{ + return (r >> 28) & 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h new file mode 100644 index 00000000..9f279207 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce_gv11b_h_ +#define _hw_ce_gv11b_h_ + +static inline u32 ce_intr_status_r(u32 i) +{ + return 0x00104410 + i*128; +} +static inline u32 ce_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h new file mode 100644 index 00000000..228bf5f2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ctxsw_prog_gv11b_h_ +#define _hw_ctxsw_prog_gv11b_h_ + +static inline u32 ctxsw_prog_fecs_header_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) +{ + return 0x00000011; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) +{ + return 0x00000012; +} +static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) +{ + return 0x00000021; +} +static inline u32 ctxsw_prog_main_image_patch_count_o(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_context_id_o(void) +{ + return 0x000000f0; +} +static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) +{ + return 0x00000014; +} +static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) +{ + return 0x00000018; +} +static inline u32 ctxsw_prog_main_image_zcull_o(void) +{ + return 0x0000001c; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) +{ + return 0x00000001; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_pm_o(void) +{ + return 0x00000028; +} +static inline u32 ctxsw_prog_main_image_pm_mode_m(void) +{ + return 0x7 << 0; +} +static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) +{ + return 0x7 << 3; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) +{ + return 0x8; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) +{ + return 0x0000002c; +} +static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) +{ + return 0x000000d0; +} +static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) +{ + return 0x000000d4; +} +static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) +{ + return 0x000000d8; +} +static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) +{ + return 0x000000dc; +} +static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) +{ + return 0x00000060; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) +{ + return 0x00000064; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) +{ + return 0x00000068; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) +{ + return 0x00000070; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) +{ + return 0x00000074; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) +{ + return 0x00000078; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) +{ + return 0x0000007c; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) +{ + return 0x600dc0de; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) +{ + return 0x000000b8; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) +{ + return 0x000000bc; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) +{ + return 0x000000c0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) +{ + return 0x000000c4; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) +{ + return 0x000000c8; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) +{ + return 0x000000cc; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) +{ + return 0x000000e0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) +{ + return 0x000000e4; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_local_image_ppc_info_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_local_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) +{ + return 0xad0becab; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) +{ + return 0x000000ec; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) +{ + return 0x000000a0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) +{ + return 2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) +{ + return 0x3 << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) +{ + return 0x2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) +{ + return 0x000000a4; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) +{ + return 0x000000a8; +} +static inline u32 ctxsw_prog_main_image_misc_options_o(void) +{ + return 0x0000003c; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) +{ + return 0x1 << 3; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) +{ + return 0x00000080; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) +{ + return 0x00000084; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) +{ + return 0x2; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h new file mode 100644 index 00000000..d2f22afa --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -0,0 +1,1485 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fb_gv11b_h_ +#define _hw_fb_gv11b_h_ + +static inline u32 fb_fbhub_num_active_ltcs_r(void) +{ + return 0x00100800; +} +static inline u32 fb_mmu_ctrl_r(void) +{ + return 0x00100c80; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) +{ + return 0x0; +} +static inline u32 fb_priv_mmu_phy_secure_r(void) +{ + return 0x00100ce4; +} +static inline u32 fb_mmu_invalidate_pdb_r(void) +{ + return 0x00100cb8; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_invalidate_r(void) +{ + return 0x00100cbc; +} +static inline u32 fb_mmu_invalidate_all_va_true_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_invalidate_replay_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_replay_f(u32 v) +{ + return (v & 0x7) << 3; +} +static inline u32 fb_mmu_invalidate_replay_m(void) +{ + return 0x7 << 3; +} +static inline u32 fb_mmu_invalidate_replay_v(u32 r) +{ + return (r >> 3) & 0x7; +} +static inline u32 fb_mmu_invalidate_replay_none_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_replay_start_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_invalidate_sys_membar_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_m(void) +{ + return 0x1 << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_invalidate_ack_s(void) +{ + return 2; +} +static inline u32 fb_mmu_invalidate_ack_f(u32 v) +{ + return (v & 0x3) << 7; +} +static inline u32 fb_mmu_invalidate_ack_m(void) +{ + return 0x3 << 7; +} +static inline u32 fb_mmu_invalidate_ack_v(u32 r) +{ + return (r >> 7) & 0x3; +} +static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) +{ + return 6; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) +{ + return (v & 0x3f) << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) +{ + return 0x3f << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) +{ + return (r >> 9) & 0x3f; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) +{ + return 5; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) +{ + return 0x1f << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) +{ + return 0x1 << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) +{ + return 0x100000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) +{ + return 0x7 << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) +{ + return (r >> 24) & 0x7; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) +{ + return 0x1000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) +{ + return 0x2000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) +{ + return 0x3000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) +{ + return 0x4000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) +{ + return 0x5000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) +{ + return 0x6000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) +{ + return 0x7000000; +} +static inline u32 fb_mmu_invalidate_trigger_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_trigger_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_invalidate_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_invalidate_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_invalidate_trigger_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_debug_wr_r(void) +{ + return 0x00100cc8; +} +static inline u32 fb_mmu_debug_wr_aperture_s(void) +{ + return 2; +} +static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_m(void) +{ + return 0x3 << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_debug_wr_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_wr_vol_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_debug_wr_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_rd_r(void) +{ + return 0x00100ccc; +} +static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_debug_rd_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_ctrl_r(void) +{ + return 0x00100cc4; +} +static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 fb_mmu_debug_ctrl_debug_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_r(void) +{ + return 0x00100cd0; +} +static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_vpr_info_fetch_false_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_fetch_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_niso_flush_sysmem_addr_r(void) +{ + return 0x00100c10; +} +static inline u32 fb_niso_intr_r(void) +{ + return 0x00100a20; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_r(u32 i) +{ + return 0x00100a24 + i*4; +} +static inline u32 fb_niso_intr_en__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_set_r(u32 i) +{ + return 0x00100a2c + i*4; +} +static inline u32 fb_niso_intr_en_set__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_r(u32 i) +{ + return 0x00100a34 + i*4; +} +static inline u32 fb_niso_intr_en_clr__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) +{ + return 0x00000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) +{ + return 0x00100e24 + i*20; +} +static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) +{ + return (r >> 1) & 0x3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x6; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) +{ + return 0x00100e28 + i*20; +} +static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_buffer_get_r(u32 i) +{ + return 0x00100e2c + i*20; +} +static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_yes_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_put_r(u32 i) +{ + return 0x00100e30 + i*20; +} +static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_size_r(u32 i) +{ + return 0x00100e34 + i*20; +} +static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) +{ + return 0x20000000; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_addr_lo_r(void) +{ + return 0x00100e4c; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_addr_hi_r(void) +{ + return 0x00100e50; +} +static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_inst_lo_r(void) +{ + return 0x00100e54; +} +static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) +{ + return (r >> 10) & 0x3; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_inst_hi_r(void) +{ + return 0x00100e58; +} +static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_info_r(void) +{ + return 0x00100e5c; +} +static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 fb_mmu_fault_info_client_v(u32 r) +{ + return (r >> 8) & 0x7f; +} +static inline u32 fb_mmu_fault_info_access_type_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 fb_mmu_fault_info_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_info_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_status_r(void) +{ + return 0x00100e60; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_replayable_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fb_mmu_fault_status_replayable_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_set_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 fb_mmu_fault_status_non_replayable_v(u32 r) +{ + return (r >> 9) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) +{ + return 0x200; +} +static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 fb_mmu_fault_status_replayable_error_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) +{ + return 0x400; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) +{ + return 0x1000; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_v(u32 r) +{ + return (r >> 13) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) +{ + return 0x2000; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_v(u32 r) +{ + return (r >> 14) & 0x1; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) +{ + return 0x4000; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 15; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) +{ + return 0x8000; +} +static inline u32 fb_mmu_fault_status_busy_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_status_busy_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_status_busy_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_busy_true_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_status_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_status_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_status_valid_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_status_valid_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_clear_f(void) +{ + return 0x80000000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h new file mode 100644 index 00000000..d68c823a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -0,0 +1,517 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fifo_gv11b_h_ +#define _hw_fifo_gv11b_h_ + +static inline u32 fifo_bar1_base_r(void) +{ + return 0x00002254; +} +static inline u32 fifo_bar1_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_bar1_base_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 fifo_bar1_base_valid_false_f(void) +{ + return 0x0; +} +static inline u32 fifo_bar1_base_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_userd_writeback_r(void) +{ + return 0x0000225c; +} +static inline u32 fifo_userd_writeback_timer_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_userd_writeback_timer_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_userd_writeback_timer_shorter_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_userd_writeback_timer_100us_v(void) +{ + return 0x00000064; +} +static inline u32 fifo_userd_writeback_timescale_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 fifo_userd_writeback_timescale_0_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_runlist_base_r(void) +{ + return 0x00002270; +} +static inline u32 fifo_runlist_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_runlist_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 fifo_runlist_r(void) +{ + return 0x00002274; +} +static inline u32 fifo_runlist_engine_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 fifo_eng_runlist_base_r(u32 i) +{ + return 0x00002280 + i*8; +} +static inline u32 fifo_eng_runlist_base__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fifo_eng_runlist_r(u32 i) +{ + return 0x00002284 + i*8; +} +static inline u32 fifo_eng_runlist__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fifo_eng_runlist_length_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fifo_eng_runlist_length_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 fifo_eng_runlist_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_pb_timeslice_r(u32 i) +{ + return 0x00002350 + i*4; +} +static inline u32 fifo_pb_timeslice_timeout_16_f(void) +{ + return 0x10; +} +static inline u32 fifo_pb_timeslice_timescale_0_f(void) +{ + return 0x0; +} +static inline u32 fifo_pb_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_pbdma_map_r(u32 i) +{ + return 0x00002390 + i*4; +} +static inline u32 fifo_intr_0_r(void) +{ + return 0x00002100; +} +static inline u32 fifo_intr_0_bind_error_pending_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_bind_error_reset_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_sched_error_pending_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_sched_error_reset_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_chsw_error_pending_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_chsw_error_reset_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_lb_error_pending_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_lb_error_reset_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_intr_0_runlist_event_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fifo_intr_0_channel_intr_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fifo_intr_en_0_r(void) +{ + return 0x00002140; +} +static inline u32 fifo_intr_en_0_sched_error_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fifo_intr_en_0_sched_error_m(void) +{ + return 0x1 << 8; +} +static inline u32 fifo_intr_en_1_r(void) +{ + return 0x00002528; +} +static inline u32 fifo_intr_bind_error_r(void) +{ + return 0x0000252c; +} +static inline u32 fifo_intr_sched_error_r(void) +{ + return 0x0000254c; +} +static inline u32 fifo_intr_sched_error_code_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) +{ + return 0x0000000a; +} +static inline u32 fifo_intr_chsw_error_r(void) +{ + return 0x0000256c; +} +static inline u32 fifo_gpc_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_hub_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_pbdma_id_r(void) +{ + return 0x000025a0; +} +static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_intr_runlist_r(void) +{ + return 0x00002a00; +} +static inline u32 fifo_fb_timeout_r(void) +{ + return 0x00002a04; +} +static inline u32 fifo_fb_timeout_period_m(void) +{ + return 0x3fffffff << 0; +} +static inline u32 fifo_fb_timeout_period_max_f(void) +{ + return 0x3fffffff; +} +static inline u32 fifo_error_sched_disable_r(void) +{ + return 0x0000262c; +} +static inline u32 fifo_sched_disable_r(void) +{ + return 0x00002630; +} +static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_sched_disable_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_sched_disable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_preempt_r(void) +{ + return 0x00002634; +} +static inline u32 fifo_preempt_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_preempt_type_channel_f(void) +{ + return 0x0; +} +static inline u32 fifo_preempt_type_tsg_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_preempt_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_preempt_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_engine_status_r(u32 i) +{ + return 0x00002640 + i*8; +} +static inline u32 fifo_engine_status__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 fifo_engine_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_engine_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_engine_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_engine_status_ctx_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_engine_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_engine_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_engine_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_faulted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fifo_engine_status_faulted_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_engine_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fifo_engine_status_engine_idle_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_engine_busy_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) +{ + return 0x8000; +} +static inline u32 fifo_pbdma_status_r(u32 i) +{ + return 0x00003080 + i*4; +} +static inline u32 fifo_pbdma_status__size_1_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_pbdma_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_pbdma_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_pbdma_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_pbdma_status_chan_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_pbdma_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_chsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_cfg0_r(void) +{ + return 0x00002004; +} +static inline u32 fifo_cfg0_num_pbdma_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) +{ + return (r >> 16) & 0xff; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h new file mode 100644 index 00000000..380f8824 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_flush_gv11b_h_ +#define _hw_flush_gv11b_h_ + +static inline u32 flush_l2_system_invalidate_r(void) +{ + return 0x00070004; +} +static inline u32 flush_l2_system_invalidate_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_system_invalidate_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_system_invalidate_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_r(void) +{ + return 0x00070010; +} +static inline u32 flush_l2_flush_dirty_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_flush_dirty_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_r(void) +{ + return 0x0007000c; +} +static inline u32 flush_l2_clean_comptags_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_clean_comptags_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_r(void) +{ + return 0x00070000; +} +static inline u32 flush_fb_flush_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_fb_flush_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_fb_flush_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_fb_flush_outstanding_true_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h new file mode 100644 index 00000000..280a048a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fuse_gv11b_h_ +#define _hw_fuse_gv11b_h_ + +static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) +{ + return 0x00021c38 + i*4; +} +static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) +{ + return 0x00021838 + i*4; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) +{ + return 0x00021944; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) +{ + return 0xff << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) +{ + return 0x00021948; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) +{ + return 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) +{ + return 0x0; +} +static inline u32 fuse_status_opt_fbio_r(void) +{ + return 0x00021c14; +} +static inline u32 fuse_status_opt_fbio_data_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fuse_status_opt_fbio_data_m(void) +{ + return 0xffff << 0; +} +static inline u32 fuse_status_opt_fbio_data_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) +{ + return 0x00021d70 + i*4; +} +static inline u32 fuse_status_opt_fbp_r(void) +{ + return 0x00021d38; +} +static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fuse_opt_ecc_en_r(void) +{ + return 0x00021228; +} +static inline u32 fuse_opt_feature_fuses_override_disable_r(void) +{ + return 0x000213f0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h new file mode 100644 index 00000000..1c523f87 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -0,0 +1,1477 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gmmu_gv11b_h_ +#define _hw_gmmu_gv11b_h_ + +static inline u32 gmmu_new_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_aperture_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_pde_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pde_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pde_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_pde__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_dual_pde_vol_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_vol_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde__size_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_new_pte__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_pte_valid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_valid_true_f(void) +{ + return 0x1; +} +static inline u32 gmmu_new_pte_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_privilege_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_privilege_true_f(void) +{ + return 0x20; +} +static inline u32 gmmu_new_pte_privilege_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_address_vid_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_vid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pte_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_aperture_video_memory_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_pte_read_only_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_read_only_true_f(void) +{ + return 0x40; +} +static inline u32 gmmu_new_pte_comptagline_f(u32 v) +{ + return (v & 0x3ffff) << 4; +} +static inline u32 gmmu_new_pte_comptagline_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_kind_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gmmu_new_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_f(u32 v) +{ + return (v & 0xff) << 4; +} +static inline u32 gmmu_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_kind_invalid_v(void) +{ + return 0x000000ff; +} +static inline u32 gmmu_pte_kind_pitch_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_pte_kind_z16_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_pte_kind_z16_2c_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) +{ + return 0x00000006; +} +static inline u32 gmmu_pte_kind_z16_2z_v(void) +{ + return 0x00000007; +} +static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) +{ + return 0x00000009; +} +static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) +{ + return 0x0000000a; +} +static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) +{ + return 0x0000000b; +} +static inline u32 gmmu_pte_kind_z16_2cz_v(void) +{ + return 0x00000036; +} +static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) +{ + return 0x00000037; +} +static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) +{ + return 0x00000038; +} +static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) +{ + return 0x00000039; +} +static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) +{ + return 0x0000005f; +} +static inline u32 gmmu_pte_kind_z16_4cz_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) +{ + return 0x0000000d; +} +static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) +{ + return 0x0000000e; +} +static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) +{ + return 0x0000000f; +} +static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_pte_kind_s8z24_v(void) +{ + return 0x00000011; +} +static inline u32 gmmu_pte_kind_s8z24_1z_v(void) +{ + return 0x00000012; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) +{ + return 0x00000013; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) +{ + return 0x00000014; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) +{ + return 0x00000015; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) +{ + return 0x00000016; +} +static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) +{ + return 0x00000017; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) +{ + return 0x00000018; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) +{ + return 0x00000019; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) +{ + return 0x0000001a; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) +{ + return 0x0000001b; +} +static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) +{ + return 0x0000001c; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) +{ + return 0x0000001d; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) +{ + return 0x0000001e; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) +{ + return 0x00000021; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) +{ + return 0x00000022; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) +{ + return 0x00000023; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) +{ + return 0x00000024; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) +{ + return 0x00000025; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) +{ + return 0x00000026; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) +{ + return 0x00000027; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) +{ + return 0x00000028; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) +{ + return 0x00000029; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) +{ + return 0x0000002e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) +{ + return 0x0000002f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) +{ + return 0x00000030; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) +{ + return 0x00000031; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) +{ + return 0x00000032; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) +{ + return 0x00000033; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) +{ + return 0x00000034; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) +{ + return 0x00000035; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) +{ + return 0x0000003a; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) +{ + return 0x0000003b; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) +{ + return 0x0000003c; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) +{ + return 0x0000003d; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) +{ + return 0x0000003e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) +{ + return 0x0000003f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) +{ + return 0x00000040; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) +{ + return 0x00000041; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) +{ + return 0x00000042; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) +{ + return 0x00000043; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) +{ + return 0x00000044; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) +{ + return 0x00000045; +} +static inline u32 gmmu_pte_kind_z24s8_v(void) +{ + return 0x00000046; +} +static inline u32 gmmu_pte_kind_z24s8_1z_v(void) +{ + return 0x00000047; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) +{ + return 0x00000048; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) +{ + return 0x00000049; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) +{ + return 0x0000004a; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) +{ + return 0x0000004b; +} +static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) +{ + return 0x0000004c; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) +{ + return 0x0000004d; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) +{ + return 0x0000004e; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) +{ + return 0x0000004f; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) +{ + return 0x00000050; +} +static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) +{ + return 0x00000051; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) +{ + return 0x00000052; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) +{ + return 0x00000053; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) +{ + return 0x00000054; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) +{ + return 0x00000055; +} +static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) +{ + return 0x00000056; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) +{ + return 0x00000057; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) +{ + return 0x00000058; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) +{ + return 0x00000059; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) +{ + return 0x0000005a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) +{ + return 0x0000005b; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) +{ + return 0x0000005c; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) +{ + return 0x0000005d; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) +{ + return 0x0000005e; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) +{ + return 0x00000063; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) +{ + return 0x00000064; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) +{ + return 0x00000065; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) +{ + return 0x00000066; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) +{ + return 0x00000067; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) +{ + return 0x00000068; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) +{ + return 0x00000069; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) +{ + return 0x0000006a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) +{ + return 0x0000006f; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) +{ + return 0x00000070; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) +{ + return 0x00000071; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) +{ + return 0x00000072; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) +{ + return 0x00000073; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) +{ + return 0x00000074; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) +{ + return 0x00000075; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) +{ + return 0x00000076; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) +{ + return 0x00000077; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) +{ + return 0x00000078; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) +{ + return 0x00000079; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) +{ + return 0x0000007a; +} +static inline u32 gmmu_pte_kind_zf32_v(void) +{ + return 0x0000007b; +} +static inline u32 gmmu_pte_kind_zf32_1z_v(void) +{ + return 0x0000007c; +} +static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) +{ + return 0x0000007d; +} +static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) +{ + return 0x0000007e; +} +static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) +{ + return 0x0000007f; +} +static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) +{ + return 0x00000080; +} +static inline u32 gmmu_pte_kind_zf32_2cs_v(void) +{ + return 0x00000081; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) +{ + return 0x00000082; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) +{ + return 0x00000083; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) +{ + return 0x00000084; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) +{ + return 0x00000085; +} +static inline u32 gmmu_pte_kind_zf32_2cz_v(void) +{ + return 0x00000086; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) +{ + return 0x00000087; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) +{ + return 0x00000088; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) +{ + return 0x00000089; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) +{ + return 0x0000008a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) +{ + return 0x0000008b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) +{ + return 0x0000008c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) +{ + return 0x0000008d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) +{ + return 0x0000008e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x0000008f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x00000090; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x00000091; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x00000092; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x00000097; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x00000098; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x00000099; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x0000009a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x0000009b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x0000009c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x0000009d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x0000009e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x0000009f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000a0; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000a1; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000a2; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000a3; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000a4; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000a5; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000a6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) +{ + return 0x000000a7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) +{ + return 0x000000a8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) +{ + return 0x000000a9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) +{ + return 0x000000aa; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x000000ab; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x000000ac; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x000000ad; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x000000ae; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x000000b3; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x000000b4; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x000000b5; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x000000b6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x000000b7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x000000b8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x000000b9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x000000ba; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x000000bb; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000bc; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000bd; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000be; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000bf; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000c0; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000c1; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000c2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) +{ + return 0x000000c3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) +{ + return 0x000000c4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) +{ + return 0x000000c5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) +{ + return 0x000000c6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) +{ + return 0x000000c7; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) +{ + return 0x000000c8; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) +{ + return 0x000000ce; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) +{ + return 0x000000cf; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) +{ + return 0x000000d0; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) +{ + return 0x000000d1; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) +{ + return 0x000000d2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) +{ + return 0x000000d3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) +{ + return 0x000000d4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) +{ + return 0x000000d5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) +{ + return 0x000000d6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) +{ + return 0x000000d7; +} +static inline u32 gmmu_pte_kind_generic_16bx2_v(void) +{ + return 0x000000fe; +} +static inline u32 gmmu_pte_kind_c32_2c_v(void) +{ + return 0x000000d8; +} +static inline u32 gmmu_pte_kind_c32_2cbr_v(void) +{ + return 0x000000d9; +} +static inline u32 gmmu_pte_kind_c32_2cba_v(void) +{ + return 0x000000da; +} +static inline u32 gmmu_pte_kind_c32_2cra_v(void) +{ + return 0x000000db; +} +static inline u32 gmmu_pte_kind_c32_2bra_v(void) +{ + return 0x000000dc; +} +static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) +{ + return 0x000000dd; +} +static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) +{ + return 0x000000de; +} +static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) +{ + return 0x000000cc; +} +static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) +{ + return 0x000000df; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) +{ + return 0x000000e0; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) +{ + return 0x000000e1; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) +{ + return 0x000000e2; +} +static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) +{ + return 0x000000e3; +} +static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) +{ + return 0x0000002c; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) +{ + return 0x000000e4; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) +{ + return 0x000000e5; +} +static inline u32 gmmu_pte_kind_c64_2c_v(void) +{ + return 0x000000e6; +} +static inline u32 gmmu_pte_kind_c64_2cbr_v(void) +{ + return 0x000000e7; +} +static inline u32 gmmu_pte_kind_c64_2cba_v(void) +{ + return 0x000000e8; +} +static inline u32 gmmu_pte_kind_c64_2cra_v(void) +{ + return 0x000000e9; +} +static inline u32 gmmu_pte_kind_c64_2bra_v(void) +{ + return 0x000000ea; +} +static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) +{ + return 0x000000eb; +} +static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) +{ + return 0x000000ec; +} +static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) +{ + return 0x000000cd; +} +static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) +{ + return 0x000000ed; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) +{ + return 0x000000ee; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) +{ + return 0x000000ef; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) +{ + return 0x000000f0; +} +static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) +{ + return 0x000000f1; +} +static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) +{ + return 0x0000002d; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) +{ + return 0x000000f2; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) +{ + return 0x000000f3; +} +static inline u32 gmmu_pte_kind_c128_2c_v(void) +{ + return 0x000000f4; +} +static inline u32 gmmu_pte_kind_c128_2cr_v(void) +{ + return 0x000000f5; +} +static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) +{ + return 0x000000f6; +} +static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) +{ + return 0x000000f7; +} +static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) +{ + return 0x000000f8; +} +static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) +{ + return 0x000000f9; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) +{ + return 0x000000fa; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) +{ + return 0x000000fb; +} +static inline u32 gmmu_pte_kind_x8c24_v(void) +{ + return 0x000000fc; +} +static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) +{ + return 0x000000fd; +} +static inline u32 gmmu_pte_kind_smsked_message_v(void) +{ + return 0x000000ca; +} +static inline u32 gmmu_pte_kind_smhost_message_v(void) +{ + return 0x000000cb; +} +static inline u32 gmmu_pte_kind_s8_v(void) +{ + return 0x0000002a; +} +static inline u32 gmmu_pte_kind_s8_2s_v(void) +{ + return 0x0000002b; +} +static inline u32 gmmu_fault_buf_size_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r) +{ + return (r >> 8) & 0x3; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) +{ + return 0; +} +static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_inst_hi_w(void) +{ + return 1; +} +static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void) +{ + return 2; +} +static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) +{ + return 2; +} +static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_addr_hi_w(void) +{ + return 3; +} +static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void) +{ + return 4; +} +static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void) +{ + return 5; +} +static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 gmmu_fault_buf_entry_engine_id_w(void) +{ + return 6; +} +static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gmmu_fault_buf_entry_fault_type_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void) +{ + return 0x80; +} +static inline u32 gmmu_fault_buf_entry_client_v(u32 r) +{ + return (r >> 8) & 0x7f; +} +static inline u32 gmmu_fault_buf_entry_client_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 gmmu_fault_buf_entry_access_type_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 gmmu_fault_buf_entry_gpc_id_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void) +{ + return 0x20000000; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) +{ + return 0x40000000; +} +static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gmmu_fault_buf_entry_valid_w(void) +{ + return 7; +} +static inline u32 gmmu_fault_buf_entry_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_buf_entry_valid_true_f(void) +{ + return 0x80000000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h new file mode 100644 index 00000000..656597ba --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -0,0 +1,3509 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gr_gv11b_h_ +#define _hw_gr_gv11b_h_ + +static inline u32 gr_intr_r(void) +{ + return 0x00400100; +} +static inline u32 gr_intr_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_notify_reset_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_semaphore_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_semaphore_reset_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_illegal_method_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_method_reset_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_notify_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_illegal_notify_reset_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_firmware_method_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_intr_firmware_method_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_firmware_method_reset_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_illegal_class_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_illegal_class_reset_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_fecs_error_pending_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_fecs_error_reset_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_class_error_pending_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_class_error_reset_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_exception_pending_f(void) +{ + return 0x200000; +} +static inline u32 gr_intr_exception_reset_f(void) +{ + return 0x200000; +} +static inline u32 gr_fecs_intr_r(void) +{ + return 0x00400144; +} +static inline u32 gr_class_error_r(void) +{ + return 0x00400110; +} +static inline u32 gr_class_error_code_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_intr_nonstall_r(void) +{ + return 0x00400120; +} +static inline u32 gr_intr_nonstall_trap_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_en_r(void) +{ + return 0x0040013c; +} +static inline u32 gr_exception_r(void) +{ + return 0x00400108; +} +static inline u32 gr_exception_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception1_r(void) +{ + return 0x00400118; +} +static inline u32 gr_exception1_gpc_0_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_exception2_r(void) +{ + return 0x0040011c; +} +static inline u32 gr_exception_en_r(void) +{ + return 0x00400138; +} +static inline u32 gr_exception_en_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception1_en_r(void) +{ + return 0x00400130; +} +static inline u32 gr_exception2_en_r(void) +{ + return 0x00400134; +} +static inline u32 gr_gpfifo_ctl_r(void) +{ + return 0x00400500; +} +static inline u32 gr_gpfifo_ctl_access_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpfifo_ctl_access_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpfifo_ctl_access_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpfifo_status_r(void) +{ + return 0x00400504; +} +static inline u32 gr_trapped_addr_r(void) +{ + return 0x00400704; +} +static inline u32 gr_trapped_addr_mthd_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 gr_trapped_addr_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 gr_trapped_data_lo_r(void) +{ + return 0x00400708; +} +static inline u32 gr_trapped_data_hi_r(void) +{ + return 0x0040070c; +} +static inline u32 gr_status_r(void) +{ + return 0x00400700; +} +static inline u32 gr_status_fe_method_upper_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_status_fe_method_lower_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_status_fe_method_lower_idle_v(void) +{ + return 0x00000000; +} +static inline u32 gr_status_fe_gi_v(u32 r) +{ + return (r >> 21) & 0x1; +} +static inline u32 gr_status_mask_r(void) +{ + return 0x00400610; +} +static inline u32 gr_status_1_r(void) +{ + return 0x00400604; +} +static inline u32 gr_status_2_r(void) +{ + return 0x00400608; +} +static inline u32 gr_engine_status_r(void) +{ + return 0x0040060c; +} +static inline u32 gr_engine_status_value_busy_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_be0_becs_be_exception_r(void) +{ + return 0x00410204; +} +static inline u32 gr_pri_be0_becs_be_exception_en_r(void) +{ + return 0x00410208; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) +{ + return 0x00502c94; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_activity_0_r(void) +{ + return 0x00400380; +} +static inline u32 gr_activity_1_r(void) +{ + return 0x00400384; +} +static inline u32 gr_activity_2_r(void) +{ + return 0x00400388; +} +static inline u32 gr_activity_4_r(void) +{ + return 0x00400390; +} +static inline u32 gr_activity_4_gpc0_s(void) +{ + return 3; +} +static inline u32 gr_activity_4_gpc0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_activity_4_gpc0_m(void) +{ + return 0x7 << 0; +} +static inline u32 gr_activity_4_gpc0_v(u32 r) +{ + return (r >> 0) & 0x7; +} +static inline u32 gr_activity_4_gpc0_empty_v(void) +{ + return 0x00000000; +} +static inline u32 gr_activity_4_gpc0_preempted_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pri_gpc0_gcc_dbg_r(void) +{ + return 0x00501000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_r(void) +{ + return 0x00419000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) +{ + return 0x0050433c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) +{ + return 0x00419b3c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_sked_activity_r(void) +{ + return 0x00407054; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) +{ + return 0x00502c80; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) +{ + return 0x00502c84; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) +{ + return 0x00502c88; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) +{ + return 0x00502c8c; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x00504500; +} +static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x00504d00; +} +static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00501d00; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) +{ + return 0x0041ac80; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) +{ + return 0x0041ac84; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) +{ + return 0x0041ac88; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) +{ + return 0x0041ac8c; +} +static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x0041c500; +} +static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x0041cd00; +} +static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00419d00; +} +static inline u32 gr_pri_be0_becs_be_activity0_r(void) +{ + return 0x00410200; +} +static inline u32 gr_pri_be1_becs_be_activity0_r(void) +{ + return 0x00410600; +} +static inline u32 gr_pri_bes_becs_be_activity0_r(void) +{ + return 0x00408a00; +} +static inline u32 gr_pri_ds_mpipe_status_r(void) +{ + return 0x00405858; +} +static inline u32 gr_pri_fe_go_idle_info_r(void) +{ + return 0x00404194; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) +{ + return 0x00504238; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) +{ + return 0x00504358; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) +{ + return 0x005042c4; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) +{ + return 0x0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) +{ + return 0x2; +} +static inline u32 gr_pri_be0_crop_status1_r(void) +{ + return 0x00410134; +} +static inline u32 gr_pri_bes_crop_status1_r(void) +{ + return 0x00408934; +} +static inline u32 gr_pri_be0_zrop_status_r(void) +{ + return 0x00410048; +} +static inline u32 gr_pri_be0_zrop_status2_r(void) +{ + return 0x0041004c; +} +static inline u32 gr_pri_bes_zrop_status_r(void) +{ + return 0x00408848; +} +static inline u32 gr_pri_bes_zrop_status2_r(void) +{ + return 0x0040884c; +} +static inline u32 gr_pipe_bundle_address_r(void) +{ + return 0x00400200; +} +static inline u32 gr_pipe_bundle_address_value_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pipe_bundle_address_veid_f(u32 v) +{ + return (v & 0x3f) << 20; +} +static inline u32 gr_pipe_bundle_address_veid_w(void) +{ + return 0; +} +static inline u32 gr_pipe_bundle_data_r(void) +{ + return 0x00400204; +} +static inline u32 gr_pipe_bundle_config_r(void) +{ + return 0x00400208; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fe_hww_esr_r(void) +{ + return 0x00404000; +} +static inline u32 gr_fe_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_fe_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) +{ + return 0x00419ea8; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) +{ + return 0x00419eac; +} +static inline u32 gr_fe_go_idle_timeout_r(void) +{ + return 0x00404154; +} +static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) +{ + return 0x1800; +} +static inline u32 gr_fe_object_table_r(u32 i) +{ + return 0x00404200 + i*4; +} +static inline u32 gr_fe_object_table_nvclass_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fe_tpc_fs_r(u32 i) +{ + return 0x0040a200 + i*4; +} +static inline u32 gr_pri_mme_shadow_raw_index_r(void) +{ + return 0x00404488; +} +static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pri_mme_shadow_raw_data_r(void) +{ + return 0x0040448c; +} +static inline u32 gr_mme_hww_esr_r(void) +{ + return 0x00404490; +} +static inline u32 gr_mme_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_mme_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_memfmt_hww_esr_r(void) +{ + return 0x00404600; +} +static inline u32 gr_memfmt_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_memfmt_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fecs_cpuctl_r(void) +{ + return 0x00409100; +} +static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_cpuctl_alias_r(void) +{ + return 0x00409130; +} +static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_dmactl_r(void) +{ + return 0x0040910c; +} +static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_fecs_os_r(void) +{ + return 0x00409080; +} +static inline u32 gr_fecs_idlestate_r(void) +{ + return 0x0040904c; +} +static inline u32 gr_fecs_mailbox0_r(void) +{ + return 0x00409040; +} +static inline u32 gr_fecs_mailbox1_r(void) +{ + return 0x00409044; +} +static inline u32 gr_fecs_irqstat_r(void) +{ + return 0x00409008; +} +static inline u32 gr_fecs_irqmode_r(void) +{ + return 0x0040900c; +} +static inline u32 gr_fecs_irqmask_r(void) +{ + return 0x00409018; +} +static inline u32 gr_fecs_irqdest_r(void) +{ + return 0x0040901c; +} +static inline u32 gr_fecs_curctx_r(void) +{ + return 0x00409050; +} +static inline u32 gr_fecs_nxtctx_r(void) +{ + return 0x00409054; +} +static inline u32 gr_fecs_engctl_r(void) +{ + return 0x004090a4; +} +static inline u32 gr_fecs_debug1_r(void) +{ + return 0x00409090; +} +static inline u32 gr_fecs_debuginfo_r(void) +{ + return 0x00409094; +} +static inline u32 gr_fecs_icd_cmd_r(void) +{ + return 0x00409200; +} +static inline u32 gr_fecs_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 gr_fecs_icd_rdata_r(void) +{ + return 0x0040920c; +} +static inline u32 gr_fecs_imemc_r(u32 i) +{ + return 0x00409180 + i*16; +} +static inline u32 gr_fecs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_imemd_r(u32 i) +{ + return 0x00409184 + i*16; +} +static inline u32 gr_fecs_imemt_r(u32 i) +{ + return 0x00409188 + i*16; +} +static inline u32 gr_fecs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_dmemc_r(u32 i) +{ + return 0x004091c0 + i*8; +} +static inline u32 gr_fecs_dmemc_offs_s(void) +{ + return 6; +} +static inline u32 gr_fecs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 gr_fecs_dmemc_offs_v(u32 r) +{ + return (r >> 2) & 0x3f; +} +static inline u32 gr_fecs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_dmemd_r(u32 i) +{ + return 0x004091c4 + i*8; +} +static inline u32 gr_fecs_dmatrfbase_r(void) +{ + return 0x00409110; +} +static inline u32 gr_fecs_dmatrfmoffs_r(void) +{ + return 0x00409114; +} +static inline u32 gr_fecs_dmatrffboffs_r(void) +{ + return 0x0040911c; +} +static inline u32 gr_fecs_dmatrfcmd_r(void) +{ + return 0x00409118; +} +static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_fecs_bootvec_r(void) +{ + return 0x00409104; +} +static inline u32 gr_fecs_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_falcon_hwcfg_r(void) +{ + return 0x00409108; +} +static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) +{ + return 0x0041a108; +} +static inline u32 gr_fecs_falcon_rm_r(void) +{ + return 0x00409084; +} +static inline u32 gr_fecs_current_ctx_r(void) +{ + return 0x00409b00; +} +static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_current_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_current_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_current_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_current_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 gr_fecs_current_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_current_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_current_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_current_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_current_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_method_data_r(void) +{ + return 0x00409500; +} +static inline u32 gr_fecs_method_push_r(void) +{ + return 0x00409504; +} +static inline u32 gr_fecs_method_push_adr_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) +{ + return 0x00000003; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) +{ + return 0x3; +} +static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) +{ + return 0x00000009; +} +static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) +{ + return 0x00000015; +} +static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) +{ + return 0x00000016; +} +static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) +{ + return 0x00000025; +} +static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) +{ + return 0x00000030; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) +{ + return 0x00000031; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) +{ + return 0x00000032; +} +static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) +{ + return 0x00000038; +} +static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) +{ + return 0x00000039; +} +static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) +{ + return 0x21; +} +static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) +{ + return 0x0000001a; +} +static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) +{ + return 0x00000004; +} +static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) +{ + return 0x0000003a; +} +static inline u32 gr_fecs_host_int_status_r(void) +{ + return 0x00409c18; +} +static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_host_int_clear_r(void) +{ + return 0x00409c20; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_r(void) +{ + return 0x00409c24; +} +static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) +{ + return 0x10000; +} +static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) +{ + return 0x20000; +} +static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) +{ + return 0x40000; +} +static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) +{ + return 0x80000; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) +{ + return 0x00409614; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) +{ + return 0x10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) +{ + return 0x20; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) +{ + return 0x40; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) +{ + return 0x100; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) +{ + return 0x200; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) +{ + return 0x400; +} +static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) +{ + return 0x0040960c; +} +static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) +{ + return 0x00409800 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) +{ + return 0x00000001; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) +{ + return 0x00000002; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) +{ + return 0x004098c0 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) +{ + return 0x00409840 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_fs_r(void) +{ + return 0x00409604; +} +static inline u32 gr_fecs_fs_num_available_gpcs_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_fs_num_available_fbps_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_m(void) +{ + return 0x1f << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_fecs_cfg_r(void) +{ + return 0x00409620; +} +static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_fecs_rc_lanes_r(void) +{ + return 0x00409880; +} +static inline u32 gr_fecs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_fecs_ctxsw_status_1_r(void) +{ + return 0x00409400; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_adr_r(void) +{ + return 0x00409a24; +} +static inline u32 gr_fecs_new_ctx_r(void) +{ + return 0x00409b04; +} +static inline u32 gr_fecs_new_ctx_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_new_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_new_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_new_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_new_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_new_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_new_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_new_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_new_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_ptr_r(void) +{ + return 0x00409a0c; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_arb_ctx_cmd_r(void) +{ + return 0x00409a10; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) +{ + return 5; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) +{ + return 0x00409c00; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) +{ + return 0x00502c04; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) +{ + return 0x00502400; +} +static inline u32 gr_fecs_ctxsw_idlestate_r(void) +{ + return 0x00409420; +} +static inline u32 gr_fecs_feature_override_ecc_r(void) +{ + return 0x00409658; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) +{ + return 0x00502420; +} +static inline u32 gr_rstr2d_gpc_map_r(u32 i) +{ + return 0x0040780c + i*4; +} +static inline u32 gr_rstr2d_map_table_cfg_r(void) +{ + return 0x004078bc; +} +static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_hww_esr_r(void) +{ + return 0x00406018; +} +static inline u32 gr_pd_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pd_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) +{ + return 0x00406028 + i*4; +} +static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) +{ + return (v & 0xf) << 24; +} +static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) +{ + return (v & 0xf) << 28; +} +static inline u32 gr_pd_ab_dist_cfg0_r(void) +{ + return 0x004064c0; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) +{ + return 0x0; +} +static inline u32 gr_pd_ab_dist_cfg1_r(void) +{ + return 0x004064c4; +} +static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) +{ + return 0xffff; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) +{ + return 0x00000080; +} +static inline u32 gr_pd_ab_dist_cfg2_r(void) +{ + return 0x004064c8; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) +{ + return (v & 0x1fff) << 0; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) +{ + return 0x00000380; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) +{ + return (v & 0x1fff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) +{ + return 0x00000302; +} +static inline u32 gr_pd_dist_skip_table_r(u32 i) +{ + return 0x004064d0 + i*4; +} +static inline u32 gr_pd_dist_skip_table__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_ds_debug_r(void) +{ + return 0x00405800; +} +static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) +{ + return 0x8000000; +} +static inline u32 gr_ds_zbc_color_r_r(void) +{ + return 0x00405804; +} +static inline u32 gr_ds_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_g_r(void) +{ + return 0x00405808; +} +static inline u32 gr_ds_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_b_r(void) +{ + return 0x0040580c; +} +static inline u32 gr_ds_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_a_r(void) +{ + return 0x00405810; +} +static inline u32 gr_ds_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_r(void) +{ + return 0x00405814; +} +static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) +{ + return (v & 0x7f) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) +{ + return 0x00000002; +} +static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) +{ + return 0x00000004; +} +static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) +{ + return 0x00000028; +} +static inline u32 gr_ds_zbc_z_r(void) +{ + return 0x00405818; +} +static inline u32 gr_ds_zbc_z_val_s(void) +{ + return 32; +} +static inline u32 gr_ds_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_z_val_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_ds_zbc_z_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_ds_zbc_z_val__init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_ds_zbc_z_val__init_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_r(void) +{ + return 0x0040581c; +} +static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_tbl_index_r(void) +{ + return 0x00405820; +} +static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_ds_zbc_tbl_ld_r(void) +{ + return 0x00405824; +} +static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_tga_constraintlogic_beta_r(void) +{ + return 0x00405830; +} +static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) +{ + return 0x0040585c; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_ds_hww_esr_r(void) +{ + return 0x00405840; +} +static inline u32 gr_ds_hww_esr_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_esr_2_r(void) +{ + return 0x00405848; +} +static inline u32 gr_ds_hww_esr_2_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_2_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_2_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_report_mask_r(void) +{ + return 0x00405844; +} +static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) +{ + return 0x2; +} +static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) +{ + return 0x8; +} +static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) +{ + return 0x10; +} +static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) +{ + return 0x20; +} +static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) +{ + return 0x40; +} +static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) +{ + return 0x80; +} +static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) +{ + return 0x100; +} +static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) +{ + return 0x200; +} +static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) +{ + return 0x400; +} +static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) +{ + return 0x800; +} +static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) +{ + return 0x1000; +} +static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) +{ + return 0x20000; +} +static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) +{ + return 0x80000; +} +static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) +{ + return 0x100000; +} +static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) +{ + return 0x200000; +} +static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_ds_hww_report_mask_2_r(void) +{ + return 0x0040584c; +} +static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) +{ + return 0x00405870 + i*4; +} +static inline u32 gr_scc_bundle_cb_base_r(void) +{ + return 0x00408004; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_bundle_cb_size_r(void) +{ + return 0x00408008; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) +{ + return 0x00000030; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_pagepool_base_r(void) +{ + return 0x0040800c; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_pagepool_r(void) +{ + return 0x00408010; +} +static inline u32 gr_scc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) +{ + return 0x00000200; +} +static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_pagepool_max_valid_pages_s(void) +{ + return 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) +{ + return (v & 0x3ff) << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_m(void) +{ + return 0x3ff << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) +{ + return (r >> 10) & 0x3ff; +} +static inline u32 gr_scc_pagepool_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_init_r(void) +{ + return 0x0040802c; +} +static inline u32 gr_scc_init_ram_trigger_f(void) +{ + return 0x1; +} +static inline u32 gr_scc_hww_esr_r(void) +{ + return 0x00408030; +} +static inline u32 gr_scc_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_scc_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_sked_hww_esr_r(void) +{ + return 0x00407020; +} +static inline u32 gr_sked_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_cwd_fs_r(void) +{ + return 0x00405b00; +} +static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) +{ + return 0x00405b60 + i*4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_cwd_sm_id_r(u32 i) +{ + return 0x00405ba0 + i*4; +} +static inline u32 gr_cwd_sm_id__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpc0_fs_gpc_r(void) +{ + return 0x00502608; +} +static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_gpc0_cfg_r(void) +{ + return 0x00502620; +} +static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpccs_rc_lanes_r(void) +{ + return 0x00502880; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_rc_lane_size_r(void) +{ + return 0x00502910; +} +static inline u32 gr_gpccs_rc_lane_size_v_s(void) +{ + return 24; +} +static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_m(void) +{ + return 0xffffff << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_zcull_fs_r(void) +{ + return 0x00500910; +} +static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_gpc0_zcull_ram_addr_r(void) +{ + return 0x00500914; +} +static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) +{ + return 0x00500918; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) +{ + return 0x00800000; +} +static inline u32 gr_gpc0_zcull_total_ram_size_r(void) +{ + return 0x00500920; +} +static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) +{ + return 0x00500a04 + i*32; +} +static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) +{ + return 0x00000040; +} +static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) +{ + return 0x00000010; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) +{ + return 0x00500c10 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) +{ + return 0x00500c30 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) +{ + return 0x00504088; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) +{ + return 0x00504608; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_r(void) +{ + return 0x00504330; +} +static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) +{ + return (r >> 8) & 0xfff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) +{ + return (r >> 20) & 0xfff; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) +{ + return 0x00503018; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) +{ + return 0x005030c0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) +{ + return 0x00001100; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) +{ + return 0x005030f4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) +{ + return 0x005030e4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) +{ + return 0x005030f8; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) +{ + return 0x005030f0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) +{ + return 0x00419e00; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) +{ + return 0x00419e04; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) +{ + return 21; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) +{ + return (v & 0x1fffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) +{ + return 0x1fffff << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) +{ + return (r >> 0) & 0x1fffff; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) +{ + return 0x80; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpccs_falcon_addr_r(void) +{ + return 0x0041a0ac; +} +static inline u32 gr_gpccs_falcon_addr_lsb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_msb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_m(void) +{ + return 0x3f << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) +{ + return (r >> 6) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_ext_s(void) +{ + return 12; +} +static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_m(void) +{ + return 0xfff << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_gpccs_cpuctl_r(void) +{ + return 0x0041a100; +} +static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpccs_dmactl_r(void) +{ + return 0x0041a10c; +} +static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpccs_imemc_r(u32 i) +{ + return 0x0041a180 + i*16; +} +static inline u32 gr_gpccs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_imemd_r(u32 i) +{ + return 0x0041a184 + i*16; +} +static inline u32 gr_gpccs_imemt_r(u32 i) +{ + return 0x0041a188 + i*16; +} +static inline u32 gr_gpccs_imemt__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_gpccs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpccs_dmemc_r(u32 i) +{ + return 0x0041a1c0 + i*8; +} +static inline u32 gr_gpccs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_dmemd_r(u32 i) +{ + return 0x0041a1c4 + i*8; +} +static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) +{ + return 0x0041a800 + i*4; +} +static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) +{ + return 0x00418e24; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) +{ + return 32; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) +{ + return 0x00418e28; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) +{ + return 11; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) +{ + return 0x7ff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) +{ + return (r >> 0) & 0x7ff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) +{ + return 0x00000030; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) +{ + return 0x30; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) +{ + return 0x005001dc; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) +{ + return 0x00000170; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) +{ + return 0x005001d8; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) +{ + return 0x004181e4; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) +{ + return 0x0041befc; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) +{ + return 0x00418ea0 + i*4; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) +{ + return 0x00418010 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) +{ + return 0x0041804c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) +{ + return 0x00418088 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) +{ + return 0x004180c4 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) +{ + return 0x00418100; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) +{ + return 0x00418110 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) +{ + return 0x0041814c; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) +{ + return 0x0041815c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) +{ + return 0x00418198; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) +{ + return 0x00418810; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) +{ + return 0x0000000c; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_crstr_gpc_map_r(u32 i) +{ + return 0x00418b08 + i*4; +} +static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) +{ + return (v & 0x1f) << 5; +} +static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) +{ + return (v & 0x1f) << 10; +} +static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) +{ + return (v & 0x1f) << 20; +} +static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) +{ + return (v & 0x1f) << 25; +} +static inline u32 gr_crstr_map_table_cfg_r(void) +{ + return 0x00418bb8; +} +static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) +{ + return 0x00418980 + i*4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_gpm_pd_cfg_r(void) +{ + return 0x00418c6c; +} +static inline u32 gr_gpcs_gcc_pagepool_base_r(void) +{ + return 0x00419004; +} +static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_gcc_pagepool_r(void) +{ + return 0x00419008; +} +static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) +{ + return 0x0041980c; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) +{ + return 0x00419848; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) +{ + return 0x00419c00; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) +{ + return 0x00419c2c; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_r(void) +{ + return 0x00419f28; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +{ + return 0x200; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +{ + return 0x800; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_r(void) +{ + return 0x00419f2c; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) +{ + return 0x00419d0c; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) +{ + return 0x0041ac94; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) +{ + return 0x00504704; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) +{ + return 0x00504708; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) +{ + return 0x00504710; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) +{ + return 0x00504718; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_bpt_pause_mask_r(void) +{ + return 0x00419f10; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) +{ + return 0x00504700; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_r(void) +{ + return 0x00419f34; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) +{ + return 0x00504734; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) +{ + return 0x00504730; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) +{ + return 0xff << 16; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) +{ + return 0xf << 24; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) +{ + return 0x00504738; +} +static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) +{ + return 0x005043a0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) +{ + return 0x00419ba0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) +{ + return 0x005043b0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) +{ + return 0x00419bb0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) +{ + return 0x0041be08; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) +{ + return 0x4; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) +{ + return 0x0041bf00 + i*4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) +{ + return 0x0041bfd0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) +{ + return (v & 0x7) << 21; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) +{ + return 0x0041bfd4; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) +{ + return 0x0041bfb0 + i*4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) +{ + return 0x00000005; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_bes_zrop_settings_r(void) +{ + return 0x00408850; +} +static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_be0_crop_debug3_r(void) +{ + return 0x00410108; +} +static inline u32 gr_bes_crop_debug3_r(void) +{ + return 0x00408908; +} +static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_bes_crop_settings_r(void) +{ + return 0x00408958; +} +static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) +{ + return 0x000000c0; +} +static inline u32 gr_zcull_subregion_qty_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fe_pwr_mode_r(void) +{ + return 0x00404170; +} +static inline u32 gr_fe_pwr_mode_mode_auto_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) +{ + return 0x2; +} +static inline u32 gr_fe_pwr_mode_req_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_fe_pwr_mode_req_send_f(void) +{ + return 0x10; +} +static inline u32 gr_fe_pwr_mode_req_done_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) +{ + return 0x00418880; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) +{ + return 0x3 << 3; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) +{ + return 0x3 << 5; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) +{ + return 0x00418890; +} +static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) +{ + return 0x00418894; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) +{ + return 0x004188b0; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) +{ + return 0x004188b4; +} +static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) +{ + return 0x004188b8; +} +static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) +{ + return 0x004188ac; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_r(void) +{ + return 0x00419f04; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_fe_gfxp_wfi_timeout_r(void) +{ + return 0x004041c0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) +{ + return 0x00419bd8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) +{ + return 0x7 << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) +{ + return 0x00419ba4; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) +{ + return 0x3 << 11; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) +{ + return 0x1000; +} +static inline u32 gr_gpcs_tc_debug0_r(void) +{ + return 0x00418708; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) +{ + return 0x1ff << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h new file mode 100644 index 00000000..6968c699 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -0,0 +1,593 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ltc_gv11b_h_ +#define _hw_ltc_gv11b_h_ + +static inline u32 ltc_pltcg_base_v(void) +{ + return 0x00140000; +} +static inline u32 ltc_pltcg_extent_v(void) +{ + return 0x0017ffff; +} +static inline u32 ltc_ltc0_ltss_v(void) +{ + return 0x00140200; +} +static inline u32 ltc_ltc0_lts0_v(void) +{ + return 0x00140400; +} +static inline u32 ltc_ltcs_ltss_v(void) +{ + return 0x0017e200; +} +static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) +{ + return 0x00140518; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) +{ + return 0x0017e318; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) +{ + return 0x1 << 15; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) +{ + return 0x00140494; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) +{ + return (r >> 16) & 0x3; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) +{ + return 0x00000000; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) +{ + return 0x00000002; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) +{ + return 0x0017e26c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) +{ + return 0x2; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) +{ + return 0x4; +} +static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) +{ + return 0x0017e270; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) +{ + return 0x0017e274; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) +{ + return 0x0003ffff; +} +static inline u32 ltc_ltcs_ltss_cbc_base_r(void) +{ + return 0x0017e278; +} +static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) +{ + return (r >> 0) & 0x3ffffff; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) +{ + return 0x0017e27c; +} +static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) +{ + return 0x0017e000; +} +static inline u32 ltc_ltcs_ltss_cbc_param_r(void) +{ + return 0x0017e280; +} +static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) +{ + return (r >> 28) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) +{ + return 0x0017e3f4; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) +{ + return 0x0017e2ac; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) +{ + return 0x0017e338; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) +{ + return 0x0017e33c + i*4; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) +{ + return 0x0017e34c; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) +{ + return 32; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) +{ + return 0x0017e204; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) +{ + return 8; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) +{ + return 0x0017e2b0; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_g_elpg_r(void) +{ + return 0x0017e214; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_r(void) +{ + return 0x00140214; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_r(void) +{ + return 0x00142214; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_intr_r(void) +{ + return 0x0017e20c; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) +{ + return 0x100; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) +{ + return 0x200; +} +static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) +{ + return 0x1 << 20; +} +static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) +{ + return 0x1 << 30; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 ltc_ltc0_lts0_intr_r(void) +{ + return 0x0014040c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) +{ + return 0x0014051c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) +{ + return 0xff << 16; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) +{ + return 0x0017e2a0; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) +{ + return 0x0017e2a4; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) +{ + return 0x10000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) +{ + return 0x001402a0; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) +{ + return 0x001402a4; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) +{ + return 0x001422a0; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) +{ + return 0x001422a4; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) +{ + return 0x0014058c; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h new file mode 100644 index 00000000..98bec43a --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_mc_gv11b_h_ +#define _hw_mc_gv11b_h_ + +static inline u32 mc_boot_0_r(void) +{ + return 0x00000000; +} +static inline u32 mc_boot_0_architecture_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 mc_boot_0_implementation_v(u32 r) +{ + return (r >> 20) & 0xf; +} +static inline u32 mc_boot_0_major_revision_v(u32 r) +{ + return (r >> 4) & 0xf; +} +static inline u32 mc_boot_0_minor_revision_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 mc_intr_r(u32 i) +{ + return 0x00000100 + i*4; +} +static inline u32 mc_intr_pfifo_pending_f(void) +{ + return 0x100; +} +static inline u32 mc_intr_hub_pending_f(void) +{ + return 0x200; +} +static inline u32 mc_intr_pgraph_pending_f(void) +{ + return 0x1000; +} +static inline u32 mc_intr_pmu_pending_f(void) +{ + return 0x1000000; +} +static inline u32 mc_intr_ltc_pending_f(void) +{ + return 0x2000000; +} +static inline u32 mc_intr_priv_ring_pending_f(void) +{ + return 0x40000000; +} +static inline u32 mc_intr_pbus_pending_f(void) +{ + return 0x10000000; +} +static inline u32 mc_intr_en_r(u32 i) +{ + return 0x00000140 + i*4; +} +static inline u32 mc_intr_en_set_r(u32 i) +{ + return 0x00000160 + i*4; +} +static inline u32 mc_intr_en_clear_r(u32 i) +{ + return 0x00000180 + i*4; +} +static inline u32 mc_enable_r(void) +{ + return 0x00000200; +} +static inline u32 mc_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_enable_l2_enabled_f(void) +{ + return 0x8; +} +static inline u32 mc_enable_pmedia_s(void) +{ + return 1; +} +static inline u32 mc_enable_pmedia_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 mc_enable_pmedia_m(void) +{ + return 0x1 << 4; +} +static inline u32 mc_enable_pmedia_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 mc_enable_priv_ring_enabled_f(void) +{ + return 0x20; +} +static inline u32 mc_enable_ce0_m(void) +{ + return 0x1 << 6; +} +static inline u32 mc_enable_pfifo_enabled_f(void) +{ + return 0x100; +} +static inline u32 mc_enable_pgraph_enabled_f(void) +{ + return 0x1000; +} +static inline u32 mc_enable_pwr_v(u32 r) +{ + return (r >> 13) & 0x1; +} +static inline u32 mc_enable_pwr_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 mc_enable_pwr_enabled_f(void) +{ + return 0x2000; +} +static inline u32 mc_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_enable_ce2_m(void) +{ + return 0x1 << 21; +} +static inline u32 mc_enable_ce2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 mc_enable_blg_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 mc_enable_perfmon_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 mc_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 mc_intr_ltc_r(void) +{ + return 0x000001c0; +} +static inline u32 mc_enable_pb_r(void) +{ + return 0x00000204; +} +static inline u32 mc_enable_pb_0_s(void) +{ + return 1; +} +static inline u32 mc_enable_pb_0_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 mc_enable_pb_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 mc_enable_pb_0_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 mc_enable_pb_0_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 mc_elpg_enable_r(void) +{ + return 0x0000020c; +} +static inline u32 mc_elpg_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_elpg_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_elpg_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h new file mode 100644 index 00000000..c4d3a631 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -0,0 +1,633 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pbdma_gv11b_h_ +#define _hw_pbdma_gv11b_h_ + +static inline u32 pbdma_gp_entry1_r(void) +{ + return 0x10000004; +} +static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pbdma_gp_entry1_length_f(u32 v) +{ + return (v & 0x1fffff) << 10; +} +static inline u32 pbdma_gp_entry1_length_v(u32 r) +{ + return (r >> 10) & 0x1fffff; +} +static inline u32 pbdma_gp_base_r(u32 i) +{ + return 0x00040048 + i*8192; +} +static inline u32 pbdma_gp_base__size_1_v(void) +{ + return 0x00000003; +} +static inline u32 pbdma_gp_base_offset_f(u32 v) +{ + return (v & 0x1fffffff) << 3; +} +static inline u32 pbdma_gp_base_rsvd_s(void) +{ + return 3; +} +static inline u32 pbdma_gp_base_hi_r(u32 i) +{ + return 0x0004004c + i*8192; +} +static inline u32 pbdma_gp_base_hi_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 pbdma_gp_fetch_r(u32 i) +{ + return 0x00040050 + i*8192; +} +static inline u32 pbdma_gp_get_r(u32 i) +{ + return 0x00040014 + i*8192; +} +static inline u32 pbdma_gp_put_r(u32 i) +{ + return 0x00040000 + i*8192; +} +static inline u32 pbdma_pb_fetch_r(u32 i) +{ + return 0x00040054 + i*8192; +} +static inline u32 pbdma_pb_fetch_hi_r(u32 i) +{ + return 0x00040058 + i*8192; +} +static inline u32 pbdma_get_r(u32 i) +{ + return 0x00040018 + i*8192; +} +static inline u32 pbdma_get_hi_r(u32 i) +{ + return 0x0004001c + i*8192; +} +static inline u32 pbdma_put_r(u32 i) +{ + return 0x0004005c + i*8192; +} +static inline u32 pbdma_put_hi_r(u32 i) +{ + return 0x00040060 + i*8192; +} +static inline u32 pbdma_pb_header_r(u32 i) +{ + return 0x00040084 + i*8192; +} +static inline u32 pbdma_pb_header_priv_user_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_method_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_subchannel_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_level_main_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_pb_header_type_inc_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_pb_header_type_non_inc_f(void) +{ + return 0x60000000; +} +static inline u32 pbdma_hdr_shadow_r(u32 i) +{ + return 0x00040118 + i*8192; +} +static inline u32 pbdma_subdevice_r(u32 i) +{ + return 0x00040094 + i*8192; +} +static inline u32 pbdma_subdevice_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 pbdma_subdevice_status_active_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_subdevice_channel_dma_enable_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_method0_r(u32 i) +{ + return 0x000400c0 + i*8192; +} +static inline u32 pbdma_method0_fifo_size_v(void) +{ + return 0x00000004; +} +static inline u32 pbdma_method0_addr_f(u32 v) +{ + return (v & 0xfff) << 2; +} +static inline u32 pbdma_method0_addr_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 pbdma_method0_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 pbdma_method0_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_method0_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_method1_r(u32 i) +{ + return 0x000400c8 + i*8192; +} +static inline u32 pbdma_method2_r(u32 i) +{ + return 0x000400d0 + i*8192; +} +static inline u32 pbdma_method3_r(u32 i) +{ + return 0x000400d8 + i*8192; +} +static inline u32 pbdma_data0_r(u32 i) +{ + return 0x000400c4 + i*8192; +} +static inline u32 pbdma_acquire_r(u32 i) +{ + return 0x00040030 + i*8192; +} +static inline u32 pbdma_acquire_retry_man_2_f(void) +{ + return 0x2; +} +static inline u32 pbdma_acquire_retry_exp_2_f(void) +{ + return 0x100; +} +static inline u32 pbdma_acquire_timeout_exp_f(u32 v) +{ + return (v & 0xf) << 11; +} +static inline u32 pbdma_acquire_timeout_exp_max_v(void) +{ + return 0x0000000f; +} +static inline u32 pbdma_acquire_timeout_exp_max_f(void) +{ + return 0x7800; +} +static inline u32 pbdma_acquire_timeout_man_f(u32 v) +{ + return (v & 0xffff) << 15; +} +static inline u32 pbdma_acquire_timeout_man_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 pbdma_acquire_timeout_man_max_f(void) +{ + return 0x7fff8000; +} +static inline u32 pbdma_acquire_timeout_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_acquire_timeout_en_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_status_r(u32 i) +{ + return 0x00040100 + i*8192; +} +static inline u32 pbdma_channel_r(u32 i) +{ + return 0x00040120 + i*8192; +} +static inline u32 pbdma_signature_r(u32 i) +{ + return 0x00040010 + i*8192; +} +static inline u32 pbdma_signature_hw_valid_f(void) +{ + return 0xface; +} +static inline u32 pbdma_signature_sw_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_r(u32 i) +{ + return 0x00040008 + i*8192; +} +static inline u32 pbdma_userd_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 pbdma_userd_addr_f(u32 v) +{ + return (v & 0x7fffff) << 9; +} +static inline u32 pbdma_config_r(u32 i) +{ + return 0x000400f4 + i*8192; +} +static inline u32 pbdma_config_l2_evict_first_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_l2_evict_normal_f(void) +{ + return 0x1; +} +static inline u32 pbdma_config_l2_evict_last_f(void) +{ + return 0x2; +} +static inline u32 pbdma_config_ce_split_enable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_ce_split_disable_f(void) +{ + return 0x10; +} +static inline u32 pbdma_config_auth_level_non_privileged_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_auth_level_privileged_f(void) +{ + return 0x100; +} +static inline u32 pbdma_config_userd_writeback_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_userd_writeback_enable_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_userd_hi_r(u32 i) +{ + return 0x0004000c + i*8192; +} +static inline u32 pbdma_userd_hi_addr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_hce_ctrl_r(u32 i) +{ + return 0x000400e4 + i*8192; +} +static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_r(u32 i) +{ + return 0x00040108 + i*8192; +} +static inline u32 pbdma_intr_0_memreq_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pbdma_intr_0_memreq_pending_f(void) +{ + return 0x1; +} +static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) +{ + return 0x2; +} +static inline u32 pbdma_intr_0_memack_extra_pending_f(void) +{ + return 0x4; +} +static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) +{ + return 0x8; +} +static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) +{ + return 0x10; +} +static inline u32 pbdma_intr_0_memflush_pending_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_memop_pending_f(void) +{ + return 0x40; +} +static inline u32 pbdma_intr_0_lbconnect_pending_f(void) +{ + return 0x80; +} +static inline u32 pbdma_intr_0_lbreq_pending_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) +{ + return 0x200; +} +static inline u32 pbdma_intr_0_lback_extra_pending_f(void) +{ + return 0x400; +} +static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) +{ + return 0x800; +} +static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_intr_0_gpfifo_pending_f(void) +{ + return 0x2000; +} +static inline u32 pbdma_intr_0_gpptr_pending_f(void) +{ + return 0x4000; +} +static inline u32 pbdma_intr_0_gpentry_pending_f(void) +{ + return 0x8000; +} +static inline u32 pbdma_intr_0_gpcrc_pending_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_intr_0_pbptr_pending_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_intr_0_pbentry_pending_f(void) +{ + return 0x40000; +} +static inline u32 pbdma_intr_0_pbcrc_pending_f(void) +{ + return 0x80000; +} +static inline u32 pbdma_intr_0_method_pending_f(void) +{ + return 0x200000; +} +static inline u32 pbdma_intr_0_methodcrc_pending_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_intr_0_device_pending_f(void) +{ + return 0x800000; +} +static inline u32 pbdma_intr_0_semaphore_pending_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_intr_0_acquire_pending_f(void) +{ + return 0x4000000; +} +static inline u32 pbdma_intr_0_pri_pending_f(void) +{ + return 0x8000000; +} +static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_intr_0_pbseg_pending_f(void) +{ + return 0x40000000; +} +static inline u32 pbdma_intr_0_signature_pending_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_intr_1_r(u32 i) +{ + return 0x00040148 + i*8192; +} +static inline u32 pbdma_intr_en_0_r(u32 i) +{ + return 0x0004010c + i*8192; +} +static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_en_1_r(u32 i) +{ + return 0x0004014c + i*8192; +} +static inline u32 pbdma_intr_stall_r(u32 i) +{ + return 0x0004013c + i*8192; +} +static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_udma_nop_r(void) +{ + return 0x00000008; +} +static inline u32 pbdma_allowed_syncpoints_r(u32 i) +{ + return 0x000400e8 + i*8192; +} +static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) +{ + return (v & 0x7fff) << 16; +} +static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r) +{ + return (r >> 16) & 0x7fff; +} +static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) +{ + return (v & 0x1) << 15; +} +static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) +{ + return (v & 0x7fff) << 0; +} +static inline u32 pbdma_runlist_timeslice_r(u32 i) +{ + return 0x000400f8 + i*8192; +} +static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) +{ + return 0x80; +} +static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) +{ + return 0x3000; +} +static inline u32 pbdma_runlist_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_target_r(u32 i) +{ + return 0x000400ac + i*8192; +} +static inline u32 pbdma_target_engine_sw_f(void) +{ + return 0x1f; +} +static inline u32 pbdma_target_eng_ctx_valid_true_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_target_eng_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_ce_ctx_valid_true_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_target_ce_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) +{ + return 0x1000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) +{ + return 0x3000000; +} +static inline u32 pbdma_target_should_send_tsg_event_true_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_target_should_send_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_r(u32 i) +{ + return 0x000400fc + i*8192; +} +static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) +{ + return 0x1; +} +static inline u32 pbdma_set_channel_info_veid_f(u32 v) +{ + return (v & 0x3f) << 8; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h new file mode 100644 index 00000000..836c014b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_perf_gv11b_h_ +#define _hw_perf_gv11b_h_ + +static inline u32 perf_pmasys_control_r(void) +{ + return 0x0024a000; +} +static inline u32 perf_pmasys_control_membuf_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) +{ + return 0x10; +} +static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) +{ + return 0x20; +} +static inline u32 perf_pmasys_mem_block_r(void) +{ + return 0x0024a070; +} +static inline u32 perf_pmasys_mem_block_base_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 perf_pmasys_mem_block_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 perf_pmasys_mem_block_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 perf_pmasys_mem_block_target_lfb_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_target_lfb_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 perf_pmasys_mem_block_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 perf_pmasys_mem_block_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 perf_pmasys_mem_block_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_mem_block_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_outbase_r(void) +{ + return 0x0024a074; +} +static inline u32 perf_pmasys_outbase_ptr_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_outbaseupper_r(void) +{ + return 0x0024a078; +} +static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 perf_pmasys_outsize_r(void) +{ + return 0x0024a07c; +} +static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_mem_bytes_r(void) +{ + return 0x0024a084; +} +static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_mem_bump_r(void) +{ + return 0x0024a088; +} +static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_enginestatus_r(void) +{ + return 0x0024a0a4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) +{ + return 0x10; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h new file mode 100644 index 00000000..da2d4d2e --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pram_gv11b_h_ +#define _hw_pram_gv11b_h_ + +static inline u32 pram_data032_r(u32 i) +{ + return 0x00700000 + i*4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h new file mode 100644 index 00000000..835366c1 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringmaster_gv11b_h_ +#define _hw_pri_ringmaster_gv11b_h_ + +static inline u32 pri_ringmaster_command_r(void) +{ + return 0x0012004c; +} +static inline u32 pri_ringmaster_command_cmd_m(void) +{ + return 0x3f << 0; +} +static inline u32 pri_ringmaster_command_cmd_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) +{ + return 0x00000000; +} +static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) +{ + return 0x2; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) +{ + return 0x3; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_command_data_r(void) +{ + return 0x00120048; +} +static inline u32 pri_ringmaster_start_results_r(void) +{ + return 0x00120050; +} +static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) +{ + return 0x00000001; +} +static inline u32 pri_ringmaster_intr_status0_r(void) +{ + return 0x00120058; +} +static inline u32 pri_ringmaster_intr_status1_r(void) +{ + return 0x0012005c; +} +static inline u32 pri_ringmaster_global_ctl_r(void) +{ + return 0x00120060; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_enum_fbp_r(void) +{ + return 0x00120074; +} +static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_gpc_r(void) +{ + return 0x00120078; +} +static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_ltc_r(void) +{ + return 0x0012006c; +} +static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h new file mode 100644 index 00000000..e192bd13 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_sys_gv11b_h_ +#define _hw_pri_ringstation_sys_gv11b_h_ + +static inline u32 pri_ringstation_sys_master_config_r(u32 i) +{ + return 0x00122300 + i*4; +} +static inline u32 pri_ringstation_sys_decode_config_r(void) +{ + return 0x00122204; +} +static inline u32 pri_ringstation_sys_decode_config_ring_m(void) +{ + return 0x7 << 0; +} +static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) +{ + return 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h new file mode 100644 index 00000000..4e30447c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_proj_gv11b_h_ +#define _hw_proj_gv11b_h_ + +static inline u32 proj_gpc_base_v(void) +{ + return 0x00500000; +} +static inline u32 proj_gpc_shared_base_v(void) +{ + return 0x00418000; +} +static inline u32 proj_gpc_stride_v(void) +{ + return 0x00008000; +} +static inline u32 proj_ltc_stride_v(void) +{ + return 0x00002000; +} +static inline u32 proj_lts_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_fbpa_stride_v(void) +{ + return 0x00004000; +} +static inline u32 proj_ppc_in_gpc_base_v(void) +{ + return 0x00003000; +} +static inline u32 proj_ppc_in_gpc_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_rop_base_v(void) +{ + return 0x00410000; +} +static inline u32 proj_rop_shared_base_v(void) +{ + return 0x00408800; +} +static inline u32 proj_rop_stride_v(void) +{ + return 0x00000400; +} +static inline u32 proj_tpc_in_gpc_base_v(void) +{ + return 0x00004000; +} +static inline u32 proj_tpc_in_gpc_stride_v(void) +{ + return 0x00000800; +} +static inline u32 proj_tpc_in_gpc_shared_base_v(void) +{ + return 0x00001800; +} +static inline u32 proj_host_num_engines_v(void) +{ + return 0x00000004; +} +static inline u32 proj_host_num_pbdma_v(void) +{ + return 0x00000003; +} +static inline u32 proj_litter_num_subctx_v(void) +{ + return 0x00000040; +} +static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) +{ + return 0x00000004; +} +static inline u32 proj_scal_litter_num_fbps_v(void) +{ + return 0x00000001; +} +static inline u32 proj_scal_litter_num_fbpas_v(void) +{ + return 0x00000001; +} +static inline u32 proj_scal_litter_num_gpcs_v(void) +{ + return 0x00000001; +} +static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_litter_num_zcull_banks_v(void) +{ + return 0x00000004; +} +static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_max_gpcs_v(void) +{ + return 0x00000020; +} +static inline u32 proj_scal_max_tpc_per_gpc_v(void) +{ + return 0x00000008; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h new file mode 100644 index 00000000..965f8663 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -0,0 +1,825 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pwr_gv11b_h_ +#define _hw_pwr_gv11b_h_ + +static inline u32 pwr_falcon_irqsset_r(void) +{ + return 0x0010a000; +} +static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqsclr_r(void) +{ + return 0x0010a004; +} +static inline u32 pwr_falcon_irqstat_r(void) +{ + return 0x0010a008; +} +static inline u32 pwr_falcon_irqstat_halt_true_f(void) +{ + return 0x10; +} +static inline u32 pwr_falcon_irqstat_exterr_true_f(void) +{ + return 0x20; +} +static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqmode_r(void) +{ + return 0x0010a00c; +} +static inline u32 pwr_falcon_irqmset_r(void) +{ + return 0x0010a010; +} +static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_r(void) +{ + return 0x0010a014; +} +static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmask_r(void) +{ + return 0x0010a018; +} +static inline u32 pwr_falcon_irqdest_r(void) +{ + return 0x0010a01c; +} +static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 pwr_falcon_curctx_r(void) +{ + return 0x0010a050; +} +static inline u32 pwr_falcon_nxtctx_r(void) +{ + return 0x0010a054; +} +static inline u32 pwr_falcon_mailbox0_r(void) +{ + return 0x0010a040; +} +static inline u32 pwr_falcon_mailbox1_r(void) +{ + return 0x0010a044; +} +static inline u32 pwr_falcon_itfen_r(void) +{ + return 0x0010a048; +} +static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1; +} +static inline u32 pwr_falcon_idlestate_r(void) +{ + return 0x0010a04c; +} +static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1) & 0x7fff; +} +static inline u32 pwr_falcon_os_r(void) +{ + return 0x0010a080; +} +static inline u32 pwr_falcon_engctl_r(void) +{ + return 0x0010a0a4; +} +static inline u32 pwr_falcon_cpuctl_r(void) +{ + return 0x0010a100; +} +static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1 << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1 << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_alias_r(void) +{ + return 0x0010a130; +} +static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_pmu_scpctl_stat_r(void) +{ + return 0x0010ac08; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) +{ + return 0x1 << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 pwr_falcon_imemc_r(u32 i) +{ + return 0x0010a180 + i*16; +} +static inline u32 pwr_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_imemd_r(u32 i) +{ + return 0x0010a184 + i*16; +} +static inline u32 pwr_falcon_imemt_r(u32 i) +{ + return 0x0010a188 + i*16; +} +static inline u32 pwr_falcon_sctl_r(void) +{ + return 0x0010a240; +} +static inline u32 pwr_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4; +} +static inline u32 pwr_falcon_bootvec_r(void) +{ + return 0x0010a104; +} +static inline u32 pwr_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_falcon_dmactl_r(void) +{ + return 0x0010a10c; +} +static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_falcon_hwcfg_r(void) +{ + return 0x0010a108; +} +static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9) & 0x1ff; +} +static inline u32 pwr_falcon_dmatrfbase_r(void) +{ + return 0x0010a110; +} +static inline u32 pwr_falcon_dmatrfbase1_r(void) +{ + return 0x0010a128; +} +static inline u32 pwr_falcon_dmatrfmoffs_r(void) +{ + return 0x0010a114; +} +static inline u32 pwr_falcon_dmatrfcmd_r(void) +{ + return 0x0010a118; +} +static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 pwr_falcon_dmatrffboffs_r(void) +{ + return 0x0010a11c; +} +static inline u32 pwr_falcon_exterraddr_r(void) +{ + return 0x0010a168; +} +static inline u32 pwr_falcon_exterrstat_r(void) +{ + return 0x0010a16c; +} +static inline u32 pwr_falcon_exterrstat_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 pwr_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 pwr_pmu_falcon_icd_cmd_r(void) +{ + return 0x0010a200; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 pwr_pmu_falcon_icd_rdata_r(void) +{ + return 0x0010a20c; +} +static inline u32 pwr_falcon_dmemc_r(u32 i) +{ + return 0x0010a1c0 + i*8; +} +static inline u32 pwr_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 pwr_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_dmemc_blk_m(void) +{ + return 0xff << 8; +} +static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_dmemd_r(u32 i) +{ + return 0x0010a1c4 + i*8; +} +static inline u32 pwr_pmu_new_instblk_r(void) +{ + return 0x0010a480; +} +static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 pwr_pmu_new_instblk_target_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_pmu_mutex_id_r(void) +{ + return 0x0010a488; +} +static inline u32 pwr_pmu_mutex_id_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_id_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) +{ + return 0x000000ff; +} +static inline u32 pwr_pmu_mutex_id_release_r(void) +{ + return 0x0010a48c; +} +static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_m(void) +{ + return 0xff << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_mutex_r(u32 i) +{ + return 0x0010a580 + i*4; +} +static inline u32 pwr_pmu_mutex__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 pwr_pmu_mutex_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_queue_head_r(u32 i) +{ + return 0x0010a800 + i*4; +} +static inline u32 pwr_pmu_queue_head__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 pwr_pmu_queue_head_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_head_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_queue_tail_r(u32 i) +{ + return 0x0010a820 + i*4; +} +static inline u32 pwr_pmu_queue_tail__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 pwr_pmu_queue_tail_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_tail_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_head_r(void) +{ + return 0x0010a4c8; +} +static inline u32 pwr_pmu_msgq_head_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_head_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_tail_r(void) +{ + return 0x0010a4cc; +} +static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_idle_mask_r(u32 i) +{ + return 0x0010a504 + i*16; +} +static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) +{ + return 0x1; +} +static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 pwr_pmu_idle_count_r(u32 i) +{ + return 0x0010a508 + i*16; +} +static inline u32 pwr_pmu_idle_count_value_f(u32 v) +{ + return (v & 0x7fffffff) << 0; +} +static inline u32 pwr_pmu_idle_count_value_v(u32 r) +{ + return (r >> 0) & 0x7fffffff; +} +static inline u32 pwr_pmu_idle_count_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pwr_pmu_idle_ctrl_r(u32 i) +{ + return 0x0010a50c + i*16; +} +static inline u32 pwr_pmu_idle_ctrl_value_m(void) +{ + return 0x3 << 0; +} +static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) +{ + return 0x2; +} +static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) +{ + return 0x3; +} +static inline u32 pwr_pmu_idle_ctrl_filter_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) +{ + return 0x0010a9f0 + i*8; +} +static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) +{ + return 0x0010a9f4 + i*8; +} +static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) +{ + return 0x0010aa30 + i*8; +} +static inline u32 pwr_pmu_debug_r(u32 i) +{ + return 0x0010a5c0 + i*4; +} +static inline u32 pwr_pmu_debug__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_mailbox_r(u32 i) +{ + return 0x0010a450 + i*4; +} +static inline u32 pwr_pmu_mailbox__size_1_v(void) +{ + return 0x0000000c; +} +static inline u32 pwr_pmu_bar0_addr_r(void) +{ + return 0x0010a7a0; +} +static inline u32 pwr_pmu_bar0_data_r(void) +{ + return 0x0010a7a4; +} +static inline u32 pwr_pmu_bar0_ctl_r(void) +{ + return 0x0010a7ac; +} +static inline u32 pwr_pmu_bar0_timeout_r(void) +{ + return 0x0010a7a8; +} +static inline u32 pwr_pmu_bar0_fecs_error_r(void) +{ + return 0x0010a988; +} +static inline u32 pwr_pmu_bar0_error_status_r(void) +{ + return 0x0010a7b0; +} +static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) +{ + return 0x0010a6c0 + i*4; +} +static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) +{ + return 0x0010a6e8 + i*4; +} +static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) +{ + return 0x0010a710 + i*4; +} +static inline u32 pwr_pmu_pg_intren_r(u32 i) +{ + return 0x0010a760 + i*4; +} +static inline u32 pwr_fbif_transcfg_r(u32 i) +{ + return 0x0010ae00 + i*4; +} +static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) +{ + return 0x1; +} +static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) +{ + return 0x2; +} +static inline u32 pwr_fbif_transcfg_mem_type_s(void) +{ + return 1; +} +static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h new file mode 100644 index 00000000..bcbb7b81 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -0,0 +1,765 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ram_gv11b_h_ +#define _hw_ram_gv11b_h_ + +static inline u32 ram_in_ramfc_s(void) +{ + return 4096; +} +static inline u32 ram_in_ramfc_w(void) +{ + return 0; +} +static inline u32 ram_in_page_dir_base_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_page_dir_base_target_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 ram_in_page_dir_base_vol_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_vol_true_f(void) +{ + return 0x4; +} +static inline u32 ram_in_page_dir_base_vol_false_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) +{ + return 0x10; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) +{ + return 0x20; +} +static inline u32 ram_in_big_page_size_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 ram_in_big_page_size_w(void) +{ + return 128; +} +static inline u32 ram_in_big_page_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 ram_in_big_page_size_64kb_f(void) +{ + return 0x800; +} +static inline u32 ram_in_page_dir_base_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_page_dir_base_lo_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_page_dir_base_hi_w(void) +{ + return 129; +} +static inline u32 ram_in_engine_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_cs_wfi_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_engine_cs_fg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_cs_fg_f(void) +{ + return 0x8; +} +static inline u32 ram_in_engine_wfi_mode_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_engine_wfi_mode_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_mode_physical_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_mode_virtual_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_wfi_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_engine_wfi_target_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_engine_wfi_target_local_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_engine_wfi_ptr_lo_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_engine_wfi_ptr_hi_w(void) +{ + return 133; +} +static inline u32 ram_in_engine_wfi_veid_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ram_in_engine_wfi_veid_w(void) +{ + return 134; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) +{ + return 136; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) +{ + return 137; +} +static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) +{ + return (v & 0x3) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) +{ + return (v & 0x1) << (2 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) +{ + return (v & 0x1) << (4 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) +{ + return (v & 0x1) << (5 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) +{ + return (v & 0x1) << (10 + i*0); +} +static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) +{ + return (v & 0x1) << (11 + i*0); +} +static inline u32 ram_in_sc_big_page_size__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_big_page_size_64kb_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) +{ + return (v & 0xfffff) << (12 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) +{ + return (v & 0xffffffff) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_sc_page_dir_base_target_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_big_page_size_0_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_sc_big_page_size_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) +{ + return 169; +} +static inline u32 ram_in_base_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_in_alloc_size_v(void) +{ + return 0x00001000; +} +static inline u32 ram_fc_size_val_v(void) +{ + return 0x00000200; +} +static inline u32 ram_fc_gp_put_w(void) +{ + return 0; +} +static inline u32 ram_fc_userd_w(void) +{ + return 2; +} +static inline u32 ram_fc_userd_hi_w(void) +{ + return 3; +} +static inline u32 ram_fc_signature_w(void) +{ + return 4; +} +static inline u32 ram_fc_gp_get_w(void) +{ + return 5; +} +static inline u32 ram_fc_pb_get_w(void) +{ + return 6; +} +static inline u32 ram_fc_pb_get_hi_w(void) +{ + return 7; +} +static inline u32 ram_fc_pb_top_level_get_w(void) +{ + return 8; +} +static inline u32 ram_fc_pb_top_level_get_hi_w(void) +{ + return 9; +} +static inline u32 ram_fc_acquire_w(void) +{ + return 12; +} +static inline u32 ram_fc_sem_addr_hi_w(void) +{ + return 14; +} +static inline u32 ram_fc_sem_addr_lo_w(void) +{ + return 15; +} +static inline u32 ram_fc_sem_payload_lo_w(void) +{ + return 16; +} +static inline u32 ram_fc_sem_payload_hi_w(void) +{ + return 39; +} +static inline u32 ram_fc_sem_execute_w(void) +{ + return 17; +} +static inline u32 ram_fc_gp_base_w(void) +{ + return 18; +} +static inline u32 ram_fc_gp_base_hi_w(void) +{ + return 19; +} +static inline u32 ram_fc_gp_fetch_w(void) +{ + return 20; +} +static inline u32 ram_fc_pb_fetch_w(void) +{ + return 21; +} +static inline u32 ram_fc_pb_fetch_hi_w(void) +{ + return 22; +} +static inline u32 ram_fc_pb_put_w(void) +{ + return 23; +} +static inline u32 ram_fc_pb_put_hi_w(void) +{ + return 24; +} +static inline u32 ram_fc_pb_header_w(void) +{ + return 33; +} +static inline u32 ram_fc_pb_count_w(void) +{ + return 34; +} +static inline u32 ram_fc_subdevice_w(void) +{ + return 37; +} +static inline u32 ram_fc_allowed_syncpoints_w(void) +{ + return 58; +} +static inline u32 ram_fc_target_w(void) +{ + return 43; +} +static inline u32 ram_fc_hce_ctrl_w(void) +{ + return 57; +} +static inline u32 ram_fc_chid_w(void) +{ + return 58; +} +static inline u32 ram_fc_chid_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_fc_chid_id_w(void) +{ + return 0; +} +static inline u32 ram_fc_config_w(void) +{ + return 61; +} +static inline u32 ram_fc_runlist_timeslice_w(void) +{ + return 62; +} +static inline u32 ram_fc_set_channel_info_w(void) +{ + return 63; +} +static inline u32 ram_userd_base_shift_v(void) +{ + return 0x00000009; +} +static inline u32 ram_userd_chan_size_v(void) +{ + return 0x00000200; +} +static inline u32 ram_userd_put_w(void) +{ + return 16; +} +static inline u32 ram_userd_get_w(void) +{ + return 17; +} +static inline u32 ram_userd_ref_w(void) +{ + return 18; +} +static inline u32 ram_userd_put_hi_w(void) +{ + return 19; +} +static inline u32 ram_userd_ref_threshold_w(void) +{ + return 20; +} +static inline u32 ram_userd_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_userd_get_hi_w(void) +{ + return 24; +} +static inline u32 ram_userd_gp_get_w(void) +{ + return 34; +} +static inline u32 ram_userd_gp_put_w(void) +{ + return 35; +} +static inline u32 ram_userd_gp_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_gp_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_rl_entry_size_v(void) +{ + return 0x00000010; +} +static inline u32 ram_rl_entry_type_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 ram_rl_entry_type_channel_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_type_tsg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) +{ + return (v & 0x3) << 4; +} +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) +{ + return (v & 0x3) << 6; +} +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_rl_entry_tsg_length_init_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_min_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_tsg_length_max_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h new file mode 100644 index 00000000..a3cfcf91 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_therm_gv11b_h_ +#define _hw_therm_gv11b_h_ + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h new file mode 100644 index 00000000..7d5750c2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_timer_gv11b_h_ +#define _hw_timer_gv11b_h_ + +static inline u32 timer_pri_timeout_r(void) +{ + return 0x00009080; +} +static inline u32 timer_pri_timeout_period_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 timer_pri_timeout_period_m(void) +{ + return 0xffffff << 0; +} +static inline u32 timer_pri_timeout_period_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 timer_pri_timeout_en_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 timer_pri_timeout_en_m(void) +{ + return 0x1 << 31; +} +static inline u32 timer_pri_timeout_en_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 timer_pri_timeout_en_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 timer_pri_timeout_en_en_disabled_f(void) +{ + return 0x0; +} +static inline u32 timer_pri_timeout_save_0_r(void) +{ + return 0x00009084; +} +static inline u32 timer_pri_timeout_save_1_r(void) +{ + return 0x00009088; +} +static inline u32 timer_pri_timeout_fecs_errcode_r(void) +{ + return 0x0000908c; +} +static inline u32 timer_time_0_r(void) +{ + return 0x00009400; +} +static inline u32 timer_time_1_r(void) +{ + return 0x00009410; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h new file mode 100644 index 00000000..2e2ff6ba --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_top_gv11b_h_ +#define _hw_top_gv11b_h_ + +static inline u32 top_num_gpcs_r(void) +{ + return 0x00022430; +} +static inline u32 top_num_gpcs_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_tpc_per_gpc_r(void) +{ + return 0x00022434; +} +static inline u32 top_tpc_per_gpc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_fbps_r(void) +{ + return 0x00022438; +} +static inline u32 top_num_fbps_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_ltc_per_fbp_r(void) +{ + return 0x00022450; +} +static inline u32 top_ltc_per_fbp_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_slices_per_ltc_r(void) +{ + return 0x0002245c; +} +static inline u32 top_slices_per_ltc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_ltcs_r(void) +{ + return 0x00022454; +} +static inline u32 top_device_info_r(u32 i) +{ + return 0x00022700 + i*4; +} +static inline u32 top_device_info__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 top_device_info_chain_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 top_device_info_chain_enable_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_engine_enum_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_runlist_enum_v(u32 r) +{ + return (r >> 21) & 0xf; +} +static inline u32 top_device_info_intr_enum_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 top_device_info_reset_enum_v(u32 r) +{ + return (r >> 9) & 0x1f; +} +static inline u32 top_device_info_type_enum_v(u32 r) +{ + return (r >> 2) & 0x1fffffff; +} +static inline u32 top_device_info_type_enum_graphics_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_type_enum_graphics_f(void) +{ + return 0x0; +} +static inline u32 top_device_info_type_enum_copy2_v(void) +{ + return 0x00000003; +} +static inline u32 top_device_info_type_enum_copy2_f(void) +{ + return 0xc; +} +static inline u32 top_device_info_type_enum_lce_v(void) +{ + return 0x00000013; +} +static inline u32 top_device_info_type_enum_lce_f(void) +{ + return 0x4c; +} +static inline u32 top_device_info_engine_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 top_device_info_runlist_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 top_device_info_intr_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 top_device_info_reset_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_entry_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 top_device_info_entry_not_valid_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_entry_enum_v(void) +{ + return 0x00000002; +} +static inline u32 top_device_info_entry_data_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_data_type_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 top_device_info_data_type_enum2_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_data_inst_id_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_data_pri_base_v(u32 r) +{ + return (r >> 12) & 0xfff; +} +static inline u32 top_device_info_data_pri_base_align_v(void) +{ + return 0x0000000c; +} +static inline u32 top_device_info_data_fault_id_enum_v(u32 r) +{ + return (r >> 3) & 0x7f; +} +static inline u32 top_device_info_data_fault_id_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_data_fault_id_valid_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h new file mode 100644 index 00000000..8bcf163f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_usermode_gv11b_h_ +#define _hw_usermode_gv11b_h_ + +static inline u32 usermode_cfg0_r(void) +{ + return 0x00810000; +} +static inline u32 usermode_cfg0_usermode_class_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 usermode_cfg0_usermode_class_id_value_v(void) +{ + return 0x0000c361; +} +static inline u32 usermode_time_0_r(void) +{ + return 0x00810080; +} +static inline u32 usermode_time_0_nsec_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 usermode_time_1_r(void) +{ + return 0x00810084; +} +static inline u32 usermode_time_1_nsec_f(u32 v) +{ + return (v & 0x1fffffff) << 0; +} +static inline u32 usermode_notify_channel_pending_r(void) +{ + return 0x00810090; +} +static inline u32 usermode_notify_channel_pending_id_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +#endif -- cgit v1.2.2 From 8797934a2663df68c1ee0e896c173266135559f3 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 24 Jan 2017 16:55:42 -0800 Subject: gpu: nvgpu: gv11b: update clock gating prod settings Update clock gating setting till HW CL#37750038 JIRA GV11B-15 Change-Id: I98c4a157df979c944122f4a7b05e3e692a28fe2f Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1294824 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 42 ++++++++++++-------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c index 9bd40eff..13d529fe 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -50,7 +50,6 @@ static const struct gating_desc gv11b_slcg_chiplet[] = { static const struct gating_desc gv11b_slcg_fb[] = { {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x001facb4, .prod = 0x00000000, .disable = 0x000001fe}, }; /* slcg fifo */ @@ -92,16 +91,16 @@ static const struct gating_desc gv11b_slcg_gr[] = { {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, {.addr = 0x00419c84, .prod = 0x0003fffe, .disable = 0x0003fffe}, {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, - {.addr = 0x00419c94, .prod = 0x00007ffe, .disable = 0x00007ffe}, + {.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe}, {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, - {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, + {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, + {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, + {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, + {.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe}, + {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, + {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, @@ -186,7 +185,6 @@ static const struct gating_desc gv11b_blcg_fb[] = { {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000}, {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x001facb0, .prod = 0x00004242, .disable = 0x00000000}, }; /* blcg fifo */ @@ -225,21 +223,21 @@ static const struct gating_desc gv11b_blcg_gr[] = { {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00419c80, .prod = 0x00000003, .disable = 0x00000000}, - {.addr = 0x00419c88, .prod = 0x00000003, .disable = 0x00000000}, - {.addr = 0x00419c90, .prod = 0x00000003, .disable = 0x00000000}, + {.addr = 0x00419c80, .prod = 0x00004048, .disable = 0x00000000}, + {.addr = 0x00419c88, .prod = 0x00004048, .disable = 0x00000000}, + {.addr = 0x00419c90, .prod = 0x00000047, .disable = 0x00000000}, {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419a40, .prod = 0x00000202, .disable = 0x00000000}, - {.addr = 0x00419a48, .prod = 0x00000202, .disable = 0x00000000}, - {.addr = 0x00419a50, .prod = 0x00000202, .disable = 0x00000000}, - {.addr = 0x00419a58, .prod = 0x00000202, .disable = 0x00000000}, - {.addr = 0x00419a60, .prod = 0x00000202, .disable = 0x00000000}, - {.addr = 0x00419a68, .prod = 0x00000202, .disable = 0x00000000}, - {.addr = 0x00419a78, .prod = 0x00000202, .disable = 0x00000000}, - {.addr = 0x00419a80, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a40, .prod = 0x00000545, .disable = 0x00000000}, + {.addr = 0x00419a48, .prod = 0x00004545, .disable = 0x00000000}, + {.addr = 0x00419a50, .prod = 0x00004545, .disable = 0x00000000}, + {.addr = 0x00419a58, .prod = 0x00004545, .disable = 0x00000000}, + {.addr = 0x00419a60, .prod = 0x00000505, .disable = 0x00000000}, + {.addr = 0x00419a68, .prod = 0x00000505, .disable = 0x00000000}, + {.addr = 0x00419a78, .prod = 0x00000505, .disable = 0x00000000}, + {.addr = 0x00419a80, .prod = 0x00004545, .disable = 0x00000000}, {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, -- cgit v1.2.2 From d00b2000b5bb2f39e3610b8321e0872e2b06bd0a Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 20 Jan 2017 16:18:47 -0800 Subject: gpu: nvgpu: gv11b: update zcull and pm pointers Update zcull and perfmon buffer pointers in context header. For gv11b maximum 49 bits gpu va possible. But, zcull and perfmon buffer pointers uses maximum 41 bit va address (258 bytes aligned). To accommodate this, high pointer registers needs to be updated in context header. JIRA GV11B-48 Change-Id: Ibe62b6bfedd32c4f3721e4d19d96cce58ef0f366 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1291852 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: svccoveritychecker --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 30 ++++++++++++++++++++++ .../include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | 6 ++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 31c1a420..daadef68 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1941,6 +1941,34 @@ static void gv11b_restore_context_header(struct gk20a *g, gk20a_mem_wr(g, ctxheader, ctxsw_prog_main_image_num_save_ops_o(), 0); } +static void gr_gv11b_write_zcull_ptr(struct gk20a *g, + struct mem_desc *mem, u64 gpu_va) +{ + u32 va_lo, va_hi; + + gpu_va = gpu_va >> 8; + va_lo = u64_lo32(gpu_va); + va_hi = u64_hi32(gpu_va); + gk20a_mem_wr(g, mem, + ctxsw_prog_main_image_zcull_ptr_o(), va_lo); + gk20a_mem_wr(g, mem, + ctxsw_prog_main_image_zcull_ptr_hi_o(), va_hi); +} + + +static void gr_gv11b_write_pm_ptr(struct gk20a *g, + struct mem_desc *mem, u64 gpu_va) +{ + u32 va_lo, va_hi; + + gpu_va = gpu_va >> 8; + va_lo = u64_lo32(gpu_va); + va_hi = u64_hi32(gpu_va); + gk20a_mem_wr(g, mem, + ctxsw_prog_main_image_pm_ptr_o(), va_lo); + gk20a_mem_wr(g, mem, + ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); +} void gv11b_init_gr(struct gpu_ops *gops) { @@ -1995,5 +2023,7 @@ void gv11b_init_gr(struct gpu_ops *gops) gr_gv11b_program_sm_id_numbering; gops->gr.commit_inst = gr_gv11b_commit_inst; gops->gr.restore_context_header = gv11b_restore_context_header; + gops->gr.write_zcull_ptr = gr_gv11b_write_zcull_ptr; + gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h index 228bf5f2..a0f40de0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -186,6 +186,10 @@ static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) { return (v & 0x1ffff) << 0; } +static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) +{ + return 0x00000094; +} static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) { return 0x00000064; -- cgit v1.2.2 From 30e1647ddf5b4b272c63843e91d4c4b41529bd75 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 27 Jan 2017 10:59:47 -0800 Subject: gpu: nvgpu: gv11b: add regops whitelists Add regops whitelists for gv11b. JIRA GV11B-35 Change-Id: I0ff5172c5b693250efb0523106632b3746383dcb Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1295401 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 3 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 + drivers/gpu/nvgpu/gv11b/regops_gv11b.c | 941 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/regops_gv11b.h | 24 + 4 files changed, 969 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/gv11b/regops_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/regops_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 4f7b5422..112abdf2 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -15,6 +15,7 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \ $(nvgpu-t19x)/gv11b/pmu_gv11b.o \ $(nvgpu-t19x)/gv11b/therm_gv11b.o \ - $(nvgpu-t19x)/gv11b/subctx_gv11b.o + $(nvgpu-t19x)/gv11b/subctx_gv11b.o \ + $(nvgpu-t19x)/gv11b/regops_gv11b.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 07f386e8..8b10245e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -38,6 +38,7 @@ #include "fb_gv11b.h" #include "fifo_gv11b.h" #include "gv11b_gating_reglist.h" +#include "regops_gv11b.h" #include @@ -199,6 +200,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); gk20a_init_dbg_session_ops(gops); + gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); gops->name = "gv11b"; diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c new file mode 100644 index 00000000..8c5305b3 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c @@ -0,0 +1,941 @@ +/* + * Tegra GV11b GPU Driver Register Ops + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/regops_gk20a.h" +#include "regops_gv11b.h" + +static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { + { 0x000004f0, 1}, + { 0x00001a00, 1}, + { 0x00009400, 1}, + { 0x00009410, 1}, + { 0x00009480, 1}, + { 0x00020200, 24}, + { 0x00021c04, 2}, + { 0x00021c14, 3}, + { 0x00021c24, 71}, + { 0x00021d44, 1}, + { 0x00021d4c, 1}, + { 0x00021d54, 1}, + { 0x00021d5c, 1}, + { 0x00021d68, 19}, + { 0x00021dbc, 16}, + { 0x00022430, 7}, + { 0x00022450, 1}, + { 0x0002245c, 2}, + { 0x00070000, 5}, + { 0x000840a8, 1}, + { 0x00084b5c, 1}, + { 0x000870a8, 1}, + { 0x000884e0, 1}, + { 0x000884f4, 1}, + { 0x0008e00c, 1}, + { 0x00100c18, 3}, + { 0x00100c84, 1}, + { 0x0010a0a8, 1}, + { 0x0010a4f0, 1}, + { 0x0013c808, 2}, + { 0x0013cc14, 1}, + { 0x0013ec18, 1}, + { 0x00140028, 1}, + { 0x00140280, 1}, + { 0x001402a0, 1}, + { 0x00140350, 1}, + { 0x00140480, 1}, + { 0x001404a0, 1}, + { 0x00140550, 1}, + { 0x00140680, 1}, + { 0x001406a0, 1}, + { 0x00140750, 1}, + { 0x00142028, 1}, + { 0x00142280, 1}, + { 0x001422a0, 1}, + { 0x00142350, 1}, + { 0x00142480, 1}, + { 0x001424a0, 1}, + { 0x00142550, 1}, + { 0x00142680, 1}, + { 0x001426a0, 1}, + { 0x00142750, 1}, + { 0x0017e028, 1}, + { 0x0017e280, 1}, + { 0x0017e294, 1}, + { 0x0017e29c, 2}, + { 0x0017e2ac, 1}, + { 0x0017e350, 1}, + { 0x0017e39c, 1}, + { 0x0017e480, 1}, + { 0x0017e4a0, 1}, + { 0x0017e550, 1}, + { 0x0017e680, 1}, + { 0x0017e6a0, 1}, + { 0x0017e750, 1}, + { 0x00180040, 41}, + { 0x001800ec, 1}, + { 0x001800f8, 4}, + { 0x0018010c, 1}, + { 0x00180240, 41}, + { 0x001802ec, 1}, + { 0x001802f8, 4}, + { 0x0018030c, 1}, + { 0x00180440, 41}, + { 0x001804ec, 1}, + { 0x001804f8, 4}, + { 0x0018050c, 1}, + { 0x00180640, 41}, + { 0x001806ec, 1}, + { 0x001806f8, 4}, + { 0x0018070c, 1}, + { 0x00180840, 41}, + { 0x001808ec, 1}, + { 0x001808f8, 4}, + { 0x0018090c, 1}, + { 0x00180a40, 41}, + { 0x00180aec, 1}, + { 0x00180af8, 4}, + { 0x00180b0c, 1}, + { 0x00180c40, 41}, + { 0x00180cec, 1}, + { 0x00180cf8, 4}, + { 0x00180d0c, 1}, + { 0x00180e40, 41}, + { 0x00180eec, 1}, + { 0x00180ef8, 4}, + { 0x00180f0c, 1}, + { 0x00181040, 41}, + { 0x001810ec, 1}, + { 0x001810f8, 4}, + { 0x0018110c, 1}, + { 0x00181240, 41}, + { 0x001812ec, 1}, + { 0x001812f8, 4}, + { 0x0018130c, 1}, + { 0x00181440, 41}, + { 0x001814ec, 1}, + { 0x001814f8, 4}, + { 0x0018150c, 1}, + { 0x00181640, 41}, + { 0x001816ec, 1}, + { 0x001816f8, 4}, + { 0x0018170c, 1}, + { 0x00181840, 41}, + { 0x001818ec, 1}, + { 0x001818f8, 4}, + { 0x0018190c, 1}, + { 0x00181a40, 41}, + { 0x00181aec, 1}, + { 0x00181af8, 4}, + { 0x00181b0c, 1}, + { 0x00181c40, 41}, + { 0x00181cec, 1}, + { 0x00181cf8, 4}, + { 0x00181d0c, 1}, + { 0x00181e40, 41}, + { 0x00181eec, 1}, + { 0x00181ef8, 4}, + { 0x00181f0c, 1}, + { 0x00182040, 41}, + { 0x001820ec, 1}, + { 0x001820f8, 4}, + { 0x0018210c, 1}, + { 0x00182240, 41}, + { 0x001822ec, 1}, + { 0x001822f8, 4}, + { 0x0018230c, 1}, + { 0x00182440, 41}, + { 0x001824ec, 1}, + { 0x001824f8, 4}, + { 0x0018250c, 1}, + { 0x00182640, 41}, + { 0x001826ec, 1}, + { 0x001826f8, 4}, + { 0x0018270c, 1}, + { 0x00182840, 41}, + { 0x001828ec, 1}, + { 0x001828f8, 4}, + { 0x0018290c, 1}, + { 0x00182a40, 41}, + { 0x00182aec, 1}, + { 0x00182af8, 4}, + { 0x00182b0c, 1}, + { 0x00182c40, 41}, + { 0x00182cec, 1}, + { 0x00182cf8, 4}, + { 0x00182d0c, 1}, + { 0x00182e40, 41}, + { 0x00182eec, 1}, + { 0x00182ef8, 4}, + { 0x00182f0c, 1}, + { 0x00183040, 41}, + { 0x001830ec, 1}, + { 0x001830f8, 4}, + { 0x0018310c, 1}, + { 0x00183240, 41}, + { 0x001832ec, 1}, + { 0x001832f8, 4}, + { 0x0018330c, 1}, + { 0x00183440, 41}, + { 0x001834ec, 1}, + { 0x001834f8, 4}, + { 0x0018350c, 1}, + { 0x00183640, 41}, + { 0x001836ec, 1}, + { 0x001836f8, 4}, + { 0x0018370c, 1}, + { 0x00183840, 41}, + { 0x001838ec, 1}, + { 0x001838f8, 4}, + { 0x0018390c, 1}, + { 0x00183a40, 41}, + { 0x00183aec, 1}, + { 0x00183af8, 4}, + { 0x00183b0c, 1}, + { 0x00183c40, 41}, + { 0x00183cec, 1}, + { 0x00183cf8, 4}, + { 0x00183d0c, 1}, + { 0x00183e40, 41}, + { 0x00183eec, 1}, + { 0x00183ef8, 4}, + { 0x00183f0c, 1}, + { 0x001c80a8, 1}, + { 0x001c9100, 1}, + { 0x001cc0a8, 1}, + { 0x001cd100, 1}, + { 0x001d00a8, 1}, + { 0x001d1100, 1}, + { 0x00200040, 41}, + { 0x002000ec, 1}, + { 0x002000f8, 4}, + { 0x0020010c, 1}, + { 0x00200240, 41}, + { 0x002002ec, 1}, + { 0x002002f8, 4}, + { 0x0020030c, 1}, + { 0x00200440, 41}, + { 0x002004ec, 1}, + { 0x002004f8, 4}, + { 0x0020050c, 1}, + { 0x00200640, 41}, + { 0x002006ec, 1}, + { 0x002006f8, 4}, + { 0x0020070c, 1}, + { 0x00200840, 41}, + { 0x002008ec, 1}, + { 0x002008f8, 4}, + { 0x0020090c, 1}, + { 0x00200a40, 41}, + { 0x00200aec, 1}, + { 0x00200af8, 4}, + { 0x00200b0c, 1}, + { 0x00200c40, 41}, + { 0x00200cec, 1}, + { 0x00200cf8, 4}, + { 0x00200d0c, 1}, + { 0x00200e40, 41}, + { 0x00200eec, 1}, + { 0x00200ef8, 4}, + { 0x00200f0c, 1}, + { 0x00201040, 41}, + { 0x002010ec, 1}, + { 0x002010f8, 4}, + { 0x0020110c, 1}, + { 0x00201240, 41}, + { 0x002012ec, 1}, + { 0x002012f8, 4}, + { 0x0020130c, 1}, + { 0x00201440, 41}, + { 0x002014ec, 1}, + { 0x002014f8, 4}, + { 0x0020150c, 1}, + { 0x00201640, 41}, + { 0x002016ec, 1}, + { 0x002016f8, 4}, + { 0x0020170c, 1}, + { 0x00201840, 41}, + { 0x002018ec, 1}, + { 0x002018f8, 4}, + { 0x0020190c, 1}, + { 0x00201a40, 41}, + { 0x00201aec, 1}, + { 0x00201af8, 4}, + { 0x00201b0c, 1}, + { 0x00201c40, 41}, + { 0x00201cec, 1}, + { 0x00201cf8, 4}, + { 0x00201d0c, 1}, + { 0x00201e40, 41}, + { 0x00201eec, 1}, + { 0x00201ef8, 4}, + { 0x00201f0c, 1}, + { 0x00202040, 41}, + { 0x002020ec, 1}, + { 0x002020f8, 4}, + { 0x0020210c, 1}, + { 0x00202240, 41}, + { 0x002022ec, 1}, + { 0x002022f8, 4}, + { 0x0020230c, 1}, + { 0x00202440, 41}, + { 0x002024ec, 1}, + { 0x002024f8, 4}, + { 0x0020250c, 1}, + { 0x00202640, 41}, + { 0x002026ec, 1}, + { 0x002026f8, 4}, + { 0x0020270c, 1}, + { 0x00202840, 41}, + { 0x002028ec, 1}, + { 0x002028f8, 4}, + { 0x0020290c, 1}, + { 0x00202a40, 41}, + { 0x00202aec, 1}, + { 0x00202af8, 4}, + { 0x00202b0c, 1}, + { 0x00202c40, 41}, + { 0x00202cec, 1}, + { 0x00202cf8, 4}, + { 0x00202d0c, 1}, + { 0x00202e40, 41}, + { 0x00202eec, 1}, + { 0x00202ef8, 4}, + { 0x00202f0c, 1}, + { 0x00203040, 41}, + { 0x002030ec, 1}, + { 0x002030f8, 4}, + { 0x0020310c, 1}, + { 0x00203240, 41}, + { 0x002032ec, 1}, + { 0x002032f8, 4}, + { 0x0020330c, 1}, + { 0x00203440, 41}, + { 0x002034ec, 1}, + { 0x002034f8, 4}, + { 0x0020350c, 1}, + { 0x00203640, 41}, + { 0x002036ec, 1}, + { 0x002036f8, 4}, + { 0x0020370c, 1}, + { 0x00203840, 41}, + { 0x002038ec, 1}, + { 0x002038f8, 4}, + { 0x0020390c, 1}, + { 0x00203a40, 41}, + { 0x00203aec, 1}, + { 0x00203af8, 4}, + { 0x00203b0c, 1}, + { 0x00203c40, 41}, + { 0x00203cec, 1}, + { 0x00203cf8, 4}, + { 0x00203d0c, 1}, + { 0x00203e40, 41}, + { 0x00203eec, 1}, + { 0x00203ef8, 4}, + { 0x00203f0c, 1}, + { 0x00240040, 41}, + { 0x002400ec, 1}, + { 0x002400f8, 4}, + { 0x0024010c, 1}, + { 0x00240240, 41}, + { 0x002402ec, 1}, + { 0x002402f8, 4}, + { 0x0024030c, 1}, + { 0x00240440, 41}, + { 0x002404ec, 1}, + { 0x002404f8, 4}, + { 0x0024050c, 1}, + { 0x00240640, 41}, + { 0x002406ec, 1}, + { 0x002406f8, 4}, + { 0x0024070c, 1}, + { 0x00240840, 41}, + { 0x002408ec, 1}, + { 0x002408f8, 4}, + { 0x0024090c, 1}, + { 0x00240a40, 41}, + { 0x00240aec, 1}, + { 0x00240af8, 4}, + { 0x00240b0c, 1}, + { 0x00240c40, 41}, + { 0x00240cec, 1}, + { 0x00240cf8, 4}, + { 0x00240d0c, 1}, + { 0x00240e40, 41}, + { 0x00240eec, 1}, + { 0x00240ef8, 4}, + { 0x00240f0c, 1}, + { 0x00241040, 41}, + { 0x002410ec, 1}, + { 0x002410f8, 4}, + { 0x0024110c, 1}, + { 0x00241240, 41}, + { 0x002412ec, 1}, + { 0x002412f8, 4}, + { 0x0024130c, 1}, + { 0x00241440, 41}, + { 0x002414ec, 1}, + { 0x002414f8, 4}, + { 0x0024150c, 1}, + { 0x00241640, 41}, + { 0x002416ec, 1}, + { 0x002416f8, 4}, + { 0x0024170c, 1}, + { 0x00241840, 41}, + { 0x002418ec, 1}, + { 0x002418f8, 4}, + { 0x0024190c, 1}, + { 0x00241a40, 41}, + { 0x00241aec, 1}, + { 0x00241af8, 4}, + { 0x00241b0c, 1}, + { 0x00241c40, 41}, + { 0x00241cec, 1}, + { 0x00241cf8, 4}, + { 0x00241d0c, 1}, + { 0x00241e40, 41}, + { 0x00241eec, 1}, + { 0x00241ef8, 4}, + { 0x00241f0c, 1}, + { 0x00242040, 41}, + { 0x002420ec, 1}, + { 0x002420f8, 4}, + { 0x0024210c, 1}, + { 0x00242240, 41}, + { 0x002422ec, 1}, + { 0x002422f8, 4}, + { 0x0024230c, 1}, + { 0x00242440, 41}, + { 0x002424ec, 1}, + { 0x002424f8, 4}, + { 0x0024250c, 1}, + { 0x00242640, 41}, + { 0x002426ec, 1}, + { 0x002426f8, 4}, + { 0x0024270c, 1}, + { 0x00242840, 41}, + { 0x002428ec, 1}, + { 0x002428f8, 4}, + { 0x0024290c, 1}, + { 0x00242a40, 41}, + { 0x00242aec, 1}, + { 0x00242af8, 4}, + { 0x00242b0c, 1}, + { 0x00242c40, 41}, + { 0x00242cec, 1}, + { 0x00242cf8, 4}, + { 0x00242d0c, 1}, + { 0x00242e40, 41}, + { 0x00242eec, 1}, + { 0x00242ef8, 4}, + { 0x00242f0c, 1}, + { 0x00243040, 41}, + { 0x002430ec, 1}, + { 0x002430f8, 4}, + { 0x0024310c, 1}, + { 0x00243240, 41}, + { 0x002432ec, 1}, + { 0x002432f8, 4}, + { 0x0024330c, 1}, + { 0x00243440, 41}, + { 0x002434ec, 1}, + { 0x002434f8, 4}, + { 0x0024350c, 1}, + { 0x00243640, 41}, + { 0x002436ec, 1}, + { 0x002436f8, 4}, + { 0x0024370c, 1}, + { 0x00243840, 41}, + { 0x002438ec, 1}, + { 0x002438f8, 4}, + { 0x0024390c, 1}, + { 0x00243a40, 41}, + { 0x00243aec, 1}, + { 0x00243af8, 4}, + { 0x00243b0c, 1}, + { 0x00243c40, 41}, + { 0x00243cec, 1}, + { 0x00243cf8, 4}, + { 0x00243d0c, 1}, + { 0x00243e40, 41}, + { 0x00243eec, 1}, + { 0x00243ef8, 4}, + { 0x00243f0c, 1}, + { 0x00244000, 1}, + { 0x00244008, 1}, + { 0x00244010, 3}, + { 0x00246000, 1}, + { 0x00246008, 1}, + { 0x00246010, 3}, + { 0x00248000, 1}, + { 0x00248008, 1}, + { 0x00248010, 3}, + { 0x0024a000, 1}, + { 0x0024a008, 1}, + { 0x0024a010, 3}, + { 0x0024a020, 3}, + { 0x0024a030, 3}, + { 0x0024a040, 3}, + { 0x0024a050, 3}, + { 0x0024a060, 4}, + { 0x0024a074, 7}, + { 0x0024a094, 3}, + { 0x0024a0a4, 1}, + { 0x0024a100, 6}, + { 0x0024a124, 1}, + { 0x00400500, 1}, + { 0x0040415c, 1}, + { 0x00404468, 1}, + { 0x00404498, 1}, + { 0x00405800, 1}, + { 0x00405840, 2}, + { 0x00405850, 1}, + { 0x00405908, 1}, + { 0x00405a00, 1}, + { 0x00405b50, 1}, + { 0x00406024, 5}, + { 0x00407010, 1}, + { 0x00407808, 1}, + { 0x0040803c, 1}, + { 0x00408804, 1}, + { 0x0040880c, 1}, + { 0x00408900, 2}, + { 0x00408910, 1}, + { 0x00408944, 1}, + { 0x00408984, 1}, + { 0x004090a8, 1}, + { 0x004098a0, 1}, + { 0x00409b00, 1}, + { 0x0041000c, 1}, + { 0x00410110, 1}, + { 0x00410184, 1}, + { 0x0041040c, 1}, + { 0x00410510, 1}, + { 0x00410584, 1}, + { 0x00418000, 1}, + { 0x00418008, 1}, + { 0x00418380, 2}, + { 0x00418400, 2}, + { 0x004184a0, 1}, + { 0x00418604, 1}, + { 0x00418680, 1}, + { 0x00418704, 1}, + { 0x00418714, 1}, + { 0x00418800, 1}, + { 0x0041881c, 1}, + { 0x00418830, 1}, + { 0x00418884, 1}, + { 0x004188b0, 1}, + { 0x004188c8, 3}, + { 0x004188fc, 1}, + { 0x00418b04, 1}, + { 0x00418c04, 1}, + { 0x00418c10, 8}, + { 0x00418c88, 1}, + { 0x00418d00, 1}, + { 0x00418e00, 1}, + { 0x00418e08, 1}, + { 0x00418e34, 1}, + { 0x00418e40, 4}, + { 0x00418e58, 16}, + { 0x00418f08, 1}, + { 0x00419000, 1}, + { 0x0041900c, 1}, + { 0x00419018, 1}, + { 0x00419854, 1}, + { 0x00419864, 1}, + { 0x00419a04, 2}, + { 0x00419b04, 1}, + { 0x00419b3c, 1}, + { 0x00419b48, 1}, + { 0x00419b50, 1}, + { 0x00419ba0, 2}, + { 0x00419bb0, 1}, + { 0x00419bdc, 1}, + { 0x00419c0c, 1}, + { 0x00419c8c, 1}, + { 0x00419d00, 1}, + { 0x00419d08, 2}, + { 0x00419e08, 1}, + { 0x00419e80, 8}, + { 0x00419ea8, 5}, + { 0x00419f00, 8}, + { 0x00419f28, 5}, + { 0x00419f80, 8}, + { 0x00419fa8, 5}, + { 0x0041a02c, 2}, + { 0x0041a0a0, 1}, + { 0x0041a0a8, 1}, + { 0x0041a890, 2}, + { 0x0041a8a0, 3}, + { 0x0041a8b0, 2}, + { 0x0041b014, 1}, + { 0x0041b0cc, 1}, + { 0x0041b1dc, 1}, + { 0x0041b214, 1}, + { 0x0041b2cc, 1}, + { 0x0041b3dc, 1}, + { 0x0041be0c, 3}, + { 0x0041becc, 1}, + { 0x0041bfdc, 1}, + { 0x0041c054, 1}, + { 0x0041c304, 1}, + { 0x0041c33c, 1}, + { 0x0041c348, 1}, + { 0x0041c350, 1}, + { 0x0041c3a0, 2}, + { 0x0041c3b0, 1}, + { 0x0041c3dc, 1}, + { 0x0041c40c, 1}, + { 0x0041c48c, 1}, + { 0x0041c500, 1}, + { 0x0041c508, 2}, + { 0x0041c608, 1}, + { 0x0041c680, 8}, + { 0x0041c6a8, 5}, + { 0x0041c700, 8}, + { 0x0041c728, 5}, + { 0x0041c780, 8}, + { 0x0041c7a8, 5}, + { 0x0041c854, 1}, + { 0x0041cb04, 1}, + { 0x0041cb3c, 1}, + { 0x0041cb48, 1}, + { 0x0041cb50, 1}, + { 0x0041cba0, 2}, + { 0x0041cbb0, 1}, + { 0x0041cbdc, 1}, + { 0x0041cc0c, 1}, + { 0x0041cc8c, 1}, + { 0x0041cd00, 1}, + { 0x0041cd08, 2}, + { 0x0041ce08, 1}, + { 0x0041ce80, 8}, + { 0x0041cea8, 5}, + { 0x0041cf00, 8}, + { 0x0041cf28, 5}, + { 0x0041cf80, 8}, + { 0x0041cfa8, 5}, + { 0x0041d054, 1}, + { 0x0041d304, 1}, + { 0x0041d33c, 1}, + { 0x0041d348, 1}, + { 0x0041d350, 1}, + { 0x0041d3a0, 2}, + { 0x0041d3b0, 1}, + { 0x0041d3dc, 1}, + { 0x0041d40c, 1}, + { 0x0041d48c, 1}, + { 0x0041d500, 1}, + { 0x0041d508, 2}, + { 0x0041d608, 1}, + { 0x0041d680, 8}, + { 0x0041d6a8, 5}, + { 0x0041d700, 8}, + { 0x0041d728, 5}, + { 0x0041d780, 8}, + { 0x0041d7a8, 5}, + { 0x0041d854, 1}, + { 0x0041db04, 1}, + { 0x0041db3c, 1}, + { 0x0041db48, 1}, + { 0x0041db50, 1}, + { 0x0041dba0, 2}, + { 0x0041dbb0, 1}, + { 0x0041dbdc, 1}, + { 0x0041dc0c, 1}, + { 0x0041dc8c, 1}, + { 0x0041dd00, 1}, + { 0x0041dd08, 2}, + { 0x0041de08, 1}, + { 0x0041de80, 8}, + { 0x0041dea8, 5}, + { 0x0041df00, 8}, + { 0x0041df28, 5}, + { 0x0041df80, 8}, + { 0x0041dfa8, 5}, + { 0x00500384, 1}, + { 0x005004a0, 1}, + { 0x00500604, 1}, + { 0x00500680, 1}, + { 0x00500714, 1}, + { 0x0050081c, 1}, + { 0x00500884, 1}, + { 0x005008b0, 1}, + { 0x005008c8, 3}, + { 0x005008fc, 1}, + { 0x00500b04, 1}, + { 0x00500c04, 1}, + { 0x00500c10, 8}, + { 0x00500c88, 1}, + { 0x00500d00, 1}, + { 0x00500e08, 1}, + { 0x00500f08, 1}, + { 0x00501000, 1}, + { 0x0050100c, 1}, + { 0x00501018, 1}, + { 0x00501854, 1}, + { 0x00501b04, 1}, + { 0x00501b3c, 1}, + { 0x00501b48, 1}, + { 0x00501b50, 1}, + { 0x00501ba0, 2}, + { 0x00501bb0, 1}, + { 0x00501bdc, 1}, + { 0x00501c0c, 1}, + { 0x00501c8c, 1}, + { 0x00501d00, 1}, + { 0x00501d08, 2}, + { 0x00501e08, 1}, + { 0x00501e80, 8}, + { 0x00501ea8, 5}, + { 0x00501f00, 8}, + { 0x00501f28, 5}, + { 0x00501f80, 8}, + { 0x00501fa8, 5}, + { 0x0050202c, 2}, + { 0x005020a0, 1}, + { 0x005020a8, 1}, + { 0x00502890, 2}, + { 0x005028a0, 3}, + { 0x005028b0, 2}, + { 0x00503014, 1}, + { 0x005030cc, 1}, + { 0x005031dc, 1}, + { 0x00503214, 1}, + { 0x005032cc, 1}, + { 0x005033dc, 1}, + { 0x00503e14, 1}, + { 0x00503ecc, 1}, + { 0x00503fdc, 1}, + { 0x00504054, 1}, + { 0x00504304, 1}, + { 0x0050433c, 1}, + { 0x00504348, 1}, + { 0x00504350, 1}, + { 0x005043a0, 2}, + { 0x005043b0, 1}, + { 0x005043dc, 1}, + { 0x0050440c, 1}, + { 0x0050448c, 1}, + { 0x00504500, 1}, + { 0x00504508, 2}, + { 0x00504608, 1}, + { 0x00504680, 8}, + { 0x005046a8, 5}, + { 0x00504700, 8}, + { 0x00504728, 5}, + { 0x00504780, 8}, + { 0x005047a8, 5}, + { 0x00504854, 1}, + { 0x00504b04, 1}, + { 0x00504b3c, 1}, + { 0x00504b48, 1}, + { 0x00504b50, 1}, + { 0x00504ba0, 2}, + { 0x00504bb0, 1}, + { 0x00504bdc, 1}, + { 0x00504c0c, 1}, + { 0x00504c8c, 1}, + { 0x00504d00, 1}, + { 0x00504d08, 2}, + { 0x00504e08, 1}, + { 0x00504e80, 8}, + { 0x00504ea8, 5}, + { 0x00504f00, 8}, + { 0x00504f28, 5}, + { 0x00504f80, 8}, + { 0x00504fa8, 5}, + { 0x00505054, 1}, + { 0x00505304, 1}, + { 0x0050533c, 1}, + { 0x00505348, 1}, + { 0x00505350, 1}, + { 0x005053a0, 2}, + { 0x005053b0, 1}, + { 0x005053dc, 1}, + { 0x0050540c, 1}, + { 0x0050548c, 1}, + { 0x00505500, 1}, + { 0x00505508, 2}, + { 0x00505608, 1}, + { 0x00505680, 8}, + { 0x005056a8, 5}, + { 0x00505700, 8}, + { 0x00505728, 5}, + { 0x00505780, 8}, + { 0x005057a8, 5}, + { 0x00505854, 1}, + { 0x00505b04, 1}, + { 0x00505b3c, 1}, + { 0x00505b48, 1}, + { 0x00505b50, 1}, + { 0x00505ba0, 2}, + { 0x00505bb0, 1}, + { 0x00505bdc, 1}, + { 0x00505c0c, 1}, + { 0x00505c8c, 1}, + { 0x00505d00, 1}, + { 0x00505d08, 2}, + { 0x00505e08, 1}, + { 0x00505e80, 8}, + { 0x00505ea8, 5}, + { 0x00505f00, 8}, + { 0x00505f28, 5}, + { 0x00505f80, 8}, + { 0x00505fa8, 5}, + { 0x00900100, 1}, + { 0x009a0100, 1}, +}; + +static const u32 gv11b_global_whitelist_ranges_count = + ARRAY_SIZE(gv11b_global_whitelist_ranges); + +/* context */ + +/* runcontrol */ +static const u32 gv11b_runcontrol_whitelist[] = { +}; +static const u32 gv11b_runcontrol_whitelist_count = + ARRAY_SIZE(gv11b_runcontrol_whitelist); + +static const struct regop_offset_range gv11b_runcontrol_whitelist_ranges[] = { +}; +static const u32 gv11b_runcontrol_whitelist_ranges_count = + ARRAY_SIZE(gv11b_runcontrol_whitelist_ranges); + + +/* quad ctl */ +static const u32 gv11b_qctl_whitelist[] = { +}; +static const u32 gv11b_qctl_whitelist_count = + ARRAY_SIZE(gv11b_qctl_whitelist); + +static const struct regop_offset_range gv11b_qctl_whitelist_ranges[] = { +}; +static const u32 gv11b_qctl_whitelist_ranges_count = + ARRAY_SIZE(gv11b_qctl_whitelist_ranges); + +static const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void) +{ + return gv11b_global_whitelist_ranges; +} + +static int gv11b_get_global_whitelist_ranges_count(void) +{ + return gv11b_global_whitelist_ranges_count; +} + +static const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void) +{ + return gv11b_global_whitelist_ranges; +} + +static int gv11b_get_context_whitelist_ranges_count(void) +{ + return gv11b_global_whitelist_ranges_count; +} + +static const u32 *gv11b_get_runcontrol_whitelist(void) +{ + return gv11b_runcontrol_whitelist; +} + +static int gv11b_get_runcontrol_whitelist_count(void) +{ + return gv11b_runcontrol_whitelist_count; +} + +static const +struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void) +{ + return gv11b_runcontrol_whitelist_ranges; +} + +static int gv11b_get_runcontrol_whitelist_ranges_count(void) +{ + return gv11b_runcontrol_whitelist_ranges_count; +} + +static const u32 *gv11b_get_qctl_whitelist(void) +{ + return gv11b_qctl_whitelist; +} + +static int gv11b_get_qctl_whitelist_count(void) +{ + return gv11b_qctl_whitelist_count; +} + +static const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void) +{ + return gv11b_qctl_whitelist_ranges; +} + +static int gv11b_get_qctl_whitelist_ranges_count(void) +{ + return gv11b_qctl_whitelist_ranges_count; +} + +static int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) +{ + /* Not needed on gv11b */ + return 0; +} + +void gv11b_init_regops(struct gpu_ops *gops) +{ + gops->regops.get_global_whitelist_ranges = + gv11b_get_global_whitelist_ranges; + gops->regops.get_global_whitelist_ranges_count = + gv11b_get_global_whitelist_ranges_count; + + gops->regops.get_context_whitelist_ranges = + gv11b_get_context_whitelist_ranges; + gops->regops.get_context_whitelist_ranges_count = + gv11b_get_context_whitelist_ranges_count; + + gops->regops.get_runcontrol_whitelist = + gv11b_get_runcontrol_whitelist; + gops->regops.get_runcontrol_whitelist_count = + gv11b_get_runcontrol_whitelist_count; + + gops->regops.get_runcontrol_whitelist_ranges = + gv11b_get_runcontrol_whitelist_ranges; + gops->regops.get_runcontrol_whitelist_ranges_count = + gv11b_get_runcontrol_whitelist_ranges_count; + + gops->regops.get_qctl_whitelist = + gv11b_get_qctl_whitelist; + gops->regops.get_qctl_whitelist_count = + gv11b_get_qctl_whitelist_count; + + gops->regops.get_qctl_whitelist_ranges = + gv11b_get_qctl_whitelist_ranges; + gops->regops.get_qctl_whitelist_ranges_count = + gv11b_get_qctl_whitelist_ranges_count; + + gops->regops.apply_smpc_war = + gv11b_apply_smpc_war; +} diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h new file mode 100644 index 00000000..b7250818 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h @@ -0,0 +1,24 @@ +/* + * + * Tegra GV11B GPU Driver Register Ops + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __REGOPS_GV11B_H_ +#define __REGOPS_GV11B_H_ + +void gv11b_init_regops(struct gpu_ops *gops); + +#endif /* __REGOPS_GV11B_H_ */ -- cgit v1.2.2 From cabba6686643dbb4bd8a023ad4622a49114b5159 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Mon, 16 Jan 2017 10:55:22 +0530 Subject: nvgpu: pmu: Assign pmu_queue_get_head/tail ops. pmu_get_queue_head/tail & pmu_get_queue_head/tail_size ops are defined for gv11b chip. JIRA GV11B-30 Change-Id: Iae139732d9f68f93e3c197469c04ccd3f0d63ce7 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1285749 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 6b56dd21..8432bd20 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -153,4 +153,8 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gp10b_init_pmu_ops(gops); gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; + gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; + gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; + gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; + gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; } -- cgit v1.2.2 From f04a84b7ce976e911bf81497796016e149d17082 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 6 Feb 2017 15:57:12 -0800 Subject: gpu: nvgpu: gv11b: chip specific init_elcg_mode Added thermal registers for gv11b. Implemented chip specific init_elcg_mode. In thermal control register, engine power auto control config is removed and added new field for engine holdoff enable signal. JIRA GV11B-58 Change-Id: I412d9a232800d25efbdb0a40f14949d3f085fb0e Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1300119 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 35 ++ .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 354 ++++++++++++++++++++- 2 files changed, 388 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index daadef68..3c332bbf 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -41,6 +41,7 @@ #include #include #include +#include static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) { @@ -1970,6 +1971,39 @@ static void gr_gv11b_write_pm_ptr(struct gk20a *g, ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); } +void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) +{ + u32 gate_ctrl; + + gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); + + switch (mode) { + case ELCG_RUN: + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_clk_m(), + therm_gate_ctrl_eng_clk_run_f()); + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_idle_holdoff_m(), + therm_gate_ctrl_idle_holdoff_on_f()); + break; + case ELCG_STOP: + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_clk_m(), + therm_gate_ctrl_eng_clk_stop_f()); + break; + case ELCG_AUTO: + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_clk_m(), + therm_gate_ctrl_eng_clk_auto_f()); + break; + default: + gk20a_err(dev_from_gk20a(g), + "invalid elcg mode %d", mode); + } + + gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2025,5 +2059,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.restore_context_header = gv11b_restore_context_header; gops->gr.write_zcull_ptr = gr_gv11b_write_zcull_ptr; gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; + gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index a3cfcf91..7be6d074 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -50,4 +50,356 @@ #ifndef _hw_therm_gv11b_h_ #define _hw_therm_gv11b_h_ +static inline u32 therm_use_a_r(void) +{ + return 0x00020798; +} +static inline u32 therm_use_a_ext_therm_0_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_use_a_ext_therm_1_enable_f(void) +{ + return 0x2; +} +static inline u32 therm_use_a_ext_therm_2_enable_f(void) +{ + return 0x4; +} +static inline u32 therm_evt_ext_therm_0_r(void) +{ + return 0x00020700; +} +static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_1_r(void) +{ + return 0x00020704; +} +static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_2_r(void) +{ + return 0x00020708; +} +static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) +{ + return 0x00000003; +} +static inline u32 therm_weight_1_r(void) +{ + return 0x00020024; +} +static inline u32 therm_config1_r(void) +{ + return 0x00020050; +} +static inline u32 therm_config2_r(void) +{ + return 0x00020130; +} +static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 therm_config2_grad_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 therm_gate_ctrl_r(u32 i) +{ + return 0x00020200 + i*4; +} +static inline u32 therm_gate_ctrl_eng_clk_m(void) +{ + return 0x3 << 0; +} +static inline u32 therm_gate_ctrl_eng_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) +{ + return 0x1; +} +static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) +{ + return 0x2; +} +static inline u32 therm_gate_ctrl_blk_clk_m(void) +{ + return 0x3 << 2; +} +static inline u32 therm_gate_ctrl_blk_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) +{ + return 0x4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_m(void) +{ + return 0x1 << 4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) +{ + return 0x10; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) +{ + return 0x1f << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) +{ + return (v & 0x7) << 13; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) +{ + return 0x7 << 13; +} +static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_before_m(void) +{ + return 0xf << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 therm_gate_ctrl_eng_delay_after_m(void) +{ + return 0xf << 20; +} +static inline u32 therm_fecs_idle_filter_r(void) +{ + return 0x00020288; +} +static inline u32 therm_fecs_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_hubmmu_idle_filter_r(void) +{ + return 0x0002028c; +} +static inline u32 therm_hubmmu_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_clk_slowdown_r(u32 i) +{ + return 0x00020160 + i*4; +} +static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) +{ + return (v & 0x3f) << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_m(void) +{ + return 0x3f << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) +{ + return (r >> 16) & 0x3f; +} +static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) +{ + return 0x0; +} +static inline u32 therm_grad_stepping_table_r(u32 i) +{ + return 0x000202c8 + i*4; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) +{ + return 0x3f << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) +{ + return 0x2; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) +{ + return 0x6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) +{ + return 0xe; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) +{ + return 0x3f << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) +{ + return (v & 0x3f) << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) +{ + return 0x3f << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) +{ + return (v & 0x3f) << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) +{ + return 0x3f << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) +{ + return 0x3f << 24; +} +static inline u32 therm_grad_stepping0_r(void) +{ + return 0x000202c0; +} +static inline u32 therm_grad_stepping0_feature_s(void) +{ + return 1; +} +static inline u32 therm_grad_stepping0_feature_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 therm_grad_stepping0_feature_m(void) +{ + return 0x1 << 0; +} +static inline u32 therm_grad_stepping0_feature_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 therm_grad_stepping0_feature_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping1_r(void) +{ + return 0x000202c4; +} +static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 therm_clk_timing_r(u32 i) +{ + return 0x000203c0 + i*4; +} +static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_m(void) +{ + return 0x1 << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) +{ + return 0x10000; +} #endif -- cgit v1.2.2 From a04aa3e3f014bcd4bdfd7c7f10fc0ec53ffede0a Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 7 Feb 2017 18:52:01 +0530 Subject: nvgpu: gpu: gv11b: Remove inclusion of unused header The driver file includes but does not use anything from this header. Remove this unnecessarily inclusion of header file. bug 200257351 Change-Id: Ibbc3c382c31a8c566ed4018fd36d1ffed08bf29e Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/1300556 Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 8fd6583e..3afd751a 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include -- cgit v1.2.2 From ed7b35ef60b38818e3d4d40869fe22c41ca80054 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 31 Jan 2017 13:35:37 -0800 Subject: gpu: nvgpu: gv11b : init gpu clocks gp10b_tegra_get_clocks called from gv11b_tegra_probe. Also gv11b_tegra_probe is called from nvgpu_probe via function ptr platform->probe JIRA GV11B-34 Change-Id: I782286e191eef84ce41bc65440fbe5ae00995af3 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1296840 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 3afd751a..e50a8add 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -27,22 +27,12 @@ #include "gk20a/platform_gk20a.h" #include "gk20a/gk20a.h" -#include "platform_tegra.h" -#include "gr_gv11b.h" +#include "gp10b/platform_gp10b.h" -/* - * gv11b_tegra_get_clocks() - * - * This function finds clocks in tegra platform and populates - * the clock information to gv11b platform data. - */ +#include "platform_tegra.h" +#include "gr_gv11b.h" -static int gv11b_tegra_get_clocks(struct device *dev) -{ - /* TODO */ - return 0; -} static int gv11b_tegra_probe(struct device *dev) { @@ -62,7 +52,7 @@ static int gv11b_tegra_probe(struct device *dev) /* soc memory accessed as system memory aperture */ platform->g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem; - gv11b_tegra_get_clocks(dev); + gp10b_tegra_get_clocks(dev); return 0; } -- cgit v1.2.2 From 83c09ff6821fc8f549e857c2c4a2ef6b494497f9 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 31 Jan 2017 16:08:13 -0800 Subject: gpu: nvgpu: gv11b : enable reset Init below fields in t19x_gpu_tegra_platform -reset_assert = gp10b_tegra_reset_assert -reset_deassert = gp10b_tegra_reset_deassert JIRA GV11B-34 Change-Id: I69cff5621d7fa7de830567f4cce87f79934809e2 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1296909 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index e50a8add..ab87d66f 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -127,4 +127,6 @@ struct gk20a_platform t19x_gpu_tegra_platform = { .vidmem_is_vidmem = true, + .reset_assert = gp10b_tegra_reset_assert, + .reset_deassert = gp10b_tegra_reset_deassert, }; -- cgit v1.2.2 From 8497f45a2ed8599053ad0be99143c8effb510acf Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 7 Feb 2017 15:58:01 -0800 Subject: nvgpu: gpu: gv11b: Remove syncpt protection support In gv11b sync point support is moved to a shim outside of GPU, and gv11b does not support sync points anymore. Remove use of the sync point protection. JIRA GV11B-47 JIRA GV11B-2 Change-Id: I70f3d2ce0cfe016453efe03f2bbf64c59baeb154 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1300964 Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 + .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 26 +--------------------- .../nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 4 ---- 3 files changed, 2 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index ab32016e..cd6007ba 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -228,6 +228,7 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.userd_gp_get = gv11b_userd_gp_get; gops->fifo.userd_gp_put = gv11b_userd_gp_put; gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; + gops->fifo.resetup_ramfc = NULL; gops->fifo.unbind_channel = channel_gv11b_unbind; gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index c4d3a631..7aea3870 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -518,30 +518,6 @@ static inline u32 pbdma_udma_nop_r(void) { return 0x00000008; } -static inline u32 pbdma_allowed_syncpoints_r(u32 i) -{ - return 0x000400e8 + i*8192; -} -static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) -{ - return (v & 0x7fff) << 16; -} -static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r) -{ - return (r >> 16) & 0x7fff; -} -static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) -{ - return (v & 0x1) << 15; -} -static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) -{ - return (v & 0x7fff) << 0; -} static inline u32 pbdma_runlist_timeslice_r(u32 i) { return 0x000400f8 + i*8192; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index bcbb7b81..69de33c6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -546,10 +546,6 @@ static inline u32 ram_fc_subdevice_w(void) { return 37; } -static inline u32 ram_fc_allowed_syncpoints_w(void) -{ - return 58; -} static inline u32 ram_fc_target_w(void) { return 43; -- cgit v1.2.2 From edad02b1b0071aa9fa0eac53d275e08a0051dca1 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 10 Feb 2017 16:15:42 -0800 Subject: gpu: nvgpu: Organize semaphore_gk20a.[ch] t19x version. Bug 1799159 Change-Id: I5e4c2a5341909d2e366ebc15adb4cdce70d695c7 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1303264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 1 - drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 3c332bbf..c5390fe4 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -24,7 +24,6 @@ #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" -#include "gk20a/semaphore_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gm20b/gr_gm20b.h" diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 02683d8b..63cce491 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -17,7 +17,6 @@ */ #include "gk20a/gk20a.h" -#include "gk20a/semaphore_gk20a.h" #include "gv11b/subctx_gv11b.h" -- cgit v1.2.2 From 53e718a739b4c6d6e3a1f4993a4722f28a40cff3 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Mon, 13 Feb 2017 15:13:12 +0530 Subject: gpu: nvgpu: gv11b: Use secure PMU reset for GV11B. PMU reset for GV11B is PRIV protected. gp106_pmu_reset() also uses the same register to reset PMU, therefore used same function for gv11b. Change-Id: I633a96256598e73ed02cbdfe0afdb9fba8b76afd Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1303740 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 8432bd20..29ef7f6c 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -21,6 +21,7 @@ #include "gk20a/gk20a.h" #include "gp10b/pmu_gp10b.h" +#include "gp106/pmu_gp106.h" #include "pmu_gv11b.h" @@ -153,6 +154,7 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gp10b_init_pmu_ops(gops); gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; + gops->pmu.reset = gp106_pmu_reset; gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; -- cgit v1.2.2 From 207e2ac7d12e62df476f4828136a4c15e156f8a6 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 22 Feb 2017 10:04:31 -0800 Subject: gpu: nvgpu: gv11b: reading max veid number To get maximum number of subctx, sw should read NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT instead of LITTER_NUM_SUBCTX. JIRA GV11B-72 Change-Id: I4d675ba49d8a600da77e7b60da449d9e5ba48971 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1309591 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 6 ++++-- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 12 ++++++++++++ drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 6 +----- 5 files changed, 17 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index c5390fe4..a67b1476 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1657,8 +1657,10 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) struct av_list_gk20a *sw_veid_bundle_init = &g->gr.ctx_vars.sw_veid_bundle_init; u32 j; - u32 num_subctx = nvgpu_get_litter_value(g, GPU_LIT_NUM_SUBCTX); - u32 err = 0; + u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r()); + u32 num_subctx, err = 0; + + num_subctx = gr_pri_fe_chip_def_info_max_veid_count_v(data); for (j = 0; j < num_subctx; j++) { diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index b2549edd..7467fea8 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -35,9 +35,6 @@ enum { VOLTA_DMA_COPY_A = 0xC3B5, }; -/* use magic number 99 for subctx litter value */ -#define GPU_LIT_NUM_SUBCTX 99 - #define NVC397_SET_SHADER_EXCEPTIONS 0x1528 #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 8b10245e..133a1e8d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -167,9 +167,6 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_FBPA_STRIDE: ret = proj_fbpa_stride_v(); break; - case GPU_LIT_NUM_SUBCTX: - ret = proj_litter_num_subctx_v(); - break; default: break; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 656597ba..592a7899 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -462,6 +462,18 @@ static inline u32 gr_pri_fe_go_idle_info_r(void) { return 0x00404194; } +static inline u32 gr_pri_fe_chip_def_info_r(void) +{ + return 0x00404030; +} +static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) +{ + return 0x00000040; +} static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) { return 0x00504238; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 4e30447c..98acee4c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -114,10 +114,6 @@ static inline u32 proj_host_num_pbdma_v(void) { return 0x00000003; } -static inline u32 proj_litter_num_subctx_v(void) -{ - return 0x00000040; -} static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) { return 0x00000004; -- cgit v1.2.2 From 2cc03def6a6427acdebd8a6053b1309280e5fe9b Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 28 Feb 2017 12:12:38 -0800 Subject: gpu: nvgpu: gv11b: update headers generate headers for pri ring, pbdma intr and gmmu with updated reg generator JIRA GV11B-47 JIRA GV11B-7 Change-Id: Id198fb338c03acc52c523754cfd07db01ff9bffd Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1312756 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 30 ++++++++- .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 18 ++---- .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 22 ++++++- .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 12 ++++ .../nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | 18 +++++- .../nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h | 73 ++++++++++++++++++++++ .../nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | 18 +++++- 7 files changed, 174 insertions(+), 17 deletions(-) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index d2f22afa..45cb0ad5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -826,6 +826,10 @@ static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) { return (v & 0xfffff) << 0; } +static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) +{ + return 0xfffff << 0; +} static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) { return (r >> 0) & 0xfffff; @@ -1330,6 +1334,10 @@ static inline u32 fb_mmu_fault_status_replayable_set_f(void) { return 0x100; } +static inline u32 fb_mmu_fault_status_replayable_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) { return (v & 0x1) << 9; @@ -1346,6 +1354,10 @@ static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) { return 0x200; } +static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) { return (v & 0x1) << 10; @@ -1362,6 +1374,10 @@ static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) { return 0x400; } +static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) { return (v & 0x1) << 11; @@ -1378,6 +1394,10 @@ static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) { return 0x800; } +static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) { return (v & 0x1) << 12; @@ -1394,6 +1414,10 @@ static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) { return 0x1000; } +static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) { return (v & 0x1) << 13; @@ -1410,6 +1434,10 @@ static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) { return 0x2000; } +static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) +{ + return 0x0; +} static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) { return (v & 0x1) << 14; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index d68c823a..911efa43 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -266,14 +266,6 @@ static inline u32 fifo_intr_chsw_error_r(void) { return 0x0000256c; } -static inline u32 fifo_gpc_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_hub_v(void) -{ - return 0x00000001; -} static inline u32 fifo_intr_pbdma_id_r(void) { return 0x000025a0; @@ -306,10 +298,6 @@ static inline u32 fifo_fb_timeout_period_max_f(void) { return 0x3fffffff; } -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262c; -} static inline u32 fifo_sched_disable_r(void) { return 0x00002630; @@ -406,6 +394,10 @@ static inline u32 fifo_engine_status_next_id_type_chid_v(void) { return 0x00000000; } +static inline u32 fifo_engine_status_eng_reload_v(u32 r) +{ + return (r >> 29) & 0x1; +} static inline u32 fifo_engine_status_faulted_v(u32 r) { return (r >> 30) & 0x1; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index 1c523f87..dc8473a5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1274,6 +1274,26 @@ static inline u32 gmmu_pte_kind_s8_2s_v(void) { return 0x0000002b; } +static inline u32 gmmu_fault_client_type_gpc_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_fault_client_type_hub_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_type_unbound_inst_block_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) +{ + return 0x0000001f; +} static inline u32 gmmu_fault_buf_size_v(void) { return 0x00000020; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 7aea3870..9c2ba7c6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -454,6 +454,10 @@ static inline u32 pbdma_intr_0_pbcrc_pending_f(void) { return 0x80000; } +static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) +{ + return 0x100000; +} static inline u32 pbdma_intr_0_method_pending_f(void) { return 0x200000; @@ -466,6 +470,10 @@ static inline u32 pbdma_intr_0_device_pending_f(void) { return 0x800000; } +static inline u32 pbdma_intr_0_eng_reset_pending_f(void) +{ + return 0x1000000; +} static inline u32 pbdma_intr_0_semaphore_pending_f(void) { return 0x2000000; @@ -514,6 +522,10 @@ static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) { return 0x100; } +static inline u32 pbdma_intr_stall_1_r(u32 i) +{ + return 0x00040140 + i*8192; +} static inline u32 pbdma_udma_nop_r(void) { return 0x00000008; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h index 835366c1..ce9e53ee 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -102,6 +102,22 @@ static inline u32 pri_ringmaster_intr_status0_r(void) { return 0x00120058; } +static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) +{ + return (r >> 8) & 0x1; +} static inline u32 pri_ringmaster_intr_status1_r(void) { return 0x0012005c; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h new file mode 100644 index 00000000..89abfa3c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_gpc_gv11b_h_ +#define _hw_pri_ringstation_gpc_gv11b_h_ + +static inline u32 pri_ringstation_gpc_master_config_r(u32 i) +{ + return 0x00128300 + i*4; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) +{ + return 0x00128120; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) +{ + return 0x00128124; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) +{ + return 0x00128128; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) +{ + return 0x0012812c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h index e192bd13..ae6ad795 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte { return 0x1; } +static inline u32 pri_ringstation_sys_priv_error_adr_r(void) +{ + return 0x00122120; +} +static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) +{ + return 0x00122124; +} +static inline u32 pri_ringstation_sys_priv_error_info_r(void) +{ + return 0x00122128; +} +static inline u32 pri_ringstation_sys_priv_error_code_r(void) +{ + return 0x0012212c; +} #endif -- cgit v1.2.2 From 58c72012f4a8b554083cdf7ea8061b98e8de02dc Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 23 Feb 2017 10:17:52 -0800 Subject: gpu: nvgpu: gv11b: add gr ops for load tpc mask gr_fe_tpc_fs_r addr is different for t19x Change-Id: Ibae4b7224ffbd4d8366890cd05649b1b66e22f02 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1310327 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index a67b1476..c512322b 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2005,6 +2005,11 @@ void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); } +static void gr_gv11b_load_tpc_mask(struct gk20a *g) +{ + /* TODO */ +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2061,5 +2066,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.write_zcull_ptr = gr_gv11b_write_zcull_ptr; gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode; + gops->gr.load_tpc_mask = gr_gv11b_load_tpc_mask; } -- cgit v1.2.2 From 434b1c588b9c8d61ac413b0c9ae402b483deb68b Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 28 Feb 2017 16:17:04 -0800 Subject: gpu: nvgpu: gv11b: handle l2 related changes Implemented gv11b specific l2 state init and Configured ltc_ltcs_ltss_cbc_num_active_ltcs_r with following info: - cbc_num_active_ltcs is read only for gv11b, so did not write any data to that field. - enforced serilized access to l2 from sysmem and peermem. - nvlink connected peer trafic sent through l2 JIRA GV11B-71 Change-Id: I63d9ee3f0a6da62e672a34e207f1f5214b6ed1b4 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1312831 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 38 ++++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 22 ++++++++++++- 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 85ff33d2..70919f24 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -20,6 +20,8 @@ #include "ltc_gv11b.h" #include +#include +#include /* * Sets the ZBC stencil for the passed index. @@ -39,8 +41,44 @@ static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); } +static void gv11b_ltc_init_fs_state(struct gk20a *g) +{ + u32 ltc_intr; + u32 reg; + + gk20a_dbg_info("initialize gv11b l2"); + + g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r()); + g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); + gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); + + reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); + reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(true) + | ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true); + gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), reg); + + gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(), + gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) | + ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m()); + + /* Disable LTC interrupts */ + reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); + reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m(); + reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(); + gk20a_writel(g, ltc_ltcs_ltss_intr_r(), reg); + + /* Enable ECC interrupts */ + ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); + ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | + ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); + gk20a_writel(g, ltc_ltcs_ltss_intr_r(), + ltc_intr); +} + + void gv11b_init_ltc(struct gpu_ops *gops) { gp10b_init_ltc(gops); gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; + gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index 6968c699..45d3df07 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -174,6 +174,26 @@ static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) { return 0x0017e27c; } +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) +{ + return (r >> 25) & 0x1; +} static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) { return 0x0017e000; -- cgit v1.2.2 From a4ea94f5d12f9c983cbcb9624fa946c0806768f1 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 10:42:31 -0800 Subject: gpu: nvgpu: init fifo ops for device_info_fault_id generated hw header for top_device_info_data_fault_id_enum_v is different between legacy chips and t19x JIRA GV11B-7 Change-Id: Ia765be740c419c5b2a61b03104b264c51f1e797e Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313383 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index cd6007ba..5304f39f 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "fifo_gv11b.h" #include "subctx_gv11b.h" @@ -232,4 +233,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.unbind_channel = channel_gv11b_unbind; gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; + gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; } -- cgit v1.2.2 From 8d6a05fc5704ae5ce0c46c4ec2a8ce0c17aacf68 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 12:01:37 -0800 Subject: gpu: nvgpu: gv11b: init is_fault_engine_subid_gpc ops *client_type_gpc_v moved from fifo to gmmu JIRA GV11B-7 Change-Id: Icd28a2ac8c0d0ae212cfca9410dfe781972367df Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313435 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 5304f39f..7f19d3c8 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "fifo_gv11b.h" #include "subctx_gv11b.h" @@ -217,6 +218,11 @@ static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) return ccsr_channel__size_1_v(); } +static bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) +{ + return (engine_subid == gmmu_fault_client_type_gpc_v()); +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -234,4 +240,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; + gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; } -- cgit v1.2.2 From 5e4ca8f5e8fca20b8357056242356bc608e54e27 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 15:51:32 -0800 Subject: gpu: nvgpu: gv11b: trigger mmu fault is not supported For gv11b fifo recovery, triggering fake mmu fault is not required. JIRA GV11B-7 Change-Id: I6c8c9672085dbbbd77e0d991d840c4cc75c2ab43 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313496 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 7f19d3c8..656c5421 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -241,4 +241,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; + gops->fifo.trigger_mmu_fault = NULL; } -- cgit v1.2.2 From 26cd7b3d822b0b759468300777ff6e43cb5f0f7e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 3 Mar 2017 11:59:29 -0800 Subject: gpu: nvgpu: gv11b: ltc related changes There is no peermem access for gv11b nvlink. So no need to enable peermem access through l2. Implemented gv11b specific ltc_cbc_fix_config function to read correct num_active_ltcs. JIRA GV11B-71 Change-Id: I348ce3bbf42e864341494e386b6f33478badb3a8 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1315148 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 70919f24..daad8718 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -53,8 +53,7 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); - reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(true) - | ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true); + reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true); gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), reg); gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(), @@ -75,10 +74,24 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) ltc_intr); } +u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) +{ + u32 val = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); + + if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) == 2) + return base * 2; + else if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) != 1) { + gk20a_err(dev_from_gk20a(g), + "Invalid number of active ltcs: %08x\n", val); + } + return base; +} + void gv11b_init_ltc(struct gpu_ops *gops) { gp10b_init_ltc(gops); gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; + gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; } -- cgit v1.2.2 From 679086c42ea58ce3c355e1dd8c17f662f84a2faf Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 9 Feb 2017 13:58:02 -0800 Subject: gpu: nvgpu: gv11b: support debug dump Added dump for pbdma, engine status, channel status and ramfc JIRA GV11B-45 Change-Id: I25442932c61310005fea481455f68ba10c361381 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1302425 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 93 +++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 656c5421..e33b8ee2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -15,8 +15,9 @@ #include #include +#include "nvgpu/semaphore.h" + #include "gk20a/gk20a.h" -#include "gk20a/fifo_gk20a.h" #include "gp10b/fifo_gp10b.h" @@ -223,6 +224,93 @@ static bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) return (engine_subid == gmmu_fault_client_type_gpc_v()); } +static void gv11b_dump_channel_status_ramfc(struct gk20a *g, + struct gk20a_debug_output *o, + u32 hw_chid, + struct ch_state *ch_state) +{ + u32 channel = gk20a_readl(g, ccsr_channel_r(hw_chid)); + u32 status = ccsr_channel_status_v(channel); + u32 *inst_mem; + struct channel_gk20a *c = g->fifo.channel + hw_chid; + struct nvgpu_semaphore_int *hw_sema = NULL; + + if (c->hw_sema) + hw_sema = c->hw_sema; + + if (!ch_state) + return; + + inst_mem = &ch_state->inst_block[0]; + + gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", hw_chid, + dev_name(g->dev), + ch_state->pid, + ch_state->refs); + gk20a_debug_output(o, "channel status: %s in use %s %s\n", + ccsr_channel_enable_v(channel) ? "" : "not", + gk20a_decode_ccsr_chan_status(status), + ccsr_channel_busy_v(channel) ? "busy" : "not busy"); + gk20a_debug_output(o, "RAMFC : TOP: %016llx PUT: %016llx GET: %016llx " + "FETCH: %016llx\nHEADER: %08x COUNT: %08x\n" + "SEMAPHORE: addr hi: %08x addr lo: %08x\n" + "payload %08x execute %08x\n", + (u64)inst_mem[ram_fc_pb_top_level_get_w()] + + ((u64)inst_mem[ram_fc_pb_top_level_get_hi_w()] << 32ULL), + (u64)inst_mem[ram_fc_pb_put_w()] + + ((u64)inst_mem[ram_fc_pb_put_hi_w()] << 32ULL), + (u64)inst_mem[ram_fc_pb_get_w()] + + ((u64)inst_mem[ram_fc_pb_get_hi_w()] << 32ULL), + (u64)inst_mem[ram_fc_pb_fetch_w()] + + ((u64)inst_mem[ram_fc_pb_fetch_hi_w()] << 32ULL), + inst_mem[ram_fc_pb_header_w()], + inst_mem[ram_fc_pb_count_w()], + inst_mem[ram_fc_sem_addr_hi_w()], + inst_mem[ram_fc_sem_addr_lo_w()], + inst_mem[ram_fc_sem_payload_lo_w()], + inst_mem[ram_fc_sem_execute_w()]); + if (hw_sema) + gk20a_debug_output(o, "SEMA STATE: value: 0x%08x " + "next_val: 0x%08x addr: 0x%010llx\n", + readl(hw_sema->value), + atomic_read(&hw_sema->next_value), + nvgpu_hw_sema_addr(hw_sema)); + gk20a_debug_output(o, "\n"); +} + +static void gv11b_dump_eng_status(struct gk20a *g, + struct gk20a_debug_output *o) +{ + u32 i, host_num_engines; + + host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES); + + for (i = 0; i < host_num_engines; i++) { + u32 status = gk20a_readl(g, fifo_engine_status_r(i)); + u32 ctx_status = fifo_engine_status_ctx_status_v(status); + + gk20a_debug_output(o, "%s eng %d: ", dev_name(g->dev), i); + gk20a_debug_output(o, + "id: %d (%s), next_id: %d (%s), ctx status: %s ", + fifo_engine_status_id_v(status), + fifo_engine_status_id_type_v(status) ? + "tsg" : "channel", + fifo_engine_status_next_id_v(status), + fifo_engine_status_next_id_type_v(status) ? + "tsg" : "channel", + gk20a_decode_pbdma_chan_eng_ctx_status(ctx_status)); + + if (fifo_engine_status_eng_reload_v(status)) + gk20a_debug_output(o, "ctx_reload "); + if (fifo_engine_status_faulted_v(status)) + gk20a_debug_output(o, "faulted "); + if (fifo_engine_status_engine_v(status)) + gk20a_debug_output(o, "busy "); + gk20a_debug_output(o, "\n"); + } + gk20a_debug_output(o, "\n"); +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -242,4 +330,7 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; gops->fifo.trigger_mmu_fault = NULL; + gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; + gops->fifo.dump_eng_status = gv11b_dump_eng_status; + gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; } -- cgit v1.2.2 From a29521e8d84241ea27b83f14f80547a2da601a97 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 3 Mar 2017 14:31:39 -0800 Subject: gpu: nvgpu: gv11b: add tpc floor sweeping code Added TPC floor sweeping code for gv11b. JIRA GV11B-73 Change-Id: Ib0d05e2d606fe13dff119948fbc9022e8af0fa7f Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1315257 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: Navneet Kumar --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index c512322b..fabc6819 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2007,7 +2007,32 @@ void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) static void gr_gv11b_load_tpc_mask(struct gk20a *g) { - /* TODO */ + u32 pes_tpc_mask = 0, fuse_tpc_mask; + u32 gpc, pes, val; + u32 num_tpc_per_gpc = nvgpu_get_litter_value(g, + GPU_LIT_NUM_TPC_PER_GPC); + + /* gv11b has 1 GPC and 4 TPC/GPC, so mask will not overflow u32 */ + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + for (pes = 0; pes < g->gr.pe_count_per_gpc; pes++) { + pes_tpc_mask |= g->gr.pes_tpc_mask[pes][gpc] << + num_tpc_per_gpc * gpc; + } + } + + gk20a_dbg_info("pes_tpc_mask %u\n", pes_tpc_mask); + fuse_tpc_mask = g->ops.gr.get_gpc_tpc_mask(g, gpc); + if (g->tpc_fs_mask_user && + g->tpc_fs_mask_user != fuse_tpc_mask && + fuse_tpc_mask == (0x1U << g->gr.max_tpc_count) - 1U) { + val = g->tpc_fs_mask_user; + val &= (0x1U << g->gr.max_tpc_count) - 1U; + val = (0x1U << hweight32(val)) - 1U; + gk20a_writel(g, gr_fe_tpc_fs_r(0), val); + } else { + gk20a_writel(g, gr_fe_tpc_fs_r(0), pes_tpc_mask); + } + } void gv11b_init_gr(struct gpu_ops *gops) -- cgit v1.2.2 From d5fe11091b6d74016e482d9c41580924cc70f520 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 10 Mar 2017 12:18:40 -0800 Subject: gpu: nvgpu: gv11b: fix stall interrupt enablement Currently priv, pbus and ltc interrupts are enabled as non-stall but being handled in stall isr. Fix is to configure them as stall interrupt. Change-Id: I86adc04f480d5f4befe7e9255b582ce13fa4efc1 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1319018 Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 65aad786..83c03029 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -30,8 +30,11 @@ static void mc_gv11b_intr_enable(struct gk20a *g) gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = - mc_intr_pfifo_pending_f() - | eng_intr_mask; + mc_intr_pfifo_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f() | + eng_intr_mask; gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); @@ -39,9 +42,6 @@ static void mc_gv11b_intr_enable(struct gk20a *g) 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = mc_intr_pfifo_pending_f() - | mc_intr_priv_ring_pending_f() - | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f() | eng_intr_mask; gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); -- cgit v1.2.2 From 18a0a89f4535d2f14e4a282ac01482a4c3e2e805 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 15:27:13 -0800 Subject: gpu: nvgpu: init intr_0_error_mask fifo ops mmu fault is now part of hub interrupt Change-Id: I9ce523d5f11955ac9552510d154eaa2f17a6cbf6 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313484 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index e33b8ee2..eb8f44d7 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -311,6 +311,18 @@ static void gv11b_dump_eng_status(struct gk20a *g, gk20a_debug_output(o, "\n"); } +static u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g) +{ + u32 intr_0_error_mask = + fifo_intr_0_bind_error_pending_f() | + fifo_intr_0_sched_error_pending_f() | + fifo_intr_0_chsw_error_pending_f() | + fifo_intr_0_fb_flush_timeout_pending_f() | + fifo_intr_0_lb_error_pending_f(); + + return intr_0_error_mask; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -333,4 +345,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; gops->fifo.dump_eng_status = gv11b_dump_eng_status; gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; + gops->fifo.intr_0_error_mask = gv11b_fifo_intr_0_error_mask; } -- cgit v1.2.2 From 8929fb2b1db9ddb986070efd998772e56e669e70 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 22 Feb 2017 16:01:20 -0800 Subject: gpu: nvgpu: gv11b: implement is_preempt_pending preempt completion should be decided based on pbdma and engine status. preempt_pending field is no longer used to detect if preempt finished. add a new function to to be used for preeempting ch and tsg during recovery. If preempt timeouts while in recovery, do not issue recovery. JIRA GPUT19X-7 Change-Id: I0d69d12ee6a118f6628b33be5ba387c72983b32a Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1309850 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 305 +++++++++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index eb8f44d7..b671628a 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -16,6 +16,7 @@ #include #include "nvgpu/semaphore.h" +#include #include "gk20a/gk20a.h" @@ -323,6 +324,306 @@ static u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g) return intr_0_error_mask; } +static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, + u32 pbdma_id, unsigned int timeout_rc_type) +{ + struct nvgpu_timeout timeout; + unsigned long delay = GR_IDLE_CHECK_DEFAULT; + u32 pbdma_stat; + u32 chan_stat; + int ret = -EBUSY; + + /* + * If the PBDMA has a stalling interrupt and receives a NACK, the PBDMA + * won't save out until the STALLING interrupt is cleared. Note that + * the stalling interrupt need not be directly addressed, as simply + * clearing of the interrupt bit will be sufficient to allow the PBDMA + * to save out. If the stalling interrupt was due to a SW method or + * another deterministic failure, the PBDMA will assert it when the + * channel is reloaded/resumed. Note that the fault will still be + * reported to SW. + */ + + if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* called from recovery */ + u32 pbdma_intr_0, pbdma_intr_1; + + pbdma_intr_0 = gk20a_readl(g, pbdma_intr_0_r(pbdma_id)); + pbdma_intr_1 = gk20a_readl(g, pbdma_intr_1_r(pbdma_id)); + + if (pbdma_intr_0) + gk20a_writel(g, pbdma_intr_0_r(pbdma_id), pbdma_intr_0); + if (pbdma_intr_1) + gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); + } + + /* Verify that ch/tsg is no longer on the pbdma */ + do { + pbdma_stat = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id)); + chan_stat = fifo_pbdma_status_chan_status_v(pbdma_stat); + + gk20a_dbg_info("wait preempt pbdma"); + + if (chan_stat == + fifo_pbdma_status_chan_status_valid_v() || + chan_stat == + fifo_pbdma_status_chan_status_chsw_save_v()) { + + if (id != fifo_pbdma_status_id_v(pbdma_stat)) { + ret = 0; + break; + } + + } else if (chan_stat == + fifo_pbdma_status_chan_status_chsw_load_v()) { + + if (id != fifo_pbdma_status_next_id_v(pbdma_stat)) { + ret = 0; + break; + } + + } else if (chan_stat == + fifo_pbdma_status_chan_status_chsw_switch_v()) { + + if ((id != fifo_pbdma_status_next_id_v(pbdma_stat)) && + (id != fifo_pbdma_status_id_v(pbdma_stat))) { + ret = 0; + break; + } + } else { + /* pbdma status is invalid i.e. it is not loaded */ + ret = 0; + break; + } + + usleep_range(delay, delay * 2); + delay = min_t(unsigned long, + delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired_msg(&timeout, + "preempt timeout pbdma")); + return ret; +} + +static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, + u32 engine_idx, u32 *reset_eng_bitmask, + unsigned int timeout_rc_type) +{ + struct nvgpu_timeout timeout; + unsigned long delay = GR_IDLE_CHECK_DEFAULT; + u32 eng_stat; + u32 ctx_stat; + int ret = -EBUSY; + + /* Check if ch/tsg has saved off the engine or if ctxsw is hung */ + do { + eng_stat = gk20a_readl(g, fifo_engine_status_r(engine_idx)); + ctx_stat = fifo_engine_status_ctx_status_v(eng_stat); + + if (ctx_stat == + fifo_engine_status_ctx_status_ctxsw_switch_v()) { + gk20a_dbg_info("engine save hasn't started yet"); + + } else if (ctx_stat == + fifo_engine_status_ctx_status_valid_v() || + ctx_stat == + fifo_engine_status_ctx_status_ctxsw_save_v()) { + + if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* called from recovery, eng seems to be hung */ + if (id == fifo_engine_status_id_v(eng_stat)) { + *reset_eng_bitmask |= BIT(engine_idx); + ret = 0; + break; + } + } + + } else if (ctx_stat == + fifo_engine_status_ctx_status_ctxsw_load_v()) { + + if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* called from recovery, eng seems to be hung */ + if (id == + fifo_engine_status_next_id_v(eng_stat)) { + + *reset_eng_bitmask |= BIT(engine_idx); + ret = 0; + break; + } + } + + } else { + /* Preempt should be finished */ + ret = 0; + break; + } + + usleep_range(delay, delay * 2); + delay = min_t(unsigned long, + delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired_msg(&timeout, + "preempt timeout engine")); + return ret; +} + +int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, + unsigned int id_type, unsigned int timeout_rc_type) +{ + struct fifo_gk20a *f = &g->fifo; + unsigned long runlist_served_pbdmas; + unsigned long runlist_served_engines; + u32 pbdma_id; + u32 act_eng_id; + u32 runlist_id; + int func_ret; + int ret = 0; + + gk20a_dbg_fn(""); + + if (id_type == ID_TYPE_TSG) + runlist_id = f->tsg[id].runlist_id; + else + runlist_id = f->channel[id].runlist_id; + + runlist_served_pbdmas = f->runlist_info[runlist_id].pbdma_bitmask; + runlist_served_engines = f->runlist_info[runlist_id].eng_bitmask; + + for_each_set_bit(pbdma_id, &runlist_served_pbdmas, f->num_pbdma) { + + func_ret = gv11b_fifo_poll_pbdma_chan_status(g, id, pbdma_id, + timeout_rc_type); + if (func_ret != 0) { + gk20a_dbg_info("preempt timeout pbdma %d", pbdma_id); + ret |= func_ret; + } + } + + f->runlist_info[runlist_id].reset_eng_bitmask = 0; + + for_each_set_bit(act_eng_id, &runlist_served_engines, f->num_engines) { + + func_ret = gv11b_fifo_poll_eng_ctx_status(g, id, act_eng_id, + &f->runlist_info[runlist_id].reset_eng_bitmask, + timeout_rc_type); + + if (func_ret != 0) { + gk20a_dbg_info("preempt timeout engine %d", act_eng_id); + ret |= func_ret; + } + } + + return ret; +} + +static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) +{ + struct fifo_gk20a *f = &g->fifo; + u32 ret = 0; + u32 token = PMU_INVALID_MUTEX_OWNER_ID; + u32 mutex_ret = 0; + u32 runlist_id; + + gk20a_dbg_fn("%d", hw_chid); + + runlist_id = f->channel[hw_chid].runlist_id; + gk20a_dbg_fn("runlist_id %d", runlist_id); + + nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); + + mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + ret = __locked_fifo_preempt(g, hw_chid, false); + + if (!mutex_ret) + pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); + + return ret; +} + +static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) +{ + struct fifo_gk20a *f = &g->fifo; + u32 ret = 0; + u32 token = PMU_INVALID_MUTEX_OWNER_ID; + u32 mutex_ret = 0; + u32 runlist_id; + + gk20a_dbg_fn("%d", tsgid); + + runlist_id = f->tsg[tsgid].runlist_id; + gk20a_dbg_fn("runlist_id %d", runlist_id); + + nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); + + mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + ret = __locked_fifo_preempt(g, tsgid, true); + + if (!mutex_ret) + pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); + + return ret; +} + +static int __locked_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, + unsigned int id_type, unsigned int timeout_rc_type) +{ + int ret; + + /* issue preempt */ + gk20a_fifo_issue_preempt(g, id, id_type); + + /* wait for preempt */ + ret = g->ops.fifo.is_preempt_pending(g, id, id_type, + timeout_rc_type); + + if (ret && (timeout_rc_type == PREEMPT_TIMEOUT_RC)) + __locked_fifo_preempt_timeout_rc(g, id, id_type); + + return ret; +} + + +static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, + unsigned int id_type, unsigned int timeout_rc_type) +{ + struct fifo_gk20a *f = &g->fifo; + u32 ret = 0; + u32 token = PMU_INVALID_MUTEX_OWNER_ID; + u32 mutex_ret = 0; + u32 runlist_id; + + if (id_type == ID_TYPE_TSG) + runlist_id = f->tsg[id].runlist_id; + else if (id_type == ID_TYPE_CHANNEL) + runlist_id = f->channel[id].runlist_id; + else + return -EINVAL; + + if (runlist_id >= g->fifo.max_runlists) { + gk20a_dbg_info("runlist_id = %d", runlist_id); + return -EINVAL; + } + + gk20a_dbg_fn("preempt id = %d, runlist_id = %d", id, runlist_id); + + nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); + + mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + ret = __locked_fifo_preempt_ch_tsg(g, id, id_type, timeout_rc_type); + + if (!mutex_ret) + pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); + + return ret; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -346,4 +647,8 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.dump_eng_status = gv11b_dump_eng_status; gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; gops->fifo.intr_0_error_mask = gv11b_fifo_intr_0_error_mask; + gops->fifo.preempt_channel = gv11b_fifo_preempt_channel; + gops->fifo.preempt_tsg = gv11b_fifo_preempt_tsg; + gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending; + gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; } -- cgit v1.2.2 From e83372e0cc78a16777f0d2f43936e772f40308d2 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Tue, 14 Mar 2017 13:37:58 +0200 Subject: gpu: nvgpu: gv11b: abstract away dma alloc attrs Don't use gk20a_gmmu_free_attr because the attrs are embedded in struct mem_desc now. Bug 1853519 Change-Id: Iaa4309d4c2cd334346e09c4fbf15ce826f2ff640 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1321314 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 1 - drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 9 ++++----- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 404ee921..d49c3b73 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -14,7 +14,6 @@ */ #include -#include #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 63cce491..6344b5fb 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -37,7 +37,7 @@ void gv11b_free_subctx_header(struct channel_gk20a *c) gk20a_gmmu_unmap(c->vm, ctx->mem.gpu_va, ctx->mem.size, gk20a_mem_flag_none); - gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, &ctx->mem); + gk20a_gmmu_free(g, &ctx->mem); } } @@ -51,8 +51,8 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) gk20a_dbg_fn(""); if (ctx->mem.gpu_va == 0) { - ret = gk20a_gmmu_alloc_attr_sys(g, - DMA_ATTR_NO_KERNEL_MAPPING, + ret = gk20a_gmmu_alloc_flags_sys(g, + NVGPU_DMA_NO_KERNEL_MAPPING, gr->ctx_vars.golden_image_size, &ctx->mem); if (ret) { @@ -69,8 +69,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) if (!ctx->mem.gpu_va) { gk20a_err(dev_from_gk20a(g), "failed to map ctx header"); - gk20a_gmmu_free_attr(g, DMA_ATTR_NO_KERNEL_MAPPING, - &ctx->mem); + gk20a_gmmu_free(g, &ctx->mem); return -ENOMEM; } /* Now clear the buffer */ -- cgit v1.2.2 From e24ed1f6d77dc8b277a1b4735228c5c0011559d4 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 3 Mar 2017 13:51:07 -0800 Subject: gpu: nvgpu: gv11b: init mm ops for mmu_fault_pending mmu fault reporting is moved from fifo* to fb* and gmmu* hw registers. JIRA GPUT19X-7 Change-Id: If2040ab661229c2e734042f2eec1592030615fee Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1315203 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index d49c3b73..fd77ed10 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -42,6 +42,15 @@ static void gv11b_init_inst_block(struct mem_desc *inst_block, g->ops.mm.set_big_page_size(g, inst_block, big_page_size); } +static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) +{ + if (gk20a_readl(g, fb_niso_intr_r()) & + (fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f() | + fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f())) + return true; + + return false; +} void gv11b_init_mm(struct gpu_ops *gops) { @@ -50,4 +59,5 @@ void gv11b_init_mm(struct gpu_ops *gops) gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; + gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; } -- cgit v1.2.2 From 09126db3e4bec8fd65afb4386a2a24fe307ed1b7 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Wed, 22 Mar 2017 14:38:47 +0200 Subject: gpu: nvgpu: gv11b: remove .late_probe and .remove The calls to nvhost_{register,unregister}_client_domain don't do anything, so remove the platform device's late_probe and remove ops that serve no other purpose than calling those empty functions. Remove also the corresponding #includes which are now unused. Bug 1853519 Change-Id: I67149d1575be5b3cacc60e6c28e6f2debfabf71c Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1326126 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index ab87d66f..75b72992 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -14,12 +14,10 @@ */ #include -#include #include #include #include #include -#include #include #include @@ -57,22 +55,6 @@ static int gv11b_tegra_probe(struct device *dev) return 0; } -static int gv11b_tegra_late_probe(struct device *dev) -{ - /* Make gk20a power domain a subdomain of host1x */ - nvhost_register_client_domain(dev_to_genpd(dev)); - return 0; -} - -static int gv11b_tegra_remove(struct device *dev) -{ - /* remove gk20a power subdomain from host1x */ - nvhost_unregister_client_domain(dev_to_genpd(dev)); - - return 0; - -} - static bool gv11b_tegra_is_railgated(struct device *dev) { bool ret = false; @@ -105,8 +87,6 @@ struct gk20a_platform t19x_gpu_tegra_platform = { .ptimer_src_freq = 31250000, .probe = gv11b_tegra_probe, - .late_probe = gv11b_tegra_late_probe, - .remove = gv11b_tegra_remove, /* power management callbacks */ .suspend = gv11b_tegra_suspend, -- cgit v1.2.2 From b83f2e282a8f12e2713a7ee0a2e6ef21069b2e84 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Wed, 22 Mar 2017 14:38:39 +0200 Subject: gpu: nvgpu: gv11b: remove unnecessary tegra_edp header Drop one #include, its contents are not used. Bug 1853519 Change-Id: I51480b1d75b36c993af3a5005ee9b7fc6dee8a54 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1326127 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 75b72992..87fd304f 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include -- cgit v1.2.2 From d409d7ebc136470906b861f3bebb7da63e1557e6 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 17 Mar 2017 13:47:54 -0700 Subject: gpu: nvgpu: Add bus HAL Add bus HAL and separate bus related functions from mm_gv11b: timer access. Change-Id: I311f258857238233103688fb653d27e4e79005a4 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1323354 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/gv11b/bus_gv11b.c | 26 ++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/bus_gv11b.h | 21 +++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 ++- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 1 - 5 files changed, 50 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv11b/bus_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/bus_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 112abdf2..d1b6a67c 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -2,6 +2,7 @@ nvgpu-t19x := ../../../../nvgpu-t19x/drivers/gpu/nvgpu nvgpu-y += \ $(nvgpu-t19x)/gv11b/gv11b.o \ + $(nvgpu-t19x)/gv11b/bus_gv11b.o \ $(nvgpu-t19x)/gv11b/mc_gv11b.o \ $(nvgpu-t19x)/gv11b/ltc_gv11b.o \ $(nvgpu-t19x)/gv11b/hal_gv11b.o \ diff --git a/drivers/gpu/nvgpu/gv11b/bus_gv11b.c b/drivers/gpu/nvgpu/gv11b/bus_gv11b.c new file mode 100644 index 00000000..9a70b41c --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/bus_gv11b.c @@ -0,0 +1,26 @@ +/* + * GV11B BUS + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "bus_gv11b.h" +#include "gk20a/gk20a.h" +#include "gk20a/bus_gk20a.h" + +void gv11b_init_bus(struct gpu_ops *gops) +{ + gops->bus.init_hw = gk20a_bus_init_hw; + gops->bus.isr = gk20a_bus_isr; + gops->bus.read_ptimer = gk20a_read_ptimer; + gops->bus.bar1_bind = NULL; +} diff --git a/drivers/gpu/nvgpu/gv11b/bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/bus_gv11b.h new file mode 100644 index 00000000..fde0b14b --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/bus_gv11b.h @@ -0,0 +1,21 @@ +/* + * GV11B BUS + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef BUS_GV11B_H +#define BUS_GV11B_H + +struct gpu_ops; + +void gv11b_init_bus(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 133a1e8d..1b580558 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -21,6 +21,7 @@ #include "gk20a/gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/bus_gk20a.h" #include "gm20b/gr_gm20b.h" @@ -185,6 +186,7 @@ int gv11b_init_hal(struct gk20a *g) gops->privsecurity = 0; gops->securegpccs = 0; + gk20a_init_bus(gops); gv11b_init_mc(gops); gv11b_init_ltc(gops); gv11b_init_gr(gops); @@ -203,7 +205,6 @@ int gv11b_init_hal(struct gk20a *g) gops->name = "gv11b"; gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; gops->get_litter_value = gv11b_get_litter_value; - gops->read_ptimer = gk20a_read_ptimer; c->twod_class = FERMI_TWOD_A; c->threed_class = VOLTA_A; diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index fd77ed10..84a9449a 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -55,7 +55,6 @@ static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); - gops->mm.bar1_bind = NULL; gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; -- cgit v1.2.2 From 40d2f609032a5b492decd0da4c5f50e00f765f37 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 21 Mar 2017 11:22:57 -0700 Subject: gpu: nvgpu: gv11b: implement init_pbdma_intr_desc fifo ops Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w variables for pbdma_intr_0 interrupt masks. pbdma_intr_0 field changes for gv11b:- bit 8(lbreq) does not exists in hw. bit 28 (syncpoint_illegal)is removed in hw. bit 20 is reused for clear_faulted_error in hw. bit 24 (eng_reset) and bit 25 (semaphore) always existed in hw but never handled in s/w. These are added as channel fatal. JIRA GPUT19X-47 Change-Id: I13673430408f1cf7ef762075a29b94196f79a349 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1325401 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 48 ++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b671628a..7e310984 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -624,6 +624,53 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, return ret; } +static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) +{ + /* + * These are all errors which indicate something really wrong + * going on in the device + */ + f->intr.pbdma.device_fatal_0 = + pbdma_intr_0_memreq_pending_f() | + pbdma_intr_0_memack_timeout_pending_f() | + pbdma_intr_0_memack_extra_pending_f() | + pbdma_intr_0_memdat_timeout_pending_f() | + pbdma_intr_0_memdat_extra_pending_f() | + pbdma_intr_0_memflush_pending_f() | + pbdma_intr_0_memop_pending_f() | + pbdma_intr_0_lbconnect_pending_f() | + pbdma_intr_0_lback_timeout_pending_f() | + pbdma_intr_0_lback_extra_pending_f() | + pbdma_intr_0_lbdat_timeout_pending_f() | + pbdma_intr_0_lbdat_extra_pending_f() | + pbdma_intr_0_pri_pending_f(); + + /* + * These are data parsing, framing errors or others which can be + * recovered from with intervention... or just resetting the + * channel + */ + f->intr.pbdma.channel_fatal_0 = + pbdma_intr_0_gpfifo_pending_f() | + pbdma_intr_0_gpptr_pending_f() | + pbdma_intr_0_gpentry_pending_f() | + pbdma_intr_0_gpcrc_pending_f() | + pbdma_intr_0_pbptr_pending_f() | + pbdma_intr_0_pbentry_pending_f() | + pbdma_intr_0_pbcrc_pending_f() | + pbdma_intr_0_method_pending_f() | + pbdma_intr_0_methodcrc_pending_f() | + pbdma_intr_0_pbseg_pending_f() | + pbdma_intr_0_clear_faulted_error_pending_f() | + pbdma_intr_0_eng_reset_pending_f() | + pbdma_intr_0_semaphore_pending_f() | + pbdma_intr_0_signature_pending_f(); + + /* Can be used for sw-methods, or represents a recoverable timeout. */ + f->intr.pbdma.restartable_0 = + pbdma_intr_0_device_pending_f(); +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -651,4 +698,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.preempt_tsg = gv11b_fifo_preempt_tsg; gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending; gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; + gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; } -- cgit v1.2.2 From e1cad55e529aa44d1d3646de83e563e037d80b67 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 17 Mar 2017 11:32:41 -0700 Subject: gpu: nvgpu: gv11b: null check for fault_ch gk20a_gr_get_channel_from_ctx() could return NULL as a result fault_ch could be null JIRA GPUT19X-7 Change-Id: If89507d3d3fa5a95ba75c4a90eb212d0c8b2214a Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1323255 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index fabc6819..d109dbf8 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1413,8 +1413,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, bool *early_exit, bool *ignore_debugger) { int ret; - bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode == - NVGPU_COMPUTE_PREEMPTION_MODE_CILP) ; + bool cilp_enabled = false; u32 global_mask = 0, dbgr_control0, global_esr_copy; u32 offset = proj_gpc_stride_v() * gpc + proj_tpc_in_gpc_stride_v() * tpc; @@ -1422,6 +1421,10 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, *early_exit = false; *ignore_debugger = false; + if (fault_ch) + cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode == + NVGPU_COMPUTE_PREEMPTION_MODE_CILP); + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n", gpc, tpc, global_esr); -- cgit v1.2.2 From 2dae0acaef95d959c3aee3d862f66d26562d2d0b Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 21 Mar 2017 10:13:37 -0700 Subject: gpu: nvgpu: Enable CE always All GPUs have a copy engine. So delete the flag has_ce, because it's always true. JIRA NVGPU-16 Change-Id: I6daa77ff70ccc0195352109916cb98b43a2109de Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1325357 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 87fd304f..b8479b89 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -100,8 +100,6 @@ struct gk20a_platform t19x_gpu_tegra_platform = { .default_big_page_size = SZ_64K, - .has_ce = true, - .soc_name = "tegra19x", .vidmem_is_vidmem = true, -- cgit v1.2.2 From 173cf315ad43267a22a5c3265fd65960b28fcf68 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 23 Mar 2017 15:49:58 -0700 Subject: gpu: nvgpu: gv11b: hal should use gv11b_init_bus gk20a_init_bus should not be used for gv11b hal init as bar1_bind is not supported. Change-Id: I59b6e991b12d8355b1f54ae3eaf78dc94ca6d767 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1327171 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 1b580558..ef09fc68 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -26,6 +26,7 @@ #include "gm20b/gr_gm20b.h" #include "hal_gv11b.h" +#include "bus_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" #include "ltc_gv11b.h" @@ -186,7 +187,7 @@ int gv11b_init_hal(struct gk20a *g) gops->privsecurity = 0; gops->securegpccs = 0; - gk20a_init_bus(gops); + gv11b_init_bus(gops); gv11b_init_mc(gops); gv11b_init_ltc(gops); gv11b_init_gr(gops); -- cgit v1.2.2 From b076c349b26a471776b8c487a702f791e13fb3a4 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 23 Mar 2017 15:25:37 -0700 Subject: gpu: nvgpu: gv11b: fix engine context preempt completion CTX_STATUS_SWITCH: Engine save hasn't started yet, continue to poll CTX_STATUS_INVALID: The engine context has switched off. The preemption step for this engine is complete. CTX_STATUS_VALID or CTX_STATUS_CTXSW_SAVE: check the ID field: * If ID matches the TSG for the context being torn down, the engine reset procedure can be performed, or SW can continue waiting for preempt to finish if id is not being torn down. * If ID does NOT match, the context isn't running on the engine. CTX_STATUS_LOAD: check the NEXT_ID field: * If NEXT_ID matches the TSG of the context being torn down, the engine is loading the context and reset can be performed immediately or after a delay to allow the context a chance to load and be saved off, or sw can continue waiting for preempt to finish if id is not being torn down. * If NEXT_ID does not match the TSG ID or CHID then the context is no longer on the engine. SW may alternatively wait for the CTX_STATUS to reach INVALID, but this may take longer if an unrelated context is currently on the engine or being switched to. JIRA GPUT19X-7 Change-Id: I61499f932019de32e0200084c4c41b21a7cbbd2b Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1327164 Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 7e310984..1bbf09ec 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -428,27 +428,40 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, ctx_stat == fifo_engine_status_ctx_status_ctxsw_save_v()) { - if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { - /* called from recovery, eng seems to be hung */ - if (id == fifo_engine_status_id_v(eng_stat)) { + if (id == fifo_engine_status_id_v(eng_stat)) { + if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* called from recovery, eng seems to be hung */ *reset_eng_bitmask |= BIT(engine_idx); ret = 0; break; + } else { + gk20a_dbg_info("wait preempt engine. " + "ctx_status (valid/save)=%u", ctx_stat); } + } else { + /* context is not running on the engine */ + ret = 0; + break; } } else if (ctx_stat == fifo_engine_status_ctx_status_ctxsw_load_v()) { - if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { - /* called from recovery, eng seems to be hung */ - if (id == - fifo_engine_status_next_id_v(eng_stat)) { + if (id == fifo_engine_status_next_id_v(eng_stat)) { + if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* called from recovery, eng seems to be hung */ *reset_eng_bitmask |= BIT(engine_idx); ret = 0; break; + } else { + gk20a_dbg_info("wait preempt engine. " + "ctx_status (load)=%u", ctx_stat); } + } else { + /* context is not running on the engine */ + ret = 0; + break; } } else { -- cgit v1.2.2 From 1bce980d09995947ff59b6d7f39cfaff51a70c74 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 21 Mar 2017 10:00:44 -0700 Subject: gpu: nvgpu: gv11b: init and implement reset_enable_hw -implement gv11b specific reset_enable_hw fifo ops -timeout period in fifo_fb_timeout_r() is set to init instead of max This register specifies the number of microseconds Host should wait for a response from FB before initiating a timeout interrupt. For bringup, this value should be set to a lower value than usual, such as ~.5 milliseconds (500), to help find out bugs in the memory subsystem. -timeout period in pbdma_timeout_r() is set to init instead of max This register contains a value used for detecting timeouts. The timeout value is in microsecond ticks. The timeouts that use this value are: GPfifo fetch timeouts to FB for acks, reqs, rdats. PBDMA connection to LB. GPfifo processor timeouts to FB for acks, reqs, rdats. Method processor timeouts to FB for acks, reqs, rdats. The init value is changed to 64K us based on bug 1816557. JIRA GPUT19X-74 JIRA GPUT19X-47 Change-Id: I6f818e129c3ea67571d206c5e735607cbfcf6ec6 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1325352 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 88 ++++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 4 + .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 16 ++++ 3 files changed, 108 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 1bbf09ec..bb9def35 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "fifo_gv11b.h" #include "subctx_gv11b.h" @@ -684,6 +685,92 @@ static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) pbdma_intr_0_device_pending_f(); } +static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g) +{ + u32 intr_0_en_mask; + + intr_0_en_mask = g->ops.fifo.intr_0_error_mask(g); + + intr_0_en_mask |= fifo_intr_0_runlist_event_pending_f() | + fifo_intr_0_pbdma_intr_pending_f(); + + return intr_0_en_mask; +} + +int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) +{ + u32 intr_stall; + u32 mask; + u32 timeout; + unsigned int i; + u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); + + gk20a_dbg_fn(""); + + /* enable pmc pfifo */ + g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); + + if (g->ops.clock_gating.slcg_ce2_load_gating_prod) + g->ops.clock_gating.slcg_ce2_load_gating_prod(g, + g->slcg_enabled); + if (g->ops.clock_gating.slcg_fifo_load_gating_prod) + g->ops.clock_gating.slcg_fifo_load_gating_prod(g, + g->slcg_enabled); + if (g->ops.clock_gating.blcg_fifo_load_gating_prod) + g->ops.clock_gating.blcg_fifo_load_gating_prod(g, + g->blcg_enabled); + + /* enable pbdma */ + mask = 0; + for (i = 0; i < host_num_pbdma; ++i) + mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i); + gk20a_writel(g, mc_enable_pb_r(), mask); + + + timeout = gk20a_readl(g, fifo_fb_timeout_r()); + timeout = set_field(timeout, fifo_fb_timeout_period_m(), + fifo_fb_timeout_period_init_f()); + gk20a_dbg_info("fifo_fb_timeout reg val = 0x%08x", timeout); + gk20a_writel(g, fifo_fb_timeout_r(), timeout); + + /* write pbdma timeout value */ + for (i = 0; i < host_num_pbdma; i++) { + timeout = gk20a_readl(g, pbdma_timeout_r(i)); + timeout = set_field(timeout, pbdma_timeout_period_m(), + pbdma_timeout_period_init_f()); + gk20a_dbg_info("pbdma_timeout reg val = 0x%08x", timeout); + gk20a_writel(g, pbdma_timeout_r(i), timeout); + } + /* clear and enable pbdma interrupt */ + for (i = 0; i < host_num_pbdma; i++) { + gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); + gk20a_writel(g, pbdma_intr_1_r(i), 0xFFFFFFFF); + + intr_stall = gk20a_readl(g, pbdma_intr_stall_r(i)); + gk20a_dbg_info("pbdma id:%u, intr_en_0 0x%08x", i, intr_stall); + gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall); + + intr_stall = gk20a_readl(g, pbdma_intr_stall_1_r(i)); + gk20a_dbg_info("pbdma id:%u, intr_en_1 0x%08x", i, intr_stall); + gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall); + } + + /* clear runlist interrupts */ + gk20a_writel(g, fifo_intr_runlist_r(), ~0); + + /* clear and enable pfifo interrupt */ + gk20a_writel(g, fifo_intr_0_r(), 0xFFFFFFFF); + mask = gv11b_fifo_intr_0_en_mask(g); + gk20a_dbg_info("fifo_intr_en_0 0x%08x", mask); + gk20a_writel(g, fifo_intr_en_0_r(), mask); + gk20a_dbg_info("fifo_intr_en_1 = 0x80000000"); + gk20a_writel(g, fifo_intr_en_1_r(), 0x80000000); + + gk20a_dbg_fn("done"); + + return 0; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -712,4 +799,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending; gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; + gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index 911efa43..b9249128 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -298,6 +298,10 @@ static inline u32 fifo_fb_timeout_period_max_f(void) { return 0x3fffffff; } +static inline u32 fifo_fb_timeout_period_init_f(void) +{ + return 0x3c00; +} static inline u32 fifo_sched_disable_r(void) { return 0x00002630; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 9c2ba7c6..ed63cebc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -618,4 +618,20 @@ static inline u32 pbdma_set_channel_info_veid_f(u32 v) { return (v & 0x3f) << 8; } +static inline u32 pbdma_timeout_r(u32 i) +{ + return 0x0004012c + i*8192; +} +static inline u32 pbdma_timeout_period_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 pbdma_timeout_period_max_f(void) +{ + return 0xffffffff; +} +static inline u32 pbdma_timeout_period_init_f(void) +{ + return 0x10000; +} #endif -- cgit v1.2.2 From 9773dbf905acd7dbb7ebfbbdfae529ff6f9f8ab8 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 24 Mar 2017 10:55:21 -0700 Subject: gpu: nvgpu: Remove unnecessary use of dev_name() Move the name field from struct gpu_ops up to struct gk20a. The field is not a function op, so it doesn't belong in gpu_ops. Replace all uses of dev_name() with use of g->name when possible. JIRA NVGPU-16 Change-Id: I053aeb256f591af2ea9ef5094a20e33a395cdd33 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1328535 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ef09fc68..32fd52d6 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -203,7 +203,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); - gops->name = "gv11b"; + g->name = "gv11b"; gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; gops->get_litter_value = gv11b_get_litter_value; -- cgit v1.2.2 From 3032acfc04f5c483dc08434f27f9912e7dee72c9 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 17 Mar 2017 15:40:34 -0700 Subject: gpu: nvgpu: Move programming of host registers to fifo Move code that touches host registers to fifo HAL. This sorts out some of the dependencies between fifo HAL and channel HAL. Change-Id: I2bff0443ae1c1fa5608e620974b440696d1cfdc4 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1323385 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index bb9def35..2044bb22 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -19,6 +19,7 @@ #include #include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" #include "gp10b/fifo_gp10b.h" @@ -105,7 +106,8 @@ static void gv11b_userd_writeback_config(struct gk20a *g) } static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, - u64 gpfifo_base, u32 gpfifo_entries, u32 flags) + u64 gpfifo_base, u32 gpfifo_entries, + unsigned long acquire_timeout, u32 flags) { struct gk20a *g = c->g; struct mem_desc *mem = &c->inst_block; @@ -145,7 +147,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, pbdma_target_engine_sw_f()); gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), - channel_gk20a_pbdma_acquire_val(c)); + g->ops.fifo.pbdma_acquire_val(acquire_timeout)); gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), pbdma_runlist_timeslice_timeout_128_f() | @@ -165,7 +167,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, gk20a_mem_wr32(g, mem, ram_fc_config_w(), pbdma_config_auth_level_privileged_f()); - gk20a_channel_setup_ramfc_for_privileged_channel(c); + gk20a_fifo_setup_ramfc_for_privileged_channel(c); } /* Enable userd writeback */ @@ -213,7 +215,7 @@ static void channel_gv11b_unbind(struct channel_gk20a *ch) { gk20a_dbg_fn(""); - channel_gk20a_unbind(ch); + gk20a_fifo_channel_unbind(ch); } static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) -- cgit v1.2.2 From 7b5f1bd68d8e4b90d0d5d861dbea256d982c69e5 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 13:43:40 -0800 Subject: gpu: ngpu: gv11b: support hub interrupt Hub interrupt handler will be added later JIRA GPUT19X-7 Change-Id: I892e392c6c1fe7d92795b2cab2301f2e68e787c3 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313453 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 19 ++++++++++++++++++- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 8 ++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 9588287f..61b23711 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -23,6 +23,7 @@ #include "gv11b/fb_gv11b.h" #include +#include static void gv11b_init_uncompressed_kind_map(void) { @@ -73,10 +74,26 @@ static void gv11b_init_kind_attr(void) } } +static void gv11b_fb_hub_isr(struct gk20a *g) +{ + u32 niso_intr = gk20a_readl(g, fb_niso_intr_r()); + + gk20a_dbg_info("enter hub isr, niso_intr = 0x%x", niso_intr); + + if (niso_intr & + (fb_niso_intr_hub_access_counter_notify_pending_f() | + fb_niso_intr_hub_access_counter_error_pending_f())) { + + gk20a_dbg_info("hub access counter notify/error"); + } else { + gk20a_dbg_info("mmu fault : TODO"); + } +} + void gv11b_init_fb(struct gpu_ops *gops) { gp10b_init_fb(gops); - + gops->fb.hub_isr = gv11b_fb_hub_isr; gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 83c03029..c901fd76 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -31,10 +31,12 @@ static void mc_gv11b_intr_enable(struct gk20a *g) 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = mc_intr_pfifo_pending_f() | + mc_intr_hub_pending_f() | mc_intr_priv_ring_pending_f() | mc_intr_pbus_pending_f() | mc_intr_ltc_pending_f() | eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); @@ -47,8 +49,14 @@ static void mc_gv11b_intr_enable(struct gk20a *g) g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); } +static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) +{ + return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false); +} + void gv11b_init_mc(struct gpu_ops *gops) { gp10b_init_mc(gops); gops->mc.intr_enable = mc_gv11b_intr_enable; + gops->mc.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending; } -- cgit v1.2.2 From 2766420dfbe15e539a4b9514bbf41480fc636a28 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 16 Mar 2017 15:04:29 -0700 Subject: gpu: nvgpu: gv11b: implement teardown_ch_tsg fifo ops Context TSG teardown procedure: 1. Disable scheduling for the engine's runlist via NV_PFIFO_SCHED_DISABLE. This enables SW to determine whether a context has hung later in the process: otherwise, ongoing work on the runlist may keep ENG_STATUS from reaching a steady state. 2. Disable all channels in the TSG being torn down or submit a new runlist that does not contain the TSG. This is to prevent the TSG from being rescheduled once scheduling is reenabled in step 6. 3. Initiate a preempt of the engine by writing the bit associated with its runlist to NV_PFIFO_RUNLIST_PREEMPT. This allows to begin the preempt process prior to doing the slow register reads needed to determine whether the context has hit any interrupts or is hung. Do not poll NV_PFIFO_RUNLIST_PREEMPT for the preempt to complete. 4. Check for interrupts or hangs while waiting for the preempt to complete. During the pbdma/eng preempt finish polling, any stalling interrupts relating to runlist must be detected and handled in order for the preemption to complete. 5. If a reset is needed as determined by step 4: a. Halt the memory interface for the engine (as per the relevant engine procedure). b. Reset the engine via NV_PMC_ENABLE. c. Take the engine out of reset and reinit the engine (as per relevant engine procedure) 6. Re-enable scheduling for the engine's runlist via NV_PFIFO_SCHED_ENABLE. JIRA GPUT19X-7 Change-Id: I1354dd12b4a4f0e4b4a8d9721581126c02288a85 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1327931 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 370 ++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 3 + .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 16 + 3 files changed, 388 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 2044bb22..57fd24de 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -18,8 +18,10 @@ #include "nvgpu/semaphore.h" #include + #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" +#include "gk20a/ctxsw_trace_gk20a.h" #include "gp10b/fifo_gp10b.h" @@ -360,6 +362,9 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); } + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + /* Verify that ch/tsg is no longer on the pbdma */ do { pbdma_stat = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id)); @@ -417,6 +422,9 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, u32 ctx_stat; int ret = -EBUSY; + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + /* Check if ch/tsg has saved off the engine or if ctxsw is hung */ do { eng_stat = gk20a_readl(g, fifo_engine_status_r(engine_idx)); @@ -472,12 +480,153 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, ret = 0; break; } + usleep_range(delay, delay * 2); + delay = min_t(unsigned long, + delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired_msg(&timeout, + "preempt timeout eng")); + return ret; +} + +static void gv11b_reset_eng_faulted_ch(struct gk20a *g, u32 hw_chid) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, ccsr_channel_r(hw_chid)); + reg_val |= ccsr_channel_eng_faulted_reset_f(); + gk20a_writel(g, ccsr_channel_r(hw_chid), reg_val); +} + +static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg) +{ + struct gk20a *g = tsg->g; + struct channel_gk20a *ch; + + down_read(&tsg->ch_list_lock); + list_for_each_entry(ch, &tsg->ch_list, ch_entry) { + gv11b_reset_eng_faulted_ch(g, ch->hw_chid); + } + up_read(&tsg->ch_list_lock); +} + +static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 hw_chid) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, ccsr_channel_r(hw_chid)); + reg_val |= ccsr_channel_pbdma_faulted_reset_f(); + gk20a_writel(g, ccsr_channel_r(hw_chid), reg_val); +} + +static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) +{ + struct gk20a *g = tsg->g; + struct channel_gk20a *ch; + + down_read(&tsg->ch_list_lock); + list_for_each_entry(ch, &tsg->ch_list, ch_entry) { + gv11b_reset_pbdma_faulted_ch(g, ch->hw_chid); + } + up_read(&tsg->ch_list_lock); +} + +u32 gv11b_fifo_get_runlists_mask(struct gk20a *g, u32 act_eng_bitmask, + u32 id, unsigned int id_type, unsigned int rc_type, + struct mmu_fault_info *mmfault) +{ + u32 runlists_mask = 0; + struct fifo_gk20a *f = &g->fifo; + struct fifo_runlist_info_gk20a *runlist; + u32 pbdma_bitmask = 0; + + if (id_type != ID_TYPE_UNKNOWN) { + if (id_type == ID_TYPE_TSG) + runlists_mask = fifo_sched_disable_runlist_m( + f->tsg[id].runlist_id); + else + runlists_mask = fifo_sched_disable_runlist_m( + f->channel[id].runlist_id); + } else { + if (rc_type == RC_TYPE_MMU_FAULT && mmfault) { + if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) + pbdma_bitmask = BIT(mmfault->faulted_pbdma); + + for (id = 0; id < f->max_runlists; id++) { + + runlist = &f->runlist_info[id]; + + if (runlist->eng_bitmask & act_eng_bitmask) + runlists_mask |= + fifo_sched_disable_runlist_m(id); + + if (runlist->pbdma_bitmask & pbdma_bitmask) + runlists_mask |= + fifo_sched_disable_runlist_m(id); + } + } else { + /* ID is unknown */ + for (id = 0; id < f->max_runlists; id++) { + runlist = &f->runlist_info[id]; + if (runlist->eng_bitmask & act_eng_bitmask) + runlists_mask |= + fifo_sched_disable_runlist_m(id); + } + } + } + gk20a_dbg_info("runlists_mask = %08x", runlists_mask); + return runlists_mask; +} + +static void gv11b_fifo_runlist_event_intr_disable(struct gk20a *g) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fifo_intr_en_0_r()); + reg_val &= fifo_intr_0_runlist_event_pending_f(); + gk20a_writel(g, fifo_intr_en_0_r(), reg_val); +} + +static void gv11b_fifo_runlist_event_intr_enable(struct gk20a *g) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fifo_intr_en_0_r()); + reg_val |= fifo_intr_0_runlist_event_pending_f(); + gk20a_writel(g, fifo_intr_en_0_r(), reg_val); +} + +static void gv11b_fifo_issue_runlist_preempt(struct gk20a *g, + u32 runlists_mask) +{ + u32 reg_val; + + /* issue runlist preempt */ + reg_val = gk20a_readl(g, fifo_runlist_preempt_r()); + reg_val |= runlists_mask; + gk20a_writel(g, fifo_runlist_preempt_r(), reg_val); +} + +static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g, + u32 runlists_mask) +{ + struct nvgpu_timeout timeout; + u32 delay = GR_IDLE_CHECK_DEFAULT; + int ret = -EBUSY; + + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + do { + if (!((gk20a_readl(g, fifo_runlist_preempt_r())) & + runlists_mask)) { + ret = 0; + break; + } usleep_range(delay, delay * 2); delay = min_t(unsigned long, delay << 1, GR_IDLE_CHECK_MAX); } while (!nvgpu_timeout_expired_msg(&timeout, - "preempt timeout engine")); + "runlist preempt timeout")); return ret; } @@ -557,6 +706,31 @@ static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) return ret; } +static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) +{ + int ret; + + /* + * Disable runlist event interrupt as it will get + * triggered after runlist preempt finishes + */ + gv11b_fifo_runlist_event_intr_disable(g); + + /* issue runlist preempt */ + gv11b_fifo_issue_runlist_preempt(g, runlists_mask); + + /* poll for runlist preempt done */ + ret = gv11b_fifo_poll_runlist_preempt_pending(g, runlists_mask); + + /* Clear outstanding runlist event */ + gk20a_fifo_handle_runlist_event(g); + + /* Enable runlist event interrupt*/ + gv11b_fifo_runlist_event_intr_enable(g); + + return ret; +} + static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) { struct fifo_gk20a *f = &g->fifo; @@ -584,6 +758,38 @@ static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) return ret; } + +static int gv11b_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) +{ + int ret = 0; + u32 token = PMU_INVALID_MUTEX_OWNER_ID; + u32 mutex_ret = 0; + u32 runlist_id; + + gk20a_dbg_fn(""); + + for (runlist_id = 0; runlist_id < g->fifo.max_runlists; runlist_id++) { + if (runlists_mask & fifo_runlist_preempt_runlist_m(runlist_id)) + nvgpu_mutex_acquire(&g->fifo. + runlist_info[runlist_id].mutex); + } + + mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + ret = __locked_fifo_preempt_runlists(g, runlists_mask); + + if (!mutex_ret) + pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + for (runlist_id = 0; runlist_id < g->fifo.max_runlists; runlist_id++) { + if (runlists_mask & fifo_runlist_preempt_runlist_m(runlist_id)) + nvgpu_mutex_release(&g->fifo. + runlist_info[runlist_id].mutex); + } + + return ret; +} + static int __locked_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type) { @@ -638,6 +844,167 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); return ret; + +} + +void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, + u32 id, unsigned int id_type, unsigned int rc_type, + struct mmu_fault_info *mmfault) +{ + bool verbose = false; + struct tsg_gk20a *tsg = NULL; + struct channel_gk20a *refch = NULL; + u32 runlists_mask, runlist_id; + struct fifo_runlist_info_gk20a *runlist = NULL; + u32 engine_id, client_type = ~0; + + gk20a_dbg_info("active engine ids bitmask =0x%x", act_eng_bitmask); + gk20a_dbg_info("hw id =%d", id); + gk20a_dbg_info("id_type =%d", id_type); + gk20a_dbg_info("rc_type =%d", rc_type); + gk20a_dbg_info("mmu_fault =%p", mmfault); + + runlists_mask = gv11b_fifo_get_runlists_mask(g, act_eng_bitmask, id, + id_type, rc_type, mmfault); + + gk20a_fifo_set_runlist_state(g, runlists_mask, RUNLIST_DISABLED, + !RUNLIST_INFO_MUTEX_LOCKED); + + g->fifo.deferred_reset_pending = false; + + /* Disable power management */ + if (support_gk20a_pmu(g->dev) && g->elpg_enabled) { + if (gk20a_pmu_disable_elpg(g)) + gk20a_err(dev_from_gk20a(g), + "failed to set disable elpg"); + } + if (g->ops.clock_gating.slcg_gr_load_gating_prod) + g->ops.clock_gating.slcg_gr_load_gating_prod(g, + false); + if (g->ops.clock_gating.slcg_perf_load_gating_prod) + g->ops.clock_gating.slcg_perf_load_gating_prod(g, + false); + if (g->ops.clock_gating.slcg_ltc_load_gating_prod) + g->ops.clock_gating.slcg_ltc_load_gating_prod(g, + false); + + gr_gk20a_init_cg_mode(g, ELCG_MODE, ELCG_RUN); + + if (rc_type == RC_TYPE_MMU_FAULT) + gk20a_debug_dump(g->dev); + + /* get the channel/TSG */ + if (rc_type == RC_TYPE_MMU_FAULT && mmfault && mmfault->refch) { + refch = mmfault->refch; + client_type = mmfault->client_type; + if (gk20a_is_channel_marked_as_tsg(refch)) { + tsg = &g->fifo.tsg[refch->tsgid]; + if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) + gv11b_reset_pbdma_faulted_tsg(tsg); + if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) + gv11b_reset_eng_faulted_tsg(tsg); + } else { + if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) + gv11b_reset_pbdma_faulted_ch(g, refch->hw_chid); + if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) + gv11b_reset_eng_faulted_ch(g, refch->hw_chid); + } + } else { + if (id_type == ID_TYPE_TSG) + tsg = &g->fifo.tsg[id]; + else if (id_type == ID_TYPE_CHANNEL) + refch = gk20a_channel_get(&g->fifo.channel[id]); + } + + if (id_type == ID_TYPE_TSG || id_type == ID_TYPE_CHANNEL) { + g->ops.fifo.preempt_ch_tsg(g, id, id_type, + PREEMPT_TIMEOUT_NORC); + } else { + gv11b_fifo_preempt_runlists(g, runlists_mask); + } + + if (tsg) { + if (!g->fifo.deferred_reset_pending) { + if (rc_type == RC_TYPE_MMU_FAULT) { + gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg); + verbose = gk20a_fifo_error_tsg(g, tsg); + } + } + gk20a_fifo_abort_tsg(g, tsg->tsgid, false); + if (refch) + gk20a_channel_put(refch); + } else if (refch) { + if (!g->fifo.deferred_reset_pending) { + if (rc_type == RC_TYPE_MMU_FAULT) { + gk20a_fifo_set_ctx_mmu_error_ch(g, refch); + verbose = gk20a_fifo_error_ch(g, refch); + } + } + gk20a_channel_abort(refch, false); + gk20a_channel_put(refch); + } else { + gk20a_err(dev_from_gk20a(g), "id unknown, abort runlist"); + for (runlist_id = 0; runlist_id < g->fifo.max_runlists; + runlist_id++) { + if (runlists_mask & BIT(runlist_id)) + g->ops.fifo.update_runlist(g, runlist_id, + FIFO_INVAL_CHANNEL_ID, false, true); + } + } + + /* check if engine reset should be deferred */ + for (runlist_id = 0; runlist_id < g->fifo.max_runlists; runlist_id++) { + + runlist = &g->fifo.runlist_info[runlist_id]; + if ((runlists_mask & BIT(runlist_id)) && + runlist->reset_eng_bitmask) { + + unsigned long __reset_eng_bitmask = + runlist->reset_eng_bitmask; + + for_each_set_bit(engine_id, &__reset_eng_bitmask, 32) { + if ((refch || tsg) && + gk20a_fifo_should_defer_engine_reset(g, + engine_id, client_type, false)) { + + g->fifo.deferred_fault_engines |= + BIT(engine_id); + + /* handled during channel free */ + g->fifo.deferred_reset_pending = true; + gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, + "sm debugger attached," + " deferring channel recovery to channel free"); + } else { + /* + * if lock is already taken, a reset is + * taking place so no need to repeat + */ + if (nvgpu_mutex_tryacquire( + &g->fifo.gr_reset_mutex)) { + + gk20a_fifo_reset_engine(g, + engine_id); + + nvgpu_mutex_release( + &g->fifo.gr_reset_mutex); + } + } + } + } + } + + if (refch) + gk20a_ctxsw_trace_channel_reset(g, refch); + else if (tsg) + gk20a_ctxsw_trace_tsg_reset(g, tsg); + + gk20a_fifo_set_runlist_state(g, runlists_mask, RUNLIST_ENABLED, + !RUNLIST_INFO_MUTEX_LOCKED); + + /* It is safe to enable ELPG again. */ + if (support_gk20a_pmu(g->dev) && g->elpg_enabled) + gk20a_pmu_enable_elpg(g); } static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) @@ -802,4 +1169,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw; + gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg; } diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 5b95ad9e..07a39da0 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -15,6 +15,9 @@ #ifndef FIFO_GV11B_H #define FIFO_GV11B_H + +#define FIFO_INVAL_PBDMA_ID ((u32)~0) + struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index b9249128..f05df49e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -318,6 +318,22 @@ static inline u32 fifo_sched_disable_true_v(void) { return 0x00000001; } +static inline u32 fifo_runlist_preempt_r(void) +{ + return 0x00002638; +} +static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_runlist_preempt_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_runlist_preempt_runlist_pending_v(void) +{ + return 0x00000001; +} static inline u32 fifo_preempt_r(void) { return 0x00002634; -- cgit v1.2.2 From 633d331ae2db50fbcce829fe324c19fc44b82c24 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 22 Mar 2017 10:00:24 -0700 Subject: gpu: nvgpu: Rename gk20a_mem_* functions Rename the functions used for mem_desc access to nvgpu_mem_*. JIRA NVGPU-12 Change-Id: I5a1180c9a08d33c3dfc361ce8579c3c767fa5656 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1326193 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 32 +++++++++++----------- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 50 +++++++++++++++++----------------- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 24 ++++++++-------- 3 files changed, 53 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 57fd24de..dd56a6f9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -117,20 +117,20 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, gk20a_dbg_fn(""); - gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v()); + nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v()); - gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(), + nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(), pbdma_gp_base_offset_f( u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); - gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), + nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); - gk20a_mem_wr32(g, mem, ram_fc_signature_w(), + nvgpu_mem_wr32(g, mem, ram_fc_signature_w(), c->g->ops.fifo.get_pbdma_signature(c->g)); - gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(), + nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(), pbdma_pb_header_priv_user_f() | pbdma_pb_header_method_zero_f() | pbdma_pb_header_subchannel_zero_f() | @@ -138,44 +138,44 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, pbdma_pb_header_first_true_f() | pbdma_pb_header_type_inc_f()); - gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(), + nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(), pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) | pbdma_subdevice_status_active_f() | pbdma_subdevice_channel_dma_enable_f()); - gk20a_mem_wr32(g, mem, ram_fc_target_w(), + nvgpu_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_eng_ctx_valid_true_f() | pbdma_target_ce_ctx_valid_true_f() | pbdma_target_engine_sw_f()); - gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), + nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(), g->ops.fifo.pbdma_acquire_val(acquire_timeout)); - gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), + nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), pbdma_runlist_timeslice_timeout_128_f() | pbdma_runlist_timeslice_timescale_3_f() | pbdma_runlist_timeslice_enable_true_f()); - gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); /* Until full subcontext is supported, always use VEID0 */ - gk20a_mem_wr32(g, mem, ram_fc_set_channel_info_w(), + nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), pbdma_set_channel_info_scg_type_graphics_compute0_f() | pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); if (c->is_privileged_channel) { /* Set privilege level for channel */ - gk20a_mem_wr32(g, mem, ram_fc_config_w(), + nvgpu_mem_wr32(g, mem, ram_fc_config_w(), pbdma_config_auth_level_privileged_f()); gk20a_fifo_setup_ramfc_for_privileged_channel(c); } /* Enable userd writeback */ - data = gk20a_mem_rd32(g, mem, ram_fc_config_w()); + data = nvgpu_mem_rd32(g, mem, ram_fc_config_w()); data = data | pbdma_config_userd_writeback_enable_f(); - gk20a_mem_wr32(g, mem, ram_fc_config_w(),data); + nvgpu_mem_wr32(g, mem, ram_fc_config_w(),data); gv11b_userd_writeback_config(g); @@ -196,7 +196,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) struct mem_desc *userd_mem = &g->fifo.userd; u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); - return gk20a_mem_rd32(g, userd_mem, + return nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_gp_get_w()); } @@ -205,7 +205,7 @@ static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) struct mem_desc *userd_mem = &g->fifo.userd; u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); - gk20a_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), + nvgpu_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), c->gpfifo.put); /* commit everything to cpu */ smp_mb(); diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index d109dbf8..ddaaa350 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -780,36 +780,36 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, { struct mem_desc *mem = &gr_ctx->mem; - if (gk20a_mem_begin(g, mem)) { + if (nvgpu_mem_begin(g, mem)) { WARN_ON("Cannot map context"); return; } gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_magic_value_o()), ctxsw_prog_main_image_magic_value_v_value_v()); gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_save_ops_o())); gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_wfi_save_ops_o())); gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_cta_save_ops_o())); gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_gfxp_save_ops_o())); gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_cilp_save_ops_o())); gk20a_err(dev_from_gk20a(g), "image gfx preemption option (GFXP is 1) %x\n", - gk20a_mem_rd(g, mem, + nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_graphics_preemption_options_o())); - gk20a_mem_end(g, mem); + nvgpu_mem_end(g, mem); } static void gr_gv11b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, @@ -847,13 +847,13 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) { gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_graphics_preemption_options_o(), + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_graphics_preemption_options_o(), gfxp_preempt_option); } if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) { gk20a_dbg_info("CILP: %x", cilp_preempt_option); - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_compute_preemption_options_o(), + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_compute_preemption_options_o(), cilp_preempt_option); } @@ -862,7 +862,7 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, u32 size; u32 cbes_reserve; - gk20a_mem_wr(g, mem, ctxsw_prog_main_image_full_preemption_ptr_o(), + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_full_preemption_ptr_o(), gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8); err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); @@ -1858,12 +1858,12 @@ static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) addr_hi = u64_hi32(ctx->mem.gpu_va); /* point this address to engine_wfi_ptr */ - gk20a_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(), + nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(), ram_in_engine_cs_wfi_v() | ram_in_engine_wfi_mode_f(ram_in_engine_wfi_mode_virtual_v()) | ram_in_engine_wfi_ptr_lo_f(addr_lo)); - gk20a_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_ptr_hi_w(), + nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_ptr_hi_w(), ram_in_engine_wfi_ptr_hi_f(addr_hi)); return 0; @@ -1930,20 +1930,20 @@ static void gv11b_restore_context_header(struct gk20a *g, u32 va_lo, va_hi; struct gr_gk20a *gr = &g->gr; - va_hi = gk20a_mem_rd(g, ctxheader, + va_hi = nvgpu_mem_rd(g, ctxheader, ctxsw_prog_main_image_context_buffer_ptr_hi_o()); - va_lo = gk20a_mem_rd(g, ctxheader, + va_lo = nvgpu_mem_rd(g, ctxheader, ctxsw_prog_main_image_context_buffer_ptr_o()); - gk20a_mem_wr_n(g, ctxheader, 0, + nvgpu_mem_wr_n(g, ctxheader, 0, gr->ctx_vars.local_golden_image, gr->ctx_vars.golden_image_size); - gk20a_mem_wr(g, ctxheader, + nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_context_buffer_ptr_hi_o(), va_hi); - gk20a_mem_wr(g, ctxheader, + nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_context_buffer_ptr_o(), va_lo); - gk20a_mem_wr(g, ctxheader, + nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_num_restore_ops_o(), 0); - gk20a_mem_wr(g, ctxheader, + nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_num_save_ops_o(), 0); } static void gr_gv11b_write_zcull_ptr(struct gk20a *g, @@ -1954,9 +1954,9 @@ static void gr_gv11b_write_zcull_ptr(struct gk20a *g, gpu_va = gpu_va >> 8; va_lo = u64_lo32(gpu_va); va_hi = u64_hi32(gpu_va); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_zcull_ptr_o(), va_lo); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_zcull_ptr_hi_o(), va_hi); } @@ -1969,9 +1969,9 @@ static void gr_gv11b_write_pm_ptr(struct gk20a *g, gpu_va = gpu_va >> 8; va_lo = u64_lo32(gpu_va); va_hi = u64_hi32(gpu_va); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_pm_ptr_o(), va_lo); - gk20a_mem_wr(g, mem, + nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); } diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 6344b5fb..8bf0631e 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -73,11 +73,11 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) return -ENOMEM; } /* Now clear the buffer */ - if (gk20a_mem_begin(g, &ctx->mem)) + if (nvgpu_mem_begin(g, &ctx->mem)) return -ENOMEM; - gk20a_memset(g, &ctx->mem, 0, 0, ctx->mem.size); - gk20a_mem_end(g, &ctx->mem); + nvgpu_memset(g, &ctx->mem, 0, 0, ctx->mem.size); + nvgpu_mem_end(g, &ctx->mem); gv11b_init_subcontext_pdb(c, &c->inst_block); @@ -111,14 +111,14 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); lo = ram_in_sc_page_dir_base_vol_0_w(); hi = ram_in_sc_page_dir_base_hi_0_w(); - gk20a_mem_wr32(g, inst_block, lo, format_word); - gk20a_mem_wr32(g, inst_block, hi, pdb_addr_hi); + nvgpu_mem_wr32(g, inst_block, lo, format_word); + nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); /* make subcontext0 address space to valid */ /* TODO fix proper hw register definations */ - gk20a_mem_wr32(g, inst_block, 166, 0x1); - gk20a_mem_wr32(g, inst_block, 167, 0); - gk20a_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), + nvgpu_mem_wr32(g, inst_block, 166, 0x1); + nvgpu_mem_wr32(g, inst_block, 167, 0); + nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), ram_in_engine_wfi_veid_f(0)); } @@ -136,13 +136,13 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) gr_mem = &ctx->mem; g->ops.mm.l2_flush(g, true); - if (gk20a_mem_begin(g, gr_mem)) + if (nvgpu_mem_begin(g, gr_mem)) return -ENOMEM; - gk20a_mem_wr(g, gr_mem, + nvgpu_mem_wr(g, gr_mem, ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi); - gk20a_mem_wr(g, gr_mem, + nvgpu_mem_wr(g, gr_mem, ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo); - gk20a_mem_end(g, gr_mem); + nvgpu_mem_end(g, gr_mem); return ret; } -- cgit v1.2.2 From c876bec8bab5a1e4d6dea529700ef19c5eac5e64 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 22 Mar 2017 10:01:14 -0700 Subject: gpu: nvgpu: rename mem_desc to nvgpu_mem $ find -type f | \ xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g' JIRA NVGPU-12 Change-Id: I2b5d015e45185269bfae7c6d4199fe843ff26834 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1326194 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 6 +++--- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 12 ++++++------ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 +- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 6 +++--- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index dd56a6f9..30d695ff 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -112,7 +112,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, unsigned long acquire_timeout, u32 flags) { struct gk20a *g = c->g; - struct mem_desc *mem = &c->inst_block; + struct nvgpu_mem *mem = &c->inst_block; u32 data; gk20a_dbg_fn(""); @@ -193,7 +193,7 @@ static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) { - struct mem_desc *userd_mem = &g->fifo.userd; + struct nvgpu_mem *userd_mem = &g->fifo.userd; u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); return nvgpu_mem_rd32(g, userd_mem, @@ -202,7 +202,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) { - struct mem_desc *userd_mem = &g->fifo.userd; + struct nvgpu_mem *userd_mem = &g->fifo.userd; u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); nvgpu_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index ddaaa350..6e6b5630 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -642,7 +642,7 @@ static int gr_gv11b_init_ctx_state(struct gk20a *g) } int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, - struct mem_desc *mem) + struct nvgpu_mem *mem) { int err; @@ -778,7 +778,7 @@ fail_free_gk20a_ctx: static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx) { - struct mem_desc *mem = &gr_ctx->mem; + struct nvgpu_mem *mem = &gr_ctx->mem; if (nvgpu_mem_begin(g, mem)) { WARN_ON("Cannot map context"); @@ -834,7 +834,7 @@ static void gr_gv11b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, - struct mem_desc *mem) + struct nvgpu_mem *mem) { struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; u32 gfxp_preempt_option = @@ -1925,7 +1925,7 @@ static int gr_gv11b_commit_global_timeslice(struct gk20a *g, } static void gv11b_restore_context_header(struct gk20a *g, - struct mem_desc *ctxheader) + struct nvgpu_mem *ctxheader) { u32 va_lo, va_hi; struct gr_gk20a *gr = &g->gr; @@ -1947,7 +1947,7 @@ static void gv11b_restore_context_header(struct gk20a *g, ctxsw_prog_main_image_num_save_ops_o(), 0); } static void gr_gv11b_write_zcull_ptr(struct gk20a *g, - struct mem_desc *mem, u64 gpu_va) + struct nvgpu_mem *mem, u64 gpu_va) { u32 va_lo, va_hi; @@ -1962,7 +1962,7 @@ static void gr_gv11b_write_zcull_ptr(struct gk20a *g, static void gr_gv11b_write_pm_ptr(struct gk20a *g, - struct mem_desc *mem, u64 gpu_va) + struct nvgpu_mem *mem, u64 gpu_va) { u32 va_lo, va_hi; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 7467fea8..9d9f969d 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -44,7 +44,7 @@ enum { void gv11b_init_gr(struct gpu_ops *ops); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, - struct mem_desc *mem); + struct nvgpu_mem *mem); /*zcull*/ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, u32 *zcull_map_tiles); diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 84a9449a..269108ff 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -28,7 +28,7 @@ static bool gv11b_mm_is_bar1_supported(struct gk20a *g) return false; } -static void gv11b_init_inst_block(struct mem_desc *inst_block, +static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, u32 big_page_size) { struct gk20a *g = gk20a_from_vm(vm); diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 8bf0631e..757baa6e 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -24,7 +24,7 @@ #include static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, - struct mem_desc *inst_block); + struct nvgpu_mem *inst_block); void gv11b_free_subctx_header(struct channel_gk20a *c) { @@ -86,7 +86,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) } static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, - struct mem_desc *inst_block) + struct nvgpu_mem *inst_block) { struct gk20a *g = c->g; struct vm_gk20a *vm; @@ -126,7 +126,7 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) { struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; - struct mem_desc *gr_mem; + struct nvgpu_mem *gr_mem; struct gk20a *g = c->g; int ret = 0; u32 addr_lo, addr_hi; -- cgit v1.2.2 From 26159aed046393e5d01060323a76f838d2f5bba3 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 4 Apr 2017 23:59:09 +0100 Subject: gpu: nvgpu: Move DMA API to dma.h Handle gv11b specific of gpu: nvgpu: Move DMA API to dma.h In the main nvgpu repository. JIRA NVGPU-12 Change-Id: I9645c4eedc5f61585d15caeee54db92bc4cca079 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1455212 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 1 + drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 6e6b5630..a9f0d1e0 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -21,6 +21,7 @@ #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 757baa6e..a2b7de1c 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -16,6 +16,8 @@ * this program. */ +#include + #include "gk20a/gk20a.h" #include "gv11b/subctx_gv11b.h" -- cgit v1.2.2 From 1a426c981c4fa2816d969b27163ab2dbc2fa4e89 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 5 Apr 2017 00:08:52 +0100 Subject: gpu: nvgpu: Rename nvgpu DMA APIs gv11b changes to go along with gpu: nvgpu: Rename nvgpu DMA APIs In the main nvgpu repo. JIRA NVGPU-12 Change-Id: I5e28b13448d171e1511ace0842e53700385f8489 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1455213 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 18 +++++++++--------- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 6 +++--- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index a9f0d1e0..f4e31ec0 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -649,7 +649,7 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, gk20a_dbg_fn(""); - err = gk20a_gmmu_alloc_sys(vm->mm->g, size, mem); + err = nvgpu_dma_alloc_sys(vm->mm->g, size, mem); if (err) return err; @@ -669,7 +669,7 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, return 0; fail_free: - gk20a_gmmu_free(vm->mm->g, mem); + nvgpu_dma_free(vm->mm->g, mem); return err; } @@ -764,11 +764,11 @@ static int gr_gv11b_alloc_gr_ctx(struct gk20a *g, return err; fail_free_betacb: - gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.betacb_ctxsw_buffer); + nvgpu_dma_unmap_free(vm, &(*gr_ctx)->t18x.betacb_ctxsw_buffer); fail_free_spill: - gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.spill_ctxsw_buffer); + nvgpu_dma_unmap_free(vm, &(*gr_ctx)->t18x.spill_ctxsw_buffer); fail_free_preempt: - gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.preempt_ctxsw_buffer); + nvgpu_dma_unmap_free(vm, &(*gr_ctx)->t18x.preempt_ctxsw_buffer); fail_free_gk20a_ctx: gr_gk20a_free_gr_ctx(g, vm, *gr_ctx); *gr_ctx = NULL; @@ -824,10 +824,10 @@ static void gr_gv11b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, if (g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close) dump_ctx_switch_stats(g, vm, gr_ctx); - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); + nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); + nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); + nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); + nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); gr_gk20a_free_gr_ctx(g, vm, gr_ctx); gk20a_dbg_fn("done"); } diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index a2b7de1c..8b322296 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -39,7 +39,7 @@ void gv11b_free_subctx_header(struct channel_gk20a *c) gk20a_gmmu_unmap(c->vm, ctx->mem.gpu_va, ctx->mem.size, gk20a_mem_flag_none); - gk20a_gmmu_free(g, &ctx->mem); + nvgpu_dma_free(g, &ctx->mem); } } @@ -53,7 +53,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) gk20a_dbg_fn(""); if (ctx->mem.gpu_va == 0) { - ret = gk20a_gmmu_alloc_flags_sys(g, + ret = nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_NO_KERNEL_MAPPING, gr->ctx_vars.golden_image_size, &ctx->mem); @@ -71,7 +71,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) if (!ctx->mem.gpu_va) { gk20a_err(dev_from_gk20a(g), "failed to map ctx header"); - gk20a_gmmu_free(g, &ctx->mem); + nvgpu_dma_free(g, &ctx->mem); return -ENOMEM; } /* Now clear the buffer */ -- cgit v1.2.2 From 7fe4b6572ba80dda58d513969b69e22437901077 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 10 Apr 2017 11:09:13 -0700 Subject: gpu: nvgpu: gv11b: Use new error macros gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I8c0d8944f625e3c5b16a9f5a2a59d95a680f4e55 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1459822 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 5 ++- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 63 ++++++++++++++-------------------- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 11 +++--- 3 files changed, 32 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 30d695ff..3c1982fe 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -875,8 +875,7 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, /* Disable power management */ if (support_gk20a_pmu(g->dev) && g->elpg_enabled) { if (gk20a_pmu_disable_elpg(g)) - gk20a_err(dev_from_gk20a(g), - "failed to set disable elpg"); + nvgpu_err(g, "failed to set disable elpg"); } if (g->ops.clock_gating.slcg_gr_load_gating_prod) g->ops.clock_gating.slcg_gr_load_gating_prod(g, @@ -943,7 +942,7 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, gk20a_channel_abort(refch, false); gk20a_channel_put(refch); } else { - gk20a_err(dev_from_gk20a(g), "id unknown, abort runlist"); + nvgpu_err(g, "id unknown, abort runlist"); for (runlist_id = 0; runlist_id < g->fifo.max_runlists; runlist_id++) { if (runlists_mask & BIT(runlist_id)) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index f4e31ec0..5b0526b0 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -22,6 +22,7 @@ #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" @@ -234,8 +235,7 @@ static int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, u32 index = query_params->index_size; if (index >= GK20A_ZBC_TABLE_SIZE) { - gk20a_err(dev_from_gk20a(g), - "invalid zbc stencil table index\n"); + nvgpu_err(g, "invalid zbc stencil table index"); return -EINVAL; } query_params->depth = gr->zbc_s_tbl[index].stencil; @@ -332,8 +332,7 @@ static int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, if (!err) { gr->max_default_s_index = 3; } else { - gk20a_err(dev_from_gk20a(g), - "fail to load default zbc stencil table\n"); + nvgpu_err(g, "fail to load default zbc stencil table"); return err; } @@ -628,8 +627,7 @@ static int gr_gv11b_init_ctx_state(struct gk20a *g) op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size; err = gr_gk20a_submit_fecs_method_op(g, op, false); if (err) { - gk20a_err(dev_from_gk20a(g), - "query preempt image size failed"); + nvgpu_err(g, "query preempt image size failed"); return err; } } @@ -717,8 +715,7 @@ static int gr_gv11b_alloc_gr_ctx(struct gk20a *g, g->gr.t18x.ctx_vars.preempt_image_size, &(*gr_ctx)->t18x.preempt_ctxsw_buffer); if (err) { - gk20a_err(dev_from_gk20a(vm->mm->g), - "cannot allocate preempt buffer"); + nvgpu_err(vm->mm->g, "cannot allocate preempt buffer"); goto fail_free_gk20a_ctx; } @@ -726,8 +723,7 @@ static int gr_gv11b_alloc_gr_ctx(struct gk20a *g, spill_size, &(*gr_ctx)->t18x.spill_ctxsw_buffer); if (err) { - gk20a_err(dev_from_gk20a(vm->mm->g), - "cannot allocate spill buffer"); + nvgpu_err(vm->mm->g, "cannot allocate spill buffer"); goto fail_free_preempt; } @@ -735,8 +731,7 @@ static int gr_gv11b_alloc_gr_ctx(struct gk20a *g, attrib_cb_size, &(*gr_ctx)->t18x.betacb_ctxsw_buffer); if (err) { - gk20a_err(dev_from_gk20a(vm->mm->g), - "cannot allocate beta buffer"); + nvgpu_err(vm->mm->g, "cannot allocate beta buffer"); goto fail_free_spill; } @@ -744,8 +739,7 @@ static int gr_gv11b_alloc_gr_ctx(struct gk20a *g, pagepool_size, &(*gr_ctx)->t18x.pagepool_ctxsw_buffer); if (err) { - gk20a_err(dev_from_gk20a(vm->mm->g), - "cannot allocate page pool"); + nvgpu_err(vm->mm->g, "cannot allocate page pool"); goto fail_free_betacb; } @@ -785,29 +779,28 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, WARN_ON("Cannot map context"); return; } - gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n", + nvgpu_err(g, "ctxsw_prog_main_image_magic_value_o : %x (expect %x)", nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_magic_value_o()), ctxsw_prog_main_image_magic_value_v_value_v()); - gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", + nvgpu_err(g, "NUM_SAVE_OPERATIONS : %d", nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_save_ops_o())); - gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n", + nvgpu_err(g, "WFI_SAVE_OPERATIONS : %d", nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_wfi_save_ops_o())); - gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n", + nvgpu_err(g, "CTA_SAVE_OPERATIONS : %d", nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_cta_save_ops_o())); - gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n", + nvgpu_err(g, "GFXP_SAVE_OPERATIONS : %d", nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_gfxp_save_ops_o())); - gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n", + nvgpu_err(g, "CILP_SAVE_OPERATIONS : %d", nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_num_cilp_save_ops_o())); - gk20a_err(dev_from_gk20a(g), - "image gfx preemption option (GFXP is 1) %x\n", + nvgpu_err(g, "image gfx preemption option (GFXP is 1) %x", nvgpu_mem_rd(g, mem, ctxsw_prog_main_image_graphics_preemption_options_o())); nvgpu_mem_end(g, mem); @@ -868,8 +861,7 @@ static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); if (err) { - gk20a_err(dev_from_gk20a(g), - "can't map patch context"); + nvgpu_err(g, "can't map patch context"); goto out; } @@ -1118,7 +1110,7 @@ static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, } while (!nvgpu_timeout_expired(&timeout)); - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "timeout, ctxsw busy : %d, gr busy : %d, %08x, %08x, %08x, %08x", ctxsw_active, gr_busy, activity0, activity1, activity2, activity4); @@ -1272,15 +1264,13 @@ static int gr_gv11b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a ret = gk20a_disable_channel_tsg(g, fault_ch); if (ret) { - gk20a_err(dev_from_gk20a(g), - "CILP: failed to disable channel/TSG!\n"); + nvgpu_err(g, "CILP: failed to disable channel/TSG!"); return ret; } ret = g->ops.fifo.update_runlist(g, fault_ch->runlist_id, ~0, true, false); if (ret) { - gk20a_err(dev_from_gk20a(g), - "CILP: failed to restart runlist 0!"); + nvgpu_err(g, "CILP: failed to restart runlist 0!"); return ret; } @@ -1319,7 +1309,7 @@ static int gr_gv11b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk2 "CILP: looking up ctx id"); ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->t18x.ctx_id); if (ret) { - gk20a_err(dev_from_gk20a(g), "CILP: error looking up ctx id!\n"); + nvgpu_err(g, "CILP: error looking up ctx id!"); return ret; } gr_ctx->t18x.ctx_id_valid = true; @@ -1343,8 +1333,7 @@ static int gr_gv11b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk2 .cond.fail = GR_IS_UCODE_OP_SKIP}); if (ret) { - gk20a_err(dev_from_gk20a(g), - "CILP: failed to enable ctxsw interrupt!"); + nvgpu_err(g, "CILP: failed to enable ctxsw interrupt!"); return ret; } @@ -1357,8 +1346,7 @@ static int gr_gv11b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk2 ret = gr_gv11b_disable_channel_or_tsg(g, fault_ch); if (ret) { - gk20a_err(dev_from_gk20a(g), - "CILP: failed to disable channel!!"); + nvgpu_err(g, "CILP: failed to disable channel!!"); return ret; } @@ -1472,7 +1460,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Setting CILP preempt pending\n"); ret = gr_gv11b_set_cilp_preempt_pending(g, fault_ch); if (ret) { - gk20a_err(dev_from_gk20a(g), "CILP: error while setting CILP preempt pending!\n"); + nvgpu_err(g, "CILP: error while setting CILP preempt pending!"); return ret; } @@ -1562,7 +1550,7 @@ static int gr_gv11b_handle_fecs_error(struct gk20a *g, /* set preempt_pending to false */ ret = gr_gv11b_clear_cilp_preempt_pending(g, ch); if (ret) { - gk20a_err(dev_from_gk20a(g), "CILP: error while unsetting CILP preempt pending!\n"); + nvgpu_err(g, "CILP: error while unsetting CILP preempt pending!"); gk20a_channel_put(ch); goto clean_up; } @@ -2002,8 +1990,7 @@ void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) therm_gate_ctrl_eng_clk_auto_f()); break; default: - gk20a_err(dev_from_gk20a(g), - "invalid elcg mode %d", mode); + nvgpu_err(g, "invalid elcg mode %d", mode); } gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 8b322296..4d68926f 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -16,12 +16,13 @@ * this program. */ -#include - #include "gk20a/gk20a.h" #include "gv11b/subctx_gv11b.h" +#include +#include + #include #include @@ -58,8 +59,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) gr->ctx_vars.golden_image_size, &ctx->mem); if (ret) { - gk20a_err(dev_from_gk20a(g), - "failed to allocate sub ctx header"); + nvgpu_err(g, "failed to allocate sub ctx header"); return ret; } ctx->mem.gpu_va = gk20a_gmmu_map(c->vm, @@ -69,8 +69,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) gk20a_mem_flag_none, true, ctx->mem.aperture); if (!ctx->mem.gpu_va) { - gk20a_err(dev_from_gk20a(g), - "failed to map ctx header"); + nvgpu_err(g, "failed to map ctx header"); nvgpu_dma_free(g, &ctx->mem); return -ENOMEM; } -- cgit v1.2.2 From fbce374aa0f6101d27ca5b3de97905d2798c6f04 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Thu, 6 Apr 2017 12:08:08 +0530 Subject: gpu: nvgpu: Enable PMU support for T19X. JIRA GPUT19X-30 Change-Id: Ib9cb19eb1850c70f3e6db60660184569f5165263 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1253565 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 29ef7f6c..4cc45197 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -31,7 +31,7 @@ static bool gv11b_is_pmu_supported(struct gk20a *g) { - return false; + return true; } static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu) -- cgit v1.2.2 From 457f176785af5c8821889d00d89db05bbaf8f772 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 8 Mar 2017 22:34:49 -0800 Subject: gpu: nvgpu: gv11b: init handle sched_error & ctxsw_timout ops - detect and decode sched_error type. Any sched error starting with xxx_* is not supported in h/w and should never be seen by s/w - for bad_tsg sched error, preempt all runlists to recover as faulted ch/tsg is unknown. For other errors, just report error. - ctxsw timeout is not part of sched error fifo interrupt. A new fifo interrupt, ctxsw timeout is added in gv11b. Add s/w handling. Bug 1856152 JIRA GPUT19X-74 Change-Id: I474e1a3cda29a450691fe2ea1dc1e239ce57df1a Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1317615 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 237 ++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 14 ++ .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 104 +++++++++ 3 files changed, 352 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 3c1982fe..6883d867 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -15,13 +15,15 @@ #include #include -#include "nvgpu/semaphore.h" +#include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" #include "gk20a/ctxsw_trace_gk20a.h" +#include "gk20a/channel_gk20a.h" #include "gp10b/fifo_gp10b.h" @@ -862,7 +864,7 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, gk20a_dbg_info("hw id =%d", id); gk20a_dbg_info("id_type =%d", id_type); gk20a_dbg_info("rc_type =%d", rc_type); - gk20a_dbg_info("mmu_fault =%p", mmfault); + gk20a_dbg_info("mmu_fault =0x%p", mmfault); runlists_mask = gv11b_fifo_get_runlists_mask(g, act_eng_bitmask, id, id_type, rc_type, mmfault); @@ -1060,7 +1062,8 @@ static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g) intr_0_en_mask = g->ops.fifo.intr_0_error_mask(g); intr_0_en_mask |= fifo_intr_0_runlist_event_pending_f() | - fifo_intr_0_pbdma_intr_pending_f(); + fifo_intr_0_pbdma_intr_pending_f() | + fifo_intr_0_ctxsw_timeout_pending_f(); return intr_0_en_mask; } @@ -1072,6 +1075,7 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) u32 timeout; unsigned int i; u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); + struct gk20a_platform *platform = dev_get_drvdata(g->dev); gk20a_dbg_fn(""); @@ -1123,6 +1127,16 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall); } + /* clear ctxsw timeout interrupts */ + gk20a_writel(g, fifo_intr_ctxsw_timeout_r(), ~0); + + /* enable ctxsw timeout */ + timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; + timeout = scale_ptimer(timeout, + ptimer_scalingfactor10x(platform->ptimer_src_freq)); + timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); + gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); + /* clear runlist interrupts */ gk20a_writel(g, fifo_intr_runlist_r(), ~0); @@ -1139,6 +1153,221 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) return 0; } +static const char *const gv11b_sched_error_str[] = { + "xxx-0", + "xxx-1", + "xxx-2", + "xxx-3", + "xxx-4", + "engine_reset", + "rl_ack_timeout", + "rl_ack_extra", + "rl_rdat_timeout", + "rl_rdat_extra", + "xxx-a", + "xxx-b", + "rl_req_timeout", + "new_runlist", + "code_config_while_busy", + "xxx-f", + "xxx-0x10", + "xxx-0x11", + "xxx-0x12", + "xxx-0x13", + "xxx-0x14", + "xxx-0x15", + "xxx-0x16", + "xxx-0x17", + "xxx-0x18", + "xxx-0x19", + "xxx-0x1a", + "xxx-0x1b", + "xxx-0x1c", + "xxx-0x1d", + "xxx-0x1e", + "xxx-0x1f", + "bad_tsg", +}; + +static bool gv11b_fifo_handle_sched_error(struct gk20a *g) +{ + u32 sched_error; + + sched_error = gk20a_readl(g, fifo_intr_sched_error_r()); + + if (sched_error < ARRAY_SIZE(gv11b_sched_error_str)) + nvgpu_err(g, "fifo sched error :%s", + gv11b_sched_error_str[sched_error]); + else + nvgpu_err(g, "fifo sched error code not supported"); + + if (sched_error == SCHED_ERROR_CODE_BAD_TSG ) { + /* id is unknown, preempt all runlists and do recovery */ + gk20a_fifo_recover(g, 0, 0, false, false, false); + } + + return false; +} + +static u32 gv11b_fifo_ctxsw_timeout_info(struct gk20a *g, u32 active_eng_id) +{ + u32 tsgid = FIFO_INVAL_TSG_ID; + u32 timeout_info; + u32 ctx_status, info_status; + + timeout_info = gk20a_readl(g, + fifo_intr_ctxsw_timeout_info_r(active_eng_id)); + + /* + * ctxsw_state and tsgid are snapped at the point of the timeout and + * will not change while the corresponding INTR_CTXSW_TIMEOUT_ENGINE bit + * is PENDING. + */ + ctx_status = fifo_intr_ctxsw_timeout_info_ctxsw_state_v(timeout_info); + if (ctx_status == + fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v()) { + + tsgid = fifo_intr_ctxsw_timeout_info_next_tsgid_v(timeout_info); + + } else if (ctx_status == + fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v() || + ctx_status == + fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v()) { + + tsgid = fifo_intr_ctxsw_timeout_info_prev_tsgid_v(timeout_info); + } + gk20a_dbg_info("ctxsw timeout info: tsgid = %d", tsgid); + + /* + * STATUS indicates whether the context request ack was eventually + * received and whether a subsequent request timed out. This field is + * updated live while the corresponding INTR_CTXSW_TIMEOUT_ENGINE bit + * is PENDING. STATUS starts in AWAITING_ACK, and progresses to + * ACK_RECEIVED and finally ends with DROPPED_TIMEOUT. + * + * AWAITING_ACK - context request ack still not returned from engine. + * ENG_WAS_RESET - The engine was reset via a PRI write to NV_PMC_ENABLE + * or NV_PMC_ELPG_ENABLE prior to receiving the ack. Host will not + * expect ctx ack to return, but if it is already in flight, STATUS will + * transition shortly to ACK_RECEIVED unless the interrupt is cleared + * first. Once the engine is reset, additional context switches can + * occur; if one times out, STATUS will transition to DROPPED_TIMEOUT + * if the interrupt isn't cleared first. + * ACK_RECEIVED - The ack for the timed-out context request was + * received between the point of the timeout and this register being + * read. Note this STATUS can be reported during the load stage of the + * same context switch that timed out if the timeout occurred during the + * save half of a context switch. Additional context requests may have + * completed or may be outstanding, but no further context timeout has + * occurred. This simplifies checking for spurious context switch + * timeouts. + * DROPPED_TIMEOUT - The originally timed-out context request acked, + * but a subsequent context request then timed out. + * Information about the subsequent timeout is not stored; in fact, that + * context request may also have already been acked by the time SW + * SW reads this register. If not, there is a chance SW can get the + * dropped information by clearing the corresponding + * INTR_CTXSW_TIMEOUT_ENGINE bit and waiting for the timeout to occur + * again. Note, however, that if the engine does time out again, + * it may not be from the original request that caused the + * DROPPED_TIMEOUT state, as that request may + * be acked in the interim. + */ + info_status = fifo_intr_ctxsw_timeout_info_status_v(timeout_info); + if (info_status == + fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v()) { + + gk20a_dbg_info("ctxsw timeout info : awaiting ack"); + + } else if (info_status == + fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v()) { + + gk20a_dbg_info("ctxsw timeout info : eng was reset"); + + } else if (info_status == + fifo_intr_ctxsw_timeout_info_status_ack_received_v()) { + + gk20a_dbg_info("ctxsw timeout info : ack received"); + /* no need to recover */ + tsgid = FIFO_INVAL_TSG_ID; + + } else if (info_status == + fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v()) { + + gk20a_dbg_info("ctxsw timeout info : dropped timeout"); + /* no need to recover */ + tsgid = FIFO_INVAL_TSG_ID; + + } else { + gk20a_dbg_info("ctxsw timeout info status = %u", info_status); + } + + return tsgid; +} + +static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) +{ + bool ret = false; + u32 tsgid = FIFO_INVAL_TSG_ID; + u32 engine_id, active_eng_id; + u32 timeout_val, ctxsw_timeout_engines; + + + if (!(fifo_intr & fifo_intr_0_ctxsw_timeout_pending_f())) + return ret; + + /* get ctxsw timedout engines */ + ctxsw_timeout_engines = gk20a_readl(g, fifo_intr_ctxsw_timeout_r()); + if (ctxsw_timeout_engines == 0) { + nvgpu_err(g, "no eng ctxsw timeout pending"); + return ret; + } + + timeout_val = gk20a_readl(g, fifo_eng_ctxsw_timeout_r()); + timeout_val = fifo_eng_ctxsw_timeout_period_v(timeout_val); + + gk20a_dbg_info("eng ctxsw timeout period = 0x%x", timeout_val); + + for (engine_id = 0; engine_id < g->fifo.num_engines; engine_id++) { + active_eng_id = g->fifo.active_engines_list[engine_id]; + + if (ctxsw_timeout_engines & + fifo_intr_ctxsw_timeout_engine_pending_f( + active_eng_id)) { + + struct fifo_gk20a *f = &g->fifo; + u32 ms = 0; + bool verbose = false; + + tsgid = gv11b_fifo_ctxsw_timeout_info(g, active_eng_id); + + if (tsgid == FIFO_INVAL_TSG_ID) + continue; + + if (gk20a_fifo_check_tsg_ctxsw_timeout( + &f->tsg[tsgid], &verbose, &ms)) { + ret = true; + nvgpu_err(g, + "ctxsw timeout error:" + "active engine id =%u, %s=%d, ms=%u", + active_eng_id, "tsg", tsgid, ms); + + /* Cancel all channels' timeout */ + gk20a_channel_timeout_restart_all_channels(g); + gk20a_fifo_recover(g, BIT(active_eng_id), tsgid, + true, true, verbose); + } else { + gk20a_dbg_info( + "fifo is waiting for ctx switch: " + "for %d ms, %s=%d", ms, "tsg", tsgid); + } + } + } + /* clear interrupt */ + gk20a_writel(g, fifo_intr_ctxsw_timeout_r(), ctxsw_timeout_engines); + return ret; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -1169,4 +1398,6 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw; gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg; + gops->fifo.handle_sched_error = gv11b_fifo_handle_sched_error; + gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; } diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 07a39da0..ab56b876 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -18,6 +18,20 @@ #define FIFO_INVAL_PBDMA_ID ((u32)~0) +/* engine context-switch request occurred while the engine was in reset */ +#define SCHED_ERROR_CODE_ENGINE_RESET 0x00000005 + +/* +* ERROR_CODE_BAD_TSG indicates that Host encountered a badly formed TSG header +* or a badly formed channel type runlist entry in the runlist. This is typically +* caused by encountering a new TSG entry in the middle of a TSG definition. +* A channel type entry having wrong runqueue selector can also cause this. +* Additionally this error code can indicate when a channel is encountered on +* the runlist which is outside of a TSG. +*/ +#define SCHED_ERROR_CODE_BAD_TSG 0x00000020 + + struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index f05df49e..dbcb02c8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -230,6 +230,10 @@ static inline u32 fifo_intr_0_channel_intr_pending_f(void) { return 0x80000000; } +static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) +{ + return 0x2; +} static inline u32 fifo_intr_en_0_r(void) { return 0x00002140; @@ -242,6 +246,10 @@ static inline u32 fifo_intr_en_0_sched_error_m(void) { return 0x1 << 8; } +static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void) +{ + return 0x2; +} static inline u32 fifo_intr_en_1_r(void) { return 0x00002528; @@ -266,6 +274,82 @@ static inline u32 fifo_intr_chsw_error_r(void) { return 0x0000256c; } +static inline u32 fifo_intr_ctxsw_timeout_r(void) +{ + return 0x00002a30; +} +static inline u32 fifo_intr_ctxsw_timeout_engine_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_intr_ctxsw_timeout_engine_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fifo_intr_ctxsw_timeout_engine__size_1_v(void) +{ + return 0x00000020; +} +static inline u32 fifo_intr_ctxsw_timeout_engine_pending_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_ctxsw_timeout_engine_pending_f(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_intr_ctxsw_timeout_info_r(u32 i) +{ + return 0x00003200 + i*4; +} +static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v(void) +{ + return 0x00000002; +} +static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) +{ + return (r >> 4) & 0xfff; +} +static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_ctxsw_timeout_info_status_ack_received_v(void) +{ + return 0x00000002; +} +static inline u32 fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v(void) +{ + return 0x00000003; +} static inline u32 fifo_intr_pbdma_id_r(void) { return 0x000025a0; @@ -450,6 +534,26 @@ static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) { return 0x8000; } +static inline u32 fifo_eng_ctxsw_timeout_r(void) +{ + return 0x00002a0c; +} +static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) +{ + return (v & 0x7fffffff) << 0; +} +static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) +{ + return (r >> 0) & 0x7fffffff; +} +static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) +{ + return 0x80000000; +} static inline u32 fifo_pbdma_status_r(u32 i) { return 0x00003080 + i*4; -- cgit v1.2.2 From 60d0ba2d37b4f2b67ecf0be4d6566af5a289ccb9 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 7 Apr 2017 12:39:10 -0700 Subject: gpu: nvgpu: gv11b: fix *get_runlists_mask* if ch/tsg id is unknown and bit mask for the engines that need to be recovered is not set, runlist mask should correspond to max number of supported runlists JIRA GPUT19X-7 Change-Id: I08e67af0846784a7918510d68de34e9162a42bf6 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1458155 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 45 +++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 6883d867..d3411d32 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -543,35 +543,42 @@ u32 gv11b_fifo_get_runlists_mask(struct gk20a *g, u32 act_eng_bitmask, if (id_type != ID_TYPE_UNKNOWN) { if (id_type == ID_TYPE_TSG) - runlists_mask = fifo_sched_disable_runlist_m( + runlists_mask |= fifo_sched_disable_runlist_m( f->tsg[id].runlist_id); else - runlists_mask = fifo_sched_disable_runlist_m( + runlists_mask |= fifo_sched_disable_runlist_m( f->channel[id].runlist_id); - } else { - if (rc_type == RC_TYPE_MMU_FAULT && mmfault) { - if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) - pbdma_bitmask = BIT(mmfault->faulted_pbdma); + } - for (id = 0; id < f->max_runlists; id++) { + if (rc_type == RC_TYPE_MMU_FAULT && mmfault) { + if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) + pbdma_bitmask = BIT(mmfault->faulted_pbdma); - runlist = &f->runlist_info[id]; + for (id = 0; id < f->max_runlists; id++) { - if (runlist->eng_bitmask & act_eng_bitmask) - runlists_mask |= - fifo_sched_disable_runlist_m(id); + runlist = &f->runlist_info[id]; - if (runlist->pbdma_bitmask & pbdma_bitmask) - runlists_mask |= - fifo_sched_disable_runlist_m(id); - } - } else { - /* ID is unknown */ - for (id = 0; id < f->max_runlists; id++) { + if (runlist->eng_bitmask & act_eng_bitmask) + runlists_mask |= + fifo_sched_disable_runlist_m(id); + + if (runlist->pbdma_bitmask & pbdma_bitmask) + runlists_mask |= + fifo_sched_disable_runlist_m(id); + } + } + + if (id_type == ID_TYPE_UNKNOWN) { + for (id = 0; id < f->max_runlists; id++) { + if (act_eng_bitmask) { + /* eng ids are known */ runlist = &f->runlist_info[id]; if (runlist->eng_bitmask & act_eng_bitmask) runlists_mask |= - fifo_sched_disable_runlist_m(id); + fifo_sched_disable_runlist_m(id); + } else { + runlists_mask |= + fifo_sched_disable_runlist_m(id); } } } -- cgit v1.2.2 From 1b4849cda595b5b4e55fdb51e7ecd6c09e1a5fa4 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 16 Feb 2017 16:55:08 -0800 Subject: gpu: nvgpu: gv11b: init pbdma_intr_0 handler Add handling for below two interrupts on top of legacy ones. When pending, PBDMA is stalled and s/w is expected to execute teardown. clear_faulted_error: host is asked to clear fault status when no fault has been asserted. eng_reset: An engine was reset while the PBDMA unit was processing a channel from a runlist which serves the engine. JIRA GPUT19X-47 Change-Id: I776e5799a73a1b63c394048fa61b597e621cf544 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1306558 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index d3411d32..e4dd6a63 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1375,6 +1375,33 @@ static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) return ret; } +static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_0, + u32 *handled, u32 *error_notifier) +{ + unsigned int rc_type = RC_TYPE_NO_RC; + + rc_type = gk20a_fifo_handle_pbdma_intr_0(g, pbdma_id, + pbdma_intr_0, handled, error_notifier); + + if (pbdma_intr_0 & pbdma_intr_0_clear_faulted_error_pending_f()) { + gk20a_dbg(gpu_dbg_intr, "clear faulted error on pbdma id %d", + pbdma_id); + gk20a_fifo_reset_pbdma_method(g, pbdma_id, 0); + *handled |= pbdma_intr_0_clear_faulted_error_pending_f(); + rc_type = RC_TYPE_PBDMA_FAULT; + } + + if (pbdma_intr_0 & pbdma_intr_0_eng_reset_pending_f()) { + gk20a_dbg(gpu_dbg_intr, "eng reset intr on pbdma id %d", + pbdma_id); + *handled |= pbdma_intr_0_eng_reset_pending_f(); + rc_type = RC_TYPE_PBDMA_FAULT; + } + + return rc_type; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -1407,4 +1434,6 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg; gops->fifo.handle_sched_error = gv11b_fifo_handle_sched_error; gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; + gops->fifo.handle_pbdma_intr_0 = + gv11b_fifo_handle_pbdma_intr_0; } -- cgit v1.2.2 From 7b5b4fc84ff0067fb0e7b5a3b86a4b16784e8ffa Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 9 Mar 2017 11:30:14 -0800 Subject: gpu: nvgpu: gv11b: function to get max veid Defined function to get max number of subcontexs supported and used it where max subcontext count required. JIRA GV11B-23 Change-Id: I4f6307162486bab1e91cbf66abfee7763c70fe7b Signed-off-by: seshendra Gadagottu Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1318146 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 3 +-- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 8 ++++++++ drivers/gpu/nvgpu/gv11b/subctx_gv11b.h | 4 +++- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 5b0526b0..33a5067e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1649,10 +1649,9 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) struct av_list_gk20a *sw_veid_bundle_init = &g->gr.ctx_vars.sw_veid_bundle_init; u32 j; - u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r()); u32 num_subctx, err = 0; - num_subctx = gr_pri_fe_chip_def_info_max_veid_count_v(data); + num_subctx = gv11b_get_max_subctx_count(g); for (j = 0; j < num_subctx; j++) { diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 4d68926f..c3ff9185 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -25,6 +25,7 @@ #include #include +#include static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block); @@ -147,3 +148,10 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) nvgpu_mem_end(g, gr_mem); return ret; } + +int gv11b_get_max_subctx_count(struct gk20a *g) +{ + u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r()); + + return gr_pri_fe_chip_def_info_max_veid_count_v(data); +} diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h index 357cd254..fdfe9e3b 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h @@ -2,7 +2,7 @@ * * Volta GPU series Subcontext * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016 - 2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,4 +24,6 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c); void gv11b_free_subctx_header(struct channel_gk20a *c); int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va); + +int gv11b_get_max_subctx_count(struct gk20a *g); #endif /* __SUBCONTEXT_GV11B_H__ */ -- cgit v1.2.2 From 6dabea9882ee965041cf42c95e8b2bcff95fbfa0 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 10 Apr 2017 11:09:13 -0700 Subject: gpu: nvgpu: gv11b: Use new error macros gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert the last remaining user of old macros to new ones. JIRA NVGPU-16 Change-Id: Ib665cfb395fe46ac988ed14d67adef885098e524 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1462968 Reviewed-by: Alex Waterman Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index daad8718..415266af 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -81,8 +81,7 @@ u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) == 2) return base * 2; else if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) != 1) { - gk20a_err(dev_from_gk20a(g), - "Invalid number of active ltcs: %08x\n", val); + nvgpu_err(g, "Invalid number of active ltcs: %08x\n", val); } return base; } -- cgit v1.2.2 From 1d4b22ed88d2764b4708d27cbabcfbbdf9d04ba2 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 17 Apr 2017 10:50:54 -0700 Subject: gpu: nvgpu: gv11b: set soc credits after fs_hub is out of reset Without these credits, gpu mmu binds over nvlink to soc are hanging. Also add l2_enabled for mc_elpg_enable. Bug 1899460 Change-Id: I0b26410d5c8ec9b4c88b319ddd9442f2fd91b321 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1463204 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 57 ++++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 20 ++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 6 ++- 3 files changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 61b23711..98aad4e0 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -24,6 +24,61 @@ #include #include +#include +#include + +static void gv11b_init_nvlink_soc_credits(struct gk20a *g) +{ + void __iomem *soc1 = ioremap(0x02b10010, 4096); + void __iomem *soc2 = ioremap(0x02b20010, 4096); + void __iomem *soc3 = ioremap(0x02b30010, 4096); + void __iomem *soc4 = ioremap(0x02b40010, 4096); + + gk20a_dbg_info("init nvlink soc credits"); + + writel_relaxed(0x14050000, soc1); + writel_relaxed(0x08020000, soc1 + 4); + writel_relaxed(0x14050000, soc2); + writel_relaxed(0x08020000, soc2 + 4); + writel_relaxed(0x14050000, soc3); + writel_relaxed(0x08020000, soc3 + 4); + writel_relaxed(0x14050000, soc4); + writel_relaxed(0x08020000, soc4 + 4); + +} + +static void gv11b_fb_reset(struct gk20a *g) +{ + u32 val; + + gk20a_dbg_info("reset gv11b fb"); + + g->ops.mc.reset(g, mc_enable_pfb_enabled_f() | + mc_enable_l2_enabled_f() | + mc_enable_xbar_enabled_f() | + mc_enable_hub_enabled_f()); + + val = gk20a_readl(g, mc_elpg_enable_r()); + val |= mc_elpg_enable_xbar_enabled_f() | + mc_elpg_enable_pfb_enabled_f() | + mc_elpg_enable_l2_enabled_f() | + mc_elpg_enable_hub_enabled_f(); + gk20a_writel(g, mc_elpg_enable_r(), val); + + /* fs hub should be out of reset by now */ + gv11b_init_nvlink_soc_credits(g); + + val = gk20a_readl(g, fifo_fb_iface_r()); + gk20a_dbg_info("fifo_fb_iface val = 0x%x", val); + if (!(val & fifo_fb_iface_control_enable_f() && + val & fifo_fb_iface_status_enabled_f())) { + gk20a_dbg_info("fifo_fb_iface set control enable"); + gk20a_writel(g, fifo_fb_iface_r(), + fifo_fb_iface_control_enable_f()); + val = gk20a_readl(g, fifo_fb_iface_r()); + gk20a_dbg_info("fifo_fb_iface val = 0x%x", val); + } +} static void gv11b_init_uncompressed_kind_map(void) { @@ -94,6 +149,8 @@ void gv11b_init_fb(struct gpu_ops *gops) { gp10b_init_fb(gops); gops->fb.hub_isr = gv11b_fb_hub_isr; + gops->fb.reset = gv11b_fb_reset; + gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index dbcb02c8..bd2f628c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -630,4 +630,24 @@ static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) { return (r >> 16) & 0xff; } +static inline u32 fifo_fb_iface_r(void) +{ + return 0x000026f0; +} +static inline u32 fifo_fb_iface_control_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fifo_fb_iface_control_enable_f(void) +{ + return 0x1; +} +static inline u32 fifo_fb_iface_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 fifo_fb_iface_status_enabled_f(void) +{ + return 0x10; +} #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index 98bec43a..f05910a9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -242,4 +242,8 @@ static inline u32 mc_elpg_enable_hub_enabled_f(void) { return 0x20000000; } +static inline u32 mc_elpg_enable_l2_enabled_f(void) +{ + return 0x8; +} #endif -- cgit v1.2.2 From 1c1b01d067c62e2f3bd102503131c8070291a5fc Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 18 Apr 2017 14:24:25 -0700 Subject: gpu: nvgpu: gv11b: init css ops Bug 1870532 Change-Id: Ib8d61e92ad825b9ae5345f62ed2df343b50231b0 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1464994 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 32fd52d6..220d646b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -20,6 +20,7 @@ #include #include "gk20a/gk20a.h" +#include "gk20a/css_gr_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" @@ -203,6 +204,9 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); +#if defined(CONFIG_GK20A_CYCLE_STATS) + gk20a_init_css_ops(gops); +#endif g->name = "gv11b"; gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; gops->get_litter_value = gv11b_get_litter_value; -- cgit v1.2.2 From 90d029fd28c25904bb84f929f1a65075a8d9b6e4 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 18 Apr 2017 16:08:54 -0700 Subject: gpu: nvgpu: gv11b: enable big pages Do not depend on bypass_smmu to set disable_bigpage Bug 1805409 Change-Id: Ie602e3567162896acbc6a2da5f7f2db5cfb8021f Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1465071 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index b8479b89..892fa442 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -36,7 +36,7 @@ static int gv11b_tegra_probe(struct device *dev) struct gk20a_platform *platform = dev_get_drvdata(dev); platform->bypass_smmu = !device_is_iommuable(dev); - platform->disable_bigpage = platform->bypass_smmu; + platform->disable_bigpage = false; platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close = false; -- cgit v1.2.2 From 7872900486bd31cf186930848adec46d0a13b68a Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 17 Apr 2017 21:20:19 +0100 Subject: gpu: nvgpu: Move Linux nvgpu_mem fields t19x part for this change in nvgpu. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I31116b4241076b39a6638273281630a1527bcd35 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1464109 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Konsta Holtta GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 33a5067e..190e3df5 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -652,7 +652,7 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, return err; mem->gpu_va = gk20a_gmmu_map(vm, - &mem->sgt, + &mem->priv.sgt, size, NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none, diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index c3ff9185..dcf69adf 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -64,7 +64,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) return ret; } ctx->mem.gpu_va = gk20a_gmmu_map(c->vm, - &ctx->mem.sgt, + &ctx->mem.priv.sgt, ctx->mem.size, NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none, true, @@ -99,7 +99,7 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, gk20a_dbg_fn(""); /* load main pdb as veid0 pdb also */ vm = c->vm; - pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.sgt->sgl, 0); + pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.priv.sgt->sgl, 0); pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); pdb_addr_hi = u64_hi32(pdb_addr); format_word = ram_in_sc_page_dir_base_target_f( -- cgit v1.2.2 From e1c27d4e84d518bef88305d1ca848deb07433677 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 14 Apr 2017 16:15:50 -0700 Subject: gpu: nvgpu: gv11b: Use new clk HAL Use the new clk HAL to request clock rate instead of direct calls to Clock Framework. This cuts one direct dependency to Linux APIs. Also change the HAL to not clear clk ops after they've been initialized. JIRA NVGPU-16 Change-Id: I1ab3eac8268f1f3f3305d49782c6a0eb57c6d617 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1463536 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 2 ++ drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 3 +-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 220d646b..7e2c35dc 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -182,7 +182,7 @@ int gv11b_init_hal(struct gk20a *g) struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; - *gops = gv11b_ops; + gops->clock_gating = gv11b_ops.clock_gating; /* boot in non-secure modes for time beeing */ gops->privsecurity = 0; diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 892fa442..a2a6cfd3 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -24,6 +24,7 @@ #include "gk20a/platform_gk20a.h" #include "gk20a/gk20a.h" +#include "tegra/linux/clk.h" #include "gp10b/platform_gp10b.h" @@ -50,6 +51,7 @@ static int gv11b_tegra_probe(struct device *dev) platform->g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem; gp10b_tegra_get_clocks(dev); + nvgpu_linux_init_clk_support(platform->g); return 0; } diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 4cc45197..4784ee4a 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -37,7 +37,6 @@ static bool gv11b_is_pmu_supported(struct gk20a *g) static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); - struct gk20a_platform *platform = dev_get_drvdata(g->dev); struct mm_gk20a *mm = &g->mm; struct pmu_ucode_desc *desc = pmu->desc; u64 addr_code_lo, addr_data_lo, addr_load_lo; @@ -64,7 +63,7 @@ static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu) pmu, GK20A_PMU_DMAIDX_VIRT); g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, - clk_get_rate(platform->clk[1])); + g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); addr_args = (pwr_falcon_hwcfg_dmem_size_v( gk20a_readl(g, pwr_falcon_hwcfg_r())) -- cgit v1.2.2 From be6d308c18d991d4937e6ca467cd41918a3199e8 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 17 Apr 2017 22:01:23 +0100 Subject: gpu: nvgpu: Move semaphore impl to nvgpu_mem t19x version of similarly named patch in nvgpu. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I5b0ce285a25a456d019670fc25b25ed564444643 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1464110 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index e4dd6a63..8346de59 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -280,7 +280,7 @@ static void gv11b_dump_channel_status_ramfc(struct gk20a *g, if (hw_sema) gk20a_debug_output(o, "SEMA STATE: value: 0x%08x " "next_val: 0x%08x addr: 0x%010llx\n", - readl(hw_sema->value), + __nvgpu_semaphore_read(hw_sema), atomic_read(&hw_sema->next_value), nvgpu_hw_sema_addr(hw_sema)); gk20a_debug_output(o, "\n"); -- cgit v1.2.2 From 7fdf02f554a5e922d0cc6797854c5fcfd78bf55f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 14 Apr 2017 16:10:59 -0700 Subject: gpu: nvgpu: gv11b: Access ptimer_src_freq from gk20a Access ptimer_src_freq from gk20a instead of gk20a_platform. JIRA NVGPU-16 Change-Id: I3f2fcd22eb8a14c83ee2d481ff9f5acdf00f9c07 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1463534 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 8346de59..f16fbb98 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1082,7 +1082,6 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) u32 timeout; unsigned int i; u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); - struct gk20a_platform *platform = dev_get_drvdata(g->dev); gk20a_dbg_fn(""); @@ -1140,7 +1139,7 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) /* enable ctxsw timeout */ timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; timeout = scale_ptimer(timeout, - ptimer_scalingfactor10x(platform->ptimer_src_freq)); + ptimer_scalingfactor10x(g->ptimer_src_freq)); timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); -- cgit v1.2.2 From 92895a57a733cffe9f4318be9a5064c9e32350e1 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 27 Apr 2017 11:02:41 -0700 Subject: gpu: nvgpu: gv11b: fix error for static code analysis Functions that are not declared in header files are made static Bug 200299572 Change-Id: Ibf9e9cc9f48ad9ceaa202d1bb7ed57724057cda0 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1471538 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 8 ++++---- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index f16fbb98..421ccd15 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -532,7 +532,7 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) up_read(&tsg->ch_list_lock); } -u32 gv11b_fifo_get_runlists_mask(struct gk20a *g, u32 act_eng_bitmask, +static u32 gv11b_fifo_get_runlists_mask(struct gk20a *g, u32 act_eng_bitmask, u32 id, unsigned int id_type, unsigned int rc_type, struct mmu_fault_info *mmfault) { @@ -639,7 +639,7 @@ static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g, return ret; } -int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, +static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type) { struct fifo_gk20a *f = &g->fifo; @@ -856,7 +856,7 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, } -void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, +static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, u32 id, unsigned int id_type, unsigned int rc_type, struct mmu_fault_info *mmfault) { @@ -1075,7 +1075,7 @@ static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g) return intr_0_en_mask; } -int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) +static int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) { u32 intr_stall; u32 mask; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 190e3df5..7638baaf 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1963,7 +1963,7 @@ static void gr_gv11b_write_pm_ptr(struct gk20a *g, ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); } -void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) +static void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) { u32 gate_ctrl; diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 415266af..c1398f92 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -74,7 +74,7 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) ltc_intr); } -u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) +static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) { u32 val = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); -- cgit v1.2.2 From 10540e3915d9be82863d8472e31a2683a8f73097 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 14 Apr 2017 16:13:04 -0700 Subject: gpu: nvgpu: gv11b: Use new support_pmu flag Use new gk20a->support_pmu flag instead of using the old support_gk20a_pmu() macro. The latter depends on access to Linux device structure. JIRA NVGPU-16 Change-Id: I6b843305b15b29893a1e3b0d60f37c44bdb3b2cb Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1463535 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 421ccd15..df7ab5af 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -882,7 +882,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, g->fifo.deferred_reset_pending = false; /* Disable power management */ - if (support_gk20a_pmu(g->dev) && g->elpg_enabled) { + if (g->support_pmu && g->elpg_enabled) { if (gk20a_pmu_disable_elpg(g)) nvgpu_err(g, "failed to set disable elpg"); } @@ -1011,7 +1011,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, !RUNLIST_INFO_MUTEX_LOCKED); /* It is safe to enable ELPG again. */ - if (support_gk20a_pmu(g->dev) && g->elpg_enabled) + if (g->support_pmu && g->elpg_enabled) gk20a_pmu_enable_elpg(g); } -- cgit v1.2.2 From d805731c8e333f16e42517cae50648954b99c870 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 20 Apr 2017 12:47:45 -0700 Subject: gpu: nvgpu: gv11b: hw header update for CL38424879 Bug 200300756 Change-Id: I2991d306905d2681cfb3031301e1b45a215ff89b Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1466955 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 20 -------------------- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 4 ---- 2 files changed, 24 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index dc8473a5..22ad23bc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -386,26 +386,6 @@ static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) { return 0x0000005f; } -static inline u32 gmmu_pte_kind_z16_4cz_v(void) -{ - return 0x0000000c; -} -static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) -{ - return 0x0000000d; -} -static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) -{ - return 0x0000000e; -} -static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) -{ - return 0x0000000f; -} -static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) -{ - return 0x00000010; -} static inline u32 gmmu_pte_kind_s8z24_v(void) { return 0x00000011; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index f05910a9..38040723 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -142,10 +142,6 @@ static inline u32 mc_enable_pmedia_v(u32 r) { return (r >> 4) & 0x1; } -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20; -} static inline u32 mc_enable_ce0_m(void) { return 0x1 << 6; -- cgit v1.2.2 From 2266270e2a2dc34c20f25f5cf256662e9747c4ac Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 2 May 2017 21:18:34 +0530 Subject: gpu: nvgpu: init interface layer support for PMU falcon Change-Id: Iadd72196ed7df7384b1ecdc06ecd98828061fd3e Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1473685 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 7e2c35dc..de14f1dd 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -23,6 +23,7 @@ #include "gk20a/css_gr_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" +#include "gk20a/flcn_gk20a.h" #include "gm20b/gr_gm20b.h" @@ -198,6 +199,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); + gk20a_falcon_init_hal(gops); gv11b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); gk20a_init_dbg_session_ops(gops); -- cgit v1.2.2 From 2fc607eb3ba8151099ef7a851081a9355af92b6b Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 3 May 2017 16:01:46 -0700 Subject: gpu: nvgpu: gv11b: fix sparse warning Fixed following sparse warning by including relevant header: $TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c:82:23: warning: symbol 't19x_gpu_tegra_platform' was not declared. Should it be static? Bug 200299572 Change-Id: Ibf7b69da9b76e72d610571135bd412c865b69a5f Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1474940 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam Reviewed-by: Amit Sharma (SW-TEGRA) Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index a2a6cfd3..07e3d8cf 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -30,6 +30,7 @@ #include "platform_tegra.h" #include "gr_gv11b.h" +#include "nvgpu_gpuid_t19x.h" static int gv11b_tegra_probe(struct device *dev) -- cgit v1.2.2 From 0c1f5c457410adb0b0f417c0a77521409731986b Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 4 May 2017 09:27:23 -0700 Subject: Revert "gpu: nvgpu: gv11b: enable big pages" This reverts commit 90d029fd28c25904bb84f929f1a65075a8d9b6e4. Bug 200305653 Change-Id: I2baa4b286e14ce57e68ab1e9cc15630ee24f5bc9 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1475515 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 07e3d8cf..b9efc683 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -38,7 +38,7 @@ static int gv11b_tegra_probe(struct device *dev) struct gk20a_platform *platform = dev_get_drvdata(dev); platform->bypass_smmu = !device_is_iommuable(dev); - platform->disable_bigpage = false; + platform->disable_bigpage = platform->bypass_smmu; platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close = false; -- cgit v1.2.2 From 4b990224df5ab7bc2fc92a66ba8e5d9bba023ca8 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 24 Jan 2017 15:39:29 -0800 Subject: gpu: nvgpu: gv11b: changes related to preemeption Added function pointers to check chip specific valid gfx class and compute class. Also added function pointer to update ctx header with preemption buffer pointers. Also fall back to gp10b functions, where nothing is changed from gp10b to gv11b. Bug 200292090 Change-Id: I69900e32bbcce4576c4c0f7a7119c7dd8e984928 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1293503 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 502 +++++-------------------------------- 1 file changed, 60 insertions(+), 442 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 7638baaf..b8993052 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -73,6 +73,41 @@ static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) return valid; } +static bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) +{ + bool valid = false; + + switch (class_num) { + case VOLTA_A: + case PASCAL_A: + case MAXWELL_B: + valid = true; + break; + + default: + break; + } + return valid; +} + +static bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) +{ + bool valid = false; + + switch (class_num) { + case VOLTA_COMPUTE_A: + case PASCAL_COMPUTE_A: + case MAXWELL_COMPUTE_B: + valid = true; + break; + + default: + break; + } + return valid; +} + + static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event, struct channel_gk20a *fault_ch, u32 *hww_global_esr) @@ -113,122 +148,6 @@ static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, return 0; } -static int gr_gv11b_commit_global_cb_manager(struct gk20a *g, - struct channel_gk20a *c, bool patch) -{ - struct gr_gk20a *gr = &g->gr; - struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; - struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; - u32 attrib_offset_in_chunk = 0; - u32 alpha_offset_in_chunk = 0; - u32 pd_ab_max_output; - u32 gpc_index, ppc_index; - u32 temp, temp2; - u32 cbm_cfg_size_beta, cbm_cfg_size_alpha, cbm_cfg_size_steadystate; - u32 attrib_size_in_chunk, cb_attrib_cache_size_init; - - gk20a_dbg_fn(""); - - if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) { - attrib_size_in_chunk = gr->attrib_cb_default_size + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - cb_attrib_cache_size_init = gr->attrib_cb_default_size + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - } else { - attrib_size_in_chunk = gr->attrib_cb_size; - cb_attrib_cache_size_init = gr->attrib_cb_default_size; - } - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(), - gr->attrib_cb_default_size, patch); - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_alpha_r(), - gr->alpha_cb_default_size, patch); - - pd_ab_max_output = (gr->alpha_cb_default_size * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()) / - gr_pd_ab_dist_cfg1_max_output_granularity_v(); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg1_r(), - gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | - gr_pd_ab_dist_cfg1_max_batches_init_f(), patch); - - attrib_offset_in_chunk = alpha_offset_in_chunk + - gr->tpc_count * gr->alpha_cb_size; - - for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { - temp = proj_gpc_stride_v() * gpc_index; - temp2 = proj_scal_litter_num_pes_per_gpc_v() * gpc_index; - for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; - ppc_index++) { - cbm_cfg_size_beta = cb_attrib_cache_size_init * - gr->pes_tpc_count[ppc_index][gpc_index]; - cbm_cfg_size_alpha = gr->alpha_cb_default_size * - gr->pes_tpc_count[ppc_index][gpc_index]; - cbm_cfg_size_steadystate = gr->attrib_cb_default_size * - gr->pes_tpc_count[ppc_index][gpc_index]; - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - cbm_cfg_size_beta, patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - attrib_offset_in_chunk, patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - cbm_cfg_size_steadystate, - patch); - - attrib_offset_in_chunk += attrib_size_in_chunk * - gr->pes_tpc_count[ppc_index][gpc_index]; - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - cbm_cfg_size_alpha, patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - alpha_offset_in_chunk, patch); - - alpha_offset_in_chunk += gr->alpha_cb_size * - gr->pes_tpc_count[ppc_index][gpc_index]; - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + temp2), - gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size_steadystate), - patch); - } - } - - return 0; -} - -static void gr_gv11b_commit_global_pagepool(struct gk20a *g, - struct channel_ctx_gk20a *ch_ctx, - u64 addr, u32 size, bool patch) -{ - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_base_r(), - gr_scc_pagepool_base_addr_39_8_f(addr), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_r(), - gr_scc_pagepool_total_pages_f(size) | - gr_scc_pagepool_valid_true_f(), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_base_r(), - gr_gpcs_gcc_pagepool_base_addr_39_8_f(addr), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_r(), - gr_gpcs_gcc_pagepool_total_pages_f(size), patch); -} - static int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, struct zbc_query_params *query_params) { @@ -604,42 +523,6 @@ static void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data) } } -static int gr_gv11b_init_ctx_state(struct gk20a *g) -{ - struct fecs_method_op_gk20a op = { - .mailbox = { .id = 0, .data = 0, - .clr = ~0, .ok = 0, .fail = 0}, - .method.data = 0, - .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL, - .cond.fail = GR_IS_UCODE_OP_SKIP, - }; - int err; - - gk20a_dbg_fn(""); - - err = gr_gk20a_init_ctx_state(g); - if (err) - return err; - - if (!g->gr.t18x.ctx_vars.preempt_image_size) { - op.method.addr = - gr_fecs_method_push_adr_discover_preemption_image_size_v(); - op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size; - err = gr_gk20a_submit_fecs_method_op(g, op, false); - if (err) { - nvgpu_err(g, "query preempt image size failed"); - return err; - } - } - - gk20a_dbg_info("preempt image size: %u", - g->gr.t18x.ctx_vars.preempt_image_size); - - gk20a_dbg_fn("done"); - - return 0; -} - int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct nvgpu_mem *mem) { @@ -671,253 +554,6 @@ fail_free: return err; } -static int gr_gv11b_alloc_gr_ctx(struct gk20a *g, - struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm, - u32 class, - u32 flags) -{ - int err; - - gk20a_dbg_fn(""); - - err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags); - if (err) - return err; - - (*gr_ctx)->t18x.ctx_id_valid = false; - - if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) - flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; - - if (class == PASCAL_COMPUTE_A && - g->gr.t18x.ctx_vars.force_preemption_cilp) - flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP; - - if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { - u32 spill_size = - gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * - gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); - u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * - gr_scc_pagepool_total_pages_byte_granularity_v(); - u32 betacb_size = g->gr.attrib_cb_default_size + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * - g->gr.max_tpc_count; - attrib_cb_size = ALIGN(attrib_cb_size, 128); - - gk20a_dbg_info("gfxp context spill_size=%d", spill_size); - gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size); - gk20a_dbg_info("gfxp context attrib_cb_size=%d", - attrib_cb_size); - err = gr_gv11b_alloc_buffer(vm, - g->gr.t18x.ctx_vars.preempt_image_size, - &(*gr_ctx)->t18x.preempt_ctxsw_buffer); - if (err) { - nvgpu_err(vm->mm->g, "cannot allocate preempt buffer"); - goto fail_free_gk20a_ctx; - } - - err = gr_gv11b_alloc_buffer(vm, - spill_size, - &(*gr_ctx)->t18x.spill_ctxsw_buffer); - if (err) { - nvgpu_err(vm->mm->g, "cannot allocate spill buffer"); - goto fail_free_preempt; - } - - err = gr_gv11b_alloc_buffer(vm, - attrib_cb_size, - &(*gr_ctx)->t18x.betacb_ctxsw_buffer); - if (err) { - nvgpu_err(vm->mm->g, "cannot allocate beta buffer"); - goto fail_free_spill; - } - - err = gr_gv11b_alloc_buffer(vm, - pagepool_size, - &(*gr_ctx)->t18x.pagepool_ctxsw_buffer); - if (err) { - nvgpu_err(vm->mm->g, "cannot allocate page pool"); - goto fail_free_betacb; - } - - (*gr_ctx)->graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; - } - - if (class == PASCAL_COMPUTE_A) { - if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) - (*gr_ctx)->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP; - else - (*gr_ctx)->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CTA; - } - - gk20a_dbg_fn("done"); - - return err; - -fail_free_betacb: - nvgpu_dma_unmap_free(vm, &(*gr_ctx)->t18x.betacb_ctxsw_buffer); -fail_free_spill: - nvgpu_dma_unmap_free(vm, &(*gr_ctx)->t18x.spill_ctxsw_buffer); -fail_free_preempt: - nvgpu_dma_unmap_free(vm, &(*gr_ctx)->t18x.preempt_ctxsw_buffer); -fail_free_gk20a_ctx: - gr_gk20a_free_gr_ctx(g, vm, *gr_ctx); - *gr_ctx = NULL; - - return err; -} - -static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, - struct gr_ctx_desc *gr_ctx) -{ - struct nvgpu_mem *mem = &gr_ctx->mem; - - if (nvgpu_mem_begin(g, mem)) { - WARN_ON("Cannot map context"); - return; - } - nvgpu_err(g, "ctxsw_prog_main_image_magic_value_o : %x (expect %x)", - nvgpu_mem_rd(g, mem, - ctxsw_prog_main_image_magic_value_o()), - ctxsw_prog_main_image_magic_value_v_value_v()); - - - nvgpu_err(g, "NUM_SAVE_OPERATIONS : %d", - nvgpu_mem_rd(g, mem, - ctxsw_prog_main_image_num_save_ops_o())); - nvgpu_err(g, "WFI_SAVE_OPERATIONS : %d", - nvgpu_mem_rd(g, mem, - ctxsw_prog_main_image_num_wfi_save_ops_o())); - nvgpu_err(g, "CTA_SAVE_OPERATIONS : %d", - nvgpu_mem_rd(g, mem, - ctxsw_prog_main_image_num_cta_save_ops_o())); - nvgpu_err(g, "GFXP_SAVE_OPERATIONS : %d", - nvgpu_mem_rd(g, mem, - ctxsw_prog_main_image_num_gfxp_save_ops_o())); - nvgpu_err(g, "CILP_SAVE_OPERATIONS : %d", - nvgpu_mem_rd(g, mem, - ctxsw_prog_main_image_num_cilp_save_ops_o())); - nvgpu_err(g, "image gfx preemption option (GFXP is 1) %x", - nvgpu_mem_rd(g, mem, - ctxsw_prog_main_image_graphics_preemption_options_o())); - nvgpu_mem_end(g, mem); -} - -static void gr_gv11b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, - struct gr_ctx_desc *gr_ctx) -{ - gk20a_dbg_fn(""); - - if (!gr_ctx) - return; - - if (g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close) - dump_ctx_switch_stats(g, vm, gr_ctx); - - nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); - nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); - nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); - nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); - gr_gk20a_free_gr_ctx(g, vm, gr_ctx); - gk20a_dbg_fn("done"); -} - - -static void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, - struct channel_ctx_gk20a *ch_ctx, - struct nvgpu_mem *mem) -{ - struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; - u32 gfxp_preempt_option = - ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); - u32 cilp_preempt_option = - ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(); - int err; - - gk20a_dbg_fn(""); - - if (gr_ctx->graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) { - gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); - nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_graphics_preemption_options_o(), - gfxp_preempt_option); - } - - if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) { - gk20a_dbg_info("CILP: %x", cilp_preempt_option); - nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_compute_preemption_options_o(), - cilp_preempt_option); - } - - if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) { - u32 addr; - u32 size; - u32 cbes_reserve; - - nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_full_preemption_ptr_o(), - gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8); - - err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); - if (err) { - nvgpu_err(g, "can't map patch context"); - goto out; - } - - addr = (u64_lo32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) >> - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) | - (u64_hi32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) << - (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); - - gk20a_dbg_info("attrib cb addr : 0x%016x", addr); - g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true); - - addr = (u64_lo32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) >> - gr_scc_pagepool_base_addr_39_8_align_bits_v()) | - (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << - (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); - size = gr_ctx->t18x.pagepool_ctxsw_buffer.size; - - if (size == g->ops.gr.pagepool_default_size(g)) - size = gr_scc_pagepool_total_pages_hwmax_v(); - - g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true); - - addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >> - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | - (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) << - (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); - size = gr_ctx->t18x.spill_ctxsw_buffer.size / - gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_swdx_rm_spill_buffer_addr_r(), - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(addr), - true); - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_swdx_rm_spill_buffer_size_r(), - gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size), - true); - - cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(); - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpcs_swdx_beta_cb_ctrl_r(), - gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f( - cbes_reserve), - true); - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(), - gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f( - cbes_reserve), - true); - - gr_gk20a_ctx_patch_write_end(g, ch_ctx); - } - -out: - gk20a_dbg_fn("done"); -} static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, struct gk20a_debug_output *o) @@ -1145,41 +781,6 @@ static void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch); } -static void gr_gv11b_commit_global_bundle_cb(struct gk20a *g, - struct channel_ctx_gk20a *ch_ctx, - u64 addr, u64 size, bool patch) -{ - u32 data; - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_base_r(), - gr_scc_bundle_cb_base_addr_39_8_f(addr), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_size_r(), - gr_scc_bundle_cb_size_div_256b_f(size) | - gr_scc_bundle_cb_size_valid_true_f(), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_base_r(), - gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(addr), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_size_r(), - gr_gpcs_swdx_bundle_cb_size_div_256b_f(size) | - gr_gpcs_swdx_bundle_cb_size_valid_true_f(), patch); - - /* data for state_limit */ - data = (g->gr.bundle_cb_default_size * - gr_scc_bundle_cb_size_div_256b_byte_granularity_v()) / - gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(); - - data = min_t(u32, data, g->gr.min_gpm_fifo_depth); - - gk20a_dbg_info("bundle cb token limit : %d, state limit : %d", - g->gr.bundle_cb_token_limit, data); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg2_r(), - gr_pd_ab_dist_cfg2_token_limit_f(g->gr.bundle_cb_token_limit) | - gr_pd_ab_dist_cfg2_state_limit_f(data), patch); -} - static int gr_gv11b_init_fs_state(struct gk20a *g) { return gr_gp10b_init_fs_state(g); @@ -2025,6 +1626,28 @@ static void gr_gv11b_load_tpc_mask(struct gk20a *g) } +static void gr_gv11b_write_preemption_ptr(struct gk20a *g, + struct nvgpu_mem *mem, u64 gpu_va) +{ + u32 addr_lo, addr_hi; + + addr_lo = u64_lo32(gpu_va); + addr_hi = u64_hi32(gpu_va); + + nvgpu_mem_wr(g, mem, + ctxsw_prog_main_image_full_preemption_ptr_o(), addr_lo); + nvgpu_mem_wr(g, mem, + ctxsw_prog_main_image_full_preemption_ptr_hi_o(), addr_hi); + + nvgpu_mem_wr(g, mem, + ctxsw_prog_main_image_full_preemption_ptr_veid0_o(), addr_lo); + nvgpu_mem_wr(g, mem, + ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(), + addr_hi); + +} + + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2032,8 +1655,9 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.init_fs_state = gr_gv11b_init_fs_state; gops->gr.detect_sm_arch = gr_gv11b_detect_sm_arch; gops->gr.is_valid_class = gr_gv11b_is_valid_class; - gops->gr.commit_global_cb_manager = gr_gv11b_commit_global_cb_manager; - gops->gr.commit_global_pagepool = gr_gv11b_commit_global_pagepool; + gops->gr.is_valid_gfx_class = gr_gv11b_is_valid_gfx_class; + gops->gr.is_valid_compute_class = gr_gv11b_is_valid_compute_class; + gops->gr.write_preemption_ptr = gr_gv11b_write_preemption_ptr; gops->gr.add_zbc_s = gr_gv11b_add_zbc_stencil; gops->gr.load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl; gops->gr.load_zbc_s_tbl = gr_gv11b_load_stencil_tbl; @@ -2043,7 +1667,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.calc_global_ctx_buffer_size = gr_gv11b_calc_global_ctx_buffer_size; gops->gr.commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb; - gops->gr.commit_global_bundle_cb = gr_gv11b_commit_global_bundle_cb; gops->gr.handle_sw_method = gr_gv11b_handle_sw_method; gops->gr.bundle_cb_defaults = gr_gv11b_bundle_cb_defaults; gops->gr.cb_size_default = gr_gv11b_cb_size_default; @@ -2051,11 +1674,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gr_gv11b_set_alpha_circular_buffer_size; gops->gr.set_circular_buffer_size = gr_gv11b_set_circular_buffer_size; - gops->gr.init_ctx_state = gr_gv11b_init_ctx_state; - gops->gr.alloc_gr_ctx = gr_gv11b_alloc_gr_ctx; - gops->gr.free_gr_ctx = gr_gv11b_free_gr_ctx; - gops->gr.update_ctxsw_preemption_mode = - gr_gv11b_update_ctxsw_preemption_mode; gops->gr.dump_gr_regs = gr_gv11b_dump_gr_status_regs; gops->gr.wait_empty = gr_gv11b_wait_empty; gops->gr.init_cyclestats = gr_gv11b_init_cyclestats; -- cgit v1.2.2 From 44dcc5a53fabc68a32f16a1a3a46a2582b5b192b Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 17 Apr 2017 22:16:00 +0100 Subject: gpu: nvgpu: Separate GMMU out of mm_gk20a.c t19x version of same named patch in nvgpu. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I0b176577c0edcdcc587f22a6908045a960f830e2 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1464111 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 5 +++-- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 8 ++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index b8993052..46626bb7 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -21,6 +21,7 @@ #include #include +#include #include #include @@ -534,8 +535,8 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, if (err) return err; - mem->gpu_va = gk20a_gmmu_map(vm, - &mem->priv.sgt, + mem->gpu_va = nvgpu_gmmu_map(vm, + mem, size, NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none, diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index dcf69adf..6aa58337 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -22,6 +22,7 @@ #include #include +#include #include #include @@ -38,8 +39,7 @@ void gv11b_free_subctx_header(struct channel_gk20a *c) gk20a_dbg_fn(""); if (ctx->mem.gpu_va) { - gk20a_gmmu_unmap(c->vm, ctx->mem.gpu_va, - ctx->mem.size, gk20a_mem_flag_none); + nvgpu_gmmu_unmap(c->vm, &ctx->mem, ctx->mem.gpu_va); nvgpu_dma_free(g, &ctx->mem); } @@ -63,8 +63,8 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) nvgpu_err(g, "failed to allocate sub ctx header"); return ret; } - ctx->mem.gpu_va = gk20a_gmmu_map(c->vm, - &ctx->mem.priv.sgt, + ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm, + &ctx->mem, ctx->mem.size, NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none, true, -- cgit v1.2.2 From 8c246cb18df28bac83297df2c9d0c47725b94273 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 5 May 2017 14:22:06 -0700 Subject: gpu: nvgpu: gv11b: MMU parity HWW error intr Adding support for ISR handling of ecc uncorrectable errors for volta resiliency (Volta-686) TODO: move interrupt init out of MC bug 1881052 JIRA: GPUT19X-82 Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1476603 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 136 +++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 29 ++++- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 5 + .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 68 +++++++++++ 4 files changed, 229 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 98aad4e0..c3524953 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -27,6 +27,8 @@ #include #include +#include + static void gv11b_init_nvlink_soc_credits(struct gk20a *g) { void __iomem *soc1 = ioremap(0x02b10010, 4096); @@ -34,7 +36,7 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) void __iomem *soc3 = ioremap(0x02b30010, 4096); void __iomem *soc4 = ioremap(0x02b40010, 4096); - gk20a_dbg_info("init nvlink soc credits"); + nvgpu_info(g, "init nvlink soc credits"); writel_relaxed(0x14050000, soc1); writel_relaxed(0x08020000, soc1 + 4); @@ -51,7 +53,7 @@ static void gv11b_fb_reset(struct gk20a *g) { u32 val; - gk20a_dbg_info("reset gv11b fb"); + nvgpu_info(g, "reset gv11b fb"); g->ops.mc.reset(g, mc_enable_pfb_enabled_f() | mc_enable_l2_enabled_f() | @@ -69,14 +71,14 @@ static void gv11b_fb_reset(struct gk20a *g) gv11b_init_nvlink_soc_credits(g); val = gk20a_readl(g, fifo_fb_iface_r()); - gk20a_dbg_info("fifo_fb_iface val = 0x%x", val); + nvgpu_info(g, "fifo_fb_iface val = 0x%x", val); if (!(val & fifo_fb_iface_control_enable_f() && val & fifo_fb_iface_status_enabled_f())) { - gk20a_dbg_info("fifo_fb_iface set control enable"); + nvgpu_info(g, "fifo_fb_iface set control enable"); gk20a_writel(g, fifo_fb_iface_r(), fifo_fb_iface_control_enable_f()); val = gk20a_readl(g, fifo_fb_iface_r()); - gk20a_dbg_info("fifo_fb_iface val = 0x%x", val); + nvgpu_info(g, "fifo_fb_iface val = 0x%x", val); } } @@ -129,19 +131,137 @@ static void gv11b_init_kind_attr(void) } } +static void gv11b_fb_intr_en_set(struct gk20a *g, + unsigned int index, u32 mask) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fb_niso_intr_en_set_r(index)); + reg_val |= mask; + gk20a_writel(g, fb_niso_intr_en_set_r(index), reg_val); +} + +static void gv11b_fb_intr_en_clr(struct gk20a *g, + unsigned int index, u32 mask) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fb_niso_intr_en_clr_r(index)); + reg_val |= mask; + gk20a_writel(g, fb_niso_intr_en_clr_r(index), reg_val); +} + +static u32 gv11b_fb_get_hub_intr_clr_mask(struct gk20a *g, + unsigned int intr_type) +{ + u32 mask = 0; + + if (intr_type == HUB_INTR_TYPE_ALL) { + mask |= + fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(); + return mask; + } + + if (intr_type & HUB_INTR_TYPE_ECC_UNCORRECTED) { + mask |= + fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(); + } + + return mask; +} + +static u32 gv11b_fb_get_hub_intr_en_mask(struct gk20a *g, + unsigned int intr_type) +{ + u32 mask = 0; + + if (intr_type == HUB_INTR_TYPE_ALL) { + mask |= + fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(); + return mask; + } + + if (intr_type & HUB_INTR_TYPE_ECC_UNCORRECTED) { + mask |= + fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(); + } + + return mask; +} + +void gv11b_fb_enable_hub_intr(struct gk20a *g, + unsigned int index, unsigned int intr_type) +{ + u32 mask = 0; + + mask = gv11b_fb_get_hub_intr_en_mask(g, intr_type); + + if (mask) + gv11b_fb_intr_en_set(g, index, mask); +} + +void gv11b_fb_disable_hub_intr(struct gk20a *g, + unsigned int index, unsigned int intr_type) +{ + u32 mask = 0; + + mask = gv11b_fb_get_hub_intr_clr_mask(g, intr_type); + + if (mask) + gv11b_fb_intr_en_clr(g, index, mask); +} + static void gv11b_fb_hub_isr(struct gk20a *g) { + u32 status; u32 niso_intr = gk20a_readl(g, fb_niso_intr_r()); - gk20a_dbg_info("enter hub isr, niso_intr = 0x%x", niso_intr); + nvgpu_info(g, "enter hub isr, niso_intr = 0x%x", niso_intr); if (niso_intr & (fb_niso_intr_hub_access_counter_notify_pending_f() | fb_niso_intr_hub_access_counter_error_pending_f())) { - gk20a_dbg_info("hub access counter notify/error"); + nvgpu_info(g, "hub access counter notify/error"); + } else if (niso_intr & + fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f()) { + + nvgpu_info(g, "ecc uncorrected error notify"); + + /* disable interrupts during handling */ + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, + HUB_INTR_TYPE_ECC_UNCORRECTED); + + status = gk20a_readl(g, fb_mmu_l2tlb_ecc_status_r()); + if (status) { + nvgpu_info(g, "hub mmu L2 ecc status: 0x%x", + status); + gk20a_writel(g, fb_mmu_l2tlb_ecc_status_r(), + fb_mmu_l2tlb_ecc_status_reset_clear_f()); + } + + status = gk20a_readl(g, fb_mmu_hubtlb_ecc_status_r()); + if (status) { + nvgpu_info(g, "hub mmu hub tlb ecc status: 0x%x", + status); + gk20a_writel(g, fb_mmu_hubtlb_ecc_status_r(), + fb_mmu_hubtlb_ecc_status_reset_clear_f()); + } + + status = gk20a_readl(g, fb_mmu_fillunit_ecc_status_r()); + if (status) { + nvgpu_info(g, "hub mmu fill unit ecc status: 0x%x", + status); + gk20a_writel(g, fb_mmu_fillunit_ecc_status_r(), + fb_mmu_fillunit_ecc_status_reset_clear_f()); + } + + /* re-enable interrupts after handling */ + gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, + HUB_INTR_TYPE_ECC_UNCORRECTED); + } else { - gk20a_dbg_info("mmu fault : TODO"); + nvgpu_info(g, "mmu fault : TODO"); } } diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index ab688aba..eff3c25d 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -1,7 +1,7 @@ /* * GV11B FB * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,5 +17,32 @@ #define _NVGPU_GV11B_FB struct gpu_ops; +#define STALL_REG_INDEX 0 +#define NONSTALL_REG_INDEX 1 + +#define NONREPLAY_REG_INDEX 0 +#define REPLAY_REG_INDEX 1 + +#define FAULT_BUF_DISABLED 0 +#define FAULT_BUF_ENABLED 1 + +#define FAULT_BUF_VALID 1 +#define CHECK_NEXT_FAULT_BUF 1 + +#define HUB_INTR_TYPE_OTHER 1 /* bit 0 */ +#define HUB_INTR_TYPE_NONREPLAY 2 /* bit 1 */ +#define HUB_INTR_TYPE_REPLAY 4 /* bit 2 */ +#define HUB_INTR_TYPE_ECC_UNCORRECTED 8 /* bit 3 */ +#define HUB_INTR_TYPE_ACCESS_COUNTER 16 /* bit 4 */ +#define HUB_INTR_TYPE_ALL (HUB_INTR_TYPE_OTHER | \ + HUB_INTR_TYPE_NONREPLAY | \ + HUB_INTR_TYPE_REPLAY | \ + HUB_INTR_TYPE_ECC_UNCORRECTED | \ + HUB_INTR_TYPE_ACCESS_COUNTER) + +void gv11b_fb_enable_hub_intr(struct gk20a *g, + unsigned int index, unsigned int intr_type); +void gv11b_fb_disable_hub_intr(struct gk20a *g, + unsigned int index, unsigned int intr_type); void gv11b_init_fb(struct gpu_ops *gops); #endif diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index c901fd76..8b8fcea0 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -20,6 +20,7 @@ #include "gp10b/mc_gp10b.h" #include "mc_gv11b.h" +#include "fb_gv11b.h" #include @@ -47,6 +48,10 @@ static void mc_gv11b_intr_enable(struct gk20a *g) | eng_intr_mask; gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); + + /* TODO: Enable PRI faults for HUB ECC err intr */ + gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, + HUB_INTR_TYPE_ECC_UNCORRECTED); } static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index 45cb0ad5..76b4e902 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -462,6 +462,42 @@ static inline u32 fb_mmu_vpr_info_fetch_true_v(void) { return 0x00000001; } +static inline u32 fb_mmu_l2tlb_ecc_status_r(void) +{ + return 0x00100e70; +} +static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_hubtlb_ecc_status_r(void) +{ + return 0x00100e84; +} +static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fillunit_ecc_status_r(void) +{ + return 0x00100e98; +} +static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) +{ + return 0x40000000; +} static inline u32 fb_niso_flush_sysmem_addr_r(void) { return 0x00100c10; @@ -526,6 +562,14 @@ static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) { return 0x80000000; } +static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_f(u32 v) +{ + return (v & 0x1) << 26; +} +static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) +{ + return 0x4000000; +} static inline u32 fb_niso_intr_en_r(u32 i) { return 0x00100a24 + i*4; @@ -590,6 +634,14 @@ static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) { return 0x80000000; } +static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(u32 v) +{ + return (v & 0x1) << 26; +} +static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f(void) +{ + return 0x4000000; +} static inline u32 fb_niso_intr_en_set_r(u32 i) { return 0x00100a2c + i*4; @@ -654,6 +706,14 @@ static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) { return 0x80000000; } +static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_f(u32 v) +{ + return (v & 0x1) << 26; +} +static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) +{ + return 0x4000000; +} static inline u32 fb_niso_intr_en_clr_r(u32 i) { return 0x00100a34 + i*4; @@ -718,6 +778,14 @@ static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) { return 0x80000000; } +static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_f(u32 v) +{ + return (v & 0x1) << 26; +} +static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) +{ + return 0x4000000; +} static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) { return 0x00000000; -- cgit v1.2.2 From 8c257ec5e24c658b375ff2118efdb6396ccdffce Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 14 Apr 2017 16:16:45 -0700 Subject: gpu: nvgpu: gv11b: Fix path for platform_tegra.h platform_tegra.h got moved under tegra/linux, so fix the path. JIRA NVGPU-16 Change-Id: I18d4e35e4ea781b6d67f7999e4470862752aafaf Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1463537 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index b9efc683..97845035 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -28,7 +28,7 @@ #include "gp10b/platform_gp10b.h" -#include "platform_tegra.h" +#include "tegra/linux/platform_gk20a_tegra.h" #include "gr_gv11b.h" #include "nvgpu_gpuid_t19x.h" -- cgit v1.2.2 From b7af57e41b3b0b6e84bba07fbe371a77ee4eecb6 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 20 Apr 2017 16:44:36 -0700 Subject: gpu: nvgpu: gv11b: init priv ring HAL Initialize priv ring HAL. Bug 1846641 Change-Id: I738489627e76855328bb2d5ffb2fac1ec8c53dc8 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1473698 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Tested-by: Terje Bergstrom Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index de14f1dd..c3d4ac3f 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -27,6 +27,8 @@ #include "gm20b/gr_gm20b.h" +#include "gp10b/priv_ring_gp10b.h" + #include "hal_gv11b.h" #include "bus_gv11b.h" #include "gr_gv11b.h" @@ -191,6 +193,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_bus(gops); gv11b_init_mc(gops); + gp10b_init_priv_ring(gops); gv11b_init_ltc(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); -- cgit v1.2.2 From df03ec9e3064b027fe5459675f445fb591ef96ee Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Fri, 12 May 2017 17:39:57 +0530 Subject: gpu: nvgpu: pmu: Re-use elpg stats function. Assign gp106_pmu_elpg_statistics() for pmu elpg stats in gv11b. Bug 200305607 Change-Id: I18b2b4b7a527d692894e190871db0909bec5aebc Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1480844 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 4784ee4a..50ddb07b 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -158,4 +158,5 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; + gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; } -- cgit v1.2.2 From 808af68d962b85594c2accd1069c6a2de35c50e4 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Tue, 16 May 2017 15:37:02 +0300 Subject: gpu: nvgpu: gv11b: check subctx header err codes React to possible errors in gr_gv11b_commit_inst() from allocating and updating subcontext header. Bug 1927306 Change-Id: I668e13ce13af296e9a7badb3b167fa7a7cd26212 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1483043 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 46626bb7..179c7d33 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1436,12 +1436,17 @@ static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) u32 addr_lo; u32 addr_hi; struct ctx_header_desc *ctx; + int err; gk20a_dbg_fn(""); - gv11b_alloc_subctx_header(c); + err = gv11b_alloc_subctx_header(c); + if (err) + return err; - gv11b_update_subctx_header(c, gpu_va); + err = gv11b_update_subctx_header(c, gpu_va); + if (err) + return err; ctx = &c->ch_ctx.ctx_header; addr_lo = u64_lo32(ctx->mem.gpu_va) >> ram_in_base_shift_v(); -- cgit v1.2.2 From ffc37e50fa8e869e9a160b35f3cf414040e8a360 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 10 May 2017 12:38:08 +0530 Subject: gpu: nvgpu: gv11b: Add L1 tags parity support This CL covers the following parity support (corrected + uncorrected), 1) SM's L1 tags 2) SM's S2R's pixel PRF buffer 3) SM's L1 D-cache miss latency FIFOs Volta Resiliency Id - Volta-720, Volta-721, Volta-637 JIRA GPUT19X-85 JIRA GPUT19X-104 JIRA GPUT19X-100 JIRA GPUT19X-103 Bug 1825948 Bug 1825962 Bug 1775457 Change-Id: I53d7231a36b2c7c252395eca27b349eca80dec63 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1478881 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 87 +++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 8 ++ drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 59 +++++++++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 72 ++++++++++++++++++ 4 files changed, 225 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 179c7d33..ad34233c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -108,6 +108,89 @@ static bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) return valid; } +static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr) +{ + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); + u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; + u32 l1_tag_ecc_status, l1_tag_ecc_corrected_err_status = 0; + u32 l1_tag_ecc_uncorrected_err_status = 0; + u32 l1_tag_corrected_err_count_delta = 0; + u32 l1_tag_uncorrected_err_count_delta = 0; + bool is_l1_tag_ecc_corrected_total_err_overflow = 0; + bool is_l1_tag_ecc_uncorrected_total_err_overflow = 0; + + /* Check for L1 tag ECC errors. */ + l1_tag_ecc_status = gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r() + offset); + l1_tag_ecc_corrected_err_status = l1_tag_ecc_status & + (gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m() | + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m() | + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m() | + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m()); + l1_tag_ecc_uncorrected_err_status = l1_tag_ecc_status & + (gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m() | + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m() | + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m() | + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m()); + + if ((l1_tag_ecc_corrected_err_status == 0) && (l1_tag_ecc_uncorrected_err_status == 0)) + return 0; + + l1_tag_corrected_err_count_delta = + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r() + + offset)); + l1_tag_uncorrected_err_count_delta = + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r() + + offset)); + is_l1_tag_ecc_corrected_total_err_overflow = + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(l1_tag_ecc_status); + is_l1_tag_ecc_uncorrected_total_err_overflow = + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(l1_tag_ecc_status); + + if ((l1_tag_corrected_err_count_delta > 0) || is_l1_tag_ecc_corrected_total_err_overflow) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "corrected error (SBE) detected in SM L1 tag! err_mask [%08x] is_overf [%d]", + l1_tag_ecc_corrected_err_status, is_l1_tag_ecc_corrected_total_err_overflow); + + /* HW uses 16-bits counter */ + l1_tag_corrected_err_count_delta += + (is_l1_tag_ecc_corrected_total_err_overflow << + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s()); + g->gr.t19x.ecc_stats.sm_l1_tag_corrected_err_count.counters[tpc] += + l1_tag_corrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r() + offset, + 0); + } + if ((l1_tag_uncorrected_err_count_delta > 0) || is_l1_tag_ecc_uncorrected_total_err_overflow) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Uncorrected error (DBE) detected in SM L1 tag! err_mask [%08x] is_overf [%d]", + l1_tag_ecc_uncorrected_err_status, is_l1_tag_ecc_uncorrected_total_err_overflow); + + /* HW uses 16-bits counter */ + l1_tag_uncorrected_err_count_delta += + (is_l1_tag_ecc_uncorrected_total_err_overflow << + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s()); + g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count.counters[tpc] += + l1_tag_uncorrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r() + offset, + 0); + } + + gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r() + offset, + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f()); + + return 0; + +} static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event, struct channel_gk20a *fault_ch, @@ -118,7 +201,8 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, proj_tpc_in_gpc_stride_v() * tpc; u32 lrf_ecc_status; - gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); + /* Check for L1 tag ECC errors. */ + gr_gv11b_handle_l1_tag_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); /* Check for LRF ECC errors. */ lrf_ecc_status = gk20a_readl(g, @@ -1692,6 +1776,7 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception; gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error; + gops->gr.create_gr_sysfs = gr_gv11b_create_sysfs; gops->gr.setup_rop_mapping = gr_gv11b_setup_rop_mapping; gops->gr.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle; gops->gr.program_zcull_mapping = gr_gv11b_program_zcull_mapping; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 9d9f969d..2d6e3d1f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -35,6 +35,13 @@ enum { VOLTA_DMA_COPY_A = 0xC3B5, }; +struct gr_t19x { + struct { + struct gr_gp10b_ecc_stat sm_l1_tag_corrected_err_count; + struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; + } ecc_stats; +}; + #define NVC397_SET_SHADER_EXCEPTIONS 0x1528 #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc @@ -48,4 +55,5 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, /*zcull*/ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, u32 *zcull_map_tiles); +void gr_gv11b_create_sysfs(struct device *dev); #endif diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 97845035..8ca9dd30 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -27,11 +27,13 @@ #include "tegra/linux/clk.h" #include "gp10b/platform_gp10b.h" +#include "tegra/linux/platform_gp10b_tegra.h" #include "tegra/linux/platform_gk20a_tegra.h" #include "gr_gv11b.h" #include "nvgpu_gpuid_t19x.h" +static void gr_gv11b_remove_sysfs(struct device *dev); static int gv11b_tegra_probe(struct device *dev) { @@ -57,6 +59,15 @@ static int gv11b_tegra_probe(struct device *dev) return 0; } +static int gv11b_tegra_remove(struct device *dev) +{ + gp10b_tegra_remove(dev); + + gr_gv11b_remove_sysfs(dev); + + return 0; +} + static bool gv11b_tegra_is_railgated(struct device *dev) { bool ret = false; @@ -89,6 +100,7 @@ struct gk20a_platform t19x_gpu_tegra_platform = { .ptimer_src_freq = 31250000, .probe = gv11b_tegra_probe, + .remove = gv11b_tegra_remove, /* power management callbacks */ .suspend = gv11b_tegra_suspend, @@ -110,3 +122,50 @@ struct gk20a_platform t19x_gpu_tegra_platform = { .reset_assert = gp10b_tegra_reset_assert, .reset_deassert = gp10b_tegra_reset_deassert, }; + +static struct device_attribute *dev_attr_sm_l1_tag_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array; + +void gr_gv11b_create_sysfs(struct device *dev) +{ + struct gk20a *g = get_gk20a(dev); + int error = 0; + /* This stat creation function is called on GR init. GR can get + initialized multiple times but we only need to create the ECC + stats once. Therefore, add the following check to avoid + creating duplicate stat sysfs nodes. */ + if (g->gr.t19x.ecc_stats.sm_l1_tag_corrected_err_count.counters != NULL) + return; + + gr_gp10b_create_sysfs(dev); + + error |= gr_gp10b_ecc_stat_create(dev, + 0, + "sm_l1_tag_ecc_corrected_err_count", + &g->gr.t19x.ecc_stats.sm_l1_tag_corrected_err_count, + dev_attr_sm_l1_tag_ecc_corrected_err_count_array); + + error |= gr_gp10b_ecc_stat_create(dev, + 0, + "sm_l1_tag_ecc_uncorrected_err_count", + &g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count, + dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); + + if (error) + dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); +} + +static void gr_gv11b_remove_sysfs(struct device *dev) +{ + struct gk20a *g = get_gk20a(dev); + + gr_gp10b_ecc_stat_remove(dev, + 0, + &g->gr.t19x.ecc_stats.sm_l1_tag_corrected_err_count, + dev_attr_sm_l1_tag_ecc_corrected_err_count_array); + + gr_gp10b_ecc_stat_remove(dev, + 0, + &g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count, + dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); +} diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 592a7899..d45385a8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -482,6 +482,78 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { return 0x00504358; } +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) +{ + return 0x00504624; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r(void) +{ + return 0x00504628; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r(void) +{ + return 0x0050462c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) { return 0x005042c4; -- cgit v1.2.2 From d503a234440b0b5912f64314de68689b3211bbcd Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Mon, 15 May 2017 15:32:21 +0530 Subject: gpu: nvgpu: gv11b: Add LRF + CBU parity support This CL covers the following parity support (uncorrected error), 1) SM's LRF 2) SM's CBU Volta Resiliency Id - Volta-637 JIRA GPUT19X-85 JIRA GPUT19X-110 Bug 1775457 Change-Id: I3befb1fe22719d06aa819ef27654aaf97f911a9b Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1481791 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 187 ++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 + drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 25 +++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 172 +++++++++++++++++++ 4 files changed, 379 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index ad34233c..d36aa6ec 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -192,24 +192,197 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, } +static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr) +{ + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); + u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; + u32 lrf_ecc_status, lrf_ecc_corrected_err_status = 0; + u32 lrf_ecc_uncorrected_err_status = 0; + u32 lrf_corrected_err_count_delta = 0; + u32 lrf_uncorrected_err_count_delta = 0; + bool is_lrf_ecc_corrected_total_err_overflow = 0; + bool is_lrf_ecc_uncorrected_total_err_overflow = 0; + + /* Check for LRF ECC errors. */ + lrf_ecc_status = gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); + lrf_ecc_corrected_err_status = lrf_ecc_status & + (gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m()); + lrf_ecc_uncorrected_err_status = lrf_ecc_status & + (gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m()); + + if ((lrf_ecc_corrected_err_status == 0) && (lrf_ecc_uncorrected_err_status == 0)) + return 0; + + lrf_corrected_err_count_delta = + gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() + + offset)); + lrf_uncorrected_err_count_delta = + gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() + + offset)); + is_lrf_ecc_corrected_total_err_overflow = + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(lrf_ecc_status); + is_lrf_ecc_uncorrected_total_err_overflow = + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(lrf_ecc_status); + + if ((lrf_corrected_err_count_delta > 0) || is_lrf_ecc_corrected_total_err_overflow) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "corrected error (SBE) detected in SM LRF! err_mask [%08x] is_overf [%d]", + lrf_ecc_corrected_err_status, is_lrf_ecc_corrected_total_err_overflow); + + /* HW uses 16-bits counter */ + lrf_corrected_err_count_delta += + (is_lrf_ecc_corrected_total_err_overflow << + gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s()); + g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] += + lrf_corrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() + offset, + 0); + } + if ((lrf_uncorrected_err_count_delta > 0) || is_lrf_ecc_uncorrected_total_err_overflow) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Uncorrected error (DBE) detected in SM LRF! err_mask [%08x] is_overf [%d]", + lrf_ecc_uncorrected_err_status, is_lrf_ecc_uncorrected_total_err_overflow); + + /* HW uses 16-bits counter */ + lrf_uncorrected_err_count_delta += + (is_lrf_ecc_uncorrected_total_err_overflow << + gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s()); + g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] += + lrf_uncorrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() + offset, + 0); + } + + gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f()); + + return 0; + +} + +static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr) +{ + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); + u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; + u32 cbu_ecc_status, cbu_ecc_corrected_err_status = 0; + u32 cbu_ecc_uncorrected_err_status = 0; + u32 cbu_corrected_err_count_delta = 0; + u32 cbu_uncorrected_err_count_delta = 0; + bool is_cbu_ecc_corrected_total_err_overflow = 0; + bool is_cbu_ecc_uncorrected_total_err_overflow = 0; + + /* Check for CBU ECC errors. */ + cbu_ecc_status = gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r() + offset); + cbu_ecc_corrected_err_status = cbu_ecc_status & + (gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m() | + gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m() | + gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m() | + gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m()); + cbu_ecc_uncorrected_err_status = cbu_ecc_status & + (gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m() | + gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m() | + gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m() | + gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m()); + + if ((cbu_ecc_corrected_err_status == 0) && (cbu_ecc_uncorrected_err_status == 0)) + return 0; + + cbu_corrected_err_count_delta = + gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() + + offset)); + cbu_uncorrected_err_count_delta = + gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() + + offset)); + is_cbu_ecc_corrected_total_err_overflow = + gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(cbu_ecc_status); + is_cbu_ecc_uncorrected_total_err_overflow = + gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(cbu_ecc_status); + + if ((cbu_corrected_err_count_delta > 0) || is_cbu_ecc_corrected_total_err_overflow) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "corrected error (SBE) detected in SM CBU! err_mask [%08x] is_overf [%d]", + cbu_ecc_corrected_err_status, is_cbu_ecc_corrected_total_err_overflow); + + /* HW uses 16-bits counter */ + cbu_corrected_err_count_delta += + (is_cbu_ecc_corrected_total_err_overflow << + gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s()); + g->gr.t19x.ecc_stats.sm_cbu_corrected_err_count.counters[tpc] += + cbu_corrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() + offset, + 0); + } + if ((cbu_uncorrected_err_count_delta > 0) || is_cbu_ecc_uncorrected_total_err_overflow) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Uncorrected error (DBE) detected in SM CBU! err_mask [%08x] is_overf [%d]", + cbu_ecc_uncorrected_err_status, is_cbu_ecc_uncorrected_total_err_overflow); + + /* HW uses 16-bits counter */ + cbu_uncorrected_err_count_delta += + (is_cbu_ecc_uncorrected_total_err_overflow << + gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()); + g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count.counters[tpc] += + cbu_uncorrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() + offset, + 0); + } + + gk20a_writel(g, gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r() + offset, + gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f()); + + return 0; + +} + static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event, struct channel_gk20a *fault_ch, u32 *hww_global_esr) { int ret = 0; - u32 offset = proj_gpc_stride_v() * gpc + - proj_tpc_in_gpc_stride_v() * tpc; - u32 lrf_ecc_status; /* Check for L1 tag ECC errors. */ gr_gv11b_handle_l1_tag_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); /* Check for LRF ECC errors. */ - lrf_ecc_status = gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); + gr_gv11b_handle_lrf_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); + + /* Check for CBU ECC errors. */ + gr_gv11b_handle_cbu_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); - gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, - lrf_ecc_status); return ret; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 2d6e3d1f..b350862c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -39,6 +39,8 @@ struct gr_t19x { struct { struct gr_gp10b_ecc_stat sm_l1_tag_corrected_err_count; struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; + struct gr_gp10b_ecc_stat sm_cbu_corrected_err_count; + struct gr_gp10b_ecc_stat sm_cbu_uncorrected_err_count; } ecc_stats; }; diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 8ca9dd30..d235b261 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -125,6 +125,8 @@ struct gk20a_platform t19x_gpu_tegra_platform = { static struct device_attribute *dev_attr_sm_l1_tag_ecc_corrected_err_count_array; static struct device_attribute *dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_sm_cbu_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_sm_cbu_ecc_uncorrected_err_count_array; void gr_gv11b_create_sysfs(struct device *dev) { @@ -151,6 +153,18 @@ void gr_gv11b_create_sysfs(struct device *dev) &g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count, dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); + error |= gr_gp10b_ecc_stat_create(dev, + 0, + "sm_cbu_ecc_corrected_err_count", + &g->gr.t19x.ecc_stats.sm_cbu_corrected_err_count, + dev_attr_sm_cbu_ecc_corrected_err_count_array); + + error |= gr_gp10b_ecc_stat_create(dev, + 0, + "sm_cbu_ecc_uncorrected_err_count", + &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, + dev_attr_sm_cbu_ecc_uncorrected_err_count_array); + if (error) dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); } @@ -168,4 +182,15 @@ static void gr_gv11b_remove_sysfs(struct device *dev) 0, &g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count, dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); + + gr_gp10b_ecc_stat_remove(dev, + 0, + &g->gr.t19x.ecc_stats.sm_cbu_corrected_err_count, + dev_attr_sm_cbu_ecc_corrected_err_count_array); + + gr_gp10b_ecc_stat_remove(dev, + 0, + &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, + dev_attr_sm_cbu_ecc_uncorrected_err_count_array); + } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index d45385a8..4b2e8c32 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -482,6 +482,106 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { return 0x00504358; } +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) +{ + return 0x1 << 13; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) +{ + return 0x1 << 14; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) +{ + return 0x1 << 15; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 26) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) +{ + return 0x0050435c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) +{ + return 0x00504360; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) { return 0x00504624; @@ -554,6 +654,78 @@ static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u { return (r >> 0) & 0xffff; } +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) +{ + return 0x00504638; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 18) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) +{ + return 0x0050463c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) +{ + return 0x00504640; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) { return 0x005042c4; -- cgit v1.2.2 From 5a08eafbe076fba98de62883636ee6b0751cf7e9 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 17 May 2017 11:42:24 +0530 Subject: gpu: nvgpu: gv11b: Add L1 DATA + iCACHE parity This CL covers the following parity support (uncorrected error), 1) SM's L1 DATA 2) SM's L0 && L1 icache Volta Resiliency Id - Volta-634 JIRA GPUT19X-113 JIRA GPUT19X-99 Bug 1807553 Change-Id: Iacbf492028983529dadc5753007e43510b8cb786 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1483681 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 170 +++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 4 + drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 48 ++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 128 ++++++++++++++++ 4 files changed, 350 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index d36aa6ec..0c0b4261 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -368,6 +368,170 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, } +static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr) +{ + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); + u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; + u32 l1_data_ecc_status, l1_data_ecc_corrected_err_status = 0; + u32 l1_data_ecc_uncorrected_err_status = 0; + u32 l1_data_corrected_err_count_delta = 0; + u32 l1_data_uncorrected_err_count_delta = 0; + bool is_l1_data_ecc_corrected_total_err_overflow = 0; + bool is_l1_data_ecc_uncorrected_total_err_overflow = 0; + + /* Check for L1 data ECC errors. */ + l1_data_ecc_status = gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r() + offset); + l1_data_ecc_corrected_err_status = l1_data_ecc_status & + (gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m() | + gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m()); + l1_data_ecc_uncorrected_err_status = l1_data_ecc_status & + (gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m() | + gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m()); + + if ((l1_data_ecc_corrected_err_status == 0) && (l1_data_ecc_uncorrected_err_status == 0)) + return 0; + + l1_data_corrected_err_count_delta = + gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() + + offset)); + l1_data_uncorrected_err_count_delta = + gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() + + offset)); + is_l1_data_ecc_corrected_total_err_overflow = + gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(l1_data_ecc_status); + is_l1_data_ecc_uncorrected_total_err_overflow = + gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(l1_data_ecc_status); + + if ((l1_data_corrected_err_count_delta > 0) || is_l1_data_ecc_corrected_total_err_overflow) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "corrected error (SBE) detected in SM L1 data! err_mask [%08x] is_overf [%d]", + l1_data_ecc_corrected_err_status, is_l1_data_ecc_corrected_total_err_overflow); + + /* HW uses 16-bits counter */ + l1_data_corrected_err_count_delta += + (is_l1_data_ecc_corrected_total_err_overflow << + gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s()); + g->gr.t19x.ecc_stats.sm_l1_data_corrected_err_count.counters[tpc] += + l1_data_corrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() + offset, + 0); + } + if ((l1_data_uncorrected_err_count_delta > 0) || is_l1_data_ecc_uncorrected_total_err_overflow) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Uncorrected error (DBE) detected in SM L1 data! err_mask [%08x] is_overf [%d]", + l1_data_ecc_uncorrected_err_status, is_l1_data_ecc_uncorrected_total_err_overflow); + + /* HW uses 16-bits counter */ + l1_data_uncorrected_err_count_delta += + (is_l1_data_ecc_uncorrected_total_err_overflow << + gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()); + g->gr.t19x.ecc_stats.sm_l1_data_uncorrected_err_count.counters[tpc] += + l1_data_uncorrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() + offset, + 0); + } + + gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r() + offset, + gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f()); + + return 0; + +} + +static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr) +{ + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); + u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; + u32 icache_ecc_status, icache_ecc_corrected_err_status = 0; + u32 icache_ecc_uncorrected_err_status = 0; + u32 icache_corrected_err_count_delta = 0; + u32 icache_uncorrected_err_count_delta = 0; + bool is_icache_ecc_corrected_total_err_overflow = 0; + bool is_icache_ecc_uncorrected_total_err_overflow = 0; + + /* Check for L0 && L1 icache ECC errors. */ + icache_ecc_status = gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_icache_ecc_status_r() + offset); + icache_ecc_corrected_err_status = icache_ecc_status & + (gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m() | + gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m() | + gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m() | + gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m()); + icache_ecc_uncorrected_err_status = icache_ecc_status & + (gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m() | + gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m() | + gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m() | + gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m()); + + if ((icache_ecc_corrected_err_status == 0) && (icache_ecc_uncorrected_err_status == 0)) + return 0; + + icache_corrected_err_count_delta = + gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() + + offset)); + icache_uncorrected_err_count_delta = + gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() + + offset)); + is_icache_ecc_corrected_total_err_overflow = + gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(icache_ecc_status); + is_icache_ecc_uncorrected_total_err_overflow = + gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(icache_ecc_status); + + if ((icache_corrected_err_count_delta > 0) || is_icache_ecc_corrected_total_err_overflow) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "corrected error (SBE) detected in SM L0 && L1 icache! err_mask [%08x] is_overf [%d]", + icache_ecc_corrected_err_status, is_icache_ecc_corrected_total_err_overflow); + + /* HW uses 16-bits counter */ + icache_corrected_err_count_delta += + (is_icache_ecc_corrected_total_err_overflow << + gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()); + g->gr.t19x.ecc_stats.sm_icache_corrected_err_count.counters[tpc] += + icache_corrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() + offset, + 0); + } + if ((icache_uncorrected_err_count_delta > 0) || is_icache_ecc_uncorrected_total_err_overflow) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Uncorrected error (DBE) detected in SM L0 && L1 icache! err_mask [%08x] is_overf [%d]", + icache_ecc_uncorrected_err_status, is_icache_ecc_uncorrected_total_err_overflow); + + /* HW uses 16-bits counter */ + icache_uncorrected_err_count_delta += + (is_icache_ecc_uncorrected_total_err_overflow << + gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()); + g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count.counters[tpc] += + icache_uncorrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() + offset, + 0); + } + + gk20a_writel(g, gr_pri_gpc0_tpc0_sm_icache_ecc_status_r() + offset, + gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f()); + + return 0; + +} + static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event, struct channel_gk20a *fault_ch, u32 *hww_global_esr) @@ -383,6 +547,12 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, /* Check for CBU ECC errors. */ gr_gv11b_handle_cbu_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); + /* Check for L1 data ECC errors. */ + gr_gv11b_handle_l1_data_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); + + /* Check for L0 && L1 icache ECC errors. */ + gr_gv11b_handle_icache_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); + return ret; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index b350862c..5bcbe667 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -41,6 +41,10 @@ struct gr_t19x { struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; struct gr_gp10b_ecc_stat sm_cbu_corrected_err_count; struct gr_gp10b_ecc_stat sm_cbu_uncorrected_err_count; + struct gr_gp10b_ecc_stat sm_l1_data_corrected_err_count; + struct gr_gp10b_ecc_stat sm_l1_data_uncorrected_err_count; + struct gr_gp10b_ecc_stat sm_icache_corrected_err_count; + struct gr_gp10b_ecc_stat sm_icache_uncorrected_err_count; } ecc_stats; }; diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index d235b261..009e5716 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -127,6 +127,10 @@ static struct device_attribute *dev_attr_sm_l1_tag_ecc_corrected_err_count_array static struct device_attribute *dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array; static struct device_attribute *dev_attr_sm_cbu_ecc_corrected_err_count_array; static struct device_attribute *dev_attr_sm_cbu_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_sm_l1_data_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_sm_l1_data_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_sm_icache_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_sm_icache_ecc_uncorrected_err_count_array; void gr_gv11b_create_sysfs(struct device *dev) { @@ -165,6 +169,30 @@ void gr_gv11b_create_sysfs(struct device *dev) &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, dev_attr_sm_cbu_ecc_uncorrected_err_count_array); + error |= gr_gp10b_ecc_stat_create(dev, + 0, + "sm_l1_data_ecc_corrected_err_count", + &g->gr.t19x.ecc_stats.sm_l1_data_corrected_err_count, + dev_attr_sm_l1_data_ecc_corrected_err_count_array); + + error |= gr_gp10b_ecc_stat_create(dev, + 0, + "sm_l1_data_ecc_uncorrected_err_count", + &g->gr.t19x.ecc_stats.sm_l1_data_uncorrected_err_count, + dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); + + error |= gr_gp10b_ecc_stat_create(dev, + 0, + "sm_icache_ecc_corrected_err_count", + &g->gr.t19x.ecc_stats.sm_icache_corrected_err_count, + dev_attr_sm_icache_ecc_corrected_err_count_array); + + error |= gr_gp10b_ecc_stat_create(dev, + 0, + "sm_icache_ecc_uncorrected_err_count", + &g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count, + dev_attr_sm_icache_ecc_uncorrected_err_count_array); + if (error) dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); } @@ -193,4 +221,24 @@ static void gr_gv11b_remove_sysfs(struct device *dev) &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, dev_attr_sm_cbu_ecc_uncorrected_err_count_array); + gr_gp10b_ecc_stat_remove(dev, + 0, + &g->gr.t19x.ecc_stats.sm_l1_data_corrected_err_count, + dev_attr_sm_l1_data_ecc_corrected_err_count_array); + + gr_gp10b_ecc_stat_remove(dev, + 0, + &g->gr.t19x.ecc_stats.sm_l1_data_uncorrected_err_count, + dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); + + gr_gp10b_ecc_stat_remove(dev, + 0, + &g->gr.t19x.ecc_stats.sm_icache_corrected_err_count, + dev_attr_sm_icache_ecc_corrected_err_count_array); + + gr_gp10b_ecc_stat_remove(dev, + 0, + &g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count, + dev_attr_sm_icache_ecc_uncorrected_err_count_array); + } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 4b2e8c32..4ce69743 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -582,6 +582,134 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 { return (r >> 0) & 0xffff; } +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) +{ + return 0x0050436c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) +{ + return 0x00504370; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) +{ + return 0x00504374; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void) +{ + return 0x0050464c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 18) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void) +{ + return 0x00504650; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void) +{ + return 0x00504654; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) { return 0x00504624; -- cgit v1.2.2 From 45ca7cb8c5774cfc15015973b1883faa1d93b9e6 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Fri, 19 May 2017 15:40:41 +0530 Subject: gpu: nvgpu: gv11b: Add GCC L1.5 parity support Add handling of GCC L1.5 parity exception. JIRA GPUT19X-86 Change-Id: Ie83fc306d3dff79b0ddaf2616dcf0ff71fccd4ca Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1485834 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 82 +++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 + drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 24 +++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 64 +++++++++++++++++ 4 files changed, 171 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 0c0b4261..014ba537 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -556,6 +556,84 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, return ret; } +static int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr) +{ + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 offset = gpc_stride * gpc; + u32 gcc_l15_ecc_status, gcc_l15_ecc_corrected_err_status = 0; + u32 gcc_l15_ecc_uncorrected_err_status = 0; + u32 gcc_l15_corrected_err_count_delta = 0; + u32 gcc_l15_uncorrected_err_count_delta = 0; + bool is_gcc_l15_ecc_corrected_total_err_overflow = 0; + bool is_gcc_l15_ecc_uncorrected_total_err_overflow = 0; + + /* Check for gcc l15 ECC errors. */ + gcc_l15_ecc_status = gk20a_readl(g, + gr_pri_gpc0_gcc_l15_ecc_status_r() + offset); + gcc_l15_ecc_corrected_err_status = gcc_l15_ecc_status & + (gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m() | + gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m()); + gcc_l15_ecc_uncorrected_err_status = gcc_l15_ecc_status & + (gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m() | + gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m()); + + if ((gcc_l15_ecc_corrected_err_status == 0) && (gcc_l15_ecc_uncorrected_err_status == 0)) + return 0; + + gcc_l15_corrected_err_count_delta = + gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r() + + offset)); + gcc_l15_uncorrected_err_count_delta = + gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v( + gk20a_readl(g, + gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r() + + offset)); + is_gcc_l15_ecc_corrected_total_err_overflow = + gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(gcc_l15_ecc_status); + is_gcc_l15_ecc_uncorrected_total_err_overflow = + gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(gcc_l15_ecc_status); + + if ((gcc_l15_corrected_err_count_delta > 0) || is_gcc_l15_ecc_corrected_total_err_overflow) { + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_intr, + "corrected error (SBE) detected in GCC L1.5! err_mask [%08x] is_overf [%d]", + gcc_l15_ecc_corrected_err_status, is_gcc_l15_ecc_corrected_total_err_overflow); + + /* HW uses 16-bits counter */ + gcc_l15_corrected_err_count_delta += + (is_gcc_l15_ecc_corrected_total_err_overflow << + gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s()); + g->gr.t19x.ecc_stats.gcc_l15_corrected_err_count.counters[gpc] += + gcc_l15_corrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r() + offset, + 0); + } + if ((gcc_l15_uncorrected_err_count_delta > 0) || is_gcc_l15_ecc_uncorrected_total_err_overflow) { + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_intr, + "Uncorrected error (DBE) detected in GCC L1.5! err_mask [%08x] is_overf [%d]", + gcc_l15_ecc_uncorrected_err_status, is_gcc_l15_ecc_uncorrected_total_err_overflow); + + /* HW uses 16-bits counter */ + gcc_l15_uncorrected_err_count_delta += + (is_gcc_l15_ecc_uncorrected_total_err_overflow << + gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s()); + g->gr.t19x.ecc_stats.gcc_l15_uncorrected_err_count.counters[gpc] += + gcc_l15_uncorrected_err_count_delta; + gk20a_writel(g, + gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r() + offset, + 0); + } + + gk20a_writel(g, gr_pri_gpc0_gcc_l15_ecc_status_r() + offset, + gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f()); + + return 0; +} + static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; @@ -567,7 +645,8 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) tpc_mask = gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); - gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), tpc_mask); + gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), + (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1))); } static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, @@ -2113,6 +2192,7 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask; gops->gr.get_access_map = gr_gv11b_get_access_map; gops->gr.handle_sm_exception = gr_gv11b_handle_sm_exception; + gops->gr.handle_gcc_exception = gr_gv11b_handle_gcc_exception; gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; gops->gr.mask_hww_warp_esr = gv11b_mask_hww_warp_esr; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 5bcbe667..cf3842b6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -45,6 +45,8 @@ struct gr_t19x { struct gr_gp10b_ecc_stat sm_l1_data_uncorrected_err_count; struct gr_gp10b_ecc_stat sm_icache_corrected_err_count; struct gr_gp10b_ecc_stat sm_icache_uncorrected_err_count; + struct gr_gp10b_ecc_stat gcc_l15_corrected_err_count; + struct gr_gp10b_ecc_stat gcc_l15_uncorrected_err_count; } ecc_stats; }; diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 009e5716..39ae68eb 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -131,6 +131,8 @@ static struct device_attribute *dev_attr_sm_l1_data_ecc_corrected_err_count_arra static struct device_attribute *dev_attr_sm_l1_data_ecc_uncorrected_err_count_array; static struct device_attribute *dev_attr_sm_icache_ecc_corrected_err_count_array; static struct device_attribute *dev_attr_sm_icache_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_gcc_l15_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_gcc_l15_ecc_uncorrected_err_count_array; void gr_gv11b_create_sysfs(struct device *dev) { @@ -193,6 +195,18 @@ void gr_gv11b_create_sysfs(struct device *dev) &g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count, dev_attr_sm_icache_ecc_uncorrected_err_count_array); + error |= gr_gp10b_ecc_stat_create(dev, + 0, + "gcc_l15_ecc_corrected_err_count", + &g->gr.t19x.ecc_stats.gcc_l15_corrected_err_count, + dev_attr_gcc_l15_ecc_corrected_err_count_array); + + error |= gr_gp10b_ecc_stat_create(dev, + 0, + "gcc_l15_ecc_uncorrected_err_count", + &g->gr.t19x.ecc_stats.gcc_l15_uncorrected_err_count, + dev_attr_gcc_l15_ecc_uncorrected_err_count_array); + if (error) dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); } @@ -241,4 +255,14 @@ static void gr_gv11b_remove_sysfs(struct device *dev) &g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count, dev_attr_sm_icache_ecc_uncorrected_err_count_array); + gr_gp10b_ecc_stat_remove(dev, + 0, + &g->gr.t19x.ecc_stats.gcc_l15_corrected_err_count, + dev_attr_gcc_l15_ecc_corrected_err_count_array); + + gr_gp10b_ecc_stat_remove(dev, + 0, + &g->gr.t19x.ecc_stats.gcc_l15_uncorrected_err_count, + dev_attr_gcc_l15_ecc_uncorrected_err_count_array); + } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 4ce69743..6f38cf5b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3370,6 +3370,10 @@ static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) { return 0x0041ac94; } +static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) +{ + return (v & 0x1) << 2; +} static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { return (v & 0xff) << 16; @@ -3378,6 +3382,10 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { return 0x00502c90; } +static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) +{ + return (r >> 2) & 0x1; +} static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) { return (r >> 16) & 0xff; @@ -3386,6 +3394,62 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) { return 0x00000001; } +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) +{ + return 0x00501048; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r(void) +{ + return 0x0050104c; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r(void) +{ + return 0x00501054; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { return 0x00504508; -- cgit v1.2.2 From 2173add7ae7210606afdaa56995a61d012b9a2f1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 12 May 2017 11:07:00 -0700 Subject: gpu: nvgpu: per-chip GPCCS exception support Adding support for ISR handling of GPCCS exceptions and GCC ECC support JIRA: GPUT19X-83 Change-Id: Ica749dc678f152d536052cf47f2ea2b205a231d6 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1480997 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 122 +++++- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 460 +++++++++++++++++++++ 2 files changed, 580 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 014ba537..764374cc 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -634,6 +634,70 @@ static int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, return 0; } +static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, + u32 exception) +{ + int ret = 0; + u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; + int hww_esr; + u32 offset = proj_gpc_stride_v() * gpc; + + hww_esr = gk20a_readl(g, gr_gpc0_gpccs_hww_esr_r() + offset); + + if (!(hww_esr & (gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m() | + gr_gpc0_gpccs_hww_esr_ecc_corrected_m()))) + return ret; + + ecc_status = gk20a_readl(g, + gr_gpc0_gpccs_falcon_ecc_status_r() + offset); + ecc_addr = gk20a_readl(g, + gr_gpc0_gpccs_falcon_ecc_address_r() + offset); + corrected_cnt = gk20a_readl(g, + gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r() + offset); + uncorrected_cnt = gk20a_readl(g, + gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r() + offset); + + /* clear the interrupt */ + gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset, + gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()); + + nvgpu_log(g, gpu_dbg_intr, + "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); + + if (ecc_status & gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m()) + nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected"); + if (ecc_status & + gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m()) + nvgpu_log(g, gpu_dbg_intr, "imem ecc error uncorrected"); + if (ecc_status & + gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m()) + nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected"); + if (ecc_status & + gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m()) + nvgpu_log(g, gpu_dbg_intr, "dmem ecc error uncorrected"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error row address: 0x%x", + gr_gpc0_gpccs_falcon_ecc_address_row_address_v(ecc_addr)); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error count corrected: %d, uncorrected %d", + gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(corrected_cnt), + gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(uncorrected_cnt)); + + return ret; +} + +static int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, + u32 gpc_exception) +{ + if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpccs_m()) + return gr_gv11b_handle_gpccs_ecc_exception(g, gpc, + gpc_exception); + + return 0; +} + static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; @@ -646,7 +710,8 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), - (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1))); + (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) + gr_gpcs_gpccs_gpc_exception_en_gpccs_f(1)); } static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, @@ -1622,6 +1687,55 @@ static int gr_gv11b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) return ret; } +static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) +{ + u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; + + if (intr & (gr_fecs_host_int_status_ecc_uncorrected_m() | + gr_fecs_host_int_status_ecc_corrected_m())) { + ecc_status = gk20a_readl(g, gr_fecs_falcon_ecc_status_r()); + ecc_addr = gk20a_readl(g, + gr_fecs_falcon_ecc_address_r()); + corrected_cnt = gk20a_readl(g, + gr_fecs_falcon_ecc_corrected_err_count_r()); + uncorrected_cnt = gk20a_readl(g, + gr_fecs_falcon_ecc_uncorrected_err_count_r()); + + /* clear the interrupt */ + gk20a_writel(g, gr_fecs_falcon_ecc_status_r(), + gr_fecs_falcon_ecc_status_reset_task_f()); + + nvgpu_log(g, gpu_dbg_intr, + "fecs ecc interrupt intr: 0x%x", intr); + + if (ecc_status & + gr_fecs_falcon_ecc_status_corrected_err_imem_m()) + nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected"); + if (ecc_status & + gr_fecs_falcon_ecc_status_uncorrected_err_imem_m()) + nvgpu_log(g, gpu_dbg_intr, + "imem ecc error uncorrected"); + if (ecc_status & + gr_fecs_falcon_ecc_status_corrected_err_dmem_m()) + nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected"); + if (ecc_status & + gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m()) + nvgpu_log(g, gpu_dbg_intr, + "dmem ecc error uncorrected"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error row address: 0x%x", + gr_fecs_falcon_ecc_address_row_address_v(ecc_addr)); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error count corrected: %d, uncorrected %d", + gr_fecs_falcon_ecc_corrected_err_count_total_v( + corrected_cnt), + gr_fecs_falcon_ecc_uncorrected_err_count_total_v( + uncorrected_cnt)); + } +} + static int gr_gv11b_handle_fecs_error(struct gk20a *g, struct channel_gk20a *__ch, struct gr_gk20a_isr_data *isr_data) @@ -1680,6 +1794,9 @@ static int gr_gv11b_handle_fecs_error(struct gk20a *g, gk20a_channel_put(ch); } + /* Handle ECC errors */ + gr_gv11b_handle_fecs_ecc_error(g, gr_fecs_intr); + clean_up: /* handle any remaining interrupts */ return gk20a_gr_handle_fecs_error(g, __ch, isr_data); @@ -2214,5 +2331,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode; gops->gr.load_tpc_mask = gr_gv11b_load_tpc_mask; - + gops->gr.handle_gpc_gpccs_exception = + gr_gv11b_handle_gpc_gpccs_exception; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 6f38cf5b..9917f86d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -1398,6 +1398,22 @@ static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) { return (v & 0xffff) << 0; } +static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) +{ + return 0x1 << 21; +} +static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) +{ + return 0x1 << 22; +} static inline u32 gr_fecs_host_int_clear_r(void) { return 0x00409c20; @@ -3378,6 +3394,10 @@ static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { return (v & 0xff) << 16; } +static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) +{ + return (v & 0x1) << 14; +} static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { return 0x00502c90; @@ -3450,6 +3470,18 @@ static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) { return (r >> 0) & 0xffff; } +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) +{ + return 0x1 << 14; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) +{ + return 0x4000; +} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { return 0x00504508; @@ -3954,4 +3986,432 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { return 0x1ff << 0; } +static inline u32 gr_gpc0_gpccs_hww_esr_r(void) +{ + return 0x00502c98; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void) +{ + return 0x00502678; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) +{ + return 0x400; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x800; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x200; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void) +{ + return 0x00502684; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v) +{ + return (v & 0x7fffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void) +{ + return 20; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) +{ + return 0xfffff << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void) +{ + return 0x0050267c; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void) +{ + return 0x00502680; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_status_r(void) +{ + return 0x00409678; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) +{ + return 0x400; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x800; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x200; +} +static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fecs_falcon_ecc_address_r(void) +{ + return 0x00409684; +} +static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v) +{ + return (v & 0x7fffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void) +{ + return 20; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) +{ + return 0xfffff << 0; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void) +{ + return 0x0040967c; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void) +{ + return 0x00409680; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} #endif -- cgit v1.2.2 From c771d0b979cd9f42a21da520d5010873d2a6aa47 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 18 May 2017 16:45:40 -0700 Subject: gpu: nvgpu: add GPC parity counters (1) Re-arrange the structure for ecc counters reporting so multiple units can be managed (2) Add counters and handling for additional GPC counters JIRA: GPUT19X-84 Change-Id: I74fd474d7daf7590fc7f7ddc9837bb692512d208 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1485277 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/ecc_t19x.h | 20 +++++ drivers/gpu/nvgpu/gv11b/ecc_gv11b.h | 36 +++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 103 ++++++++++++++++++++----- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 15 ---- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 94 +++++++++++++++++----- 5 files changed, 212 insertions(+), 56 deletions(-) create mode 100644 drivers/gpu/nvgpu/ecc_t19x.h create mode 100644 drivers/gpu/nvgpu/gv11b/ecc_gv11b.h diff --git a/drivers/gpu/nvgpu/ecc_t19x.h b/drivers/gpu/nvgpu/ecc_t19x.h new file mode 100644 index 00000000..27f00c6c --- /dev/null +++ b/drivers/gpu/nvgpu/ecc_t19x.h @@ -0,0 +1,20 @@ +/* + * NVIDIA T19x ECC + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _NVGPU_ECC_T19X_H_ +#define _NVGPU_ECC_T19X_H_ + +#include "gv11b/ecc_gv11b.h" + +#endif diff --git a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h new file mode 100644 index 00000000..6b471655 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h @@ -0,0 +1,36 @@ +/* + * GV11B GPU ECC + * + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_ECC_GV11B_H_ +#define _NVGPU_ECC_GV11B_H_ + +struct ecc_gr_t19x { + struct gk20a_ecc_stat sm_l1_tag_corrected_err_count; + struct gk20a_ecc_stat sm_l1_tag_uncorrected_err_count; + struct gk20a_ecc_stat sm_cbu_corrected_err_count; + struct gk20a_ecc_stat sm_cbu_uncorrected_err_count; + struct gk20a_ecc_stat sm_l1_data_corrected_err_count; + struct gk20a_ecc_stat sm_l1_data_uncorrected_err_count; + struct gk20a_ecc_stat sm_icache_corrected_err_count; + struct gk20a_ecc_stat sm_icache_uncorrected_err_count; + struct gk20a_ecc_stat gcc_l15_corrected_err_count; + struct gk20a_ecc_stat gcc_l15_uncorrected_err_count; + struct gk20a_ecc_stat fecs_corrected_err_count; + struct gk20a_ecc_stat fecs_uncorrected_err_count; + struct gk20a_ecc_stat gpccs_corrected_err_count; + struct gk20a_ecc_stat gpccs_uncorrected_err_count; +}; + +#endif diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 764374cc..8b4471ca 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -163,7 +163,7 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, l1_tag_corrected_err_count_delta += (is_l1_tag_ecc_corrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s()); - g->gr.t19x.ecc_stats.sm_l1_tag_corrected_err_count.counters[tpc] += + g->ecc.gr.t19x.sm_l1_tag_corrected_err_count.counters[tpc] += l1_tag_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r() + offset, @@ -178,7 +178,7 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, l1_tag_uncorrected_err_count_delta += (is_l1_tag_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s()); - g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count.counters[tpc] += + g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count.counters[tpc] += l1_tag_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r() + offset, @@ -255,7 +255,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, lrf_corrected_err_count_delta += (is_lrf_ecc_corrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s()); - g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] += + g->ecc.gr.t18x.sm_lrf_single_err_count.counters[tpc] += lrf_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() + offset, @@ -270,7 +270,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, lrf_uncorrected_err_count_delta += (is_lrf_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s()); - g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] += + g->ecc.gr.t18x.sm_lrf_double_err_count.counters[tpc] += lrf_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() + offset, @@ -339,7 +339,7 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, cbu_corrected_err_count_delta += (is_cbu_ecc_corrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s()); - g->gr.t19x.ecc_stats.sm_cbu_corrected_err_count.counters[tpc] += + g->ecc.gr.t19x.sm_cbu_corrected_err_count.counters[tpc] += cbu_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() + offset, @@ -354,7 +354,7 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, cbu_uncorrected_err_count_delta += (is_cbu_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()); - g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count.counters[tpc] += + g->ecc.gr.t19x.sm_cbu_uncorrected_err_count.counters[tpc] += cbu_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() + offset, @@ -419,7 +419,7 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, l1_data_corrected_err_count_delta += (is_l1_data_ecc_corrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s()); - g->gr.t19x.ecc_stats.sm_l1_data_corrected_err_count.counters[tpc] += + g->ecc.gr.t19x.sm_l1_data_corrected_err_count.counters[tpc] += l1_data_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() + offset, @@ -434,7 +434,7 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, l1_data_uncorrected_err_count_delta += (is_l1_data_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()); - g->gr.t19x.ecc_stats.sm_l1_data_uncorrected_err_count.counters[tpc] += + g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count.counters[tpc] += l1_data_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() + offset, @@ -503,7 +503,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, icache_corrected_err_count_delta += (is_icache_ecc_corrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()); - g->gr.t19x.ecc_stats.sm_icache_corrected_err_count.counters[tpc] += + g->ecc.gr.t19x.sm_icache_corrected_err_count.counters[tpc] += icache_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() + offset, @@ -518,7 +518,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, icache_uncorrected_err_count_delta += (is_icache_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()); - g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count.counters[tpc] += + g->ecc.gr.t19x.sm_icache_uncorrected_err_count.counters[tpc] += icache_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() + offset, @@ -606,7 +606,7 @@ static int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, gcc_l15_corrected_err_count_delta += (is_gcc_l15_ecc_corrected_total_err_overflow << gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s()); - g->gr.t19x.ecc_stats.gcc_l15_corrected_err_count.counters[gpc] += + g->ecc.gr.t19x.gcc_l15_corrected_err_count.counters[gpc] += gcc_l15_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r() + offset, @@ -621,7 +621,7 @@ static int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, gcc_l15_uncorrected_err_count_delta += (is_gcc_l15_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s()); - g->gr.t19x.ecc_stats.gcc_l15_uncorrected_err_count.counters[gpc] += + g->ecc.gr.t19x.gcc_l15_uncorrected_err_count.counters[gpc] += gcc_l15_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r() + offset, @@ -639,6 +639,9 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, { int ret = 0; u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; + u32 corrected_delta, uncorrected_delta; + u32 corrected_overflow, uncorrected_overflow; + int hww_esr; u32 offset = proj_gpc_stride_v() * gpc; @@ -657,10 +660,34 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, uncorrected_cnt = gk20a_readl(g, gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r() + offset); + corrected_delta = gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v( + corrected_cnt); + uncorrected_delta = gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v( + uncorrected_cnt); + corrected_overflow = ecc_status & + gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(); + + uncorrected_overflow = ecc_status & + gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(); + + /* clear the interrupt */ + if ((corrected_delta > 0) || corrected_overflow) + gk20a_writel(g, + gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r() + + offset, 0); + if ((uncorrected_delta > 0) || uncorrected_overflow) + gk20a_writel(g, + gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r() + + offset, 0); + gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset, gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()); + g->ecc.gr.t19x.gpccs_corrected_err_count.counters[gpc] += + corrected_delta; + g->ecc.gr.t19x.gpccs_uncorrected_err_count.counters[gpc] += + uncorrected_delta; nvgpu_log(g, gpu_dbg_intr, "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); @@ -675,6 +702,8 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, if (ecc_status & gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m()) nvgpu_log(g, gpu_dbg_intr, "dmem ecc error uncorrected"); + if (corrected_overflow || uncorrected_overflow) + nvgpu_info(g, "gpccs ecc counter overflow!"); nvgpu_log(g, gpu_dbg_intr, "ecc error row address: 0x%x", @@ -682,8 +711,8 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, nvgpu_log(g, gpu_dbg_intr, "ecc error count corrected: %d, uncorrected %d", - gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(corrected_cnt), - gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(uncorrected_cnt)); + g->ecc.gr.t19x.gpccs_corrected_err_count.counters[gpc], + g->ecc.gr.t19x.gpccs_uncorrected_err_count.counters[gpc]); return ret; } @@ -710,8 +739,8 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), - (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) - gr_gpcs_gpccs_gpc_exception_en_gpccs_f(1)); + (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) | + gr_gpcs_gpccs_gpc_exception_en_gpccs_f(1))); } static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, @@ -1690,6 +1719,8 @@ static int gr_gv11b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) { u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; + u32 corrected_delta, uncorrected_delta; + u32 corrected_overflow, uncorrected_overflow; if (intr & (gr_fecs_host_int_status_ecc_uncorrected_m() | gr_fecs_host_int_status_ecc_corrected_m())) { @@ -1701,10 +1732,42 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) uncorrected_cnt = gk20a_readl(g, gr_fecs_falcon_ecc_uncorrected_err_count_r()); + corrected_delta = + gr_fecs_falcon_ecc_corrected_err_count_total_v( + corrected_cnt); + uncorrected_delta = + gr_fecs_falcon_ecc_uncorrected_err_count_total_v( + uncorrected_cnt); + + corrected_overflow = ecc_status & + gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(); + uncorrected_overflow = ecc_status & + gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(); + + /* clear the interrupt */ + if ((corrected_delta > 0) || corrected_overflow) + gk20a_writel(g, + gr_fecs_falcon_ecc_corrected_err_count_r(), 0); + if ((uncorrected_delta > 0) || uncorrected_overflow) + gk20a_writel(g, + gr_fecs_falcon_ecc_uncorrected_err_count_r(), + 0); + + + /* clear the interrupt */ + gk20a_writel(g, gr_fecs_falcon_ecc_uncorrected_err_count_r(), + 0); + gk20a_writel(g, gr_fecs_falcon_ecc_corrected_err_count_r(), 0); + /* clear the interrupt */ gk20a_writel(g, gr_fecs_falcon_ecc_status_r(), gr_fecs_falcon_ecc_status_reset_task_f()); + g->ecc.gr.t19x.fecs_corrected_err_count.counters[0] += + corrected_delta; + g->ecc.gr.t19x.fecs_uncorrected_err_count.counters[0] += + uncorrected_delta; + nvgpu_log(g, gpu_dbg_intr, "fecs ecc interrupt intr: 0x%x", intr); @@ -1722,6 +1785,8 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m()) nvgpu_log(g, gpu_dbg_intr, "dmem ecc error uncorrected"); + if (corrected_overflow || uncorrected_overflow) + nvgpu_info(g, "gpccs ecc counter overflow!"); nvgpu_log(g, gpu_dbg_intr, "ecc error row address: 0x%x", @@ -1729,10 +1794,8 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) nvgpu_log(g, gpu_dbg_intr, "ecc error count corrected: %d, uncorrected %d", - gr_fecs_falcon_ecc_corrected_err_count_total_v( - corrected_cnt), - gr_fecs_falcon_ecc_uncorrected_err_count_total_v( - uncorrected_cnt)); + g->ecc.gr.t19x.fecs_corrected_err_count.counters[0], + g->ecc.gr.t19x.fecs_uncorrected_err_count.counters[0]); } } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index cf3842b6..9283a597 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -35,21 +35,6 @@ enum { VOLTA_DMA_COPY_A = 0xC3B5, }; -struct gr_t19x { - struct { - struct gr_gp10b_ecc_stat sm_l1_tag_corrected_err_count; - struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; - struct gr_gp10b_ecc_stat sm_cbu_corrected_err_count; - struct gr_gp10b_ecc_stat sm_cbu_uncorrected_err_count; - struct gr_gp10b_ecc_stat sm_l1_data_corrected_err_count; - struct gr_gp10b_ecc_stat sm_l1_data_uncorrected_err_count; - struct gr_gp10b_ecc_stat sm_icache_corrected_err_count; - struct gr_gp10b_ecc_stat sm_icache_uncorrected_err_count; - struct gr_gp10b_ecc_stat gcc_l15_corrected_err_count; - struct gr_gp10b_ecc_stat gcc_l15_uncorrected_err_count; - } ecc_stats; -}; - #define NVC397_SET_SHADER_EXCEPTIONS 0x1528 #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 39ae68eb..1cfa2ef2 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -134,6 +134,11 @@ static struct device_attribute *dev_attr_sm_icache_ecc_uncorrected_err_count_arr static struct device_attribute *dev_attr_gcc_l15_ecc_corrected_err_count_array; static struct device_attribute *dev_attr_gcc_l15_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_fecs_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_fecs_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_gpccs_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_gpccs_ecc_uncorrected_err_count_array; + void gr_gv11b_create_sysfs(struct device *dev) { struct gk20a *g = get_gk20a(dev); @@ -142,7 +147,7 @@ void gr_gv11b_create_sysfs(struct device *dev) initialized multiple times but we only need to create the ECC stats once. Therefore, add the following check to avoid creating duplicate stat sysfs nodes. */ - if (g->gr.t19x.ecc_stats.sm_l1_tag_corrected_err_count.counters != NULL) + if (g->ecc.gr.t19x.sm_l1_tag_corrected_err_count.counters != NULL) return; gr_gp10b_create_sysfs(dev); @@ -150,63 +155,91 @@ void gr_gv11b_create_sysfs(struct device *dev) error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_l1_tag_ecc_corrected_err_count", - &g->gr.t19x.ecc_stats.sm_l1_tag_corrected_err_count, + &g->ecc.gr.t19x.sm_l1_tag_corrected_err_count, dev_attr_sm_l1_tag_ecc_corrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_l1_tag_ecc_uncorrected_err_count", - &g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count, + &g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count, dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_cbu_ecc_corrected_err_count", - &g->gr.t19x.ecc_stats.sm_cbu_corrected_err_count, + &g->ecc.gr.t19x.sm_cbu_corrected_err_count, dev_attr_sm_cbu_ecc_corrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_cbu_ecc_uncorrected_err_count", - &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, + &g->ecc.gr.t19x.sm_cbu_uncorrected_err_count, dev_attr_sm_cbu_ecc_uncorrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_l1_data_ecc_corrected_err_count", - &g->gr.t19x.ecc_stats.sm_l1_data_corrected_err_count, + &g->ecc.gr.t19x.sm_l1_data_corrected_err_count, dev_attr_sm_l1_data_ecc_corrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_l1_data_ecc_uncorrected_err_count", - &g->gr.t19x.ecc_stats.sm_l1_data_uncorrected_err_count, + &g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count, dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_icache_ecc_corrected_err_count", - &g->gr.t19x.ecc_stats.sm_icache_corrected_err_count, + &g->ecc.gr.t19x.sm_icache_corrected_err_count, dev_attr_sm_icache_ecc_corrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_icache_ecc_uncorrected_err_count", - &g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count, + &g->ecc.gr.t19x.sm_icache_uncorrected_err_count, dev_attr_sm_icache_ecc_uncorrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "gcc_l15_ecc_corrected_err_count", - &g->gr.t19x.ecc_stats.gcc_l15_corrected_err_count, + &g->ecc.gr.t19x.gcc_l15_corrected_err_count, dev_attr_gcc_l15_ecc_corrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "gcc_l15_ecc_uncorrected_err_count", - &g->gr.t19x.ecc_stats.gcc_l15_uncorrected_err_count, + &g->ecc.gr.t19x.gcc_l15_uncorrected_err_count, dev_attr_gcc_l15_ecc_uncorrected_err_count_array); + error |= gp10b_ecc_stat_create(dev, + 1, + "gpc", + "fecs_ecc_uncorrected_err_count", + &g->ecc.gr.t19x.fecs_uncorrected_err_count, + dev_attr_fecs_ecc_uncorrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + 1, + "gpc", + "fecs_ecc_corrected_err_count", + &g->ecc.gr.t19x.fecs_corrected_err_count, + dev_attr_fecs_ecc_corrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + g->gr.gpc_count, + "gpc", + "gpccs_ecc_uncorrected_err_count", + &g->ecc.gr.t19x.gpccs_uncorrected_err_count, + dev_attr_gpccs_ecc_uncorrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + g->gr.gpc_count, + "gpc", + "gpccs_ecc_corrected_err_count", + &g->ecc.gr.t19x.gpccs_corrected_err_count, + dev_attr_gpccs_ecc_corrected_err_count_array); + if (error) dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); } @@ -217,52 +250,71 @@ static void gr_gv11b_remove_sysfs(struct device *dev) gr_gp10b_ecc_stat_remove(dev, 0, - &g->gr.t19x.ecc_stats.sm_l1_tag_corrected_err_count, + &g->ecc.gr.t19x.sm_l1_tag_corrected_err_count, dev_attr_sm_l1_tag_ecc_corrected_err_count_array); gr_gp10b_ecc_stat_remove(dev, 0, - &g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count, + &g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count, dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); gr_gp10b_ecc_stat_remove(dev, 0, - &g->gr.t19x.ecc_stats.sm_cbu_corrected_err_count, + &g->ecc.gr.t19x.sm_cbu_corrected_err_count, dev_attr_sm_cbu_ecc_corrected_err_count_array); gr_gp10b_ecc_stat_remove(dev, 0, - &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, + &g->ecc.gr.t19x.sm_cbu_uncorrected_err_count, dev_attr_sm_cbu_ecc_uncorrected_err_count_array); gr_gp10b_ecc_stat_remove(dev, 0, - &g->gr.t19x.ecc_stats.sm_l1_data_corrected_err_count, + &g->ecc.gr.t19x.sm_l1_data_corrected_err_count, dev_attr_sm_l1_data_ecc_corrected_err_count_array); gr_gp10b_ecc_stat_remove(dev, 0, - &g->gr.t19x.ecc_stats.sm_l1_data_uncorrected_err_count, + &g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count, dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); gr_gp10b_ecc_stat_remove(dev, 0, - &g->gr.t19x.ecc_stats.sm_icache_corrected_err_count, + &g->ecc.gr.t19x.sm_icache_corrected_err_count, dev_attr_sm_icache_ecc_corrected_err_count_array); gr_gp10b_ecc_stat_remove(dev, 0, - &g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count, + &g->ecc.gr.t19x.sm_icache_uncorrected_err_count, dev_attr_sm_icache_ecc_uncorrected_err_count_array); gr_gp10b_ecc_stat_remove(dev, 0, - &g->gr.t19x.ecc_stats.gcc_l15_corrected_err_count, + &g->ecc.gr.t19x.gcc_l15_corrected_err_count, dev_attr_gcc_l15_ecc_corrected_err_count_array); gr_gp10b_ecc_stat_remove(dev, 0, - &g->gr.t19x.ecc_stats.gcc_l15_uncorrected_err_count, + &g->ecc.gr.t19x.gcc_l15_uncorrected_err_count, dev_attr_gcc_l15_ecc_uncorrected_err_count_array); + gp10b_ecc_stat_remove(dev, + 1, + &g->ecc.gr.t19x.fecs_uncorrected_err_count, + dev_attr_fecs_ecc_uncorrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + 1, + &g->ecc.gr.t19x.fecs_corrected_err_count, + dev_attr_fecs_ecc_corrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + g->gr.gpc_count, + &g->ecc.gr.t19x.gpccs_uncorrected_err_count, + dev_attr_gpccs_ecc_uncorrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + g->gr.gpc_count, + &g->ecc.gr.t19x.gpccs_corrected_err_count, + dev_attr_gpccs_ecc_corrected_err_count_array); } -- cgit v1.2.2 From a5fc5e7131add41f2d9b4bbba2a9d0f318897331 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Mon, 22 May 2017 12:20:40 +0300 Subject: gpu: nvgpu: gv11b: implement userd_pb_get Add gv11b_userd_pb_get() to read the userd get pointer for watchdog. Jira NVGPU-72 Change-Id: Ie1cdb9f84edcecd70b44b6e5a6a8bc554ad5bf49 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1486956 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index df7ab5af..a153de7c 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -202,6 +202,16 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) offset + ram_userd_gp_get_w()); } +static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) +{ + struct nvgpu_mem *userd_mem = &g->fifo.userd; + u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + u32 lo = nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_get_w()); + u32 hi = nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_get_hi_w()); + + return ((u64)hi << 32) | lo; +} + static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; @@ -1412,6 +1422,7 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos; gops->fifo.userd_gp_get = gv11b_userd_gp_get; gops->fifo.userd_gp_put = gv11b_userd_gp_put; + gops->fifo.userd_pb_get = gv11b_userd_pb_get; gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; gops->fifo.resetup_ramfc = NULL; gops->fifo.unbind_channel = channel_gv11b_unbind; -- cgit v1.2.2 From 9b95bb9c4ed56b8bd8028d38d0705181076f04e3 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 22 May 2017 12:29:19 -0600 Subject: gpu: nvgpu: remove duplicate \n from log messages nvgpu_log/info/warn/err() internally add a \n to the end of the message. Hence, callers should not include a \n at the end of the message. Doing so results in duplicate \n being printed, which ends up creating empty log messages. Remove the duplicate \n from all messages. Bug 1928311 Change-Id: I21c141934a125e0cc0cead9fb19fa6502235cf06 Signed-off-by: Stephen Warren Reviewed-on: http://git-master/r/1487233 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index c1398f92..23beca5d 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -81,7 +81,7 @@ static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) == 2) return base * 2; else if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) != 1) { - nvgpu_err(g, "Invalid number of active ltcs: %08x\n", val); + nvgpu_err(g, "Invalid number of active ltcs: %08x", val); } return base; } -- cgit v1.2.2 From 1f78355c5c909e2f678a60420c0abd8ec5adbc98 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 22 Nov 2016 09:09:39 -0800 Subject: gpu: nvgpu: gv11b: add support for sync points In t19x, host1x supports sync point through memory mapped shim layer. So sync-point operations implemented through semphore methods signaling to this sync-point shim layer. Added relevant hal functions for this in fifo hal. JIRA GPUT19X-2 Change-Id: Ia514637d046ba093f4e5afa6cbd06673672fd189 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1258235 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 136 ++++++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 38 +++++++ 2 files changed, 173 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index a153de7c..4b4c97b4 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -14,11 +14,17 @@ */ #include #include +#ifdef CONFIG_TEGRA_GK20A_NVHOST +#include +#include +#endif #include #include #include - +#include +#include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -1411,6 +1417,123 @@ static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, return rc_type; } +#ifdef CONFIG_TEGRA_GK20A_NVHOST +static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf) +{ + struct page **pages; + u32 nr_pages; + u32 i; + int err = 0; + struct gk20a *g = c->g; + + /* + * Add rw mapping for entire syncpt shim for current channel vm + * TODO : This needs to replaced with a new mecahnism where + * only current syncpoint range will be rw and other sync + * points range is read only for current channel vm. Also share + * these mapping accross channels if they share same vm + */ + nr_pages = DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE); + pages = nvgpu_kzalloc(g, sizeof(struct page *) * nr_pages); + for (i = 0; i < nr_pages; i++) + pages[i] = phys_to_page(g->syncpt_unit_base + + PAGE_SIZE * i); + __nvgpu_mem_create_from_pages(g, syncpt_buf, pages, nr_pages); + nvgpu_kfree(g, pages); + syncpt_buf->gpu_va = nvgpu_gmmu_map(c->vm, syncpt_buf, + g->syncpt_unit_size, 0, gk20a_mem_flag_none, + false, APERTURE_SYSMEM); + + if (!syncpt_buf->gpu_va) { + nvgpu_err(c->g, "failed to map syncpt buffer"); + nvgpu_dma_free(c->g, syncpt_buf); + err = -ENOMEM; + } + return err; +} + +static void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, + struct nvgpu_mem *syncpt_buf) +{ + nvgpu_gmmu_unmap(c->vm, syncpt_buf, syncpt_buf->gpu_va); + nvgpu_dma_free(c->g, syncpt_buf); +} + +static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, + struct priv_cmd_entry *cmd, u32 off, + u32 id, u32 thresh, u64 gpu_va_base) +{ + u64 gpu_va = gpu_va_base + + nvhost_syncpt_unit_interface_get_byte_offset(id); + + gk20a_dbg_fn(""); + + off = cmd->off + off; + + /* semaphore_a */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004); + nvgpu_mem_wr32(g, cmd->mem, off++, + (gpu_va >> 32) & 0xff); + /* semaphore_b */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005); + /* offset */ + nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffff); + + /* semaphore_c */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); + /* payload */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x0); + /* semaphore_d */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); + /* operation: acq_geq, switch_en */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12)); +} + +static u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) +{ + return 8; +} + +static void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, + bool wfi_cmd, struct priv_cmd_entry *cmd, + u32 id, u64 gpu_va_base) +{ + u32 off = cmd->off; + u64 gpu_va = gpu_va_base + + nvhost_syncpt_unit_interface_get_byte_offset(id); + + gk20a_dbg_fn(""); + + /* semaphore_a */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004); + nvgpu_mem_wr32(g, cmd->mem, off++, + (gpu_va >> 32) & 0xff); + /* semaphore_b */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005); + /* offset */ + nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffff); + + /* semaphore_c */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); + /* payload */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x0); + /* semaphore_d */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); + + /* operation: release, wfi */ + nvgpu_mem_wr32(g, cmd->mem, off++, + 0x2 | ((wfi_cmd ? 0x0 : 0x1) << 20)); + /* ignored */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0); +} + +static u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) +{ + return 9; +} +#endif /* CONFIG_TEGRA_GK20A_NVHOST */ + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -1446,4 +1569,15 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; gops->fifo.handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0; +#ifdef CONFIG_TEGRA_GK20A_NVHOST + gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf; + gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf; + gops->fifo.add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd; + gops->fifo.get_syncpt_wait_cmd_size = + gv11b_fifo_get_syncpt_wait_cmd_size; + gops->fifo.add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd; + gops->fifo.get_syncpt_incr_cmd_size = + gv11b_fifo_get_syncpt_incr_cmd_size; +#endif + } diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 1cfa2ef2..8733cae9 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -19,6 +19,9 @@ #include #include #include +#ifdef CONFIG_TEGRA_GK20A_NVHOST +#include +#endif #include @@ -37,7 +40,42 @@ static void gr_gv11b_remove_sysfs(struct device *dev); static int gv11b_tegra_probe(struct device *dev) { + int err = 0; struct gk20a_platform *platform = dev_get_drvdata(dev); + struct gk20a *g = platform->g; + struct device_node *np = dev->of_node; + struct device_node *host1x_node; + struct platform_device *host1x_pdev; + const __be32 *host1x_ptr; + +#ifdef CONFIG_TEGRA_GK20A_NVHOST + host1x_ptr = of_get_property(np, "nvidia,host1x", NULL); + if (!host1x_ptr) { + dev_err(dev, "host1x device not available"); + return -ENOSYS; + } + + host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr)); + host1x_pdev = of_find_device_by_node(host1x_node); + if (!host1x_pdev) { + dev_err(dev, "host1x device not available"); + return -ENOSYS; + } + + platform->g->host1x_dev = host1x_pdev; + err = nvhost_syncpt_unit_interface_get_aperture( + g->host1x_dev, + &g->syncpt_unit_base, + &g->syncpt_unit_size); + if (err) { + dev_err(dev, "Failed to get syncpt interface"); + return -ENOSYS; + } + g->syncpt_size = nvhost_syncpt_unit_interface_get_byte_offset(1); + gk20a_dbg_info("syncpt_unit_base %llx syncpt_unit_size %zx size %x\n", + g->syncpt_unit_base, g->syncpt_unit_size, + g->syncpt_size); +#endif platform->bypass_smmu = !device_is_iommuable(dev); platform->disable_bigpage = platform->bypass_smmu; -- cgit v1.2.2 From da02ea50f0704ad0836177c315c9ff87288f0969 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 18 May 2017 14:15:45 -0700 Subject: gpu: nvgpu: gv11b: Don't set net name for pri-silicon In pri-silicon environment netlist names keep on changing. So to keep software backward compatible. do not set net name. So driver will check available firmwares and will pick-up the firmware that matches with current hw netlist major revision. Change-Id: I6083879fb67481be03bad1eaf6a10d0cb6eb7c09 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1485135 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h index e889e9ab..0a046eb4 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h @@ -1,7 +1,7 @@ /* * GV11B Graphics Context * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016 - 2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -21,8 +21,10 @@ #include "gk20a/gr_ctx_gk20a.h" /* production netlist, one and only one from below */ -#define GV11B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A - +/* + * Define netlist for silicon only + * #define GV11B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A +*/ void gv11b_init_gr_ctx(struct gpu_ops *gops); #endif /*__GR_CTX_GV11B_H__*/ -- cgit v1.2.2 From 0181a4e60248c2e3fbb46aa3a33c6154df8b5c5f Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 24 May 2017 12:06:39 -0700 Subject: gpu: nvgpu: gv11b: Update nvlink soc cedits This temp fix will be modified to call proper nvlink module API, once it is available. Change-Id: Id6e9651452a7d7072c285ab00330c85928cdf4d6 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1489068 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 43 +++++++++++++++++++++++++++----------- 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index c3524953..7bf7139e 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -31,21 +31,40 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) { - void __iomem *soc1 = ioremap(0x02b10010, 4096); - void __iomem *soc2 = ioremap(0x02b20010, 4096); - void __iomem *soc3 = ioremap(0x02b30010, 4096); - void __iomem *soc4 = ioremap(0x02b40010, 4096); + void __iomem *soc0 = ioremap(0x01f00010, 4096); //MSS_NVLINK_0_BASE + void __iomem *soc1 = ioremap(0x01f20010, 4096); //MSS_NVLINK_1_BASE + void __iomem *soc2 = ioremap(0x01f40010, 4096); //MSS_NVLINK_2_BASE + void __iomem *soc3 = ioremap(0x01f60010, 4096); //MSS_NVLINK_3_BASE + void __iomem *soc4 = ioremap(0x01f80010, 4096); //MSS_NVLINK_4_BASE + u32 val; + /* TODO : replace this code with proper nvlink API */ nvgpu_info(g, "init nvlink soc credits"); - writel_relaxed(0x14050000, soc1); - writel_relaxed(0x08020000, soc1 + 4); - writel_relaxed(0x14050000, soc2); - writel_relaxed(0x08020000, soc2 + 4); - writel_relaxed(0x14050000, soc3); - writel_relaxed(0x08020000, soc3 + 4); - writel_relaxed(0x14050000, soc4); - writel_relaxed(0x08020000, soc4 + 4); + val = readl_relaxed(soc0); + writel_relaxed(val, soc0); + val = readl_relaxed(soc0 + 4); + writel_relaxed(val, soc0 + 4); + + val = readl_relaxed(soc1); + writel_relaxed(val, soc1); + val = readl_relaxed(soc1 + 4); + writel_relaxed(val, soc1 + 4); + + val = readl_relaxed(soc2); + writel_relaxed(val, soc2); + val = readl_relaxed(soc2 + 4); + writel_relaxed(val, soc2 + 4); + + val = readl_relaxed(soc3); + writel_relaxed(val, soc3); + val = readl_relaxed(soc3 + 4); + writel_relaxed(val, soc3 + 4); + + val = readl_relaxed(soc4); + writel_relaxed(val, soc4); + val = readl_relaxed(soc4 + 4); + writel_relaxed(val, soc4 + 4); } -- cgit v1.2.2 From 77199c0225457c48acb2dca89d0bf93d05b33231 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 3 May 2017 13:55:27 -0700 Subject: gpu: nvgpu: gv11b: init enable_exceptions gr ops Enable FE, MEMFMT, DS and GPC exceptions only. Make sure corresponding HWW_ESR are enabled too. JIRA GPUT19X-75 Change-Id: Icf47b7e531dd72b59cbc6ac54b5902187f703d61 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1474859 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 24 +++++++++++++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 28 ++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 8b4471ca..a9f1183e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -284,6 +284,29 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, } +static void gr_gv11b_enable_exceptions(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + u32 reg_val; + + /* + * clear exceptions : + * other than SM : hww_esr are reset in *enable_hww_excetpions* + * SM : cleared in *set_hww_esr_report_mask* + */ + + /* enable exceptions */ + gk20a_writel(g, gr_exception2_en_r(), 0x0); /* BE not enabled */ + gk20a_writel(g, gr_exception1_en_r(), (1 << gr->gpc_count) - 1); + + reg_val = gr_exception_en_fe_enabled_f() | + gr_exception_en_memfmt_enabled_f() | + gr_exception_en_ds_enabled_f() | + gr_exception_en_gpc_enabled_f(); + gk20a_writel(g, gr_exception_en_r(), reg_val); + +} + static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event, struct channel_gk20a *fault_ch, u32 *hww_global_esr) @@ -2375,6 +2398,7 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.handle_gcc_exception = gr_gv11b_handle_gcc_exception; gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; + gops->gr.enable_exceptions = gr_gv11b_enable_exceptions; gops->gr.mask_hww_warp_esr = gv11b_mask_hww_warp_esr; gops->gr.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 9917f86d..2d5afb29 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -194,6 +194,34 @@ static inline u32 gr_exception_en_fe_m(void) { return 0x1 << 0; } +static inline u32 gr_exception_en_fe_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_exception_en_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_en_gpc_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 gr_exception_en_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_en_memfmt_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_exception_en_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception_en_ds_enabled_f(void) +{ + return 0x10; +} static inline u32 gr_exception1_en_r(void) { return 0x00400130; -- cgit v1.2.2 From b28e43f62bc600b0505d66d6d00d4a6ea6591744 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 22 May 2017 14:53:37 -0700 Subject: gpu: nvgpu: gv11b: fifo ops get_mmu_fault_info set to NULL mmu fault h/w registers are no longer inside fifo module JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I7d166f0e80cee7c040289b13a053ff2cdb7d8727 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1487327 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 4b4c97b4..38a402dc 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1554,6 +1554,7 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; gops->fifo.trigger_mmu_fault = NULL; + gops->fifo.get_mmu_fault_info = NULL; gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; gops->fifo.dump_eng_status = gv11b_dump_eng_status; gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; -- cgit v1.2.2 From d8d81ebda9af98fa0d9ff3b31d417867efcc4b2b Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 30 May 2017 22:58:42 -0700 Subject: gpu: nvgpu: gv11b: update regops whitelist Update regops whitelist to HW CL#38424879 JIRA GPUT19x-116 Change-Id: I4dd7b54cf04a5e298c191dcb525e6d9d8c591fb0 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1492710 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/regops_gv11b.c | 926 +++++++++++++++++++++++++-------- 1 file changed, 708 insertions(+), 218 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c index 8c5305b3..75923b6a 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c @@ -32,7 +32,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00009400, 1}, { 0x00009410, 1}, { 0x00009480, 1}, - { 0x00020200, 24}, + { 0x00020200, 32}, { 0x00021c04, 2}, { 0x00021c14, 3}, { 0x00021c24, 71}, @@ -50,8 +50,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00084b5c, 1}, { 0x000870a8, 1}, { 0x000884e0, 1}, - { 0x000884f4, 1}, - { 0x0008e00c, 1}, { 0x00100c18, 3}, { 0x00100c84, 1}, { 0x0010a0a8, 1}, @@ -94,132 +92,132 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0017e750, 1}, { 0x00180040, 41}, { 0x001800ec, 1}, - { 0x001800f8, 4}, - { 0x0018010c, 1}, + { 0x001800f8, 7}, + { 0x00180120, 2}, { 0x00180240, 41}, { 0x001802ec, 1}, - { 0x001802f8, 4}, - { 0x0018030c, 1}, + { 0x001802f8, 7}, + { 0x00180320, 2}, { 0x00180440, 41}, { 0x001804ec, 1}, - { 0x001804f8, 4}, - { 0x0018050c, 1}, + { 0x001804f8, 7}, + { 0x00180520, 2}, { 0x00180640, 41}, { 0x001806ec, 1}, - { 0x001806f8, 4}, - { 0x0018070c, 1}, + { 0x001806f8, 7}, + { 0x00180720, 2}, { 0x00180840, 41}, { 0x001808ec, 1}, - { 0x001808f8, 4}, - { 0x0018090c, 1}, + { 0x001808f8, 7}, + { 0x00180920, 2}, { 0x00180a40, 41}, { 0x00180aec, 1}, - { 0x00180af8, 4}, - { 0x00180b0c, 1}, + { 0x00180af8, 7}, + { 0x00180b20, 2}, { 0x00180c40, 41}, { 0x00180cec, 1}, - { 0x00180cf8, 4}, - { 0x00180d0c, 1}, + { 0x00180cf8, 7}, + { 0x00180d20, 2}, { 0x00180e40, 41}, { 0x00180eec, 1}, - { 0x00180ef8, 4}, - { 0x00180f0c, 1}, + { 0x00180ef8, 7}, + { 0x00180f20, 2}, { 0x00181040, 41}, { 0x001810ec, 1}, - { 0x001810f8, 4}, - { 0x0018110c, 1}, + { 0x001810f8, 7}, + { 0x00181120, 2}, { 0x00181240, 41}, { 0x001812ec, 1}, - { 0x001812f8, 4}, - { 0x0018130c, 1}, + { 0x001812f8, 7}, + { 0x00181320, 2}, { 0x00181440, 41}, { 0x001814ec, 1}, - { 0x001814f8, 4}, - { 0x0018150c, 1}, + { 0x001814f8, 7}, + { 0x00181520, 2}, { 0x00181640, 41}, { 0x001816ec, 1}, - { 0x001816f8, 4}, - { 0x0018170c, 1}, + { 0x001816f8, 7}, + { 0x00181720, 2}, { 0x00181840, 41}, { 0x001818ec, 1}, - { 0x001818f8, 4}, - { 0x0018190c, 1}, + { 0x001818f8, 7}, + { 0x00181920, 2}, { 0x00181a40, 41}, { 0x00181aec, 1}, - { 0x00181af8, 4}, - { 0x00181b0c, 1}, + { 0x00181af8, 7}, + { 0x00181b20, 2}, { 0x00181c40, 41}, { 0x00181cec, 1}, - { 0x00181cf8, 4}, - { 0x00181d0c, 1}, + { 0x00181cf8, 7}, + { 0x00181d20, 2}, { 0x00181e40, 41}, { 0x00181eec, 1}, - { 0x00181ef8, 4}, - { 0x00181f0c, 1}, + { 0x00181ef8, 7}, + { 0x00181f20, 2}, { 0x00182040, 41}, { 0x001820ec, 1}, - { 0x001820f8, 4}, - { 0x0018210c, 1}, + { 0x001820f8, 7}, + { 0x00182120, 2}, { 0x00182240, 41}, { 0x001822ec, 1}, - { 0x001822f8, 4}, - { 0x0018230c, 1}, + { 0x001822f8, 7}, + { 0x00182320, 2}, { 0x00182440, 41}, { 0x001824ec, 1}, - { 0x001824f8, 4}, - { 0x0018250c, 1}, + { 0x001824f8, 7}, + { 0x00182520, 2}, { 0x00182640, 41}, { 0x001826ec, 1}, - { 0x001826f8, 4}, - { 0x0018270c, 1}, + { 0x001826f8, 7}, + { 0x00182720, 2}, { 0x00182840, 41}, { 0x001828ec, 1}, - { 0x001828f8, 4}, - { 0x0018290c, 1}, + { 0x001828f8, 7}, + { 0x00182920, 2}, { 0x00182a40, 41}, { 0x00182aec, 1}, - { 0x00182af8, 4}, - { 0x00182b0c, 1}, + { 0x00182af8, 7}, + { 0x00182b20, 2}, { 0x00182c40, 41}, { 0x00182cec, 1}, - { 0x00182cf8, 4}, - { 0x00182d0c, 1}, + { 0x00182cf8, 7}, + { 0x00182d20, 2}, { 0x00182e40, 41}, { 0x00182eec, 1}, - { 0x00182ef8, 4}, - { 0x00182f0c, 1}, + { 0x00182ef8, 7}, + { 0x00182f20, 2}, { 0x00183040, 41}, { 0x001830ec, 1}, - { 0x001830f8, 4}, - { 0x0018310c, 1}, + { 0x001830f8, 7}, + { 0x00183120, 2}, { 0x00183240, 41}, { 0x001832ec, 1}, - { 0x001832f8, 4}, - { 0x0018330c, 1}, + { 0x001832f8, 7}, + { 0x00183320, 2}, { 0x00183440, 41}, { 0x001834ec, 1}, - { 0x001834f8, 4}, - { 0x0018350c, 1}, + { 0x001834f8, 7}, + { 0x00183520, 2}, { 0x00183640, 41}, { 0x001836ec, 1}, - { 0x001836f8, 4}, - { 0x0018370c, 1}, + { 0x001836f8, 7}, + { 0x00183720, 2}, { 0x00183840, 41}, { 0x001838ec, 1}, - { 0x001838f8, 4}, - { 0x0018390c, 1}, + { 0x001838f8, 7}, + { 0x00183920, 2}, { 0x00183a40, 41}, { 0x00183aec, 1}, - { 0x00183af8, 4}, - { 0x00183b0c, 1}, + { 0x00183af8, 7}, + { 0x00183b20, 2}, { 0x00183c40, 41}, { 0x00183cec, 1}, - { 0x00183cf8, 4}, - { 0x00183d0c, 1}, + { 0x00183cf8, 7}, + { 0x00183d20, 2}, { 0x00183e40, 41}, { 0x00183eec, 1}, - { 0x00183ef8, 4}, - { 0x00183f0c, 1}, + { 0x00183ef8, 7}, + { 0x00183f20, 2}, { 0x001c80a8, 1}, { 0x001c9100, 1}, { 0x001cc0a8, 1}, @@ -228,274 +226,272 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x001d1100, 1}, { 0x00200040, 41}, { 0x002000ec, 1}, - { 0x002000f8, 4}, - { 0x0020010c, 1}, + { 0x002000f8, 7}, + { 0x00200120, 2}, { 0x00200240, 41}, { 0x002002ec, 1}, - { 0x002002f8, 4}, - { 0x0020030c, 1}, + { 0x002002f8, 7}, + { 0x00200320, 2}, { 0x00200440, 41}, { 0x002004ec, 1}, - { 0x002004f8, 4}, - { 0x0020050c, 1}, + { 0x002004f8, 7}, + { 0x00200520, 2}, { 0x00200640, 41}, { 0x002006ec, 1}, - { 0x002006f8, 4}, - { 0x0020070c, 1}, + { 0x002006f8, 7}, + { 0x00200720, 2}, { 0x00200840, 41}, { 0x002008ec, 1}, - { 0x002008f8, 4}, - { 0x0020090c, 1}, + { 0x002008f8, 7}, + { 0x00200920, 2}, { 0x00200a40, 41}, { 0x00200aec, 1}, - { 0x00200af8, 4}, - { 0x00200b0c, 1}, + { 0x00200af8, 7}, + { 0x00200b20, 2}, { 0x00200c40, 41}, { 0x00200cec, 1}, - { 0x00200cf8, 4}, - { 0x00200d0c, 1}, + { 0x00200cf8, 7}, + { 0x00200d20, 2}, { 0x00200e40, 41}, { 0x00200eec, 1}, - { 0x00200ef8, 4}, - { 0x00200f0c, 1}, + { 0x00200ef8, 7}, + { 0x00200f20, 2}, { 0x00201040, 41}, { 0x002010ec, 1}, - { 0x002010f8, 4}, - { 0x0020110c, 1}, + { 0x002010f8, 7}, + { 0x00201120, 2}, { 0x00201240, 41}, { 0x002012ec, 1}, - { 0x002012f8, 4}, - { 0x0020130c, 1}, + { 0x002012f8, 7}, + { 0x00201320, 2}, { 0x00201440, 41}, { 0x002014ec, 1}, - { 0x002014f8, 4}, - { 0x0020150c, 1}, + { 0x002014f8, 7}, + { 0x00201520, 2}, { 0x00201640, 41}, { 0x002016ec, 1}, - { 0x002016f8, 4}, - { 0x0020170c, 1}, + { 0x002016f8, 7}, + { 0x00201720, 2}, { 0x00201840, 41}, { 0x002018ec, 1}, - { 0x002018f8, 4}, - { 0x0020190c, 1}, + { 0x002018f8, 7}, + { 0x00201920, 2}, { 0x00201a40, 41}, { 0x00201aec, 1}, - { 0x00201af8, 4}, - { 0x00201b0c, 1}, + { 0x00201af8, 7}, + { 0x00201b20, 2}, { 0x00201c40, 41}, { 0x00201cec, 1}, - { 0x00201cf8, 4}, - { 0x00201d0c, 1}, + { 0x00201cf8, 7}, + { 0x00201d20, 2}, { 0x00201e40, 41}, { 0x00201eec, 1}, - { 0x00201ef8, 4}, - { 0x00201f0c, 1}, + { 0x00201ef8, 7}, + { 0x00201f20, 2}, { 0x00202040, 41}, { 0x002020ec, 1}, - { 0x002020f8, 4}, - { 0x0020210c, 1}, + { 0x002020f8, 7}, + { 0x00202120, 2}, { 0x00202240, 41}, { 0x002022ec, 1}, - { 0x002022f8, 4}, - { 0x0020230c, 1}, + { 0x002022f8, 7}, + { 0x00202320, 2}, { 0x00202440, 41}, { 0x002024ec, 1}, - { 0x002024f8, 4}, - { 0x0020250c, 1}, + { 0x002024f8, 7}, + { 0x00202520, 2}, { 0x00202640, 41}, { 0x002026ec, 1}, - { 0x002026f8, 4}, - { 0x0020270c, 1}, + { 0x002026f8, 7}, + { 0x00202720, 2}, { 0x00202840, 41}, { 0x002028ec, 1}, - { 0x002028f8, 4}, - { 0x0020290c, 1}, + { 0x002028f8, 7}, + { 0x00202920, 2}, { 0x00202a40, 41}, { 0x00202aec, 1}, - { 0x00202af8, 4}, - { 0x00202b0c, 1}, + { 0x00202af8, 7}, + { 0x00202b20, 2}, { 0x00202c40, 41}, { 0x00202cec, 1}, - { 0x00202cf8, 4}, - { 0x00202d0c, 1}, + { 0x00202cf8, 7}, + { 0x00202d20, 2}, { 0x00202e40, 41}, { 0x00202eec, 1}, - { 0x00202ef8, 4}, - { 0x00202f0c, 1}, + { 0x00202ef8, 7}, + { 0x00202f20, 2}, { 0x00203040, 41}, { 0x002030ec, 1}, - { 0x002030f8, 4}, - { 0x0020310c, 1}, + { 0x002030f8, 7}, + { 0x00203120, 2}, { 0x00203240, 41}, { 0x002032ec, 1}, - { 0x002032f8, 4}, - { 0x0020330c, 1}, + { 0x002032f8, 7}, + { 0x00203320, 2}, { 0x00203440, 41}, { 0x002034ec, 1}, - { 0x002034f8, 4}, - { 0x0020350c, 1}, + { 0x002034f8, 7}, + { 0x00203520, 2}, { 0x00203640, 41}, { 0x002036ec, 1}, - { 0x002036f8, 4}, - { 0x0020370c, 1}, + { 0x002036f8, 7}, + { 0x00203720, 2}, { 0x00203840, 41}, { 0x002038ec, 1}, - { 0x002038f8, 4}, - { 0x0020390c, 1}, + { 0x002038f8, 7}, + { 0x00203920, 2}, { 0x00203a40, 41}, { 0x00203aec, 1}, - { 0x00203af8, 4}, - { 0x00203b0c, 1}, + { 0x00203af8, 7}, + { 0x00203b20, 2}, { 0x00203c40, 41}, { 0x00203cec, 1}, - { 0x00203cf8, 4}, - { 0x00203d0c, 1}, + { 0x00203cf8, 7}, + { 0x00203d20, 2}, { 0x00203e40, 41}, { 0x00203eec, 1}, - { 0x00203ef8, 4}, - { 0x00203f0c, 1}, + { 0x00203ef8, 7}, + { 0x00203f20, 2}, { 0x00240040, 41}, { 0x002400ec, 1}, - { 0x002400f8, 4}, - { 0x0024010c, 1}, + { 0x002400f8, 7}, + { 0x00240120, 2}, { 0x00240240, 41}, { 0x002402ec, 1}, - { 0x002402f8, 4}, - { 0x0024030c, 1}, + { 0x002402f8, 7}, + { 0x00240320, 2}, { 0x00240440, 41}, { 0x002404ec, 1}, - { 0x002404f8, 4}, - { 0x0024050c, 1}, + { 0x002404f8, 7}, + { 0x00240520, 2}, { 0x00240640, 41}, { 0x002406ec, 1}, - { 0x002406f8, 4}, - { 0x0024070c, 1}, + { 0x002406f8, 7}, + { 0x00240720, 2}, { 0x00240840, 41}, { 0x002408ec, 1}, - { 0x002408f8, 4}, - { 0x0024090c, 1}, + { 0x002408f8, 7}, + { 0x00240920, 2}, { 0x00240a40, 41}, { 0x00240aec, 1}, - { 0x00240af8, 4}, - { 0x00240b0c, 1}, + { 0x00240af8, 7}, + { 0x00240b20, 2}, { 0x00240c40, 41}, { 0x00240cec, 1}, - { 0x00240cf8, 4}, - { 0x00240d0c, 1}, + { 0x00240cf8, 7}, + { 0x00240d20, 2}, { 0x00240e40, 41}, { 0x00240eec, 1}, - { 0x00240ef8, 4}, - { 0x00240f0c, 1}, + { 0x00240ef8, 7}, + { 0x00240f20, 2}, { 0x00241040, 41}, { 0x002410ec, 1}, - { 0x002410f8, 4}, - { 0x0024110c, 1}, + { 0x002410f8, 7}, + { 0x00241120, 2}, { 0x00241240, 41}, { 0x002412ec, 1}, - { 0x002412f8, 4}, - { 0x0024130c, 1}, + { 0x002412f8, 7}, + { 0x00241320, 2}, { 0x00241440, 41}, { 0x002414ec, 1}, - { 0x002414f8, 4}, - { 0x0024150c, 1}, + { 0x002414f8, 7}, + { 0x00241520, 2}, { 0x00241640, 41}, { 0x002416ec, 1}, - { 0x002416f8, 4}, - { 0x0024170c, 1}, + { 0x002416f8, 7}, + { 0x00241720, 2}, { 0x00241840, 41}, { 0x002418ec, 1}, - { 0x002418f8, 4}, - { 0x0024190c, 1}, + { 0x002418f8, 7}, + { 0x00241920, 2}, { 0x00241a40, 41}, { 0x00241aec, 1}, - { 0x00241af8, 4}, - { 0x00241b0c, 1}, + { 0x00241af8, 7}, + { 0x00241b20, 2}, { 0x00241c40, 41}, { 0x00241cec, 1}, - { 0x00241cf8, 4}, - { 0x00241d0c, 1}, + { 0x00241cf8, 7}, + { 0x00241d20, 2}, { 0x00241e40, 41}, { 0x00241eec, 1}, - { 0x00241ef8, 4}, - { 0x00241f0c, 1}, + { 0x00241ef8, 7}, + { 0x00241f20, 2}, { 0x00242040, 41}, { 0x002420ec, 1}, - { 0x002420f8, 4}, - { 0x0024210c, 1}, + { 0x002420f8, 7}, + { 0x00242120, 2}, { 0x00242240, 41}, { 0x002422ec, 1}, - { 0x002422f8, 4}, - { 0x0024230c, 1}, + { 0x002422f8, 7}, + { 0x00242320, 2}, { 0x00242440, 41}, { 0x002424ec, 1}, - { 0x002424f8, 4}, - { 0x0024250c, 1}, + { 0x002424f8, 7}, + { 0x00242520, 2}, { 0x00242640, 41}, { 0x002426ec, 1}, - { 0x002426f8, 4}, - { 0x0024270c, 1}, + { 0x002426f8, 7}, + { 0x00242720, 2}, { 0x00242840, 41}, { 0x002428ec, 1}, - { 0x002428f8, 4}, - { 0x0024290c, 1}, + { 0x002428f8, 7}, + { 0x00242920, 2}, { 0x00242a40, 41}, { 0x00242aec, 1}, - { 0x00242af8, 4}, - { 0x00242b0c, 1}, + { 0x00242af8, 7}, + { 0x00242b20, 2}, { 0x00242c40, 41}, { 0x00242cec, 1}, - { 0x00242cf8, 4}, - { 0x00242d0c, 1}, + { 0x00242cf8, 7}, + { 0x00242d20, 2}, { 0x00242e40, 41}, { 0x00242eec, 1}, - { 0x00242ef8, 4}, - { 0x00242f0c, 1}, + { 0x00242ef8, 7}, + { 0x00242f20, 2}, { 0x00243040, 41}, { 0x002430ec, 1}, - { 0x002430f8, 4}, - { 0x0024310c, 1}, + { 0x002430f8, 7}, + { 0x00243120, 2}, { 0x00243240, 41}, { 0x002432ec, 1}, - { 0x002432f8, 4}, - { 0x0024330c, 1}, + { 0x002432f8, 7}, + { 0x00243320, 2}, { 0x00243440, 41}, { 0x002434ec, 1}, - { 0x002434f8, 4}, - { 0x0024350c, 1}, + { 0x002434f8, 7}, + { 0x00243520, 2}, { 0x00243640, 41}, { 0x002436ec, 1}, - { 0x002436f8, 4}, - { 0x0024370c, 1}, + { 0x002436f8, 7}, + { 0x00243720, 2}, { 0x00243840, 41}, { 0x002438ec, 1}, - { 0x002438f8, 4}, - { 0x0024390c, 1}, + { 0x002438f8, 7}, + { 0x00243920, 2}, { 0x00243a40, 41}, { 0x00243aec, 1}, - { 0x00243af8, 4}, - { 0x00243b0c, 1}, + { 0x00243af8, 7}, + { 0x00243b20, 2}, { 0x00243c40, 41}, { 0x00243cec, 1}, - { 0x00243cf8, 4}, - { 0x00243d0c, 1}, + { 0x00243cf8, 7}, + { 0x00243d20, 2}, { 0x00243e40, 41}, { 0x00243eec, 1}, - { 0x00243ef8, 4}, - { 0x00243f0c, 1}, + { 0x00243ef8, 7}, + { 0x00243f20, 2}, { 0x00244000, 1}, { 0x00244008, 1}, - { 0x00244010, 3}, + { 0x00244010, 2}, { 0x00246000, 1}, { 0x00246008, 1}, - { 0x00246010, 3}, + { 0x00246010, 2}, { 0x00248000, 1}, { 0x00248008, 1}, - { 0x00248010, 3}, + { 0x00248010, 2}, { 0x0024a000, 1}, { 0x0024a008, 1}, - { 0x0024a010, 3}, - { 0x0024a020, 3}, - { 0x0024a030, 3}, + { 0x0024a010, 11}, { 0x0024a040, 3}, { 0x0024a050, 3}, { 0x0024a060, 4}, @@ -503,7 +499,350 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0024a094, 3}, { 0x0024a0a4, 1}, { 0x0024a100, 6}, - { 0x0024a124, 1}, + { 0x00250040, 25}, + { 0x002500c8, 7}, + { 0x002500ec, 1}, + { 0x002500f8, 7}, + { 0x00250120, 2}, + { 0x00250240, 25}, + { 0x002502c8, 7}, + { 0x002502ec, 1}, + { 0x002502f8, 7}, + { 0x00250320, 2}, + { 0x00250840, 25}, + { 0x002508c8, 7}, + { 0x002508ec, 1}, + { 0x002508f8, 7}, + { 0x00250920, 2}, + { 0x00250a40, 25}, + { 0x00250ac8, 7}, + { 0x00250aec, 1}, + { 0x00250af8, 7}, + { 0x00250b20, 2}, + { 0x00251800, 3}, + { 0x00251810, 2}, + { 0x00251a00, 3}, + { 0x00251a10, 2}, + { 0x00278040, 25}, + { 0x002780c8, 7}, + { 0x002780ec, 1}, + { 0x002780f8, 7}, + { 0x00278120, 2}, + { 0x00278240, 25}, + { 0x002782c8, 7}, + { 0x002782ec, 1}, + { 0x002782f8, 7}, + { 0x00278320, 2}, + { 0x00278440, 25}, + { 0x002784c8, 7}, + { 0x002784ec, 1}, + { 0x002784f8, 7}, + { 0x00278520, 2}, + { 0x00278640, 25}, + { 0x002786c8, 7}, + { 0x002786ec, 1}, + { 0x002786f8, 7}, + { 0x00278720, 2}, + { 0x00278840, 25}, + { 0x002788c8, 7}, + { 0x002788ec, 1}, + { 0x002788f8, 7}, + { 0x00278920, 2}, + { 0x00278a40, 25}, + { 0x00278ac8, 7}, + { 0x00278aec, 1}, + { 0x00278af8, 7}, + { 0x00278b20, 2}, + { 0x00278c40, 25}, + { 0x00278cc8, 7}, + { 0x00278cec, 1}, + { 0x00278cf8, 7}, + { 0x00278d20, 2}, + { 0x00278e40, 25}, + { 0x00278ec8, 7}, + { 0x00278eec, 1}, + { 0x00278ef8, 7}, + { 0x00278f20, 2}, + { 0x00279040, 25}, + { 0x002790c8, 7}, + { 0x002790ec, 1}, + { 0x002790f8, 7}, + { 0x00279120, 2}, + { 0x00279240, 25}, + { 0x002792c8, 7}, + { 0x002792ec, 1}, + { 0x002792f8, 7}, + { 0x00279320, 2}, + { 0x00279440, 25}, + { 0x002794c8, 7}, + { 0x002794ec, 1}, + { 0x002794f8, 7}, + { 0x00279520, 2}, + { 0x00279640, 25}, + { 0x002796c8, 7}, + { 0x002796ec, 1}, + { 0x002796f8, 7}, + { 0x00279720, 2}, + { 0x00279840, 25}, + { 0x002798c8, 7}, + { 0x002798ec, 1}, + { 0x002798f8, 7}, + { 0x00279920, 2}, + { 0x00279a40, 25}, + { 0x00279ac8, 7}, + { 0x00279aec, 1}, + { 0x00279af8, 7}, + { 0x00279b20, 2}, + { 0x00279c40, 25}, + { 0x00279cc8, 7}, + { 0x00279cec, 1}, + { 0x00279cf8, 7}, + { 0x00279d20, 2}, + { 0x00279e40, 25}, + { 0x00279ec8, 7}, + { 0x00279eec, 1}, + { 0x00279ef8, 7}, + { 0x00279f20, 2}, + { 0x0027a040, 25}, + { 0x0027a0c8, 7}, + { 0x0027a0ec, 1}, + { 0x0027a0f8, 7}, + { 0x0027a120, 2}, + { 0x0027a240, 25}, + { 0x0027a2c8, 7}, + { 0x0027a2ec, 1}, + { 0x0027a2f8, 7}, + { 0x0027a320, 2}, + { 0x0027a440, 25}, + { 0x0027a4c8, 7}, + { 0x0027a4ec, 1}, + { 0x0027a4f8, 7}, + { 0x0027a520, 2}, + { 0x0027a640, 25}, + { 0x0027a6c8, 7}, + { 0x0027a6ec, 1}, + { 0x0027a6f8, 7}, + { 0x0027a720, 2}, + { 0x0027a840, 25}, + { 0x0027a8c8, 7}, + { 0x0027a8ec, 1}, + { 0x0027a8f8, 7}, + { 0x0027a920, 2}, + { 0x0027aa40, 25}, + { 0x0027aac8, 7}, + { 0x0027aaec, 1}, + { 0x0027aaf8, 7}, + { 0x0027ab20, 2}, + { 0x0027ac40, 25}, + { 0x0027acc8, 7}, + { 0x0027acec, 1}, + { 0x0027acf8, 7}, + { 0x0027ad20, 2}, + { 0x0027ae40, 25}, + { 0x0027aec8, 7}, + { 0x0027aeec, 1}, + { 0x0027aef8, 7}, + { 0x0027af20, 2}, + { 0x0027b040, 25}, + { 0x0027b0c8, 7}, + { 0x0027b0ec, 1}, + { 0x0027b0f8, 7}, + { 0x0027b120, 2}, + { 0x0027b240, 25}, + { 0x0027b2c8, 7}, + { 0x0027b2ec, 1}, + { 0x0027b2f8, 7}, + { 0x0027b320, 2}, + { 0x0027b440, 25}, + { 0x0027b4c8, 7}, + { 0x0027b4ec, 1}, + { 0x0027b4f8, 7}, + { 0x0027b520, 2}, + { 0x0027b640, 25}, + { 0x0027b6c8, 7}, + { 0x0027b6ec, 1}, + { 0x0027b6f8, 7}, + { 0x0027b720, 2}, + { 0x0027b840, 25}, + { 0x0027b8c8, 7}, + { 0x0027b8ec, 1}, + { 0x0027b8f8, 7}, + { 0x0027b920, 2}, + { 0x0027ba40, 25}, + { 0x0027bac8, 7}, + { 0x0027baec, 1}, + { 0x0027baf8, 7}, + { 0x0027bb20, 2}, + { 0x0027bc40, 25}, + { 0x0027bcc8, 7}, + { 0x0027bcec, 1}, + { 0x0027bcf8, 7}, + { 0x0027bd20, 2}, + { 0x0027be40, 25}, + { 0x0027bec8, 7}, + { 0x0027beec, 1}, + { 0x0027bef8, 7}, + { 0x0027bf20, 2}, + { 0x0027c040, 25}, + { 0x0027c0c8, 7}, + { 0x0027c0ec, 1}, + { 0x0027c0f8, 7}, + { 0x0027c120, 2}, + { 0x0027c240, 25}, + { 0x0027c2c8, 7}, + { 0x0027c2ec, 1}, + { 0x0027c2f8, 7}, + { 0x0027c320, 2}, + { 0x0027c440, 25}, + { 0x0027c4c8, 7}, + { 0x0027c4ec, 1}, + { 0x0027c4f8, 7}, + { 0x0027c520, 2}, + { 0x0027c640, 25}, + { 0x0027c6c8, 7}, + { 0x0027c6ec, 1}, + { 0x0027c6f8, 7}, + { 0x0027c720, 2}, + { 0x0027c840, 25}, + { 0x0027c8c8, 7}, + { 0x0027c8ec, 1}, + { 0x0027c8f8, 7}, + { 0x0027c920, 2}, + { 0x0027ca40, 25}, + { 0x0027cac8, 7}, + { 0x0027caec, 1}, + { 0x0027caf8, 7}, + { 0x0027cb20, 2}, + { 0x0027cc40, 25}, + { 0x0027ccc8, 7}, + { 0x0027ccec, 1}, + { 0x0027ccf8, 7}, + { 0x0027cd20, 2}, + { 0x0027ce40, 25}, + { 0x0027cec8, 7}, + { 0x0027ceec, 1}, + { 0x0027cef8, 7}, + { 0x0027cf20, 2}, + { 0x0027d040, 25}, + { 0x0027d0c8, 7}, + { 0x0027d0ec, 1}, + { 0x0027d0f8, 7}, + { 0x0027d120, 2}, + { 0x0027d240, 25}, + { 0x0027d2c8, 7}, + { 0x0027d2ec, 1}, + { 0x0027d2f8, 7}, + { 0x0027d320, 2}, + { 0x0027d440, 25}, + { 0x0027d4c8, 7}, + { 0x0027d4ec, 1}, + { 0x0027d4f8, 7}, + { 0x0027d520, 2}, + { 0x0027d640, 25}, + { 0x0027d6c8, 7}, + { 0x0027d6ec, 1}, + { 0x0027d6f8, 7}, + { 0x0027d720, 2}, + { 0x0027d840, 25}, + { 0x0027d8c8, 7}, + { 0x0027d8ec, 1}, + { 0x0027d8f8, 7}, + { 0x0027d920, 2}, + { 0x0027da40, 25}, + { 0x0027dac8, 7}, + { 0x0027daec, 1}, + { 0x0027daf8, 7}, + { 0x0027db20, 2}, + { 0x0027dc40, 25}, + { 0x0027dcc8, 7}, + { 0x0027dcec, 1}, + { 0x0027dcf8, 7}, + { 0x0027dd20, 2}, + { 0x0027de40, 25}, + { 0x0027dec8, 7}, + { 0x0027deec, 1}, + { 0x0027def8, 7}, + { 0x0027df20, 2}, + { 0x0027e040, 25}, + { 0x0027e0c8, 7}, + { 0x0027e0ec, 1}, + { 0x0027e0f8, 7}, + { 0x0027e120, 2}, + { 0x0027e240, 25}, + { 0x0027e2c8, 7}, + { 0x0027e2ec, 1}, + { 0x0027e2f8, 7}, + { 0x0027e320, 2}, + { 0x0027e440, 25}, + { 0x0027e4c8, 7}, + { 0x0027e4ec, 1}, + { 0x0027e4f8, 7}, + { 0x0027e520, 2}, + { 0x0027e640, 25}, + { 0x0027e6c8, 7}, + { 0x0027e6ec, 1}, + { 0x0027e6f8, 7}, + { 0x0027e720, 2}, + { 0x0027e840, 25}, + { 0x0027e8c8, 7}, + { 0x0027e8ec, 1}, + { 0x0027e8f8, 7}, + { 0x0027e920, 2}, + { 0x0027ea40, 25}, + { 0x0027eac8, 7}, + { 0x0027eaec, 1}, + { 0x0027eaf8, 7}, + { 0x0027eb20, 2}, + { 0x0027ec40, 25}, + { 0x0027ecc8, 7}, + { 0x0027ecec, 1}, + { 0x0027ecf8, 7}, + { 0x0027ed20, 2}, + { 0x0027ee40, 25}, + { 0x0027eec8, 7}, + { 0x0027eeec, 1}, + { 0x0027eef8, 7}, + { 0x0027ef20, 2}, + { 0x0027f040, 25}, + { 0x0027f0c8, 7}, + { 0x0027f0ec, 1}, + { 0x0027f0f8, 7}, + { 0x0027f120, 2}, + { 0x0027f240, 25}, + { 0x0027f2c8, 7}, + { 0x0027f2ec, 1}, + { 0x0027f2f8, 7}, + { 0x0027f320, 2}, + { 0x0027f440, 25}, + { 0x0027f4c8, 7}, + { 0x0027f4ec, 1}, + { 0x0027f4f8, 7}, + { 0x0027f520, 2}, + { 0x0027f640, 25}, + { 0x0027f6c8, 7}, + { 0x0027f6ec, 1}, + { 0x0027f6f8, 7}, + { 0x0027f720, 2}, + { 0x0027f840, 25}, + { 0x0027f8c8, 7}, + { 0x0027f8ec, 1}, + { 0x0027f8f8, 7}, + { 0x0027f920, 2}, + { 0x0027fa40, 25}, + { 0x0027fac8, 7}, + { 0x0027faec, 1}, + { 0x0027faf8, 7}, + { 0x0027fb20, 2}, + { 0x0027fc40, 25}, + { 0x0027fcc8, 7}, + { 0x0027fcec, 1}, + { 0x0027fcf8, 7}, + { 0x0027fd20, 2}, + { 0x0027fe40, 25}, + { 0x0027fec8, 7}, + { 0x0027feec, 1}, + { 0x0027fef8, 7}, + { 0x0027ff20, 2}, { 0x00400500, 1}, { 0x0040415c, 1}, { 0x00404468, 1}, @@ -566,6 +905,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00419854, 1}, { 0x00419864, 1}, { 0x00419a04, 2}, + { 0x00419ab0, 1}, { 0x00419b04, 1}, { 0x00419b3c, 1}, { 0x00419b48, 1}, @@ -574,7 +914,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00419bb0, 1}, { 0x00419bdc, 1}, { 0x00419c0c, 1}, - { 0x00419c8c, 1}, { 0x00419d00, 1}, { 0x00419d08, 2}, { 0x00419e08, 1}, @@ -585,11 +924,8 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00419f80, 8}, { 0x00419fa8, 5}, { 0x0041a02c, 2}, - { 0x0041a0a0, 1}, { 0x0041a0a8, 1}, - { 0x0041a890, 2}, { 0x0041a8a0, 3}, - { 0x0041a8b0, 2}, { 0x0041b014, 1}, { 0x0041b0cc, 1}, { 0x0041b1dc, 1}, @@ -600,6 +936,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0041becc, 1}, { 0x0041bfdc, 1}, { 0x0041c054, 1}, + { 0x0041c2b0, 1}, { 0x0041c304, 1}, { 0x0041c33c, 1}, { 0x0041c348, 1}, @@ -608,7 +945,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0041c3b0, 1}, { 0x0041c3dc, 1}, { 0x0041c40c, 1}, - { 0x0041c48c, 1}, { 0x0041c500, 1}, { 0x0041c508, 2}, { 0x0041c608, 1}, @@ -619,6 +955,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0041c780, 8}, { 0x0041c7a8, 5}, { 0x0041c854, 1}, + { 0x0041cab0, 1}, { 0x0041cb04, 1}, { 0x0041cb3c, 1}, { 0x0041cb48, 1}, @@ -627,7 +964,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0041cbb0, 1}, { 0x0041cbdc, 1}, { 0x0041cc0c, 1}, - { 0x0041cc8c, 1}, { 0x0041cd00, 1}, { 0x0041cd08, 2}, { 0x0041ce08, 1}, @@ -638,6 +974,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0041cf80, 8}, { 0x0041cfa8, 5}, { 0x0041d054, 1}, + { 0x0041d2b0, 1}, { 0x0041d304, 1}, { 0x0041d33c, 1}, { 0x0041d348, 1}, @@ -646,7 +983,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0041d3b0, 1}, { 0x0041d3dc, 1}, { 0x0041d40c, 1}, - { 0x0041d48c, 1}, { 0x0041d500, 1}, { 0x0041d508, 2}, { 0x0041d608, 1}, @@ -657,6 +993,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0041d780, 8}, { 0x0041d7a8, 5}, { 0x0041d854, 1}, + { 0x0041dab0, 1}, { 0x0041db04, 1}, { 0x0041db3c, 1}, { 0x0041db48, 1}, @@ -665,7 +1002,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0041dbb0, 1}, { 0x0041dbdc, 1}, { 0x0041dc0c, 1}, - { 0x0041dc8c, 1}, { 0x0041dd00, 1}, { 0x0041dd08, 2}, { 0x0041de08, 1}, @@ -675,6 +1011,26 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0041df28, 5}, { 0x0041df80, 8}, { 0x0041dfa8, 5}, + { 0x00481a00, 19}, + { 0x00481b00, 50}, + { 0x00481e00, 50}, + { 0x00481f00, 50}, + { 0x00484200, 19}, + { 0x00484300, 50}, + { 0x00484600, 50}, + { 0x00484700, 50}, + { 0x00484a00, 19}, + { 0x00484b00, 50}, + { 0x00484e00, 50}, + { 0x00484f00, 50}, + { 0x00485200, 19}, + { 0x00485300, 50}, + { 0x00485600, 50}, + { 0x00485700, 50}, + { 0x00485a00, 19}, + { 0x00485b00, 50}, + { 0x00485e00, 50}, + { 0x00485f00, 50}, { 0x00500384, 1}, { 0x005004a0, 1}, { 0x00500604, 1}, @@ -696,6 +1052,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x0050100c, 1}, { 0x00501018, 1}, { 0x00501854, 1}, + { 0x00501ab0, 1}, { 0x00501b04, 1}, { 0x00501b3c, 1}, { 0x00501b48, 1}, @@ -704,7 +1061,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00501bb0, 1}, { 0x00501bdc, 1}, { 0x00501c0c, 1}, - { 0x00501c8c, 1}, { 0x00501d00, 1}, { 0x00501d08, 2}, { 0x00501e08, 1}, @@ -715,11 +1071,8 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00501f80, 8}, { 0x00501fa8, 5}, { 0x0050202c, 2}, - { 0x005020a0, 1}, { 0x005020a8, 1}, - { 0x00502890, 2}, { 0x005028a0, 3}, - { 0x005028b0, 2}, { 0x00503014, 1}, { 0x005030cc, 1}, { 0x005031dc, 1}, @@ -730,6 +1083,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00503ecc, 1}, { 0x00503fdc, 1}, { 0x00504054, 1}, + { 0x005042b0, 1}, { 0x00504304, 1}, { 0x0050433c, 1}, { 0x00504348, 1}, @@ -738,7 +1092,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x005043b0, 1}, { 0x005043dc, 1}, { 0x0050440c, 1}, - { 0x0050448c, 1}, { 0x00504500, 1}, { 0x00504508, 2}, { 0x00504608, 1}, @@ -749,6 +1102,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00504780, 8}, { 0x005047a8, 5}, { 0x00504854, 1}, + { 0x00504ab0, 1}, { 0x00504b04, 1}, { 0x00504b3c, 1}, { 0x00504b48, 1}, @@ -757,7 +1111,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00504bb0, 1}, { 0x00504bdc, 1}, { 0x00504c0c, 1}, - { 0x00504c8c, 1}, { 0x00504d00, 1}, { 0x00504d08, 2}, { 0x00504e08, 1}, @@ -768,6 +1121,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00504f80, 8}, { 0x00504fa8, 5}, { 0x00505054, 1}, + { 0x005052b0, 1}, { 0x00505304, 1}, { 0x0050533c, 1}, { 0x00505348, 1}, @@ -776,7 +1130,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x005053b0, 1}, { 0x005053dc, 1}, { 0x0050540c, 1}, - { 0x0050548c, 1}, { 0x00505500, 1}, { 0x00505508, 2}, { 0x00505608, 1}, @@ -787,6 +1140,7 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00505780, 8}, { 0x005057a8, 5}, { 0x00505854, 1}, + { 0x00505ab0, 1}, { 0x00505b04, 1}, { 0x00505b3c, 1}, { 0x00505b48, 1}, @@ -795,7 +1149,6 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00505bb0, 1}, { 0x00505bdc, 1}, { 0x00505c0c, 1}, - { 0x00505c8c, 1}, { 0x00505d00, 1}, { 0x00505d08, 2}, { 0x00505e08, 1}, @@ -805,10 +1158,147 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00505f28, 5}, { 0x00505f80, 8}, { 0x00505fa8, 5}, + { 0x00581a00, 19}, + { 0x00581b00, 50}, + { 0x00581e00, 50}, + { 0x00581f00, 50}, + { 0x00584200, 19}, + { 0x00584300, 50}, + { 0x00584600, 50}, + { 0x00584700, 50}, + { 0x00584a00, 19}, + { 0x00584b00, 50}, + { 0x00584e00, 50}, + { 0x00584f00, 50}, + { 0x00585200, 19}, + { 0x00585300, 50}, + { 0x00585600, 50}, + { 0x00585700, 50}, + { 0x00585a00, 19}, + { 0x00585b00, 50}, + { 0x00585e00, 50}, + { 0x00585f00, 50}, { 0x00900100, 1}, { 0x009a0100, 1}, + { 0x00a00160, 2}, + { 0x00a007d0, 1}, + { 0x00a04200, 1}, + { 0x00a04470, 2}, + { 0x00a08190, 1}, + { 0x00a08198, 4}, + { 0x00a0c820, 2}, + { 0x00a0cc20, 2}, + { 0x00a0e470, 2}, + { 0x00a0e490, 9}, + { 0x00a0e6a8, 7}, + { 0x00a0e6c8, 2}, + { 0x00a0e6d4, 7}, + { 0x00a0e6f4, 2}, + { 0x00a0ec70, 2}, + { 0x00a0ec90, 9}, + { 0x00a0eea8, 7}, + { 0x00a0eec8, 2}, + { 0x00a0eed4, 7}, + { 0x00a0eef4, 2}, + { 0x00a10190, 1}, + { 0x00a10198, 4}, + { 0x00a14820, 2}, + { 0x00a14c20, 2}, + { 0x00a16470, 2}, + { 0x00a16490, 9}, + { 0x00a166a8, 7}, + { 0x00a166c8, 2}, + { 0x00a166d4, 7}, + { 0x00a166f4, 2}, + { 0x00a16c70, 2}, + { 0x00a16c90, 9}, + { 0x00a16ea8, 7}, + { 0x00a16ec8, 2}, + { 0x00a16ed4, 7}, + { 0x00a16ef4, 2}, + { 0x00a18190, 1}, + { 0x00a18198, 4}, + { 0x00a1c820, 2}, + { 0x00a1cc20, 2}, + { 0x00a1e470, 2}, + { 0x00a1e490, 9}, + { 0x00a1e6a8, 7}, + { 0x00a1e6c8, 2}, + { 0x00a1e6d4, 7}, + { 0x00a1e6f4, 2}, + { 0x00a1ec70, 2}, + { 0x00a1ec90, 9}, + { 0x00a1eea8, 7}, + { 0x00a1eec8, 2}, + { 0x00a1eed4, 7}, + { 0x00a1eef4, 2}, + { 0x00a20190, 1}, + { 0x00a20198, 4}, + { 0x00a24820, 2}, + { 0x00a24c20, 2}, + { 0x00a26470, 2}, + { 0x00a26490, 9}, + { 0x00a266a8, 7}, + { 0x00a266c8, 2}, + { 0x00a266d4, 7}, + { 0x00a266f4, 2}, + { 0x00a26c70, 2}, + { 0x00a26c90, 9}, + { 0x00a26ea8, 7}, + { 0x00a26ec8, 2}, + { 0x00a26ed4, 7}, + { 0x00a26ef4, 2}, + { 0x00a28190, 1}, + { 0x00a28198, 4}, + { 0x00a2c820, 2}, + { 0x00a2cc20, 2}, + { 0x00a2e470, 2}, + { 0x00a2e490, 9}, + { 0x00a2e6a8, 7}, + { 0x00a2e6c8, 2}, + { 0x00a2e6d4, 7}, + { 0x00a2e6f4, 2}, + { 0x00a2ec70, 2}, + { 0x00a2ec90, 9}, + { 0x00a2eea8, 7}, + { 0x00a2eec8, 2}, + { 0x00a2eed4, 7}, + { 0x00a2eef4, 2}, + { 0x00a30190, 1}, + { 0x00a30198, 4}, + { 0x00a34820, 2}, + { 0x00a34c20, 2}, + { 0x00a36470, 2}, + { 0x00a36490, 9}, + { 0x00a366a8, 7}, + { 0x00a366c8, 2}, + { 0x00a366d4, 7}, + { 0x00a366f4, 2}, + { 0x00a36c70, 2}, + { 0x00a36c90, 9}, + { 0x00a36ea8, 7}, + { 0x00a36ec8, 2}, + { 0x00a36ed4, 7}, + { 0x00a36ef4, 2}, + { 0x00a38190, 1}, + { 0x00a38198, 4}, + { 0x00a3c820, 2}, + { 0x00a3cc20, 2}, + { 0x00a3e470, 2}, + { 0x00a3e490, 9}, + { 0x00a3e6a8, 7}, + { 0x00a3e6c8, 2}, + { 0x00a3e6d4, 7}, + { 0x00a3e6f4, 2}, + { 0x00a3ec70, 2}, + { 0x00a3ec90, 9}, + { 0x00a3eea8, 7}, + { 0x00a3eec8, 2}, + { 0x00a3eed4, 7}, + { 0x00a3eef4, 2}, }; + static const u32 gv11b_global_whitelist_ranges_count = ARRAY_SIZE(gv11b_global_whitelist_ranges); -- cgit v1.2.2 From 39727398230bdb0fb01d9aa54e4cc572f6d39299 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 24 May 2017 13:27:28 -0700 Subject: gpu: nvgpu: gv11b: No need to set init val for fb & pbdma timeout fb_timeout and pbdma_timeout values are already set by h/w to init values. No need to reinitialize. JIRA GPUT19X-22 Change-Id: If6f1111f58940d51e53f028b046c42fa852221ee Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1493458 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 38a402dc..b6691db5 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -1122,19 +1123,13 @@ static int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) timeout = gk20a_readl(g, fifo_fb_timeout_r()); - timeout = set_field(timeout, fifo_fb_timeout_period_m(), - fifo_fb_timeout_period_init_f()); - gk20a_dbg_info("fifo_fb_timeout reg val = 0x%08x", timeout); - gk20a_writel(g, fifo_fb_timeout_r(), timeout); - - /* write pbdma timeout value */ + nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout); for (i = 0; i < host_num_pbdma; i++) { timeout = gk20a_readl(g, pbdma_timeout_r(i)); - timeout = set_field(timeout, pbdma_timeout_period_m(), - pbdma_timeout_period_init_f()); - gk20a_dbg_info("pbdma_timeout reg val = 0x%08x", timeout); - gk20a_writel(g, pbdma_timeout_r(i), timeout); + nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", + timeout); } + /* clear and enable pbdma interrupt */ for (i = 0; i < host_num_pbdma; i++) { gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); -- cgit v1.2.2 From 48afa1c69cb9a19613bde49792d4d2cbae2f7011 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 31 May 2017 21:56:20 -0700 Subject: gpu: nvgpu: gv11b: set only valid soc credits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only for following instances, mssnvlink <-> hshub will be interacting in gv11b: NV_ADDRESS_MAP_MSS_NVLINK_1_BASE NV_ADDRESS_MAP_MSS_NVLINK_2_BASE  NV_ADDRESS_MAP_MSS_NVLINK_3_BASE NV_ADDRESS_MAP_MSS_NVLINK_4_BASE   NV_ADDRESS_MAP_MSS_NVLINK_0_BASE doesnt interact with gv11b hshub, so don't set those credits. GPUT19X-116 Change-Id: I8c6737293699444ddb1e27936f1c4a2e61871c29 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1493641 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 7bf7139e..975692a6 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -31,7 +31,6 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) { - void __iomem *soc0 = ioremap(0x01f00010, 4096); //MSS_NVLINK_0_BASE void __iomem *soc1 = ioremap(0x01f20010, 4096); //MSS_NVLINK_1_BASE void __iomem *soc2 = ioremap(0x01f40010, 4096); //MSS_NVLINK_2_BASE void __iomem *soc3 = ioremap(0x01f60010, 4096); //MSS_NVLINK_3_BASE @@ -41,11 +40,6 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) /* TODO : replace this code with proper nvlink API */ nvgpu_info(g, "init nvlink soc credits"); - val = readl_relaxed(soc0); - writel_relaxed(val, soc0); - val = readl_relaxed(soc0 + 4); - writel_relaxed(val, soc0 + 4); - val = readl_relaxed(soc1); writel_relaxed(val, soc1); val = readl_relaxed(soc1 + 4); -- cgit v1.2.2 From 66d0c84f3ca42ab2453a71b850d9a2a4c556fdff Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 30 May 2017 19:50:40 +0530 Subject: gpu: nvgpu: use correct parameters for gk20a_debug_dump() Pass struct gk20a * pointer instead of device pointer to gk20a_debug_dump() API This patch is needed since definition of gk20a_debug_dump() has changed Jira NVGPU-62 Change-Id: I7e67f6b792e575ee72eb6a5b0f7c53e5122a545f Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1492113 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b6691db5..367d61f5 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -916,7 +916,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, gr_gk20a_init_cg_mode(g, ELCG_MODE, ELCG_RUN); if (rc_type == RC_TYPE_MMU_FAULT) - gk20a_debug_dump(g->dev); + gk20a_debug_dump(g); /* get the channel/TSG */ if (rc_type == RC_TYPE_MMU_FAULT && mmfault && mmfault->refch) { -- cgit v1.2.2 From 8da78a9fa7826985e8ca08a0a15eb1d6f38a222e Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 31 May 2017 13:29:06 +0530 Subject: gpu: nvgpu: include Include explicitly wherever the debug operations are used Jira NVGPU-62 Change-Id: I1845e08774b7c211e7fd954937708905f905e069 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1492818 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 + drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 367d61f5..2bd72d51 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index a9f1183e..415ad963 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index c3d4ac3f..0cdb471b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -46,6 +46,8 @@ #include "gv11b_gating_reglist.h" #include "regops_gv11b.h" +#include + #include static struct gpu_ops gv11b_ops; -- cgit v1.2.2 From 65f0c731695265f1b1b08d7c43a6778aa0300117 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 1 Jun 2017 16:15:04 -0700 Subject: gpu: nvgpu: gv11b: payload for syncpt wait Program payload for sync point wait command. JIRA GPUT19X-2 Change-Id: I1a8e0176a056aa1c7008761f8b253ec17b5703c2 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1494353 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 2bd72d51..0dd0fc40 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1479,7 +1479,7 @@ static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, /* semaphore_c */ nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); /* payload */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x0); + nvgpu_mem_wr32(g, cmd->mem, off++, thresh); /* semaphore_d */ nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); /* operation: acq_geq, switch_en */ -- cgit v1.2.2 From 81172b5df4c7dc46bf46419074b30e0a73f5ddfb Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 1 Jun 2017 12:30:49 -0700 Subject: gpu: nvgpu: gv11b: disable czf_bypass Gv11b ucode is not having support for low latency context-switching. So disable cfz_bypass mode for now. JIRA GPUT19X-116 Change-Id: I814cd254fa3c342c20906805a4b13b52c89d5b1e Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1494217 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 415ad963..8176b807 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2421,4 +2421,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.load_tpc_mask = gr_gv11b_load_tpc_mask; gops->gr.handle_gpc_gpccs_exception = gr_gv11b_handle_gpc_gpccs_exception; + gops->gr.set_czf_bypass = NULL; } -- cgit v1.2.2 From 6bc36bded05ee497a474e5a718c49dc33eb235f1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 22 May 2017 16:38:49 -0700 Subject: gpu: nvgpu: L2 cache tag ECC support Adding support for L2 cache tag ECC error handling JIRA: GPUT19X-112 Change-Id: I9a8ebefe97814b341f57a024dfb126013adaac1c Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1489029 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ecc_gv11b.h | 5 + drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 107 ++++++++++++ drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 27 +++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 184 +++++++++++++++++++++ 4 files changed, 323 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h index 6b471655..4e1696f7 100644 --- a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h @@ -33,4 +33,9 @@ struct ecc_gr_t19x { struct gk20a_ecc_stat gpccs_uncorrected_err_count; }; +struct ecc_ltc_t19x { + struct gk20a_ecc_stat l2_cache_corrected_err_count; + struct gk20a_ecc_stat l2_cache_uncorrected_err_count; +}; + #endif diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 23beca5d..b8a97ce3 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -20,6 +20,7 @@ #include "ltc_gv11b.h" #include +#include #include #include @@ -74,6 +75,111 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) ltc_intr); } +static void gv11b_ltc_isr(struct gk20a *g) +{ + u32 mc_intr, ltc_intr3; + unsigned int ltc, slice; + u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE); + u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); + u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; + u32 corrected_delta, uncorrected_delta; + u32 corrected_overflow, uncorrected_overflow; + u32 ltc_corrected, ltc_uncorrected; + + mc_intr = gk20a_readl(g, mc_intr_ltc_r()); + for (ltc = 0; ltc < g->ltc_count; ltc++) { + if ((mc_intr & 1 << ltc) == 0) + continue; + ltc_corrected = ltc_uncorrected = 0; + + for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { + u32 offset = ltc_stride * ltc + lts_stride * slice; + ltc_intr3 = gk20a_readl(g, ltc_ltc0_lts0_intr3_r() + + offset); + + /* Detect and handle ECC PARITY errors */ + + if (ltc_intr3 & + (ltc_ltcs_ltss_intr3_ecc_uncorrected_m() | + ltc_ltcs_ltss_intr3_ecc_corrected_m())) { + + ecc_status = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_status_r() + + offset); + ecc_addr = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_address_r() + + offset); + corrected_cnt = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset); + uncorrected_cnt = gk20a_readl(g, + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset); + + corrected_delta = + ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(corrected_cnt); + uncorrected_delta = + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(uncorrected_cnt); + corrected_overflow = ecc_status & + ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(); + + uncorrected_overflow = ecc_status & + ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(); + + /* clear the interrupt */ + if ((corrected_delta > 0) || corrected_overflow) { + gk20a_writel(g, ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r() + offset, 0); + } + if ((uncorrected_delta > 0) || uncorrected_overflow) { + gk20a_writel(g, + ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r() + offset, 0); + } + + gk20a_writel(g, ltc_ltc0_lts0_l2_cache_ecc_status_r() + offset, + ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f()); + + /* update counters per slice */ + if (corrected_overflow) + corrected_delta += (0x1UL << ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s()); + if (uncorrected_overflow) + uncorrected_delta += (0x1UL << ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s()); + + ltc_corrected += corrected_delta; + ltc_uncorrected += uncorrected_delta; + nvgpu_log(g, gpu_dbg_intr, + "ltc:%d lts: %d cache ecc interrupt intr: 0x%x", ltc, slice, ltc_intr3); + + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m()) + nvgpu_log(g, gpu_dbg_intr, "rstg ecc error corrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m()) + nvgpu_log(g, gpu_dbg_intr, "rstg ecc error uncorrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m()) + nvgpu_log(g, gpu_dbg_intr, "tstg ecc error corrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m()) + nvgpu_log(g, gpu_dbg_intr, "tstg ecc error uncorrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m()) + nvgpu_log(g, gpu_dbg_intr, "dstg ecc error corrected"); + if (ecc_status & ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m()) + nvgpu_log(g, gpu_dbg_intr, "dstg ecc error uncorrected"); + + if (corrected_overflow || uncorrected_overflow) + nvgpu_info(g, "ecc counter overflow!"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error address: 0x%x", ecc_addr); + + } + + } + g->ecc.ltc.t19x.l2_cache_corrected_err_count.counters[ltc] += + ltc_corrected; + g->ecc.ltc.t19x.l2_cache_uncorrected_err_count.counters[ltc] += + ltc_uncorrected; + + } + + /* fallback to other interrupts */ + gp10b_ltc_isr(g); +} + static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) { u32 val = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); @@ -93,4 +199,5 @@ void gv11b_init_ltc(struct gpu_ops *gops) gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; + gops->ltc.isr = gv11b_ltc_isr; } diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 8733cae9..432af7c1 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -177,6 +177,9 @@ static struct device_attribute *dev_attr_fecs_ecc_uncorrected_err_count_array; static struct device_attribute *dev_attr_gpccs_ecc_corrected_err_count_array; static struct device_attribute *dev_attr_gpccs_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_l2_cache_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_l2_cache_ecc_uncorrected_err_count_array; + void gr_gv11b_create_sysfs(struct device *dev) { struct gk20a *g = get_gk20a(dev); @@ -250,6 +253,20 @@ void gr_gv11b_create_sysfs(struct device *dev) &g->ecc.gr.t19x.gcc_l15_uncorrected_err_count, dev_attr_gcc_l15_ecc_uncorrected_err_count_array); + error |= gp10b_ecc_stat_create(dev, + g->ltc_count, + "ltc", + "l2_cache_uncorrected_err_count", + &g->ecc.ltc.t19x.l2_cache_uncorrected_err_count, + dev_attr_l2_cache_ecc_uncorrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + g->ltc_count, + "ltc", + "l2_cache_corrected_err_count", + &g->ecc.ltc.t19x.l2_cache_corrected_err_count, + dev_attr_l2_cache_ecc_corrected_err_count_array); + error |= gp10b_ecc_stat_create(dev, 1, "gpc", @@ -336,6 +353,16 @@ static void gr_gv11b_remove_sysfs(struct device *dev) &g->ecc.gr.t19x.gcc_l15_uncorrected_err_count, dev_attr_gcc_l15_ecc_uncorrected_err_count_array); + gp10b_ecc_stat_remove(dev, + g->ltc_count, + &g->ecc.ltc.t19x.l2_cache_uncorrected_err_count, + dev_attr_l2_cache_ecc_uncorrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + g->ltc_count, + &g->ecc.ltc.t19x.l2_cache_corrected_err_count, + dev_attr_l2_cache_ecc_corrected_err_count_array); + gp10b_ecc_stat_remove(dev, 1, &g->ecc.gr.t19x.fecs_uncorrected_err_count, diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index 45d3df07..1bcd1246 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -374,6 +374,190 @@ static inline u32 ltc_ltc0_lts0_intr_r(void) { return 0x0014040c; } +static inline u32 ltc_ltcs_ltss_intr3_r(void) +{ + return 0x0017e388; +} +static inline u32 ltc_ltcs_ltss_intr3_ecc_corrected_m(void) +{ + return 0x1 << 7; +} +static inline u32 ltc_ltcs_ltss_intr3_ecc_uncorrected_m(void) +{ + return 0x1 << 8; +} +static inline u32 ltc_ltc0_lts0_intr3_r(void) +{ + return 0x00140588; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_r(void) +{ + return 0x001404f0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m(void) +{ + return 0x1 << 1; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m(void) +{ + return 0x1 << 3; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m(void) +{ + return 0x1 << 5; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m(void) +{ + return 0x1 << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m(void) +{ + return 0x1 << 2; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m(void) +{ + return 0x1 << 4; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 18; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 19; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 17; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_address_r(void) +{ + return 0x001404fc; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(void) +{ + return 0x001404f4; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(void) +{ + return 0x001404f8; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) { return 0x0014051c; -- cgit v1.2.2 From 345eaef6a76771da9c3e8a5e375fc9d659fb1b2b Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 26 May 2017 08:31:46 -0700 Subject: gpu: nvgpu: GPC MMU ECC support Adding support for GPC MMU ECC error handling JIRA: GPUT19X-112 Change-Id: I62083bf2f144ff628ecd8c0aefc8d227a233ff36 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1490772 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ecc_gv11b.h | 2 + drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 105 +++++++++- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 25 +++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 216 +++++++++++++++++++-- 4 files changed, 332 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h index 4e1696f7..70b1bab8 100644 --- a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h @@ -31,6 +31,8 @@ struct ecc_gr_t19x { struct gk20a_ecc_stat fecs_uncorrected_err_count; struct gk20a_ecc_stat gpccs_corrected_err_count; struct gk20a_ecc_stat gpccs_uncorrected_err_count; + struct gk20a_ecc_stat mmu_l1tlb_corrected_err_count; + struct gk20a_ecc_stat mmu_l1tlb_uncorrected_err_count; }; struct ecc_ltc_t19x { diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 8176b807..701b840a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -658,16 +658,101 @@ static int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, return 0; } -static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, +static int gr_gv11b_handle_gpcmmu_ecc_exception(struct gk20a *g, u32 gpc, u32 exception) { int ret = 0; + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 offset = gpc_stride * gpc; u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; u32 corrected_delta, uncorrected_delta; u32 corrected_overflow, uncorrected_overflow; + int hww_esr; + + hww_esr = gk20a_readl(g, gr_gpc0_mmu_gpcmmu_global_esr_r() + offset); + + if (!(hww_esr & (gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m() | + gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m()))) + return ret; + + ecc_status = gk20a_readl(g, + gr_gpc0_mmu_l1tlb_ecc_status_r() + offset); + ecc_addr = gk20a_readl(g, + gr_gpc0_mmu_l1tlb_ecc_address_r() + offset); + corrected_cnt = gk20a_readl(g, + gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r() + offset); + uncorrected_cnt = gk20a_readl(g, + gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r() + offset); + + corrected_delta = gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v( + corrected_cnt); + uncorrected_delta = gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v( + uncorrected_cnt); + corrected_overflow = ecc_status & + gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(); + + uncorrected_overflow = ecc_status & + gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(); + + + /* clear the interrupt */ + if ((corrected_delta > 0) || corrected_overflow) + gk20a_writel(g, + gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r() + + offset, 0); + if ((uncorrected_delta > 0) || uncorrected_overflow) + gk20a_writel(g, + gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r() + + offset, 0); + + gk20a_writel(g, gr_gpc0_mmu_l1tlb_ecc_status_r() + offset, + gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f()); + + /* Handle overflow */ + if (corrected_overflow) + corrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s()); + if (uncorrected_overflow) + uncorrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s()); + + g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count.counters[gpc] += + corrected_delta; + g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count.counters[gpc] += + uncorrected_delta; + nvgpu_log(g, gpu_dbg_intr, + "mmu l1tlb gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); + + if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m()) + nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error"); + if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m()) + nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error"); + if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m()) + nvgpu_log(g, gpu_dbg_intr, "corrected ecc fa data error"); + if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m()) + nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc fa data error"); + if (corrected_overflow || uncorrected_overflow) + nvgpu_info(g, "mmu l1tlb ecc counter overflow!"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error address: 0x%x", ecc_addr); + nvgpu_log(g, gpu_dbg_intr, + "ecc error count corrected: %d, uncorrected %d", + g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count.counters[gpc], + g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count.counters[gpc]); + + return ret; +} + +static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, + u32 exception) +{ + int ret = 0; + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 offset = gpc_stride * gpc; + u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; + u32 corrected_delta, uncorrected_delta; + u32 corrected_overflow, uncorrected_overflow; int hww_esr; - u32 offset = proj_gpc_stride_v() * gpc; hww_esr = gk20a_readl(g, gr_gpc0_gpccs_hww_esr_r() + offset); @@ -741,6 +826,15 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, return ret; } +static int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, + u32 gpc_exception) +{ + if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpcmmu_m()) + return gr_gv11b_handle_gpcmmu_ecc_exception(g, gpc, + gpc_exception); + return 0; +} + static int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, u32 gpc_exception) { @@ -764,7 +858,8 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) | - gr_gpcs_gpccs_gpc_exception_en_gpccs_f(1))); + gr_gpcs_gpccs_gpc_exception_en_gpccs_f(1) | + gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(1))); } static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, @@ -1810,7 +1905,7 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) nvgpu_log(g, gpu_dbg_intr, "dmem ecc error uncorrected"); if (corrected_overflow || uncorrected_overflow) - nvgpu_info(g, "gpccs ecc counter overflow!"); + nvgpu_info(g, "fecs ecc counter overflow!"); nvgpu_log(g, gpu_dbg_intr, "ecc error row address: 0x%x", @@ -2422,4 +2517,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.handle_gpc_gpccs_exception = gr_gv11b_handle_gpc_gpccs_exception; gops->gr.set_czf_bypass = NULL; + gops->gr.handle_gpc_gpcmmu_exception = + gr_gv11b_handle_gpc_gpcmmu_exception; } diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 432af7c1..c69e1478 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -171,6 +171,8 @@ static struct device_attribute *dev_attr_sm_icache_ecc_corrected_err_count_array static struct device_attribute *dev_attr_sm_icache_ecc_uncorrected_err_count_array; static struct device_attribute *dev_attr_gcc_l15_ecc_corrected_err_count_array; static struct device_attribute *dev_attr_gcc_l15_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_mmu_l1tlb_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array; static struct device_attribute *dev_attr_fecs_ecc_corrected_err_count_array; static struct device_attribute *dev_attr_fecs_ecc_uncorrected_err_count_array; @@ -295,6 +297,19 @@ void gr_gv11b_create_sysfs(struct device *dev) &g->ecc.gr.t19x.gpccs_corrected_err_count, dev_attr_gpccs_ecc_corrected_err_count_array); + error |= gp10b_ecc_stat_create(dev, + g->gr.gpc_count, + "gpc", + "mmu_l1tlb_ecc_uncorrected_err_count", + &g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count, + dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + g->gr.gpc_count, + "gpc", + "mmu_l1tlb_ecc_corrected_err_count", + &g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count, + dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); if (error) dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); } @@ -382,4 +397,14 @@ static void gr_gv11b_remove_sysfs(struct device *dev) g->gr.gpc_count, &g->ecc.gr.t19x.gpccs_corrected_err_count, dev_attr_gpccs_ecc_corrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + g->gr.gpc_count, + &g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count, + dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + g->gr.gpc_count, + &g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count, + dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 2d5afb29..62307265 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3426,6 +3426,10 @@ static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) { return (v & 0x1) << 14; } +static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v) +{ + return (v & 0x1) << 15; +} static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { return 0x00502c90; @@ -3442,6 +3446,30 @@ static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) +{ + return 0x1 << 14; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) +{ + return 0x4000; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_f(u32 v) +{ + return (v & 0x1) << 15; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_m(void) +{ + return 0x1 << 15; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f(void) +{ + return 0x8000; +} static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) { return 0x00501048; @@ -3498,18 +3526,6 @@ static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) { return (r >> 0) & 0xffff; } -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) -{ - return (v & 0x1) << 14; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) -{ - return 0x1 << 14; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) -{ - return 0x4000; -} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { return 0x00504508; @@ -4014,6 +4030,182 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { return 0x1ff << 0; } +static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_r(void) +{ + return 0x00500324; +} +static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_r(void) +{ + return 0x00500314; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 18; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 19; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 17; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_r(void) +{ + return 0x00500320; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_index_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r(void) +{ + return 0x00500318; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r(void) +{ + return 0x0050031c; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} static inline u32 gr_gpc0_gpccs_hww_esr_r(void) { return 0x00502c98; -- cgit v1.2.2 From 3dc28cb1ab934ebcda33933086d7d0ffc8d1f907 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 26 May 2017 14:36:26 -0700 Subject: gpu: nvgpu: add chip specific ECC counters Add support for ECC counters for HUB MMU JIRA: GPUT19X-82 Change-Id: I691d5898d4db9fe2cd68f217baa646479ab5cb00 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1490825 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ecc_gv11b.h | 12 ++ drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 203 ++++++++++++++++-- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 80 +++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 236 +++++++++++++++++++++ 4 files changed, 513 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h index 70b1bab8..10750426 100644 --- a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h @@ -40,4 +40,16 @@ struct ecc_ltc_t19x { struct gk20a_ecc_stat l2_cache_uncorrected_err_count; }; +/* TODO: PMU and FB ECC features are still under embargo */ +struct ecc_eng_t19x { + /* FB */ + struct gk20a_ecc_stat mmu_l2tlb_corrected_err_count; + struct gk20a_ecc_stat mmu_l2tlb_uncorrected_err_count; + struct gk20a_ecc_stat mmu_hubtlb_corrected_err_count; + struct gk20a_ecc_stat mmu_hubtlb_uncorrected_err_count; + struct gk20a_ecc_stat mmu_fillunit_corrected_err_count; + struct gk20a_ecc_stat mmu_fillunit_uncorrected_err_count; + /* PMU */ +}; + #endif diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 975692a6..9a4ea36b 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -224,6 +224,185 @@ void gv11b_fb_disable_hub_intr(struct gk20a *g, gv11b_fb_intr_en_clr(g, index, mask); } +static void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status) +{ + u32 ecc_addr, corrected_cnt, uncorrected_cnt; + u32 corrected_delta, uncorrected_delta; + u32 corrected_overflow, uncorrected_overflow; + + ecc_addr = gk20a_readl(g, fb_mmu_l2tlb_ecc_address_r()); + corrected_cnt = gk20a_readl(g, + fb_mmu_l2tlb_ecc_corrected_err_count_r()); + uncorrected_cnt = gk20a_readl(g, + fb_mmu_l2tlb_ecc_uncorrected_err_count_r()); + + corrected_delta = fb_mmu_l2tlb_ecc_corrected_err_count_total_v( + corrected_cnt); + uncorrected_delta = fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v( + uncorrected_cnt); + corrected_overflow = ecc_status & + fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(); + + uncorrected_overflow = ecc_status & + fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(); + + /* clear the interrupt */ + if ((corrected_delta > 0) || corrected_overflow) + gk20a_writel(g, fb_mmu_l2tlb_ecc_corrected_err_count_r(), 0); + if ((uncorrected_delta > 0) || uncorrected_overflow) + gk20a_writel(g, fb_mmu_l2tlb_ecc_uncorrected_err_count_r(), 0); + + gk20a_writel(g, fb_mmu_l2tlb_ecc_status_r(), + fb_mmu_l2tlb_ecc_status_reset_clear_f()); + + /* Handle overflow */ + if (corrected_overflow) + corrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_corrected_err_count_total_s()); + if (uncorrected_overflow) + uncorrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s()); + + + g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0] += + corrected_delta; + g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0] += + uncorrected_delta; + + if (ecc_status & fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()) + nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error"); + if (ecc_status & fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m()) + nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error"); + if (corrected_overflow || uncorrected_overflow) + nvgpu_info(g, "mmu l2tlb ecc counter overflow!"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error address: 0x%x", ecc_addr); + nvgpu_log(g, gpu_dbg_intr, + "ecc error count corrected: %d, uncorrected %d", + g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0], + g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0]); +} + +static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) +{ + u32 ecc_addr, corrected_cnt, uncorrected_cnt; + u32 corrected_delta, uncorrected_delta; + u32 corrected_overflow, uncorrected_overflow; + + ecc_addr = gk20a_readl(g, fb_mmu_hubtlb_ecc_address_r()); + corrected_cnt = gk20a_readl(g, + fb_mmu_hubtlb_ecc_corrected_err_count_r()); + uncorrected_cnt = gk20a_readl(g, + fb_mmu_hubtlb_ecc_uncorrected_err_count_r()); + + corrected_delta = fb_mmu_hubtlb_ecc_corrected_err_count_total_v( + corrected_cnt); + uncorrected_delta = fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v( + uncorrected_cnt); + corrected_overflow = ecc_status & + fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(); + + uncorrected_overflow = ecc_status & + fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(); + + /* clear the interrupt */ + if ((corrected_delta > 0) || corrected_overflow) + gk20a_writel(g, fb_mmu_hubtlb_ecc_corrected_err_count_r(), 0); + if ((uncorrected_delta > 0) || uncorrected_overflow) + gk20a_writel(g, fb_mmu_hubtlb_ecc_uncorrected_err_count_r(), 0); + + gk20a_writel(g, fb_mmu_hubtlb_ecc_status_r(), + fb_mmu_hubtlb_ecc_status_reset_clear_f()); + + /* Handle overflow */ + if (corrected_overflow) + corrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_corrected_err_count_total_s()); + if (uncorrected_overflow) + uncorrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s()); + + + g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0] += + corrected_delta; + g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0] += + uncorrected_delta; + + if (ecc_status & fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) + nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error"); + if (ecc_status & fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m()) + nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error"); + if (corrected_overflow || uncorrected_overflow) + nvgpu_info(g, "mmu hubtlb ecc counter overflow!"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error address: 0x%x", ecc_addr); + nvgpu_log(g, gpu_dbg_intr, + "ecc error count corrected: %d, uncorrected %d", + g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0], + g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0]); +} + +static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) +{ + u32 ecc_addr, corrected_cnt, uncorrected_cnt; + u32 corrected_delta, uncorrected_delta; + u32 corrected_overflow, uncorrected_overflow; + + ecc_addr = gk20a_readl(g, fb_mmu_fillunit_ecc_address_r()); + corrected_cnt = gk20a_readl(g, + fb_mmu_fillunit_ecc_corrected_err_count_r()); + uncorrected_cnt = gk20a_readl(g, + fb_mmu_fillunit_ecc_uncorrected_err_count_r()); + + corrected_delta = fb_mmu_fillunit_ecc_corrected_err_count_total_v( + corrected_cnt); + uncorrected_delta = fb_mmu_fillunit_ecc_uncorrected_err_count_total_v( + uncorrected_cnt); + corrected_overflow = ecc_status & + fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(); + + uncorrected_overflow = ecc_status & + fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(); + + /* clear the interrupt */ + if ((corrected_delta > 0) || corrected_overflow) + gk20a_writel(g, fb_mmu_fillunit_ecc_corrected_err_count_r(), 0); + if ((uncorrected_delta > 0) || uncorrected_overflow) + gk20a_writel(g, fb_mmu_fillunit_ecc_uncorrected_err_count_r(), 0); + + gk20a_writel(g, fb_mmu_fillunit_ecc_status_r(), + fb_mmu_fillunit_ecc_status_reset_clear_f()); + + /* Handle overflow */ + if (corrected_overflow) + corrected_delta += (0x1UL << fb_mmu_fillunit_ecc_corrected_err_count_total_s()); + if (uncorrected_overflow) + uncorrected_delta += (0x1UL << fb_mmu_fillunit_ecc_uncorrected_err_count_total_s()); + + + g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0] += + corrected_delta; + g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0] += + uncorrected_delta; + + if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) + nvgpu_log(g, gpu_dbg_intr, "corrected ecc pte data error"); + if (ecc_status & fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m()) + nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc pte data error"); + if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m()) + nvgpu_log(g, gpu_dbg_intr, "corrected ecc pde0 data error"); + if (ecc_status & fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m()) + nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc pde0 data error"); + + if (corrected_overflow || uncorrected_overflow) + nvgpu_info(g, "mmu fillunit ecc counter overflow!"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error address: 0x%x", ecc_addr); + nvgpu_log(g, gpu_dbg_intr, + "ecc error count corrected: %d, uncorrected %d", + g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0], + g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0]); +} + static void gv11b_fb_hub_isr(struct gk20a *g) { u32 status; @@ -246,28 +425,16 @@ static void gv11b_fb_hub_isr(struct gk20a *g) HUB_INTR_TYPE_ECC_UNCORRECTED); status = gk20a_readl(g, fb_mmu_l2tlb_ecc_status_r()); - if (status) { - nvgpu_info(g, "hub mmu L2 ecc status: 0x%x", - status); - gk20a_writel(g, fb_mmu_l2tlb_ecc_status_r(), - fb_mmu_l2tlb_ecc_status_reset_clear_f()); - } + if (status) + gv11b_handle_l2tlb_ecc_isr(g, status); status = gk20a_readl(g, fb_mmu_hubtlb_ecc_status_r()); - if (status) { - nvgpu_info(g, "hub mmu hub tlb ecc status: 0x%x", - status); - gk20a_writel(g, fb_mmu_hubtlb_ecc_status_r(), - fb_mmu_hubtlb_ecc_status_reset_clear_f()); - } + if (status) + gv11b_handle_hubtlb_ecc_isr(g, status); status = gk20a_readl(g, fb_mmu_fillunit_ecc_status_r()); - if (status) { - nvgpu_info(g, "hub mmu fill unit ecc status: 0x%x", - status); - gk20a_writel(g, fb_mmu_fillunit_ecc_status_r(), - fb_mmu_fillunit_ecc_status_reset_clear_f()); - } + if (status) + gv11b_handle_fillunit_ecc_isr(g, status); /* re-enable interrupts after handling */ gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index c69e1478..95bbfbd3 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -182,6 +182,13 @@ static struct device_attribute *dev_attr_gpccs_ecc_uncorrected_err_count_array; static struct device_attribute *dev_attr_l2_cache_ecc_corrected_err_count_array; static struct device_attribute *dev_attr_l2_cache_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_mmu_l2tlb_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_mmu_hubtlb_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array; +static struct device_attribute *dev_attr_mmu_fillunit_ecc_corrected_err_count_array; +static struct device_attribute *dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array; + void gr_gv11b_create_sysfs(struct device *dev) { struct gk20a *g = get_gk20a(dev); @@ -310,6 +317,49 @@ void gr_gv11b_create_sysfs(struct device *dev) "mmu_l1tlb_ecc_corrected_err_count", &g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count, dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + 1, + "eng", + "mmu_l2tlb_ecc_uncorrected_err_count", + &g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count, + dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + 1, + "eng", + "mmu_l2tlb_ecc_corrected_err_count", + &g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count, + dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + 1, + "eng", + "mmu_hubtlb_ecc_uncorrected_err_count", + &g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count, + dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + 1, + "eng", + "mmu_hubtlb_ecc_corrected_err_count", + &g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count, + dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + 1, + "eng", + "mmu_fillunit_ecc_uncorrected_err_count", + &g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count, + dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); + + error |= gp10b_ecc_stat_create(dev, + 1, + "eng", + "mmu_fillunit_ecc_corrected_err_count", + &g->ecc.eng.t19x.mmu_fillunit_corrected_err_count, + dev_attr_mmu_fillunit_ecc_corrected_err_count_array); + if (error) dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); } @@ -407,4 +457,34 @@ static void gr_gv11b_remove_sysfs(struct device *dev) g->gr.gpc_count, &g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count, dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + 1, + &g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count, + dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + 1, + &g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count, + dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + 1, + &g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count, + dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + 1, + &g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count, + dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + 1, + &g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count, + dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); + + gp10b_ecc_stat_remove(dev, + 1, + &g->ecc.eng.t19x.mmu_fillunit_corrected_err_count, + dev_attr_mmu_fillunit_ecc_corrected_err_count_array); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index 76b4e902..0ddccd45 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -466,6 +466,22 @@ static inline u32 fb_mmu_l2tlb_ecc_status_r(void) { return 0x00100e70; } +static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 18; +} static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) { return (v & 0x1) << 30; @@ -474,10 +490,86 @@ static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) { return 0x40000000; } +static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void) +{ + return 0x00100e74; +} +static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void) +{ + return 0x00100e78; +} +static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_l2tlb_ecc_address_r(void) +{ + return 0x00100e7c; +} +static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void) +{ + return 32; +} +static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} static inline u32 fb_mmu_hubtlb_ecc_status_r(void) { return 0x00100e84; } +static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 18; +} static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) { return (v & 0x1) << 30; @@ -486,10 +578,94 @@ static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) { return 0x40000000; } +static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void) +{ + return 0x00100e88; +} +static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void) +{ + return 0x00100e8c; +} +static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_hubtlb_ecc_address_r(void) +{ + return 0x00100e90; +} +static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void) +{ + return 32; +} +static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} static inline u32 fb_mmu_fillunit_ecc_status_r(void) { return 0x00100e98; } +static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) +{ + return 0x1 << 3; +} +static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 18; +} static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) { return (v & 0x1) << 30; @@ -498,6 +674,66 @@ static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) { return 0x40000000; } +static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void) +{ + return 0x00100e9c; +} +static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void) +{ + return 0x00100ea0; +} +static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fb_mmu_fillunit_ecc_address_r(void) +{ + return 0x00100ea4; +} +static inline u32 fb_mmu_fillunit_ecc_address_index_s(void) +{ + return 32; +} +static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} static inline u32 fb_niso_flush_sysmem_addr_r(void) { return 0x00100c10; -- cgit v1.2.2 From 16a9ec4a12654b04a3db82de25cf6471389e4693 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 10 May 2017 23:03:28 +0530 Subject: gpu: nvgpu: renamed "struct pmu_gk20a" to "struct nvgpu_pmu" JIRA NVGPU-56 Change-Id: I73a375cf2f3d544357fb390491a8d70d12fb8562 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1479299 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 50ddb07b..35246138 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -34,7 +34,7 @@ static bool gv11b_is_pmu_supported(struct gk20a *g) return true; } -static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu) +static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); struct mm_gk20a *mm = &g->mm; -- cgit v1.2.2 From 8d63a519d99b619f13604461bbb58f82ebf87cc1 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 5 Jun 2017 14:39:14 +0530 Subject: gpu: nvgpu: pass correct parameter to gp10b_ecc_stat_create() We pass (struct device_attribute *) to gp10b_ecc_stat_create() and gr_gp10b_ecc_stat_create() and then assign a memory allocation to this pointer But since this pointer is local copy to function, static pointer variables are never set in gr_gp10b_create_sysfs() This also results in a resource leak since we never free the storage assigned to local variable Fix this by adding and passing correct parameter (struct device_attribute **) so that the address of the allocation is returned to the caller correctly Bug 200291879 Coverity id : 2567934 Change-Id: I1b1d329265f4d32739abbbe3a4e419a2af62b874 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1495907 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 48 +++++++++++++------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 95bbfbd3..8e68e6cb 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -206,159 +206,159 @@ void gr_gv11b_create_sysfs(struct device *dev) 0, "sm_l1_tag_ecc_corrected_err_count", &g->ecc.gr.t19x.sm_l1_tag_corrected_err_count, - dev_attr_sm_l1_tag_ecc_corrected_err_count_array); + &dev_attr_sm_l1_tag_ecc_corrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_l1_tag_ecc_uncorrected_err_count", &g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count, - dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); + &dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_cbu_ecc_corrected_err_count", &g->ecc.gr.t19x.sm_cbu_corrected_err_count, - dev_attr_sm_cbu_ecc_corrected_err_count_array); + &dev_attr_sm_cbu_ecc_corrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_cbu_ecc_uncorrected_err_count", &g->ecc.gr.t19x.sm_cbu_uncorrected_err_count, - dev_attr_sm_cbu_ecc_uncorrected_err_count_array); + &dev_attr_sm_cbu_ecc_uncorrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_l1_data_ecc_corrected_err_count", &g->ecc.gr.t19x.sm_l1_data_corrected_err_count, - dev_attr_sm_l1_data_ecc_corrected_err_count_array); + &dev_attr_sm_l1_data_ecc_corrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_l1_data_ecc_uncorrected_err_count", &g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count, - dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); + &dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_icache_ecc_corrected_err_count", &g->ecc.gr.t19x.sm_icache_corrected_err_count, - dev_attr_sm_icache_ecc_corrected_err_count_array); + &dev_attr_sm_icache_ecc_corrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "sm_icache_ecc_uncorrected_err_count", &g->ecc.gr.t19x.sm_icache_uncorrected_err_count, - dev_attr_sm_icache_ecc_uncorrected_err_count_array); + &dev_attr_sm_icache_ecc_uncorrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "gcc_l15_ecc_corrected_err_count", &g->ecc.gr.t19x.gcc_l15_corrected_err_count, - dev_attr_gcc_l15_ecc_corrected_err_count_array); + &dev_attr_gcc_l15_ecc_corrected_err_count_array); error |= gr_gp10b_ecc_stat_create(dev, 0, "gcc_l15_ecc_uncorrected_err_count", &g->ecc.gr.t19x.gcc_l15_uncorrected_err_count, - dev_attr_gcc_l15_ecc_uncorrected_err_count_array); + &dev_attr_gcc_l15_ecc_uncorrected_err_count_array); error |= gp10b_ecc_stat_create(dev, g->ltc_count, "ltc", "l2_cache_uncorrected_err_count", &g->ecc.ltc.t19x.l2_cache_uncorrected_err_count, - dev_attr_l2_cache_ecc_uncorrected_err_count_array); + &dev_attr_l2_cache_ecc_uncorrected_err_count_array); error |= gp10b_ecc_stat_create(dev, g->ltc_count, "ltc", "l2_cache_corrected_err_count", &g->ecc.ltc.t19x.l2_cache_corrected_err_count, - dev_attr_l2_cache_ecc_corrected_err_count_array); + &dev_attr_l2_cache_ecc_corrected_err_count_array); error |= gp10b_ecc_stat_create(dev, 1, "gpc", "fecs_ecc_uncorrected_err_count", &g->ecc.gr.t19x.fecs_uncorrected_err_count, - dev_attr_fecs_ecc_uncorrected_err_count_array); + &dev_attr_fecs_ecc_uncorrected_err_count_array); error |= gp10b_ecc_stat_create(dev, 1, "gpc", "fecs_ecc_corrected_err_count", &g->ecc.gr.t19x.fecs_corrected_err_count, - dev_attr_fecs_ecc_corrected_err_count_array); + &dev_attr_fecs_ecc_corrected_err_count_array); error |= gp10b_ecc_stat_create(dev, g->gr.gpc_count, "gpc", "gpccs_ecc_uncorrected_err_count", &g->ecc.gr.t19x.gpccs_uncorrected_err_count, - dev_attr_gpccs_ecc_uncorrected_err_count_array); + &dev_attr_gpccs_ecc_uncorrected_err_count_array); error |= gp10b_ecc_stat_create(dev, g->gr.gpc_count, "gpc", "gpccs_ecc_corrected_err_count", &g->ecc.gr.t19x.gpccs_corrected_err_count, - dev_attr_gpccs_ecc_corrected_err_count_array); + &dev_attr_gpccs_ecc_corrected_err_count_array); error |= gp10b_ecc_stat_create(dev, g->gr.gpc_count, "gpc", "mmu_l1tlb_ecc_uncorrected_err_count", &g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count, - dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); + &dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); error |= gp10b_ecc_stat_create(dev, g->gr.gpc_count, "gpc", "mmu_l1tlb_ecc_corrected_err_count", &g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count, - dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); + &dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); error |= gp10b_ecc_stat_create(dev, 1, "eng", "mmu_l2tlb_ecc_uncorrected_err_count", &g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count, - dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); + &dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); error |= gp10b_ecc_stat_create(dev, 1, "eng", "mmu_l2tlb_ecc_corrected_err_count", &g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count, - dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); + &dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); error |= gp10b_ecc_stat_create(dev, 1, "eng", "mmu_hubtlb_ecc_uncorrected_err_count", &g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count, - dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); + &dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); error |= gp10b_ecc_stat_create(dev, 1, "eng", "mmu_hubtlb_ecc_corrected_err_count", &g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count, - dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); + &dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); error |= gp10b_ecc_stat_create(dev, 1, "eng", "mmu_fillunit_ecc_uncorrected_err_count", &g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count, - dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); + &dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); error |= gp10b_ecc_stat_create(dev, 1, "eng", "mmu_fillunit_ecc_corrected_err_count", &g->ecc.eng.t19x.mmu_fillunit_corrected_err_count, - dev_attr_mmu_fillunit_ecc_corrected_err_count_array); + &dev_attr_mmu_fillunit_ecc_corrected_err_count_array); if (error) dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); -- cgit v1.2.2 From fa0cf69d0f8fe7275debef7b3fc87c9225f71f0b Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Mon, 5 Jun 2017 17:44:58 +0300 Subject: gpu: nvgpu: split vidmem_is_vidmem Use the new honors_aperture and unified_memory flags instead of vidmem_is_vidmem. Jira NVGPU-86 Change-Id: I5df8b119d30b255fa8d841cec747a187ce3fa588 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1496081 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 8e68e6cb..4b600cdd 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -88,9 +88,6 @@ static int gv11b_tegra_probe(struct device *dev) platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false; platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false; - /* soc memory accessed as system memory aperture */ - platform->g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem; - gp10b_tegra_get_clocks(dev); nvgpu_linux_init_clk_support(platform->g); @@ -155,7 +152,8 @@ struct gk20a_platform t19x_gpu_tegra_platform = { .soc_name = "tegra19x", - .vidmem_is_vidmem = true, + .honors_aperture = true, + .unified_memory = true, .reset_assert = gp10b_tegra_reset_assert, .reset_deassert = gp10b_tegra_reset_deassert, -- cgit v1.2.2 From 3e22195974ef233e12f69c5769d42b322f5adc1e Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 19 May 2017 14:01:26 -0700 Subject: gpu: nvgpu: gv11b: update init_fs_state gr ops GPUT19X-70 Change-Id: Ifc6c52ac15108d1389fcd732218abf46b6167485 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1486177 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 701b840a..503fb6f7 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1501,10 +1501,6 @@ static void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch); } -static int gr_gv11b_init_fs_state(struct gk20a *g) -{ - return gr_gp10b_init_fs_state(g); -} static void gr_gv11b_init_cyclestats(struct gk20a *g) { @@ -2458,6 +2454,30 @@ static void gr_gv11b_write_preemption_ptr(struct gk20a *g, } +static int gr_gv11b_init_fs_state(struct gk20a *g) +{ + u32 data; + + gk20a_dbg_fn(""); + + data = gk20a_readl(g, gr_gpcs_tpcs_sm_texio_control_r()); + data = set_field(data, gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(), + gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); + gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); + + data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r()); + data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(), + gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); + gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); + + if (g->gr.t18x.fecs_feature_override_ecc_val != 0) { + gk20a_writel(g, + gr_fecs_feature_override_ecc_r(), + g->gr.t18x.fecs_feature_override_ecc_val); + } + + return gr_gm20b_init_fs_state(g); +} void gv11b_init_gr(struct gpu_ops *gops) { -- cgit v1.2.2 From 3bf38954c2cd794485ed1bac50df8e61ad1100eb Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 17 May 2017 20:03:22 -0700 Subject: gpu: nvgpu: gv11b: move cbc init to mmu from ltc Added cbc_init in fb and removed cbc_init from ltc. Also avoid writing into read only registers in ltc. GPUT19X-70 GPUT19X-116 Change-Id: Ife53e8ec7f049d666baacea3b7c45179e3e13ff9 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1484525 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: svccoveritychecker --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 68 ++++++++++++++++++ drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 5 +- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 80 ++++++++++++++++++++++ 3 files changed, 149 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 9a4ea36b..3b3d775e 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -28,6 +28,7 @@ #include #include +#include static void gv11b_init_nvlink_soc_credits(struct gk20a *g) { @@ -62,6 +63,71 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) } +static void gv11b_fb_init_fs_state(struct gk20a *g) +{ + nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb"); + + nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %u", + gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); + + gk20a_writel(g, fb_mmu_num_active_ltcs_r(), + fb_mmu_num_active_ltcs_count_f(g->ltc_count)); + + nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u", + fb_mmu_num_active_ltcs_count_v( + gk20a_readl(g, fb_mmu_num_active_ltcs_r()))); +} + +static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) +{ + u32 max_size = gr->max_comptag_mem; + /* one tag line covers 64KB */ + u32 max_comptag_lines = max_size << 4; + u32 compbit_base_post_divide; + u64 compbit_base_post_multiply64; + u64 compbit_store_iova; + u64 compbit_base_post_divide64; + + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) + compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); + else + compbit_store_iova = g->ops.mm.get_iova_addr(g, + gr->compbit_store.mem.priv.sgt->sgl, 0); + + compbit_base_post_divide64 = compbit_store_iova >> + fb_mmu_cbc_base_address_alignment_shift_v(); + + do_div(compbit_base_post_divide64, g->ltc_count); + compbit_base_post_divide = u64_lo32(compbit_base_post_divide64); + + compbit_base_post_multiply64 = ((u64)compbit_base_post_divide * + g->ltc_count) << fb_mmu_cbc_base_address_alignment_shift_v(); + + if (compbit_base_post_multiply64 < compbit_store_iova) + compbit_base_post_divide++; + + if (g->ops.ltc.cbc_fix_config) + compbit_base_post_divide = + g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide); + + gk20a_writel(g, fb_mmu_cbc_base_r(), + fb_mmu_cbc_base_address_f(compbit_base_post_divide)); + + nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte, + "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n", + (u32)(compbit_store_iova >> 32), + (u32)(compbit_store_iova & 0xffffffff), + compbit_base_post_divide); + nvgpu_log(g, gpu_dbg_fn, "cbc base %x", + gk20a_readl(g, fb_mmu_cbc_base_r())); + + gr->compbit_store.base_hw = compbit_base_post_divide; + + g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate, + 0, max_comptag_lines - 1); + +} + static void gv11b_fb_reset(struct gk20a *g) { u32 val; @@ -450,6 +516,8 @@ void gv11b_init_fb(struct gpu_ops *gops) gp10b_init_fb(gops); gops->fb.hub_isr = gv11b_fb_hub_isr; gops->fb.reset = gv11b_fb_reset; + gops->fb.init_fs_state = gv11b_fb_init_fs_state; + gops->fb.init_cbc = gv11b_fb_init_cbc; gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index b8a97ce3..5b98b0aa 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -53,10 +53,6 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); - reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); - reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true); - gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), reg); - gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(), gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) | ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m()); @@ -200,4 +196,5 @@ void gv11b_init_ltc(struct gpu_ops *gops) gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; gops->ltc.isr = gv11b_ltc_isr; + gops->ltc.init_cbc = NULL; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index 0ddccd45..e261ef14 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -1814,4 +1814,84 @@ static inline u32 fb_mmu_fault_status_valid_clear_f(void) { return 0x80000000; } +static inline u32 fb_mmu_num_active_ltcs_r(void) +{ + return 0x00100ec0; +} +static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 fb_mmu_cbc_base_r(void) +{ + return 0x00100ec4; +} +static inline u32 fb_mmu_cbc_base_address_f(u32 v) +{ + return (v & 0x3ffffff) << 0; +} +static inline u32 fb_mmu_cbc_base_address_v(u32 r) +{ + return (r >> 0) & 0x3ffffff; +} +static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 fb_mmu_cbc_top_r(void) +{ + return 0x00100ec8; +} +static inline u32 fb_mmu_cbc_top_size_f(u32 v) +{ + return (v & 0x7fff) << 0; +} +static inline u32 fb_mmu_cbc_top_size_v(u32 r) +{ + return (r >> 0) & 0x7fff; +} +static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 fb_mmu_cbc_max_r(void) +{ + return 0x00100ecc; +} +static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 fb_mmu_cbc_max_safe_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_cbc_max_safe_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_cbc_max_safe_false_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void) +{ + return 0x00000001; +} #endif -- cgit v1.2.2 From c37a7a577a5cf4732a32c7747f244aab19bdeaec Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 2 Jun 2017 18:08:27 -0700 Subject: gpu: nvgpu: gv11b: ltc reset seqeunce change Access ltc registers only after bringing ltc out reset. Earlier ltc bought out of reset in fb_reset which is later than accessing ltc registers. GPUT19X-70 Change-Id: Id3b0ac4ed8787a994b7a5848598e4989154a0940 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1495167 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 2 -- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 8 ++++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 3b3d775e..7698d968 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -135,14 +135,12 @@ static void gv11b_fb_reset(struct gk20a *g) nvgpu_info(g, "reset gv11b fb"); g->ops.mc.reset(g, mc_enable_pfb_enabled_f() | - mc_enable_l2_enabled_f() | mc_enable_xbar_enabled_f() | mc_enable_hub_enabled_f()); val = gk20a_readl(g, mc_elpg_enable_r()); val |= mc_elpg_enable_xbar_enabled_f() | mc_elpg_enable_pfb_enabled_f() | - mc_elpg_enable_l2_enabled_f() | mc_elpg_enable_hub_enabled_f(); gk20a_writel(g, mc_elpg_enable_r(), val); diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 5b98b0aa..38986382 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -22,6 +22,7 @@ #include #include #include +#include #include /* @@ -49,6 +50,13 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) gk20a_dbg_info("initialize gv11b l2"); + g->ops.mc.reset(g, mc_enable_pfb_enabled_f() | + mc_enable_l2_enabled_f()); + + reg = gk20a_readl(g, mc_elpg_enable_r()); + reg |= mc_elpg_enable_l2_enabled_f(); + gk20a_writel(g, mc_elpg_enable_r(), reg); + g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r()); g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); -- cgit v1.2.2 From 366386d1898af61eb425aa8b37cfb656ff898c1a Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 2 Jun 2017 14:47:20 +0530 Subject: gpu: nvgpu: add t19x specific nvhost abstraction files Add new abstraction file common/linux/nvhost_t19x.c for all nvhost APIs exported from linux/nvhost_t194.h This file will be compiled only if config CONFIG_TEGRA_GK20A_NVHOST is set Export the new headers from file Also add dummy private header file nvhost_priv_t19x.h to store definition of private structure nvgpu_nvhost_dev This file should be deleted when nvgpu-t19x repo is merged into common nvhost repo Jira NVGPU-29 Change-Id: I8c08c9242b08cc45f7c99cc400b3e1a720f9439c Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1493792 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/common/linux/nvhost_priv_t19x.h | 29 ++++++++++++++++++ drivers/gpu/nvgpu/common/linux/nvhost_t19x.c | 36 +++++++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h | 30 +++++++++++++++++++ 4 files changed, 96 insertions(+) create mode 100644 drivers/gpu/nvgpu/common/linux/nvhost_priv_t19x.h create mode 100644 drivers/gpu/nvgpu/common/linux/nvhost_t19x.c create mode 100644 drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index d1b6a67c..244b3ed3 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -20,3 +20,4 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/regops_gv11b.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o +nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += $(nvgpu-t19x)/common/linux/nvhost_t19x.o diff --git a/drivers/gpu/nvgpu/common/linux/nvhost_priv_t19x.h b/drivers/gpu/nvgpu/common/linux/nvhost_priv_t19x.h new file mode 100644 index 00000000..7ff6184d --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/nvhost_priv_t19x.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVGPU_NVHOST_PRIV_T19X_H__ +#define __NVGPU_NVHOST_PRIV_T19X_H__ + +/* + * This file is copy of common/linux/nvhost_priv.h in nvgpu repo + * This file should be removed when nvgpu-t19x repo is merged + * into common nvgpu repo + */ +struct nvgpu_nvhost_dev { + struct platform_device *host1x_pdev; +}; + +#endif /* __NVGPU_NVHOST_PRIV_T19X_H__ */ diff --git a/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c b/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c new file mode 100644 index 00000000..0bbb3d72 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include + +#include "nvhost_priv_t19x.h" + +int nvgpu_nvhost_syncpt_unit_interface_get_aperture( + struct nvgpu_nvhost_dev *nvhost_dev, + phys_addr_t *base, + size_t *size) +{ + return nvhost_syncpt_unit_interface_get_aperture( + nvhost_dev->host1x_pdev, base, size); +} + +u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id) +{ + return nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id); +} diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h new file mode 100644 index 00000000..c456687b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVGPU_NVHOST_T19X_H__ +#define __NVGPU_NVHOST_T19X_H__ + +#ifdef CONFIG_TEGRA_GK20A_NVHOST +struct nvgpu_nvhost_dev; + +int nvgpu_nvhost_syncpt_unit_interface_get_aperture( + struct nvgpu_nvhost_dev *nvhost_dev, + phys_addr_t *base, + size_t *size); +u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id); + +#endif +#endif /* __NVGPU_NVHOST_T19X_H__ */ -- cgit v1.2.2 From 5205ab23a29d6bb2d94eecae67ba344f438c5045 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 2 Jun 2017 14:51:08 +0530 Subject: gpu: nvgpu: use nvgpu specific nvhost APIs Remove use of linux specifix header files and and use nvgpu specific header file instead This is needed to remove all Linux dependencies from nvgpu driver Replace all nvhost_*() calls by nvgpu_nvhost_*() calls from new nvgpu library Jira NVGPU-29 Change-Id: I32d59628ca5ab3ece80a10eb5aefa150b1da448b Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1494648 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 9 +++---- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 33 ++++++++------------------ 2 files changed, 13 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 0dd0fc40..b018f3d9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -14,10 +14,6 @@ */ #include #include -#ifdef CONFIG_TEGRA_GK20A_NVHOST -#include -#include -#endif #include #include @@ -27,6 +23,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -1461,7 +1458,7 @@ static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, u32 id, u32 thresh, u64 gpu_va_base) { u64 gpu_va = gpu_va_base + - nvhost_syncpt_unit_interface_get_byte_offset(id); + nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(id); gk20a_dbg_fn(""); @@ -1497,7 +1494,7 @@ static void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, { u32 off = cmd->off; u64 gpu_va = gpu_va_base + - nvhost_syncpt_unit_interface_get_byte_offset(id); + nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(id); gk20a_dbg_fn(""); diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 4b600cdd..2b6f8759 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -19,9 +19,8 @@ #include #include #include -#ifdef CONFIG_TEGRA_GK20A_NVHOST -#include -#endif +#include +#include #include @@ -40,38 +39,26 @@ static void gr_gv11b_remove_sysfs(struct device *dev); static int gv11b_tegra_probe(struct device *dev) { - int err = 0; struct gk20a_platform *platform = dev_get_drvdata(dev); - struct gk20a *g = platform->g; - struct device_node *np = dev->of_node; - struct device_node *host1x_node; - struct platform_device *host1x_pdev; - const __be32 *host1x_ptr; - #ifdef CONFIG_TEGRA_GK20A_NVHOST - host1x_ptr = of_get_property(np, "nvidia,host1x", NULL); - if (!host1x_ptr) { - dev_err(dev, "host1x device not available"); - return -ENOSYS; - } + struct gk20a *g = platform->g; + int err = 0; - host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr)); - host1x_pdev = of_find_device_by_node(host1x_node); - if (!host1x_pdev) { + err = nvgpu_get_nvhost_dev(g); + if (err) { dev_err(dev, "host1x device not available"); - return -ENOSYS; + return err; } - platform->g->host1x_dev = host1x_pdev; - err = nvhost_syncpt_unit_interface_get_aperture( - g->host1x_dev, + err = nvgpu_nvhost_syncpt_unit_interface_get_aperture( + g->nvhost_dev, &g->syncpt_unit_base, &g->syncpt_unit_size); if (err) { dev_err(dev, "Failed to get syncpt interface"); return -ENOSYS; } - g->syncpt_size = nvhost_syncpt_unit_interface_get_byte_offset(1); + g->syncpt_size = nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(1); gk20a_dbg_info("syncpt_unit_base %llx syncpt_unit_size %zx size %x\n", g->syncpt_unit_base, g->syncpt_unit_size, g->syncpt_size); -- cgit v1.2.2 From 002d6f147490cd5b3002ce5a564f4276df784ea6 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 10 May 2017 17:18:01 +0530 Subject: gpu: nvgpu: PMU IPC reorg support update - prepend PMU IPC func with nvgpu_ by replacing gk20a_ - updated gv11b HAL methods of queue & mutex to point to gk20a HAL methods. JIRA NVGPU-56 Change-Id: Iade9f5613dbd4bc11515e822ddfda3a1787bfa4f Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1479117 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 16 ++++++++-------- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 4 ++++ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b018f3d9..847bf172 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -718,12 +718,12 @@ static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); - mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); ret = __locked_fifo_preempt(g, hw_chid, false); if (!mutex_ret) - pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); @@ -770,12 +770,12 @@ static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); - mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); ret = __locked_fifo_preempt(g, tsgid, true); if (!mutex_ret) - pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); @@ -798,12 +798,12 @@ static int gv11b_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) runlist_info[runlist_id].mutex); } - mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); ret = __locked_fifo_preempt_runlists(g, runlists_mask); if (!mutex_ret) - pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); for (runlist_id = 0; runlist_id < g->fifo.max_runlists; runlist_id++) { if (runlists_mask & fifo_runlist_preempt_runlist_m(runlist_id)) @@ -858,12 +858,12 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); - mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); ret = __locked_fifo_preempt_ch_tsg(g, id, id_type, timeout_rc_type); if (!mutex_ret) - pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 35246138..4c2b6dca 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -158,5 +158,9 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; + gops->pmu.pmu_queue_head = gk20a_pmu_queue_head; + gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail; + gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; + gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; } -- cgit v1.2.2 From 9cb4cc5d07e8a894f7d0c3ea5ea932291df32c36 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 8 Jun 2017 12:55:51 +0530 Subject: gpu: nvgpu: remove duplicate nvhost_priv_t19x.h We added duplicate common/linux/nvhost_priv_t19x.h so that the definition of struct nvgpu_nvhost_dev is available in nvgpu-t19x repo But instead of duplicating the file, directly include original file with path #include "common/linux/nvhost_priv.h Jira NVGPU-29 Change-Id: I5d373227f0f6b2b4670d2fd3ad433a4655df8e4f Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1499167 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/common/linux/nvhost_priv_t19x.h | 29 ----------------------- drivers/gpu/nvgpu/common/linux/nvhost_t19x.c | 2 +- 2 files changed, 1 insertion(+), 30 deletions(-) delete mode 100644 drivers/gpu/nvgpu/common/linux/nvhost_priv_t19x.h diff --git a/drivers/gpu/nvgpu/common/linux/nvhost_priv_t19x.h b/drivers/gpu/nvgpu/common/linux/nvhost_priv_t19x.h deleted file mode 100644 index 7ff6184d..00000000 --- a/drivers/gpu/nvgpu/common/linux/nvhost_priv_t19x.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef __NVGPU_NVHOST_PRIV_T19X_H__ -#define __NVGPU_NVHOST_PRIV_T19X_H__ - -/* - * This file is copy of common/linux/nvhost_priv.h in nvgpu repo - * This file should be removed when nvgpu-t19x repo is merged - * into common nvgpu repo - */ -struct nvgpu_nvhost_dev { - struct platform_device *host1x_pdev; -}; - -#endif /* __NVGPU_NVHOST_PRIV_T19X_H__ */ diff --git a/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c b/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c index 0bbb3d72..0b2ae08c 100644 --- a/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c @@ -19,7 +19,7 @@ #include -#include "nvhost_priv_t19x.h" +#include "common/linux/nvhost_priv.h" int nvgpu_nvhost_syncpt_unit_interface_get_aperture( struct nvgpu_nvhost_dev *nvhost_dev, -- cgit v1.2.2 From 263cb402293d2050d7d08212e89e4c1dcb1d4ccc Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Sat, 10 Jun 2017 11:38:23 +0530 Subject: gpu: nvgpu: PMU init reorg support update -Updated gv11b HAL, pmu_msgq_tail & pmu_mutex_size to point to gk20a_pmu_msgq_tail() & pwr_pmu_mutex__size_1_v() JIRA NVGPU-56 JIRA NVGPU-92 Change-Id: I8fe271f778fc2d70360f8a508f36d0bfce6b341d Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1499701 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 4c2b6dca..2376e66e 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -162,5 +162,7 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail; gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; + gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; + gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; } -- cgit v1.2.2 From 4f0e19d44dee9039378bce7bd0cfb11f36fd8926 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 7 Jun 2017 13:17:22 -0700 Subject: gpu: nvgpu: gv11b: issue tsg preempt only Preempt type should be set to tsg and id should be set to tsgid in fifo_preempt_r(). Preempt type channel and id set to channel id does not initiate preemption. Bug 200289427 Bug 200292090 Bug 200289491 Change-Id: I2ae96c0b9ca8a88a8405f42775744f0879994887 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1497877 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 35 +++++++++++++---------------------- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 13 ++++++++----- 2 files changed, 21 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 847bf172..90295f52 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -706,28 +706,13 @@ static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) { struct fifo_gk20a *f = &g->fifo; - u32 ret = 0; - u32 token = PMU_INVALID_MUTEX_OWNER_ID; - u32 mutex_ret = 0; - u32 runlist_id; - - gk20a_dbg_fn("%d", hw_chid); - - runlist_id = f->channel[hw_chid].runlist_id; - gk20a_dbg_fn("runlist_id %d", runlist_id); - - nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); - - mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); - - ret = __locked_fifo_preempt(g, hw_chid, false); - - if (!mutex_ret) - nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + u32 tsgid; - nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); + tsgid = f->channel[hw_chid].tsgid; + nvgpu_log_info(g, "chid:%d tsgid:%d", hw_chid, tsgid); - return ret; + /* Preempt tsg. Channel preempt is NOOP */ + return g->ops.fifo.preempt_tsg(g, tsgid); } static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) @@ -818,9 +803,15 @@ static int __locked_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type) { int ret; + struct fifo_gk20a *f = &g->fifo; - /* issue preempt */ - gk20a_fifo_issue_preempt(g, id, id_type); + nvgpu_log_fn(g, "id:%d id_type:%d", id, id_type); + + /* Issue tsg preempt. Channel preempt is noop */ + if (id_type == ID_TYPE_CHANNEL) + gk20a_fifo_issue_preempt(g, f->channel[id].tsgid, true); + else + gk20a_fifo_issue_preempt(g, id, true); /* wait for preempt */ ret = g->ops.fifo.is_preempt_pending(g, id, id_type, diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 503fb6f7..a703e72c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1593,12 +1593,15 @@ static int gr_gv11b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist"); - if (gk20a_is_channel_marked_as_tsg(fault_ch)) + if (gk20a_is_channel_marked_as_tsg(fault_ch)) { gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true); - else - gk20a_fifo_issue_preempt(g, fault_ch->hw_chid, false); - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: preempted the channel/tsg"); + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: preempted the channel/tsg"); + } else { + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: tsgid is invalid, cannot preempt"); + WARN_ON(1); /* only TSG can be preempted */ + } return ret; } -- cgit v1.2.2 From 12a8f51aa7a056d070861b120fc945d946bc10f9 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 9 Jun 2017 16:19:17 -0700 Subject: gpu: nvgpu: gv11b: disable skedcheck18_l1_config_too_small SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL disabled Bug 200315442 Change-Id: I6d5c5f2fe6255d480350e01959c3c340579646e2 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1499568 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 22 ++++++++++++++++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 20 ++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index a703e72c..542ed1ff 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -285,6 +285,27 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, } +static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) +{ + u32 val; + + /* enable exceptions */ + gk20a_writel(g, gr_fe_hww_esr_r(), + gr_fe_hww_esr_en_enable_f() | + gr_fe_hww_esr_reset_active_f()); + gk20a_writel(g, gr_memfmt_hww_esr_r(), + gr_memfmt_hww_esr_en_enable_f() | + gr_memfmt_hww_esr_reset_active_f()); + /* WAR for 200315442 */ + val = gk20a_readl(g, gr_sked_hww_esr_en_r()); + val = set_field(val, + gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), + gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f() + ); + nvgpu_log_info(g, "sked_hww_esr_en = 0x%x", val); + gk20a_writel(g, gr_sked_hww_esr_en_r(), val); +} + static void gr_gv11b_enable_exceptions(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; @@ -2518,6 +2539,7 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; gops->gr.enable_exceptions = gr_gv11b_enable_exceptions; + gops->gr.enable_hww_exceptions = gr_gv11b_enable_hww_exceptions; gops->gr.mask_hww_warp_esr = gv11b_mask_hww_warp_esr; gops->gr.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 62307265..29a8b33c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -4634,4 +4634,24 @@ static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { return (r >> 16) & 0xffff; } +static inline u32 gr_sked_hww_esr_en_r(void) +{ + return 0x00407024; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) +{ + return 0x1 << 25; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 gr_exception_sked_m(void) +{ + return 0x1 << 8; +} #endif -- cgit v1.2.2 From e50d046ab4354a990d304316630d6aac3c4e9d76 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 8 Jun 2017 15:49:18 +0530 Subject: gpu: nvgpu: PMU PG reorg support update - Prepend ELPG enable/disable methods with nvgpu_ by replacing gk20a_ in gv11b JIRA NVGPU-97 Change-Id: I8900f7635e30578040afa71e0bd470ee835a4748 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1498400 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 90295f52..a86a9509 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -889,7 +889,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, /* Disable power management */ if (g->support_pmu && g->elpg_enabled) { - if (gk20a_pmu_disable_elpg(g)) + if (nvgpu_pmu_disable_elpg(g)) nvgpu_err(g, "failed to set disable elpg"); } if (g->ops.clock_gating.slcg_gr_load_gating_prod) @@ -1018,7 +1018,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, /* It is safe to enable ELPG again. */ if (g->support_pmu && g->elpg_enabled) - gk20a_pmu_enable_elpg(g); + nvgpu_pmu_enable_elpg(g); } static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) -- cgit v1.2.2 From 3afd4af3a73b17317021f3dbca02dbc806a0fc5f Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Fri, 26 May 2017 11:43:36 +0530 Subject: nvgpu: nvgpu: gv11b: Add/Update PMU cmds for ELPG. This patch: - Adds a PMU command needed for enabling ELPG. i.e. command to update sub-feature mask to enable ELPG. - Adds a new version of PG-GR init param command function which uses updated command interface. JIRA GPUT19X-20. Change-Id: If969c018e2e28264fdc9c897892eb28b021d12f2 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1504873 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 89 +++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 2376e66e..ef4a715d 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -27,6 +27,9 @@ #include +#define gv11b_dbg_pmu(fmt, arg...) \ + gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) + #define ALIGN_4KB 12 static bool gv11b_is_pmu_supported(struct gk20a *g) @@ -147,6 +150,90 @@ static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) return 0; } +static void pmu_handle_pg_sub_feature_msg(struct gk20a *g, struct pmu_msg *msg, + void *param, u32 handle, u32 status) +{ + gk20a_dbg_fn(""); + + if (status != 0) { + nvgpu_err(g, "Sub-feature mask update cmd aborted\n"); + return; + } + + gv11b_dbg_pmu("sub-feature mask update is acknowledged from PMU %x\n", + msg->msg.pg.msg_type); +} + +static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg, + void *param, u32 handle, u32 status) +{ + gk20a_dbg_fn(""); + + if (status != 0) { + nvgpu_err(g, "GR PARAM cmd aborted\n"); + return; + } + + gv11b_dbg_pmu("GR PARAM is acknowledged from PMU %x\n", + msg->msg.pg.msg_type); +} + +static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) +{ + struct nvgpu_pmu *pmu = &g->pmu; + struct pmu_cmd cmd; + u32 seq; + + if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_PG; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_pg_cmd_gr_init_param_v1); + cmd.cmd.pg.gr_init_param_v1.cmd_type = + PMU_PG_CMD_ID_PG_PARAM; + cmd.cmd.pg.gr_init_param_v1.sub_cmd_id = + PMU_PG_PARAM_CMD_GR_INIT_PARAM; + cmd.cmd.pg.gr_init_param_v1.featuremask = + PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; + + gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n"); + gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + pmu_handle_pg_param_msg, pmu, &seq, ~0); + + } else + return -EINVAL; + + return 0; +} + +static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) +{ + struct nvgpu_pmu *pmu = &g->pmu; + struct pmu_cmd cmd; + u32 seq; + + if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_PG; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_pg_cmd_sub_feature_mask_update); + cmd.cmd.pg.sf_mask_update.cmd_type = + PMU_PG_CMD_ID_PG_PARAM; + cmd.cmd.pg.sf_mask_update.sub_cmd_id = + PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE; + cmd.cmd.pg.sf_mask_update.ctrl_id = + PMU_PG_ELPG_ENGINE_ID_GRAPHICS; + cmd.cmd.pg.sf_mask_update.enabled_mask = + PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; + + gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); + gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + pmu_handle_pg_sub_feature_msg, pmu, &seq, ~0); + } else + return -EINVAL; + + return 0; +} void gv11b_init_pmu_ops(struct gpu_ops *gops) { @@ -165,4 +252,6 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; + gops->pmu.pmu_pg_init_param = gv11b_pg_gr_init; + gops->pmu.pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask; } -- cgit v1.2.2 From 47eed280133ee75327942539c6d07e9b89d237f4 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 15 Jun 2017 16:07:05 -0700 Subject: gpu: nvgpu: gv11b: fb_flush before/after l2_flush After enabling l2 write back in gv11b, for committing all dirty data to sysmem correctly: Added one fb_flush before l2_flush to commit dirty hshub data to l2/sysmem. Added one more fb_flush after l2_flush, to commit any new dirty data on hshub to sysmem. This done by implementing gv11b specific l2_flush function. Bug 1937331 Change-Id: Ie30edb12c98c4021783c88750bb4c4ca62e4a7ca Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1503385 Reviewed-by: Alex Waterman Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 269108ff..9d1e0f25 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -52,6 +52,15 @@ static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) return false; } +void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) +{ + nvgpu_log(g, gpu_dbg_fn, "gv11b_mm_l2_flush"); + + g->ops.mm.fb_flush(g); + gk20a_mm_l2_flush(g, invalidate); + g->ops.mm.fb_flush(g); +} + void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); @@ -59,4 +68,5 @@ void gv11b_init_mm(struct gpu_ops *gops) gops->mm.init_inst_block = gv11b_init_inst_block; gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; + gops->mm.l2_flush = gv11b_mm_l2_flush; } -- cgit v1.2.2 From 492c7cc198f3315b468fa3d612d894edf2bb5e89 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 19 Jun 2017 17:40:45 -0700 Subject: gpu: nvgpu: gv11b: make subcontext mappings non-cacheable Without non-cacheable, gpu filled subcontext data not visible to cpu without additional l2 flush. Similarly, there will be issues where cpu updates to subcontext header will not visible to gpu without additional l2 flush. Making subcontext header mapping non-cacheable fixes this issue. Bug 1937331 Change-Id: I8e25b7cac165e7481eec7c9f1f93bc7992183c46 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1505283 Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 6aa58337..79ed0d1e 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -66,7 +66,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm, &ctx->mem, ctx->mem.size, - NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_FALSE, gk20a_mem_flag_none, true, ctx->mem.aperture); if (!ctx->mem.gpu_va) { -- cgit v1.2.2 From ca76b41a642209418562c1899fdb1f0b1af4b889 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 19 Jun 2017 14:35:48 -0700 Subject: gpu: nvgpu: gv11b: Merge tegra/linux to common/linux tegra/linux path was created to separate Tegra kernel specific dependencies from common Linux specific dependencies. The split has not really worked, so merge tegra/linux to common/linux. JIRA NVGPU-38 Change-Id: I9efe078bfa5dfbef49408db9d8a3738dfda8bd1d Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1505169 Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 2b6f8759..fee4ebbf 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -26,12 +26,12 @@ #include "gk20a/platform_gk20a.h" #include "gk20a/gk20a.h" -#include "tegra/linux/clk.h" +#include "common/linux/clk.h" #include "gp10b/platform_gp10b.h" -#include "tegra/linux/platform_gp10b_tegra.h" +#include "common/linux/platform_gp10b_tegra.h" -#include "tegra/linux/platform_gk20a_tegra.h" +#include "common/linux/platform_gk20a_tegra.h" #include "gr_gv11b.h" #include "nvgpu_gpuid_t19x.h" -- cgit v1.2.2 From cdcbda97e64ec7b57f60c0183698ca41004378a0 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 7 Jun 2017 16:59:47 -0700 Subject: gpu: nvgpu: gv11b: fbhub: num_ltcs are read only In gv11b fbhub num_ltcs is read only, even though register spec says it is rw. The number of ltcs are populated by hw and no need for sw to set those values. GPUT19X-70 Change-Id: Ib9861894cacb70cf54b4958083e55d39a3a85e19 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1497992 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 7698d968..21d8cba3 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -67,12 +67,9 @@ static void gv11b_fb_init_fs_state(struct gk20a *g) { nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb"); - nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %u", + nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %x", gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); - gk20a_writel(g, fb_mmu_num_active_ltcs_r(), - fb_mmu_num_active_ltcs_count_f(g->ltc_count)); - nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u", fb_mmu_num_active_ltcs_count_v( gk20a_readl(g, fb_mmu_num_active_ltcs_r()))); -- cgit v1.2.2 From af02a002457533bebf1f77d58b8f83867a1c0c1c Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 20 Apr 2017 14:56:25 +0530 Subject: gpu: nvgpu: gv11b hw header for Falcon controller Change-Id: I21fc23fe2b5636b295b7bd1a0ef96cfba713408f Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1466610 Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 557 +++++++++++++++++++++ 1 file changed, 557 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h new file mode 100644 index 00000000..6bdc5fd1 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -0,0 +1,557 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_falcon_gv11b_h_ +#define _hw_falcon_gv11b_h_ + +static inline u32 falcon_falcon_irqsset_r(void) +{ + return 0x00000000; +} +static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40; +} +static inline u32 falcon_falcon_irqsclr_r(void) +{ + return 0x00000004; +} +static inline u32 falcon_falcon_irqstat_r(void) +{ + return 0x00000008; +} +static inline u32 falcon_falcon_irqstat_halt_true_f(void) +{ + return 0x10; +} +static inline u32 falcon_falcon_irqstat_exterr_true_f(void) +{ + return 0x20; +} +static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40; +} +static inline u32 falcon_falcon_irqmode_r(void) +{ + return 0x0000000c; +} +static inline u32 falcon_falcon_irqmset_r(void) +{ + return 0x00000010; +} +static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 falcon_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 falcon_falcon_irqmclr_r(void) +{ + return 0x00000014; +} +static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 falcon_falcon_irqmask_r(void) +{ + return 0x00000018; +} +static inline u32 falcon_falcon_irqdest_r(void) +{ + return 0x0000001c; +} +static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 falcon_falcon_curctx_r(void) +{ + return 0x00000050; +} +static inline u32 falcon_falcon_nxtctx_r(void) +{ + return 0x00000054; +} +static inline u32 falcon_falcon_mailbox0_r(void) +{ + return 0x00000040; +} +static inline u32 falcon_falcon_mailbox1_r(void) +{ + return 0x00000044; +} +static inline u32 falcon_falcon_itfen_r(void) +{ + return 0x00000048; +} +static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1; +} +static inline u32 falcon_falcon_idlestate_r(void) +{ + return 0x0000004c; +} +static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1) & 0x7fff; +} +static inline u32 falcon_falcon_os_r(void) +{ + return 0x00000080; +} +static inline u32 falcon_falcon_engctl_r(void) +{ + return 0x000000a4; +} +static inline u32 falcon_falcon_cpuctl_r(void) +{ + return 0x00000100; +} +static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1 << 4; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1 << 6; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 falcon_falcon_cpuctl_alias_r(void) +{ + return 0x00000130; +} +static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 falcon_falcon_imemc_r(u32 i) +{ + return 0x00000180 + i*16; +} +static inline u32 falcon_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 falcon_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 falcon_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 falcon_falcon_imemd_r(u32 i) +{ + return 0x00000184 + i*16; +} +static inline u32 falcon_falcon_imemt_r(u32 i) +{ + return 0x00000188 + i*16; +} +static inline u32 falcon_falcon_sctl_r(void) +{ + return 0x00000240; +} +static inline u32 falcon_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4; +} +static inline u32 falcon_falcon_bootvec_r(void) +{ + return 0x00000104; +} +static inline u32 falcon_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 falcon_falcon_dmactl_r(void) +{ + return 0x0000010c; +} +static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 falcon_falcon_hwcfg_r(void) +{ + return 0x00000108; +} +static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9) & 0x1ff; +} +static inline u32 falcon_falcon_hwcfg1_r(void) +{ + return 0x0000012c; +} +static inline u32 falcon_falcon_hwcfg1_core_rev_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 falcon_falcon_hwcfg1_security_model_v(u32 r) +{ + return (r >> 4) & 0x3; +} +static inline u32 falcon_falcon_dmatrfbase_r(void) +{ + return 0x00000110; +} +static inline u32 falcon_falcon_dmatrfbase1_r(void) +{ + return 0x00000128; +} +static inline u32 falcon_falcon_dmatrfmoffs_r(void) +{ + return 0x00000114; +} +static inline u32 falcon_falcon_dmatrfcmd_r(void) +{ + return 0x00000118; +} +static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 falcon_falcon_dmatrffboffs_r(void) +{ + return 0x0000011c; +} +static inline u32 falcon_falcon_exterraddr_r(void) +{ + return 0x00000168; +} +static inline u32 falcon_falcon_exterrstat_r(void) +{ + return 0x0000016c; +} +static inline u32 falcon_falcon_exterrstat_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 falcon_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 falcon_falcon_icd_cmd_r(void) +{ + return 0x00000200; +} +static inline u32 falcon_falcon_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 falcon_falcon_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 falcon_falcon_icd_rdata_r(void) +{ + return 0x0000020c; +} +static inline u32 falcon_falcon_dmemc_r(u32 i) +{ + return 0x000001c0 + i*8; +} +static inline u32 falcon_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 falcon_falcon_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 falcon_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 falcon_falcon_dmemc_blk_m(void) +{ + return 0xff << 8; +} +static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 falcon_falcon_dmemd_r(u32 i) +{ + return 0x000001c4 + i*8; +} +static inline u32 falcon_falcon_debug1_r(void) +{ + return 0x00000090; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) +{ + return 1; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) +{ + return 0x1 << 16; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) +{ + return 0x0; +} +static inline u32 falcon_falcon_debuginfo_r(void) +{ + return 0x00000094; +} +#endif -- cgit v1.2.2 From b8c92ae1d8b7f2fcee006729fd55f5c315ba9349 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 24 Apr 2017 22:58:53 -0700 Subject: gpu: nvgpu: gv11b: enable sync point support JIRA GPUT19X-2 Change-Id: If69567af3f6de6cd65429086578715fb4d6dfeb5 Signed-off-by: seshendra Gadagottu Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1323440 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index fee4ebbf..acec2d3a 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -114,7 +114,7 @@ static int gv11b_tegra_suspend(struct device *dev) } struct gk20a_platform t19x_gpu_tegra_platform = { - .has_syncpoints = false, + .has_syncpoints = true, /* power management configuration */ -- cgit v1.2.2 From f500f45ebf7c658d67ec6001d2e88105d7e3f875 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Jun 2017 16:31:27 -0700 Subject: gpu: nvgpu: gv11b: implement ctxnotvalid pbdma_intr_1 Pbdma which encountered the ctxnotvalid interrupt will stall and prevent the channel which was loaded at the time the interrupt fired from being swapped out until the interrupt is cleared. CTXNOTVALID pbdma interrupt indicates error conditions related to the *_CTX_VALID fields for a channel. The following conditions trigger the interrupt: * CTX_VALID bit for the targeted engine is FALSE * At channel start/resume, all preemptible eng have CTX_VALID FALSE but: - CTX_RELOAD is set in CCSR_CHANNEL_STATUS, - PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT is TRUE, or - PBDMA_TARGET_NEEDS_HOST_TSG_EVENT is TRUE JIRA GPUT19X-47 Change-Id: If65ce1fcdbaebd6b1d8313fdddf9e3e0fa51e885 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1329372 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 59 ++++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 8 +++ 2 files changed, 67 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index a86a9509..5425eaa0 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1401,6 +1401,63 @@ static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, return rc_type; } +/* + * Pbdma which encountered the ctxnotvalid interrupt will stall and + * prevent the channel which was loaded at the time the interrupt fired + * from being swapped out until the interrupt is cleared. + * CTXNOTVALID pbdma interrupt indicates error conditions related + * to the *_CTX_VALID fields for a channel. The following + * conditions trigger the interrupt: + * * CTX_VALID bit for the targeted engine is FALSE + * * At channel start/resume, all preemptible eng have CTX_VALID FALSE but: + * - CTX_RELOAD is set in CCSR_CHANNEL_STATUS, + * - PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT is TRUE, or + * - PBDMA_TARGET_NEEDS_HOST_TSG_EVENT is TRUE + * The field is left NOT_PENDING and the interrupt is not raised if the PBDMA is + * currently halted. This allows SW to unblock the PBDMA and recover. + * SW may read METHOD0, CHANNEL_STATUS and TARGET to determine whether the + * interrupt was due to an engine method, CTX_RELOAD, SHOULD_SEND_HOST_TSG_EVENT + * or NEEDS_HOST_TSG_EVENT. If METHOD0 VALID is TRUE, lazy context creation + * can be used or the TSG may be destroyed. + * If METHOD0 VALID is FALSE, the error is likely a bug in SW, and the TSG + * will have to be destroyed. + */ + +static unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_1, + u32 *handled, u32 *error_notifier) +{ + unsigned int rc_type = RC_TYPE_PBDMA_FAULT; + u32 pbdma_intr_1_current = gk20a_readl(g, pbdma_intr_1_r(pbdma_id)); + + /* minimize race with the gpu clearing the pending interrupt */ + if (!(pbdma_intr_1_current & + pbdma_intr_1_ctxnotvalid_pending_f())) + pbdma_intr_1 &= ~pbdma_intr_1_ctxnotvalid_pending_f(); + + if (pbdma_intr_1 == 0) + return RC_TYPE_NO_RC; + + if (pbdma_intr_1 & pbdma_intr_1_ctxnotvalid_pending_f()) { + gk20a_dbg(gpu_dbg_intr, "ctxnotvalid intr on pbdma id %d", + pbdma_id); + nvgpu_err(g, "pbdma_intr_1(%d)= 0x%08x ", + pbdma_id, pbdma_intr_1); + *handled |= pbdma_intr_1_ctxnotvalid_pending_f(); + } else{ + /* + * rest of the interrupts in _intr_1 are "host copy engine" + * related, which is not supported. For now just make them + * channel fatal. + */ + nvgpu_err(g, "hce err: pbdma_intr_1(%d):0x%08x", + pbdma_id, pbdma_intr_1); + *handled |= pbdma_intr_1; + } + + return rc_type; +} + #ifdef CONFIG_TEGRA_GK20A_NVHOST static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf) @@ -1554,6 +1611,8 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; gops->fifo.handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0; + gops->fifo.handle_pbdma_intr_1 = + gv11b_fifo_handle_pbdma_intr_1; #ifdef CONFIG_TEGRA_GK20A_NVHOST gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf; gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index ed63cebc..abdbc17d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -502,6 +502,14 @@ static inline u32 pbdma_intr_1_r(u32 i) { return 0x00040148 + i*8192; } +static inline u32 pbdma_intr_1_ctxnotvalid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) +{ + return 0x80000000; +} static inline u32 pbdma_intr_en_0_r(u32 i) { return 0x0004010c + i*8192; -- cgit v1.2.2 From 5107bda90a1e55d4850a8f1c27008f05c420b4ec Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 21 Jun 2017 23:36:59 +0530 Subject: gpu: nvgpu: gv11b, use nvgpu_flcn_copy_to_dmem() - replace usage of pmu_copy_to_dmem() with nvgpu_flcn_copy_to_dmem() JIRA NVGPU-99 Change-Id: I8d0ce1cb7adffc4df57044b8887d525c1f2f0237 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1506582 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index ef4a715d..01dc207c 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -73,7 +73,7 @@ static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) << GK20A_PMU_DMEM_BLKSIZE2) - g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); - pmu_copy_to_dmem(pmu, addr_args, + nvgpu_flcn_copy_to_dmem(pmu->flcn, addr_args, (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); -- cgit v1.2.2 From 5572bfa86a6afc7ae3c2f4a61e568f8e759c6ecc Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 22 Jun 2017 14:43:05 -0700 Subject: gpu: nvgpu: gv11b: sw method for NVC397_SET_TEX_IN_DBG Added sw method for NVC397_SET_TEX_IN_DBG with following data fields: data:0 PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE data:1 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD data:2 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST Bug 1934197 Change-Id: I0956d3f5c859ac23e16fb6b7372acd098dfb6d16 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master/r/1507479 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Tested-by: Wei Sun Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 28 +++++++++++++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 5 ++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 32 ++++++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 542ed1ff..7993e071 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1069,6 +1069,31 @@ static void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data) gk20a_dbg_fn("done"); } +static void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data) +{ + u32 val; + bool flag; + + gk20a_dbg_fn(""); + + val = gk20a_readl(g, gr_gpcs_tpcs_tex_in_dbg_r()); + flag = (data & NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE) ? 1 : 0; + val = set_field(val, gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(), + gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(flag)); + gk20a_writel(g, gr_gpcs_tpcs_tex_in_dbg_r(), val); + + val = gk20a_readl(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r()); + flag = (data & + NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD) ? 1 : 0; + val = set_field(val, gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(), + gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(flag)); + flag = (data & + NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST) ? 1 : 0; + val = set_field(val, gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(), + gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(flag)); + gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); +} + static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) { @@ -1120,6 +1145,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, case NVC097_SET_COALESCE_BUFFER_SIZE: gr_gv11b_set_coalesce_buffer_size(g, data); break; + case NVC397_SET_TEX_IN_DBG: + gr_gv11b_set_tex_in_dbg(g, data); + break; default: goto fail; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 9283a597..ff5782d9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -39,6 +39,11 @@ enum { #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC397_SET_TEX_IN_DBG 0x10bc + +#define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 +#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 +#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4 #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 29a8b33c..75a64be5 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3830,6 +3830,38 @@ static inline u32 gr_zcull_subregion_qty_v(void) { return 0x00000010; } +static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) +{ + return 0x00419a00; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) +{ + return 0x1 << 19; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) +{ + return 0x00419bf0; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) +{ + return 0x1 << 10; +} static inline u32 gr_fe_pwr_mode_r(void) { return 0x00404170; -- cgit v1.2.2 From a64984e7592bcd60a2dad1be8f1d24700a2e54de Mon Sep 17 00:00:00 2001 From: Sunny He Date: Thu, 22 Jun 2017 16:46:48 -0700 Subject: gpu: nvgpu: Reorganize ltc HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ltc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: If8760efb7d8e94b63dc6f1fe9efec4ddf49c0b29 Signed-off-by: Sunny He Reviewed-on: https://git-master/r/1507563 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 24 ++++++++++++++++++++---- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 20 ++++---------------- drivers/gpu/nvgpu/gv11b/ltc_gv11b.h | 10 ++++++++-- 3 files changed, 32 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0cdb471b..35b1fdc5 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,8 +25,10 @@ #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" +#include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" +#include "gp10b/ltc_gp10b.h" #include "gp10b/priv_ring_gp10b.h" #include "hal_gv11b.h" @@ -50,9 +52,23 @@ #include -static struct gpu_ops gv11b_ops; - -static struct gpu_ops gv11b_ops = { +static const struct gpu_ops gv11b_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = gv11b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gv11b_ltc_isr, + .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gp10b_ltc_sync_debugfs, +#endif + }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, @@ -187,6 +203,7 @@ int gv11b_init_hal(struct gk20a *g) struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; /* boot in non-secure modes for time beeing */ @@ -196,7 +213,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_bus(gops); gv11b_init_mc(gops); gp10b_init_priv_ring(gops); - gv11b_init_ltc(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 38986382..b1d85c5a 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -14,7 +14,6 @@ */ #include "gk20a/gk20a.h" - #include "gp10b/ltc_gp10b.h" #include "ltc_gv11b.h" @@ -28,7 +27,7 @@ /* * Sets the ZBC stencil for the passed index. */ -static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, +void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, struct zbc_entry *stencil_val, u32 index) { @@ -43,7 +42,7 @@ static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); } -static void gv11b_ltc_init_fs_state(struct gk20a *g) +void gv11b_ltc_init_fs_state(struct gk20a *g) { u32 ltc_intr; u32 reg; @@ -79,7 +78,7 @@ static void gv11b_ltc_init_fs_state(struct gk20a *g) ltc_intr); } -static void gv11b_ltc_isr(struct gk20a *g) +void gv11b_ltc_isr(struct gk20a *g) { u32 mc_intr, ltc_intr3; unsigned int ltc, slice; @@ -184,7 +183,7 @@ static void gv11b_ltc_isr(struct gk20a *g) gp10b_ltc_isr(g); } -static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) +u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) { u32 val = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); @@ -195,14 +194,3 @@ static u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base) } return base; } - - -void gv11b_init_ltc(struct gpu_ops *gops) -{ - gp10b_init_ltc(gops); - gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; - gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; - gops->ltc.cbc_fix_config = gv11b_ltc_cbc_fix_config; - gops->ltc.isr = gv11b_ltc_isr; - gops->ltc.init_cbc = NULL; -} diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h index 0b8b9459..e371afea 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,5 +15,11 @@ #define LTC_GV11B_H struct gk20a; -void gv11b_init_ltc(struct gpu_ops *gops); +void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, + struct zbc_entry *stencil_val, + u32 index); +void gv11b_ltc_init_fs_state(struct gk20a *g); +void gv11b_ltc_isr(struct gk20a *g); +u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base); + #endif -- cgit v1.2.2 From 56eaeab512fb848492d398e62ef55a2c963cc7a6 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 3 May 2017 16:08:14 -0700 Subject: gpu: nvgpu: gv11b: sm stride litter added Required to support multiple SM JIRA GPUT19X-75 Change-Id: I1fd0530550ae14270a5e746d2efbf3e913ac4c3e Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1475985 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: David Martinez Nieto --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++++ drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 35b1fdc5..0e874c8a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -191,6 +191,10 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_FBPA_STRIDE: ret = proj_fbpa_stride_v(); break; + case GPU_LIT_SM_PRI_STRIDE: + ret = proj_sm_stride_v(); + break; + default: break; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 98acee4c..a6515ba9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -154,4 +154,8 @@ static inline u32 proj_scal_max_tpc_per_gpc_v(void) { return 0x00000008; } +static inline u32 proj_sm_stride_v(void) +{ + return 0x00000080; +} #endif -- cgit v1.2.2 From 7681d6b007755e16f55951a1491a38faff8c72e9 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 20 Jun 2017 13:27:39 -0700 Subject: gpu: nvgpu: gv11b: reuse gp10b functions reuse gr_gp10b_handle_fecs_error and cilp functions Bug 200289491 Change-Id: I4040f96875ad91d174ce36aab957fb94d79c3a74 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1505952 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 223 +------------------------------------ 1 file changed, 6 insertions(+), 217 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 7993e071..41892746 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -32,6 +32,8 @@ #include "gm20b/gr_gm20b.h" +#include "gp10b/gr_gp10b.h" + #include "gv11b/gr_gv11b.h" #include "gv11b/mm_gv11b.h" #include "gv11b/subctx_gv11b.h" @@ -1622,145 +1624,6 @@ static void gr_gv11b_get_access_map(struct gk20a *g, *num_entries = ARRAY_SIZE(wl_addr_gv11b); } -static int gr_gv11b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a *fault_ch) -{ - int ret = 0; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); - - ret = gk20a_disable_channel_tsg(g, fault_ch); - if (ret) { - nvgpu_err(g, "CILP: failed to disable channel/TSG!"); - return ret; - } - - ret = g->ops.fifo.update_runlist(g, fault_ch->runlist_id, ~0, true, false); - if (ret) { - nvgpu_err(g, "CILP: failed to restart runlist 0!"); - return ret; - } - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist"); - - if (gk20a_is_channel_marked_as_tsg(fault_ch)) { - gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true); - nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: preempted the channel/tsg"); - } else { - nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: tsgid is invalid, cannot preempt"); - WARN_ON(1); /* only TSG can be preempted */ - } - - return ret; -} - -static int gr_gv11b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk20a *fault_ch) -{ - int ret; - struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); - - if (!gr_ctx) - return -EINVAL; - - if (gr_ctx->t18x.cilp_preempt_pending) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP is already pending for chid %d", - fault_ch->hw_chid); - return 0; - } - - /* get ctx_id from the ucode image */ - if (!gr_ctx->t18x.ctx_id_valid) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: looking up ctx id"); - ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->t18x.ctx_id); - if (ret) { - nvgpu_err(g, "CILP: error looking up ctx id!"); - return ret; - } - gr_ctx->t18x.ctx_id_valid = true; - } - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: ctx id is 0x%x", gr_ctx->t18x.ctx_id); - - /* send ucode method to set ctxsw interrupt */ - ret = gr_gk20a_submit_fecs_sideband_method_op(g, - (struct fecs_method_op_gk20a) { - .method.data = gr_ctx->t18x.ctx_id, - .method.addr = - gr_fecs_method_push_adr_configure_interrupt_completion_option_v(), - .mailbox = { - .id = 1 /* sideband */, .data = 0, - .clr = ~0, .ret = NULL, - .ok = gr_fecs_ctxsw_mailbox_value_pass_v(), - .fail = 0}, - .cond.ok = GR_IS_UCODE_OP_EQUAL, - .cond.fail = GR_IS_UCODE_OP_SKIP}); - - if (ret) { - nvgpu_err(g, "CILP: failed to enable ctxsw interrupt!"); - return ret; - } - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: enabled ctxsw completion interrupt"); - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: disabling channel %d", - fault_ch->hw_chid); - - ret = gr_gv11b_disable_channel_or_tsg(g, fault_ch); - if (ret) { - nvgpu_err(g, "CILP: failed to disable channel!!"); - return ret; - } - - /* set cilp_preempt_pending = true and record the channel */ - gr_ctx->t18x.cilp_preempt_pending = true; - g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid; - - if (gk20a_is_channel_marked_as_tsg(fault_ch)) { - struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; - - gk20a_tsg_event_id_post_event(tsg, - NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED); - } else { - gk20a_channel_event_id_post_event(fault_ch, - NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED); - } - - return 0; -} - -static int gr_gv11b_clear_cilp_preempt_pending(struct gk20a *g, - struct channel_gk20a *fault_ch) -{ - struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); - - if (!gr_ctx) - return -EINVAL; - - /* The ucode is self-clearing, so all we need to do here is - to clear cilp_preempt_pending. */ - if (!gr_ctx->t18x.cilp_preempt_pending) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP is already cleared for chid %d\n", - fault_ch->hw_chid); - return 0; - } - - gr_ctx->t18x.cilp_preempt_pending = false; - g->gr.t18x.cilp_preempt_pending_chid = -1; - - return 0; -} - /* @brief pre-process work on the SM exceptions to determine if we clear them or not. * * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing @@ -1827,7 +1690,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, gpc, tpc); gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Setting CILP preempt pending\n"); - ret = gr_gv11b_set_cilp_preempt_pending(g, fault_ch); + ret = gr_gp10b_set_cilp_preempt_pending(g, fault_ch); if (ret) { nvgpu_err(g, "CILP: error while setting CILP preempt pending!"); return ret; @@ -1858,31 +1721,6 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, return 0; } -static int gr_gv11b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) -{ - struct gr_ctx_desc *gr_ctx; - struct channel_gk20a *ch; - int chid; - int ret = -EINVAL; - - chid = g->gr.t18x.cilp_preempt_pending_chid; - - ch = gk20a_channel_get(gk20a_fifo_channel_from_hw_chid(g, chid)); - if (!ch) - return ret; - - gr_ctx = ch->ch_ctx.gr_ctx; - - if (gr_ctx->t18x.cilp_preempt_pending) { - *__chid = chid; - ret = 0; - } - - gk20a_channel_put(ch); - - return ret; -} - static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) { u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; @@ -1971,65 +1809,16 @@ static int gr_gv11b_handle_fecs_error(struct gk20a *g, struct gr_gk20a_isr_data *isr_data) { u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); - struct channel_gk20a *ch; - int chid = -1; - int ret = 0; + int ret; gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); - /* - * INTR1 (bit 1 of the HOST_INT_STATUS_CTXSW_INTR) - * indicates that a CILP ctxsw save has finished - */ - if (gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(2)) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: ctxsw save completed!\n"); - - /* now clear the interrupt */ - gk20a_writel(g, gr_fecs_host_int_clear_r(), - gr_fecs_host_int_clear_ctxsw_intr1_clear_f()); - - ret = gr_gv11b_get_cilp_preempt_pending_chid(g, &chid); - if (ret) - goto clean_up; - - ch = gk20a_channel_get( - gk20a_fifo_channel_from_hw_chid(g, chid)); - if (!ch) - goto clean_up; - - - /* set preempt_pending to false */ - ret = gr_gv11b_clear_cilp_preempt_pending(g, ch); - if (ret) { - nvgpu_err(g, "CILP: error while unsetting CILP preempt pending!"); - gk20a_channel_put(ch); - goto clean_up; - } - - if (gk20a_gr_sm_debugger_attached(g)) { - gk20a_dbg_gpu_post_events(ch); - - if (gk20a_is_channel_marked_as_tsg(ch)) { - struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; - - gk20a_tsg_event_id_post_event(tsg, - NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); - } else { - gk20a_channel_event_id_post_event(ch, - NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); - } - } - - gk20a_channel_put(ch); - } + ret = gr_gp10b_handle_fecs_error(g, __ch, isr_data); /* Handle ECC errors */ gr_gv11b_handle_fecs_ecc_error(g, gr_fecs_intr); -clean_up: - /* handle any remaining interrupts */ - return gk20a_gr_handle_fecs_error(g, __ch, isr_data); + return ret; } static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) -- cgit v1.2.2 From 11009e0e69a497780ddb918fab89da62089510ce Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 20 Jun 2017 15:31:46 -0700 Subject: gpu: nvgpu: gv11b: sm register changes gv11b has multiple SMs and SM register addresses have changed as compared to legacy chips. JIRA GPUT19X-75 Change-Id: I2319f4c78f3efda3430bab1f5ecf1a068e57a1ca Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1506013 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 10 +- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 318 +++++++++++---------- 2 files changed, 170 insertions(+), 158 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 41892746..59865a0f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1658,8 +1658,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f()); - global_mask = gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f() | - gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(); + global_mask = gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f() | + gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(); if (warp_esr != 0 || (global_esr & global_mask) != 0) { *ignore_debugger = true; @@ -1697,13 +1697,13 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, } dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); - if (dbgr_control0 & gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f()) { + if (dbgr_control0 & gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f()) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", gpc, tpc); dbgr_control0 = set_field(dbgr_control0, - gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(), - gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f()); + gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(), + gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f()); gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset, dbgr_control0); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 75a64be5..daa4c08a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -174,6 +174,10 @@ static inline u32 gr_exception_ds_m(void) { return 0x1 << 4; } +static inline u32 gr_exception_sked_m(void) +{ + return 0x1 << 8; +} static inline u32 gr_exception1_r(void) { return 0x00400118; @@ -966,14 +970,82 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void) { return 0x80000000; } -static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) -{ - return 0x00419ea8; -} static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) { return 0x00419eac; } +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) +{ + return 0x0050472c; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) +{ + return 0x00419eb4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) +{ + return 0x00504734; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) +{ + return 0x100; +} static inline u32 gr_fe_go_idle_timeout_r(void) { return 0x00404154; @@ -2422,6 +2494,22 @@ static inline u32 gr_sked_hww_esr_reset_active_f(void) { return 0x40000000; } +static inline u32 gr_sked_hww_esr_en_r(void) +{ + return 0x00407024; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) +{ + return 0x1 << 25; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) +{ + return 0x2000000; +} static inline u32 gr_cwd_fs_r(void) { return 0x00405b00; @@ -3302,90 +3390,74 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { return 0x10000000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_r(void) +static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) { - return 0x00419f28; + return 0x00419ea8; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) +{ + return 0x00504728; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) { return 0x2; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) { return 0x4; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) { return 0x10; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) { return 0x20; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) { return 0x40; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) { return 0x100; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) { return 0x200; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) { return 0x800; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) { return 0x2000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) { return 0x4000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) { return 0x8000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) { return 0x10000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) { return 0x40000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) { return 0x800000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) { return 0x400000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_r(void) -{ - return 0x00419f2c; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40; -} static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) { return 0x00419d0c; @@ -3562,10 +3634,22 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) +{ + return 0x1; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) { return 0x00000000; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) +{ + return 0x1 << 31; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; @@ -3574,6 +3658,10 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) +{ + return 0x1 << 3; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) { return 0x8; @@ -3590,17 +3678,37 @@ static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) { return 0x00504708; } +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) +{ + return 0x0050470c; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) { return 0x00504710; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00504714; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) { return 0x00504718; } -static inline u32 gr_gpcs_tpcs_sm0_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) +{ + return 0x0050471c; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_r(void) { - return 0x00419f10; + return 0x00419e90; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00419e94; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) +{ + return 0x00419e80; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) { @@ -3618,46 +3726,6 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) { return 0x00000001; } -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_r(void) -{ - return 0x00419f34; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) -{ - return 0x00504734; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4; -} static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) { return 0x00504730; @@ -3686,6 +3754,18 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) +{ + return 0x0050460c; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) +{ + return (r >> 1) & 0x1; +} static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) { return 0x00504738; @@ -3958,57 +4038,9 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) { return 0x004188ac; } -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_r(void) +static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) { - return 0x00419f04; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(void) -{ - return 0x1 << 3; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000; + return 0x00419e84; } static inline u32 gr_fe_gfxp_wfi_timeout_r(void) { @@ -4666,24 +4698,4 @@ static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { return (r >> 16) & 0xffff; } -static inline u32 gr_sked_hww_esr_en_r(void) -{ - return 0x00407024; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) -{ - return 0x1 << 25; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) -{ - return 0x2000000; -} -static inline u32 gr_exception_sked_m(void) -{ - return 0x1 << 8; -} #endif -- cgit v1.2.2 From d1b0920b3f595b57a38f807b040634a331aa1ddd Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 20 Jun 2017 21:56:39 -0700 Subject: gpu: nvgpu: gv11b: multiple sm support -Calculate sm reg offset by using gpc, tpc and sm numbers -Init get_esr_sm_sel gr ops JIRA GPUT19X-75 Change-Id: I74cfcae07e385cdad51774b963380c0633adfecf Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1506152 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 75 ++++++++++++++++++++++++++++---------- 1 file changed, 56 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 59865a0f..e4826376 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -111,6 +111,15 @@ static bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) return valid; } +static u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm) +{ + + u32 sm_pri_stride = nvgpu_get_litter_value(g, GPU_LIT_SM_PRI_STRIDE); + u32 sm_offset = sm_pri_stride * sm; + + return sm_offset; +} + static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event, struct channel_gk20a *fault_ch, u32 *hww_global_esr) @@ -580,7 +589,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, } static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event, struct channel_gk20a *fault_ch, + u32 sm, bool *post_event, struct channel_gk20a *fault_ch, u32 *hww_global_esr) { int ret = 0; @@ -1629,15 +1638,16 @@ static void gr_gv11b_get_access_map(struct gk20a *g, * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing */ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, - u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr, + u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, bool sm_debugger_attached, struct channel_gk20a *fault_ch, bool *early_exit, bool *ignore_debugger) { int ret; bool cilp_enabled = false; u32 global_mask = 0, dbgr_control0, global_esr_copy; - u32 offset = proj_gpc_stride_v() * gpc + - proj_tpc_in_gpc_stride_v() * tpc; + u32 offset = gk20a_gr_gpc_offset(g, gpc) + + gk20a_gr_tpc_offset(g, tpc) + + gv11b_gr_sm_offset(g, sm); *early_exit = false; *ignore_debugger = false; @@ -1646,8 +1656,9 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP); - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n", - gpc, tpc, global_esr); + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "SM Exception received on gpc %d tpc %d sm %d = 0x%08x", + gpc, tpc, sm, global_esr); if (cilp_enabled && sm_debugger_attached) { if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()) @@ -1665,20 +1676,23 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, *ignore_debugger = true; gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: starting wait for LOCKED_DOWN on gpc %d tpc %d\n", - gpc, tpc); + "CILP: starting wait for LOCKED_DOWN on " + "gpc %d tpc %d sm %d", + gpc, tpc, sm); if (gk20a_dbg_gpu_broadcast_stop_trigger(fault_ch)) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n", - gpc, tpc); + "CILP: Broadcasting STOP_TRIGGER from " + "gpc %d tpc %d sm %d", + gpc, tpc, sm); gk20a_suspend_all_sms(g, global_mask, false); gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch); } else { gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: STOP_TRIGGER from gpc %d tpc %d\n", - gpc, tpc); + "CILP: STOP_TRIGGER from " + "gpc %d tpc %d sm %d", + gpc, tpc, sm); gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true); } @@ -1686,8 +1700,9 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: HWWs cleared for gpc %d tpc %d\n", - gpc, tpc); + "CILP: HWWs cleared for " + "gpc %d tpc %d sm %d", + gpc, tpc, sm); gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Setting CILP preempt pending\n"); ret = gr_gp10b_set_cilp_preempt_pending(g, fault_ch); @@ -1699,8 +1714,9 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); if (dbgr_control0 & gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f()) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", - gpc, tpc); + "CILP: clearing SINGLE_STEP_MODE " + "before resume for gpc %d tpc %d sm %d", + gpc, tpc, sm); dbgr_control0 = set_field(dbgr_control0, gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(), gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f()); @@ -1708,12 +1724,14 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, } gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: resume for gpc %d tpc %d\n", - gpc, tpc); + "CILP: resume for gpc %d tpc %d sm %d", + gpc, tpc, sm); gk20a_resume_single_sm(g, gpc, tpc); *ignore_debugger = true; - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc); + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: All done on gpc %d, tpc %d sm %d", + gpc, tpc, sm); } *early_exit = true; @@ -2320,6 +2338,24 @@ static int gr_gv11b_init_fs_state(struct gk20a *g) return gr_gm20b_init_fs_state(g); } +static void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, + u32 *esr_sm_sel) +{ + u32 reg_val; + u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); + + reg_val = gk20a_readl(g, gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r() + offset); + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "sm tpc esr sm sel reg val: 0x%x", reg_val); + *esr_sm_sel = 0; + if (gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(reg_val)) + *esr_sm_sel = 1; + if (gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(reg_val)) + *esr_sm_sel |= 1 << 1; + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2381,4 +2417,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.set_czf_bypass = NULL; gops->gr.handle_gpc_gpcmmu_exception = gr_gv11b_handle_gpc_gpcmmu_exception; + gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; } -- cgit v1.2.2 From dedc347b94123f0e049f6845990cb41c679cbdeb Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Fri, 23 Jun 2017 17:22:48 +0530 Subject: gpu: nvgpu: PMU reset reorg support - Assigned gv11b pmu engine reset & status ops to point to gp106 ops. JIRA NVGPU-99 Change-Id: I6338e2c5a1458e88a62cf0966b59c1dbe73385b6 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1507884 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 01dc207c..ecc77e1b 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -240,7 +240,8 @@ void gv11b_init_pmu_ops(struct gpu_ops *gops) gp10b_init_pmu_ops(gops); gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; - gops->pmu.reset = gp106_pmu_reset; + gops->pmu.reset_engine = gp106_pmu_engine_reset; + gops->pmu.is_engine_in_reset = gp106_pmu_is_engine_in_reset; gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; -- cgit v1.2.2 From 54ab6fc82fafc4cf6d260a7c9a065f89fdffd282 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Tue, 27 Jun 2017 14:35:23 +0300 Subject: gpu: nvgpu: depend on gk20a for TEGRA_19x_GPU Depend on the main GK20A config for all subitems so that they get grouped properly under the top level item in the menuconfig. Change-Id: Ia44179cdebb1f5b24ea626b57ccea40bdd9b2bd8 Signed-off-by: Konsta Holtta Reviewed-on: https://git-master/r/1509336 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/Kconfig b/drivers/gpu/nvgpu/Kconfig index 6440472e..a955c3a7 100644 --- a/drivers/gpu/nvgpu/Kconfig +++ b/drivers/gpu/nvgpu/Kconfig @@ -1,6 +1,6 @@ config TEGRA_19x_GPU bool "Tegra 19x family GPU" - depends on ARCH_TEGRA_19x_SOC + depends on GK20A && ARCH_TEGRA_19x_SOC default y help Support for NVIDIA Tegra 19x family of GPU -- cgit v1.2.2 From 3e195bb02d62694728d80774cd03b486bb34ff14 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 29 Jun 2017 10:40:34 -0700 Subject: pu: nvgpu: gv11b: rename write_preemption_ptr Change function name write_preemption_ptr to set_preemption_buffer_va to match with what exactly getting done in that function. Change-Id: I91372642f1dba37e5e7bcda29ac9c4271cec4b53 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master/r/1510973 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index e4826376..612c6628 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2292,7 +2292,7 @@ static void gr_gv11b_load_tpc_mask(struct gk20a *g) } -static void gr_gv11b_write_preemption_ptr(struct gk20a *g, +static void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va) { u32 addr_lo, addr_hi; @@ -2365,7 +2365,7 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.is_valid_class = gr_gv11b_is_valid_class; gops->gr.is_valid_gfx_class = gr_gv11b_is_valid_gfx_class; gops->gr.is_valid_compute_class = gr_gv11b_is_valid_compute_class; - gops->gr.write_preemption_ptr = gr_gv11b_write_preemption_ptr; + gops->gr.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va; gops->gr.add_zbc_s = gr_gv11b_add_zbc_stencil; gops->gr.load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl; gops->gr.load_zbc_s_tbl = gr_gv11b_load_stencil_tbl; -- cgit v1.2.2 From e1655282238b4632c2af4ac809d81b297d5183f2 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Tue, 27 Jun 2017 11:15:41 -0700 Subject: gpu: nvgpu: gv11b: rename hw_chid to chid hw_chid is a relative id for vgpu. For native it's same as hw id. Renaming it to chid to avoid confusing. Jira VFND-3796 Change-Id: Ie94c1a15e9e45fc823d85790ce6a69da53a685bf Signed-off-by: Richard Zhao Reviewed-on: https://git-master/r/1509531 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 48 ++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 5425eaa0..dbde2fed 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -99,7 +99,7 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) addr_hi = u64_hi32(gk20a_mm_inst_block_addr(g, &c->inst_block)); runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) | - ram_rl_entry_chid_f(c->hw_chid); + ram_rl_entry_chid_f(c->chid); runlist[3] = ram_rl_entry_chan_inst_ptr_hi_f(addr_hi); gk20a_dbg_info("gv11b channel runlist [0] %x [1] %x [2] %x [3] %x\n", @@ -164,7 +164,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, pbdma_runlist_timeslice_enable_true_f()); - nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); /* Until full subcontext is supported, always use VEID0 */ nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), @@ -192,16 +192,16 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) { - gk20a_dbg_info("channel ring door bell %d\n", c->hw_chid); + gk20a_dbg_info("channel ring door bell %d\n", c->chid); gk20a_writel(c->g, usermode_notify_channel_pending_r(), - usermode_notify_channel_pending_id_f(c->hw_chid)); + usermode_notify_channel_pending_id_f(c->chid)); } static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; - u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); return nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_gp_get_w()); @@ -210,7 +210,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; - u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); u32 lo = nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_get_w()); u32 hi = nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_get_hi_w()); @@ -220,7 +220,7 @@ static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; - u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); nvgpu_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), c->gpfifo.put); @@ -249,13 +249,13 @@ static bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) static void gv11b_dump_channel_status_ramfc(struct gk20a *g, struct gk20a_debug_output *o, - u32 hw_chid, + u32 chid, struct ch_state *ch_state) { - u32 channel = gk20a_readl(g, ccsr_channel_r(hw_chid)); + u32 channel = gk20a_readl(g, ccsr_channel_r(chid)); u32 status = ccsr_channel_status_v(channel); u32 *inst_mem; - struct channel_gk20a *c = g->fifo.channel + hw_chid; + struct channel_gk20a *c = g->fifo.channel + chid; struct nvgpu_semaphore_int *hw_sema = NULL; if (c->hw_sema) @@ -266,7 +266,7 @@ static void gv11b_dump_channel_status_ramfc(struct gk20a *g, inst_mem = &ch_state->inst_block[0]; - gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", hw_chid, + gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", chid, dev_name(g->dev), ch_state->pid, ch_state->refs); @@ -505,13 +505,13 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, return ret; } -static void gv11b_reset_eng_faulted_ch(struct gk20a *g, u32 hw_chid) +static void gv11b_reset_eng_faulted_ch(struct gk20a *g, u32 chid) { u32 reg_val; - reg_val = gk20a_readl(g, ccsr_channel_r(hw_chid)); + reg_val = gk20a_readl(g, ccsr_channel_r(chid)); reg_val |= ccsr_channel_eng_faulted_reset_f(); - gk20a_writel(g, ccsr_channel_r(hw_chid), reg_val); + gk20a_writel(g, ccsr_channel_r(chid), reg_val); } static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg) @@ -521,18 +521,18 @@ static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg) down_read(&tsg->ch_list_lock); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { - gv11b_reset_eng_faulted_ch(g, ch->hw_chid); + gv11b_reset_eng_faulted_ch(g, ch->chid); } up_read(&tsg->ch_list_lock); } -static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 hw_chid) +static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 chid) { u32 reg_val; - reg_val = gk20a_readl(g, ccsr_channel_r(hw_chid)); + reg_val = gk20a_readl(g, ccsr_channel_r(chid)); reg_val |= ccsr_channel_pbdma_faulted_reset_f(); - gk20a_writel(g, ccsr_channel_r(hw_chid), reg_val); + gk20a_writel(g, ccsr_channel_r(chid), reg_val); } static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) @@ -542,7 +542,7 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) down_read(&tsg->ch_list_lock); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { - gv11b_reset_pbdma_faulted_ch(g, ch->hw_chid); + gv11b_reset_pbdma_faulted_ch(g, ch->chid); } up_read(&tsg->ch_list_lock); } @@ -703,13 +703,13 @@ static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, return ret; } -static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) +static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid) { struct fifo_gk20a *f = &g->fifo; u32 tsgid; - tsgid = f->channel[hw_chid].tsgid; - nvgpu_log_info(g, "chid:%d tsgid:%d", hw_chid, tsgid); + tsgid = f->channel[chid].tsgid; + nvgpu_log_info(g, "chid:%d tsgid:%d", chid, tsgid); /* Preempt tsg. Channel preempt is NOOP */ return g->ops.fifo.preempt_tsg(g, tsgid); @@ -919,9 +919,9 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, gv11b_reset_eng_faulted_tsg(tsg); } else { if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) - gv11b_reset_pbdma_faulted_ch(g, refch->hw_chid); + gv11b_reset_pbdma_faulted_ch(g, refch->chid); if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) - gv11b_reset_eng_faulted_ch(g, refch->hw_chid); + gv11b_reset_eng_faulted_ch(g, refch->chid); } } else { if (id_type == ID_TYPE_TSG) -- cgit v1.2.2 From 7346122ae66d35a39ebbdcb423de5bfc4fb66f4e Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Tue, 27 Jun 2017 16:50:28 -0700 Subject: gpu: nvgpu: gv11b: add fifo_gv11b and usermode_regs - add fifo_gv11b to store usermode_regs - consider channel_base and use usermode_regs when ring channel doorbell It'll make kickoff code re-usable for vgpu. Jira VFND-3796 Change-Id: Ia6974ccac137f201ad8763a7d372de81d5cca56b Signed-off-by: Richard Zhao Reviewed-on: https://git-master/r/1510457 Reviewed-by: Aingara Paramakuru GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/fifo_t19x.h | 21 +++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 26 +++++++++++++++++++++++--- 2 files changed, 44 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/nvgpu/fifo_t19x.h diff --git a/drivers/gpu/nvgpu/fifo_t19x.h b/drivers/gpu/nvgpu/fifo_t19x.h new file mode 100644 index 00000000..531c6f34 --- /dev/null +++ b/drivers/gpu/nvgpu/fifo_t19x.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _FIFO_T19X_H_ +#define _FIFO_T19X_H_ + +struct fifo_t19x { + void __iomem *usermode_regs; +}; + +#endif diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index dbde2fed..1194663b 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -48,6 +48,15 @@ #define CHANNEL_INFO_VEID0 0 #define PBDMA_SUBDEVICE_ID 1 +static inline void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) +{ + struct fifo_gk20a *f = &g->fifo; + void __iomem *reg = f->t19x.usermode_regs + (r - usermode_cfg0_r()); + + writel_relaxed(v, reg); + gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); +} + static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { @@ -192,10 +201,13 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) { + struct fifo_gk20a *f = &c->g->fifo; + u32 hw_chid = f->channel_base + c->chid; + gk20a_dbg_info("channel ring door bell %d\n", c->chid); - gk20a_writel(c->g, usermode_notify_channel_pending_r(), - usermode_notify_channel_pending_id_f(c->chid)); + gv11b_usermode_writel(c->g, usermode_notify_channel_pending_r(), + usermode_notify_channel_pending_id_f(hw_chid)); } static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) @@ -1575,11 +1587,19 @@ static u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) } #endif /* CONFIG_TEGRA_GK20A_NVHOST */ +static int gv11b_init_fifo_setup_hw(struct gk20a *g) +{ + struct fifo_gk20a *f = &g->fifo; + + f->t19x.usermode_regs = g->regs + usermode_cfg0_r(); + return 0; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); /* for gv11b no need to do any thing special for fifo hw setup */ - gops->fifo.init_fifo_setup_hw = NULL; + gops->fifo.init_fifo_setup_hw = gv11b_init_fifo_setup_hw; gops->fifo.runlist_entry_size = ram_rl_entry_size_v; gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry; gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry; -- cgit v1.2.2 From 6a25181882cdda68dfa4680b35f12c11b47ea036 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 10 Apr 2017 15:32:59 -0700 Subject: gpu: nvgpu: vgpu: add basic t19x HALs - Added t19x vgpu platform data - Added basic vgpu HAL for gv11b. - Added subctx header HAL. Jira VFND-3796 Change-Id: I2b99364801b41d042b53e057f1a30e1194f354c3 Signed-off-by: Richard Zhao Reviewed-on: https://git-master/r/1474729 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 7 ++ .../nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 80 ++++++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 26 +++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h | 21 ++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c | 40 +++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h | 19 +++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 40 +++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c | 70 +++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h | 22 ++++++ drivers/gpu/nvgpu/vgpu/vgpu_t19x.h | 27 ++++++++ include/linux/tegra_vgpu_t19x.h | 34 +++++++++ 11 files changed, 386 insertions(+) create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h create mode 100644 drivers/gpu/nvgpu/vgpu/vgpu_t19x.h create mode 100644 include/linux/tegra_vgpu_t19x.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 244b3ed3..8a7c768e 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -21,3 +21,10 @@ nvgpu-y += \ nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += $(nvgpu-t19x)/common/linux/nvhost_t19x.o + +nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ + $(nvgpu-t19x)/vgpu/gv11b/platform_gv11b_vgpu_tegra.o \ + $(nvgpu-t19x)/vgpu/gv11b/vgpu_hal_gv11b.o \ + $(nvgpu-t19x)/vgpu/gv11b/vgpu_gr_gv11b.o \ + $(nvgpu-t19x)/vgpu/gv11b/vgpu_fifo_gv11b.o \ + $(nvgpu-t19x)/vgpu/gv11b/vgpu_subctx_gv11b.o diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c new file mode 100644 index 00000000..a6ed67b2 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gk20a/hal_gk20a.h" +#include "gk20a/platform_gk20a.h" +#include "vgpu/clk_vgpu.h" + +#include +#include + +static int gv11b_vgpu_probe(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct gk20a_platform *platform = dev_get_drvdata(dev); + struct resource *r; + void __iomem *regs; + struct fifo_gk20a *f = &platform->g->fifo; + int ret; + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usermode"); + if (!r) { + dev_err(dev, "failed to get usermode regs\n"); + return -ENXIO; + } + regs = devm_ioremap_resource(dev, r); + if (IS_ERR(regs)) { + dev_err(dev, "failed to map usermode regs\n"); + return PTR_ERR(regs); + } + f->t19x.usermode_regs = regs; + +#ifdef CONFIG_TEGRA_GK20A_NVHOST + ret = nvgpu_get_nvhost_dev(platform->g); + if (ret) { + f->t19x.usermode_regs = NULL; + return ret; + } +#endif + vgpu_init_clk_support(platform->g); + + return 0; +} + +struct gk20a_platform gv11b_vgpu_tegra_platform = { + .has_syncpoints = false, + .aggressive_sync_destroy_thresh = 64, + + /* power management configuration */ + .can_railgate_init = false, + .can_elpg_init = false, + .enable_slcg = false, + .enable_blcg = false, + .enable_elcg = false, + .enable_elpg = false, + .enable_aelpg = false, + + .ch_wdt_timeout_ms = 5000, + + .probe = gv11b_vgpu_probe, + .default_big_page_size = SZ_64K, + + .clk_round_rate = vgpu_clk_round_rate, + .get_clk_freqs = vgpu_clk_get_freqs, + + /* frequency scaling configuration */ + .devfreq_governor = "userspace", + + .virtual_dev = true, +}; diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c new file mode 100644 index 00000000..b9df58ec --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include "vgpu_fifo_gv11b.h" +#include "vgpu_subctx_gv11b.h" + +void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops) +{ + vgpu_gp10b_init_fifo_ops(gops); + + gops->fifo.init_fifo_setup_hw = NULL; + gops->fifo.free_channel_ctx_header = vgpu_gv11b_free_subctx_header; +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h new file mode 100644 index 00000000..a9c13b5f --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _VGPU_FIFO_GV11B_H_ +#define _VGPU_FIFO_GV11B_H_ + +struct gpu_ops; + +void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c new file mode 100644 index 00000000..fcd31d20 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include + +#include "vgpu_gr_gv11b.h" +#include "vgpu_subctx_gv11b.h" + +static int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) +{ + int err; + + err = vgpu_gv11b_alloc_subctx_header(c); + if (err) + return err; + + err = vgpu_gr_commit_inst(c, gpu_va); + if (err) + vgpu_gv11b_free_subctx_header(c); + + return err; +} + +void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops) +{ + vgpu_gp10b_init_gr_ops(gops); + gops->gr.commit_inst = vgpu_gr_gv11b_commit_inst; +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h new file mode 100644 index 00000000..cc3171d4 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _VGPU_GR_GV11B_H_ +#define _VGPU_GR_GV11B_H_ + +void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c new file mode 100644 index 00000000..fff1a386 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include + +#include "vgpu_gr_gv11b.h" +#include "vgpu_fifo_gv11b.h" + +int vgpu_gv11b_init_hal(struct gk20a *g) +{ + int err; + + gk20a_dbg_fn(""); + + err = gv11b_init_hal(g); + if (err) + return err; + + vgpu_init_hal_common(g); + vgpu_gp10b_init_mm_ops(&g->ops); + + vgpu_gv11b_init_gr_ops(&g->ops); + vgpu_gv11b_init_fifo_ops(&g->ops); + + return 0; +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c new file mode 100644 index 00000000..93341427 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include + +int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c) +{ + struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_alloc_ctx_header_params *p = + &msg.params.t19x.alloc_ctx_header; + struct gr_gk20a *gr = &c->g->gr; + int err; + + msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER; + msg.handle = vgpu_get_handle(c->g); + p->ch_handle = c->virt_ctx; + p->ctx_header_va = __nvgpu_vm_alloc_va(c->vm, + gr->ctx_vars.golden_image_size, + gmmu_page_size_kernel); + if (!p->ctx_header_va) { + nvgpu_err(c->g, "alloc va failed for ctx_header"); + return -ENOMEM; + } + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (unlikely(err)) { + nvgpu_err(c->g, "alloc ctx_header failed err %d", err); + __nvgpu_vm_free_va(c->vm, p->ctx_header_va, + gmmu_page_size_kernel); + return err; + } + ctx->mem.gpu_va = p->ctx_header_va; + + return err; +} + +void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c) +{ + struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_free_ctx_header_params *p = + &msg.params.t19x.free_ctx_header; + int err; + + if (ctx->mem.gpu_va) { + msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER; + msg.handle = vgpu_get_handle(c->g); + p->ch_handle = c->virt_ctx; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (unlikely(err)) + nvgpu_err(c->g, "free ctx_header failed err %d", err); + __nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va, + gmmu_page_size_kernel); + ctx->mem.gpu_va = 0; + } +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h new file mode 100644 index 00000000..bfcfe65c --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _VGPU_SUBCTX_GV11B_H_ +#define _VGPU_SUBCTX_GV11B_H_ + +struct channel_gk20a; + +int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c); +void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/vgpu_t19x.h b/drivers/gpu/nvgpu/vgpu/vgpu_t19x.h new file mode 100644 index 00000000..de3e0f80 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/vgpu_t19x.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _VGPU_T19X_H_ +#define _VGPU_T19X_H_ + +struct gk20a; + +int vgpu_gv11b_init_hal(struct gk20a *g); + +#define vgpu_t19x_init_hal(g) vgpu_gv11b_init_hal(g) + +#define TEGRA_19x_VGPU_COMPAT_TEGRA "nvidia,gv11b-vgpu" +extern struct gk20a_platform gv11b_vgpu_tegra_platform; +#define t19x_vgpu_tegra_platform gv11b_vgpu_tegra_platform + +#endif diff --git a/include/linux/tegra_vgpu_t19x.h b/include/linux/tegra_vgpu_t19x.h new file mode 100644 index 00000000..f473275d --- /dev/null +++ b/include/linux/tegra_vgpu_t19x.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TEGRA_VGPU_T19X_H +#define __TEGRA_VGPU_T19X_H + +#define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100 +#define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101 + +struct tegra_vgpu_alloc_ctx_header_params { + u64 ch_handle; + u64 ctx_header_va; +}; + +struct tegra_vgpu_free_ctx_header_params { + u64 ch_handle; +}; + +union tegra_vgpu_t19x_params { + struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; + struct tegra_vgpu_free_ctx_header_params free_ctx_header; +}; + +#endif -- cgit v1.2.2 From 20158e09b7b7a90177945f3e7ceab57f34982b50 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 9 Jun 2017 10:17:13 -0700 Subject: gpu: nvgpu: gv11b: Corrected sm whitelist address corrected whitelist address for gr_pri_gpcs_tpcs_sms_dbgr_control0 JIRA GPUT19X-49 Bug 200311674 Change-Id: I512197c4a6ef97a59bbb303e31ab91f7727bf8d5 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1499394 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 612c6628..5258e4ce 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1625,7 +1625,7 @@ static void gr_gv11b_get_access_map(struct gk20a *g, 0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */ 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ - 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ + 0x419e84, /* gr_pri_gpcs_tpcs_sms_dbgr_control0 */ 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ }; -- cgit v1.2.2 From c5e68d6afa664b49a2045a826f83c46ee4c4485e Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 12 Jun 2017 11:22:23 -0700 Subject: gpu: nvgpu: gv11b: dump sm regs /d/gpu.0/gr_status will dump sm registers too JIRA GPUT19X-75 Change-Id: If5d19c9ef5c05b6390e8e55c39571869d3d01ae7 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1500879 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 88 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 5258e4ce..0158d706 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1334,6 +1334,87 @@ fail_free: return err; } +static void gr_gv11b_dump_gr_per_sm_regs(struct gk20a *g, + struct gk20a_debug_output *o, + u32 gpc, u32 tpc, u32 sm, u32 offset) +{ + + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_WARP_ESR: 0x%x\n", + gpc, tpc, sm, gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset)); + + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_WARP_ESR_REPORT_MASK: 0x%x\n", + gpc, tpc, sm, gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset)); + + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_GLOBAL_ESR: 0x%x\n", + gpc, tpc, sm, gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset)); + + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_GLOBAL_ESR_REPORT_MASK: 0x%x\n", + gpc, tpc, sm, gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset)); + + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_DBGR_CONTROL0: 0x%x\n", + gpc, tpc, sm, gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset)); + + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_DBGR_STATUS0: 0x%x\n", + gpc, tpc, sm, gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_status0_r() + offset)); +} + +static int gr_gv11b_dump_gr_sm_regs(struct gk20a *g, + struct gk20a_debug_output *o) +{ + u32 gpc, tpc, sm, sm_per_tpc; + u32 gpc_offset, tpc_offset, offset; + + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK: 0x%x\n", + gk20a_readl(g, + gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r())); + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK: 0x%x\n", + gk20a_readl(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r())); + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR: 0x%x\n", + gk20a_readl(g, gr_gpcs_tpcs_sms_hww_global_esr_r())); + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0: 0x%x\n", + gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_control0_r())); + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0: 0x%x\n", + gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_status0_r())); + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK: 0x%x\n", + gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_r())); + + sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + gpc_offset = gk20a_gr_gpc_offset(g, gpc); + + for (tpc = 0; tpc < g->gr.tpc_count; tpc++) { + tpc_offset = gk20a_gr_tpc_offset(g, tpc); + + for (sm = 0; sm < sm_per_tpc; sm++) { + offset = gpc_offset + tpc_offset + + gv11b_gr_sm_offset(g, sm); + + gr_gv11b_dump_gr_per_sm_regs(g, o, + gpc, tpc, sm, offset); + } + } + } + + return 0; +} static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, struct gk20a_debug_output *o) @@ -1441,6 +1522,10 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, gk20a_readl(g, gr_fecs_current_ctx_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n", gk20a_readl(g, gr_fecs_new_ctx_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE : 0x%x\n", + gk20a_readl(g, gr_fecs_host_int_enable_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n", + gk20a_readl(g, gr_fecs_host_int_status_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_CROP_STATUS1 : 0x%x\n", gk20a_readl(g, gr_pri_be0_crop_status1_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_CROP_STATUS1 : 0x%x\n", @@ -1465,6 +1550,9 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n", gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r())); + + gr_gv11b_dump_gr_sm_regs(g, o); + return 0; } -- cgit v1.2.2 From fd80220dd30ec59f270b435dff8a0e0f512d0c98 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 21 Jun 2017 10:34:20 -0700 Subject: gpu: nvgpu: gv11b: init trigger_suspend gr ops Add gv11b specific trigger_suspend function. SM register addresses have changed as compared to legacy gpu chips. JIRA GPUT19X-75 Change-Id: Ic3099e53bcba19128711a88ecc9e9883f5f7a31f Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1476532 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 0158d706..58bb08a6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2444,6 +2444,28 @@ static void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); } +static int gv11b_gr_sm_trigger_suspend(struct gk20a *g) +{ + u32 dbgr_control0; + + /* assert stop trigger. uniformity assumption: all SMs will have + * the same state in dbg_control0. + */ + dbgr_control0 = + gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_control0_r()); + dbgr_control0 |= gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(); + + /* broadcast write */ + gk20a_writel(g, + gr_gpcs_tpcs_sms_dbgr_control0_r(), dbgr_control0); + + gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, + "stop trigger enable: broadcast dbgr_control0: 0x%x ", + dbgr_control0); + + return 0; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2506,4 +2528,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.handle_gpc_gpcmmu_exception = gr_gv11b_handle_gpc_gpcmmu_exception; gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; + gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; } -- cgit v1.2.2 From f2235085d136c50c63d4f66d4baa00f1b46bf22a Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 21 Jun 2017 10:48:23 -0700 Subject: gpu: nvgpu: gv11b: init bpt_reg_info gr ops Take care of t19x reg address changes to support multiple SM JIRA GPUT19X-75 Change-Id: I92b97e60ac82c50a97fe44a85482437446479800 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1477694 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 69 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 58bb08a6..eab78119 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2466,6 +2466,74 @@ static int gv11b_gr_sm_trigger_suspend(struct gk20a *g) return 0; } +static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) +{ + /* Check if we have at least one valid warp + * get paused state on maxwell + */ + struct gr_gk20a *gr = &g->gr; + u32 gpc, tpc, sm, sm_id; + u32 offset; + u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0; + + for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) { + gpc = g->gr.sm_to_cluster[sm_id].gpc_index; + tpc = g->gr.sm_to_cluster[sm_id].tpc_index; + sm = g->gr.sm_to_cluster[sm_id].sm_index; + + offset = gk20a_gr_gpc_offset(g, gpc) + + gk20a_gr_tpc_offset(g, tpc) + + gv11b_gr_sm_offset(g, sm); + + /* 64 bit read */ + warps_valid = (u64)gk20a_readl(g, + gr_gpc0_tpc0_sm0_warp_valid_mask_r() + + offset + 4) << 32; + warps_valid |= gk20a_readl(g, + gr_gpc0_tpc0_sm0_warp_valid_mask_r() + + offset); + + /* 64 bit read */ + warps_paused = (u64)gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r() + + offset + 4) << 32; + warps_paused |= gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r() + + offset); + + /* 64 bit read */ + warps_trapped = (u64)gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r() + + offset + 4) << 32; + warps_trapped |= gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r() + + offset); + + w_state[sm_id].valid_warps[0] = warps_valid; + w_state[sm_id].trapped_warps[0] = warps_trapped; + w_state[sm_id].paused_warps[0] = warps_paused; + } + + + /* Only for debug purpose */ + for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) { + gk20a_dbg_fn("w_state[%d].valid_warps[0]: %llx\n", + sm_id, w_state[sm_id].valid_warps[0]); + gk20a_dbg_fn("w_state[%d].valid_warps[1]: %llx\n", + sm_id, w_state[sm_id].valid_warps[1]); + + gk20a_dbg_fn("w_state[%d].trapped_warps[0]: %llx\n", + sm_id, w_state[sm_id].trapped_warps[0]); + gk20a_dbg_fn("w_state[%d].trapped_warps[1]: %llx\n", + sm_id, w_state[sm_id].trapped_warps[1]); + + gk20a_dbg_fn("w_state[%d].paused_warps[0]: %llx\n", + sm_id, w_state[sm_id].paused_warps[0]); + gk20a_dbg_fn("w_state[%d].paused_warps[1]: %llx\n", + sm_id, w_state[sm_id].paused_warps[1]); + } +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2529,4 +2597,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gr_gv11b_handle_gpc_gpcmmu_exception; gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; + gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; } -- cgit v1.2.2 From f28efb987a13e87d10cc1c6d6e39fcbe9383934f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 21 Jun 2017 11:03:14 -0700 Subject: gpu: nvgpu: gv11b: init update_sm_error_state gr ops Support multiple SM and take care of SM hardware reg address changes JIRA GPUT19X-75 Change-Id: I866011a85da06ca22bc10fda5ab59f84d0782902 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1477686 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 80 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index eab78119..28284b45 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2534,6 +2534,85 @@ static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) } } +static int gv11b_gr_update_sm_error_state(struct gk20a *g, + struct channel_gk20a *ch, u32 sm_id, + struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state) +{ + u32 gpc, tpc, sm, offset; + struct gr_gk20a *gr = &g->gr; + struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; + int err = 0; + + nvgpu_mutex_acquire(&g->dbg_sessions_lock); + + gr->sm_error_states[sm_id].hww_global_esr = + sm_error_state->hww_global_esr; + gr->sm_error_states[sm_id].hww_warp_esr = + sm_error_state->hww_warp_esr; + gr->sm_error_states[sm_id].hww_warp_esr_pc = + sm_error_state->hww_warp_esr_pc; + gr->sm_error_states[sm_id].hww_global_esr_report_mask = + sm_error_state->hww_global_esr_report_mask; + gr->sm_error_states[sm_id].hww_warp_esr_report_mask = + sm_error_state->hww_warp_esr_report_mask; + + err = gr_gk20a_disable_ctxsw(g); + if (err) { + nvgpu_err(g, "unable to stop gr ctxsw"); + goto fail; + } + + gpc = g->gr.sm_to_cluster[sm_id].gpc_index; + tpc = g->gr.sm_to_cluster[sm_id].tpc_index; + sm = g->gr.sm_to_cluster[sm_id].sm_index; + + offset = gk20a_gr_gpc_offset(g, gpc) + + gk20a_gr_tpc_offset(g, tpc) + + gv11b_gr_sm_offset(g, sm); + + if (gk20a_is_channel_ctx_resident(ch)) { + gk20a_writel(g, + gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, + gr->sm_error_states[sm_id].hww_global_esr); + gk20a_writel(g, + gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset, + gr->sm_error_states[sm_id].hww_warp_esr); + gk20a_writel(g, + gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset, + gr->sm_error_states[sm_id].hww_warp_esr_pc); + gk20a_writel(g, + gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset, + gr->sm_error_states[sm_id].hww_global_esr_report_mask); + gk20a_writel(g, + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset, + gr->sm_error_states[sm_id].hww_warp_esr_report_mask); + } else { + err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); + if (err) + goto enable_ctxsw; + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() + + offset, + gr->sm_error_states[sm_id].hww_global_esr_report_mask, + true); + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() + + offset, + gr->sm_error_states[sm_id].hww_warp_esr_report_mask, + true); + + gr_gk20a_ctx_patch_write_end(g, ch_ctx); + } + +enable_ctxsw: + err = gr_gk20a_enable_ctxsw(g); + +fail: + nvgpu_mutex_release(&g->dbg_sessions_lock); + return err; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2598,4 +2677,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; + gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; } -- cgit v1.2.2 From 8f0f88d61e452e81d03670b4a1413fc0ced631c2 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 21 Jun 2017 11:15:43 -0700 Subject: gpu: nvgpu: gv11b: init set_sm_debug_mode gr ops Support multiple SM and take care of sm reg addr changes JIRA GPUT19X-75 Change-Id: Id39e269034762c7a8347edaf1fff0b2efd7f153c Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1477705 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 61 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 28284b45..c1dc7920 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -29,6 +29,7 @@ #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/regops_gk20a.h" #include "gm20b/gr_gm20b.h" @@ -2613,6 +2614,65 @@ fail: return err; } +static int gv11b_gr_set_sm_debug_mode(struct gk20a *g, + struct channel_gk20a *ch, u64 sms, bool enable) +{ + struct nvgpu_dbg_gpu_reg_op *ops; + unsigned int i = 0, sm_id; + int err; + + ops = nvgpu_kcalloc(g, g->gr.no_of_sm, sizeof(*ops)); + if (!ops) + return -ENOMEM; + for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) { + u32 gpc, tpc, sm; + u32 reg_offset, reg_mask, reg_val; + + if (!(sms & (1 << sm_id))) + continue; + + gpc = g->gr.sm_to_cluster[sm_id].gpc_index; + tpc = g->gr.sm_to_cluster[sm_id].tpc_index; + sm = g->gr.sm_to_cluster[sm_id].sm_index; + + reg_offset = gk20a_gr_gpc_offset(g, gpc) + + gk20a_gr_tpc_offset(g, tpc) + + gv11b_gr_sm_offset(g, sm); + + ops[i].op = REGOP(WRITE_32); + ops[i].type = REGOP(TYPE_GR_CTX); + ops[i].offset = gr_gpc0_tpc0_sm0_dbgr_control0_r() + reg_offset; + + reg_mask = 0; + reg_val = 0; + if (enable) { + nvgpu_log(g, gpu_dbg_gpu_dbg, + "SM:%d debuggger mode ON", sm); + reg_mask |= + gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(); + reg_val |= + gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(); + } else { + nvgpu_log(g, gpu_dbg_gpu_dbg, + "SM:%d debuggger mode Off", sm); + reg_mask |= + gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(); + reg_val |= + gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(); + } + + ops[i].and_n_mask_lo = reg_mask; + ops[i].value_lo = reg_val; + i++; + } + + err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0); + if (err) + nvgpu_err(g, "Failed to access register\n"); + nvgpu_kfree(g, ops); + return err; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2678,4 +2738,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; + gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode; } -- cgit v1.2.2 From ec71ac29576afa676e056b42c13f073a17ba57e9 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 21 Jun 2017 11:31:55 -0700 Subject: gpu: nvgpu: gv11b: init record_sm_error_state gr ops Take care of t19x sm reg address changes and support multiple SM JIRA GPUT19X-75 Change-Id: I675b76b90d08fe75331f0023f1fe722497d06373 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1477673 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 40 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index c1dc7920..8cc1cfde 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2673,6 +2673,45 @@ static int gv11b_gr_set_sm_debug_mode(struct gk20a *g, return err; } +static int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) +{ + int sm_id; + struct gr_gk20a *gr = &g->gr; + u32 offset, sm, sm_per_tpc; + u32 gpc_tpc_offset; + + nvgpu_mutex_acquire(&g->dbg_sessions_lock); + + sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); + gpc_tpc_offset = gk20a_gr_gpc_offset(g, gpc) + + gk20a_gr_tpc_offset(g, tpc); + + sm_id = gr_gpc0_tpc0_sm_cfg_tpc_id_v(gk20a_readl(g, + gr_gpc0_tpc0_sm_cfg_r() + gpc_tpc_offset)); + + sm = sm_id % sm_per_tpc; + + offset = gpc_tpc_offset + gv11b_gr_sm_offset(g, sm); + + gr->sm_error_states[sm_id].hww_global_esr = gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); + + gr->sm_error_states[sm_id].hww_warp_esr = gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset); + + gr->sm_error_states[sm_id].hww_warp_esr_pc = gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset); + + gr->sm_error_states[sm_id].hww_global_esr_report_mask = gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset); + + gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset); + + nvgpu_mutex_release(&g->dbg_sessions_lock); + + return 0; +} void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2739,4 +2778,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode; + gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; } -- cgit v1.2.2 From 6f6329c377ae12f0bf3790c15c582e454d90d3f9 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 21 Jun 2017 12:03:11 -0700 Subject: gpu: nvgpu: gv11b: init set_hww_esr_report_mask gv11b has 2 SMs per TPC. Use *gpcs_tpcs_sms_hww_warp/global_esr* registers instead of *gpcs_tpcs_sm_hww_warp/global_esr* GPUT19X-75 Change-Id: I86c7ded32b2b69214e047e6de67a1745f2cef6f3 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1474860 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 53 ++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 8cc1cfde..1291759f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1106,23 +1106,18 @@ static void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data) gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); } - static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) { - u32 val; - gk20a_dbg_fn(""); - if (data == NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE) - val = 0; - else - val = 0xffffffff; - - /* setup sm warp esr report masks */ - gk20a_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(), val); - - /* setup sm global esr report mask */ - gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(), val); + if (data == NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE) { + gk20a_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(), + 0); + gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(), + 0); + } else { + g->ops.gr.set_hww_esr_report_mask(g); + } } static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, @@ -2712,6 +2707,37 @@ static int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) return 0; } + +static void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g) +{ + + /* clear hww */ + gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_r(), 0xffffffff); + gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_r(), 0xffffffff); + + /* setup sm warp esr report masks */ + gk20a_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(), + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f() | + gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f()); + + /* setup sm global esr report mask. vat_alarm_report is not enabled */ + gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(), + gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()); +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2779,4 +2805,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode; gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; + gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask; } -- cgit v1.2.2 From 514e7aa643317209be47a5faa6f6146152a4b6ed Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Tue, 27 Jun 2017 12:56:15 +0530 Subject: gpu: nvgpu: gv11b: check flag before enabling CG. We should check if BLCG/SLCG feature is enabled before trying to enable/disable them in hardware. Bug 200314250 Change-Id: I5431f97cc559444298b7bd4d53a9f4fc598fd268 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master/r/1509184 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 96 ++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c index 13d529fe..390d89c2 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c @@ -283,6 +283,10 @@ void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_bus) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_bus[i].addr, @@ -298,6 +302,10 @@ void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_ce2) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_ce2[i].addr, @@ -313,6 +321,10 @@ void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_chiplet) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_chiplet[i].addr, @@ -333,6 +345,10 @@ void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_fb) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_fb[i].addr, @@ -348,6 +364,10 @@ void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_fifo) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_fifo[i].addr, @@ -363,6 +383,10 @@ void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_gr) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_gr[i].addr, @@ -378,6 +402,10 @@ void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_ltc) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_ltc[i].addr, @@ -393,6 +421,10 @@ void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_perf) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_perf[i].addr, @@ -408,6 +440,10 @@ void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_priring) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_priring[i].addr, @@ -423,6 +459,10 @@ void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_pwr_csb) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_pwr_csb[i].addr, @@ -438,6 +478,10 @@ void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_pmu) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_pmu[i].addr, @@ -453,6 +497,10 @@ void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_therm) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_therm[i].addr, @@ -468,6 +516,10 @@ void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_slcg_xbar) / sizeof(struct gating_desc); + + if (!g->slcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_slcg_xbar[i].addr, @@ -483,6 +535,10 @@ void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_blcg_bus) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_blcg_bus[i].addr, @@ -498,6 +554,10 @@ void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_blcg_ce) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_blcg_ce[i].addr, @@ -513,6 +573,10 @@ void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_blcg_ctxsw_prog) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_blcg_ctxsw_prog[i].addr, @@ -528,6 +592,10 @@ void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_blcg_fb) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_blcg_fb[i].addr, @@ -543,6 +611,10 @@ void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_blcg_fifo) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_blcg_fifo[i].addr, @@ -558,6 +630,10 @@ void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_blcg_gr) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_blcg_gr[i].addr, @@ -573,6 +649,10 @@ void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_blcg_ltc) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_blcg_ltc[i].addr, @@ -588,6 +668,10 @@ void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_blcg_pwr_csb) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_blcg_pwr_csb[i].addr, @@ -603,6 +687,10 @@ void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_blcg_pmu) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_blcg_pmu[i].addr, @@ -618,6 +706,10 @@ void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_blcg_xbar) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_blcg_xbar[i].addr, @@ -633,6 +725,10 @@ void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, { u32 i; u32 size = sizeof(gv11b_pg_gr) / sizeof(struct gating_desc); + + if (!g->blcg_enabled) + return; + for (i = 0; i < size; i++) { if (prod) gk20a_writel(g, gv11b_pg_gr[i].addr, -- cgit v1.2.2 From c865b16337bf37959f6b7e8ff1970d8c3d3a927e Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 23 Jun 2017 13:26:52 -0700 Subject: gpu: nvgpu: gv11b: Per chip default big page size Stop defining per-platform default big page size. It's defined via HAL and inherited from gp10b. JIRA NVGPU-38 Change-Id: If5eedd5d351d5504bdf87489d1aa091d430c43ba Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master/r/1508069 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 2 -- drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index acec2d3a..3f6b0153 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -135,8 +135,6 @@ struct gk20a_platform t19x_gpu_tegra_platform = { .dump_platform_dependencies = gk20a_tegra_debug_dump, - .default_big_page_size = SZ_64K, - .soc_name = "tegra19x", .honors_aperture = true, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index a6ed67b2..446eea26 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -12,7 +12,6 @@ */ #include "gk20a/gk20a.h" -#include "gk20a/hal_gk20a.h" #include "gk20a/platform_gk20a.h" #include "vgpu/clk_vgpu.h" @@ -68,7 +67,6 @@ struct gk20a_platform gv11b_vgpu_tegra_platform = { .ch_wdt_timeout_ms = 5000, .probe = gv11b_vgpu_probe, - .default_big_page_size = SZ_64K, .clk_round_rate = vgpu_clk_round_rate, .get_clk_freqs = vgpu_clk_get_freqs, -- cgit v1.2.2 From f525ff15c4e8b5994201585ad584237b62bf3083 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 28 Jun 2017 10:05:04 -0700 Subject: gpu: nvgpu: gv11b: add ce interrupt handling Added handling for below ce interrupts -INVALID_CONFIG interrupt will be generated if a floorswept PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG registers. This is a fatal error and the LCE will have to be reset to get back to a working state. -MTHD_BUFFER_FAULT interrupt will be triggered if any access to a method buffer during context load or save encounters a fault. This is a fatal interrupt and will require at least the LCE to be reset before operations can start again, if not the entire GPU. JIRA GPUT19X-12 JIRA GPUT19X-46 Change-Id: I2eeefc4e634f5bf53f20933c493c7594fe0ea755 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1510298 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 39 ++++++++++++++++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 20 +++++++++++ 2 files changed, 59 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index efe443cc..1ba009bd 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -16,13 +16,52 @@ * this program. */ +#include "nvgpu/log.h" + #include "gk20a/gk20a.h" #include "gp10b/ce_gp10b.h" #include "ce_gv11b.h" +#include + +static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +{ + u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); + u32 clear_intr = 0; + + nvgpu_log(g, gpu_dbg_intr, "ce isr 0x%08x 0x%08x", ce_intr, inst_id); + + /* An INVALID_CONFIG interrupt will be generated if a floorswept + * PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG + * registers. This is a fatal error and the LCE will have to be + * reset to get back to a working state. + */ + if (ce_intr & ce_intr_status_invalid_config_pending_f()) { + nvgpu_log(g, gpu_dbg_intr, + "ce: inst %d: invalid config", inst_id); + clear_intr |= ce_intr_status_invalid_config_reset_f(); + } + + /* A MTHD_BUFFER_FAULT interrupt will be triggered if any access + * to a method buffer during context load or save encounters a fault. + * This is a fatal interrupt and will require at least the LCE to be + * reset before operations can start again, if not the entire GPU. + */ + if (ce_intr & ce_intr_status_mthd_buffer_fault_pending_f()) { + nvgpu_log(g, gpu_dbg_intr, + "ce: inst %d: mthd buffer fault", inst_id); + clear_intr |= ce_intr_status_mthd_buffer_fault_reset_f(); + } + + gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr); + + gp10b_ce_isr(g, inst_id, pri_base); +} + void gv11b_init_ce(struct gpu_ops *gops) { gp10b_init_ce(gops); + gops->ce2.isr_stall = gv11b_ce_isr; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h index 9f279207..fbf10b82 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h @@ -78,4 +78,24 @@ static inline u32 ce_intr_status_launcherr_reset_f(void) { return 0x4; } +static inline u32 ce_intr_status_invalid_config_pending_f(void) +{ + return 0x8; +} +static inline u32 ce_intr_status_invalid_config_reset_f(void) +{ + return 0x8; +} +static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) +{ + return 0x10; +} +static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) +{ + return 0x10; +} +static inline u32 ce_pce_map_r(void) +{ + return 0x00104028; +} #endif -- cgit v1.2.2 From 5a57be6ba1d491b4a3258281c82345fdb4a83675 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 30 Jun 2017 14:07:38 -0700 Subject: gpu: nvgpu: gv11b: init get_num_pce ce ops Implement get_num_pce ce ops to get number of physical copy engines. This is required to calculate eng method buffer size JIRA GPUT19X-46 Change-Id: I5a37eb26ec11bc358700d1761cfdb6ca060e4287 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1511788 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 1ba009bd..0bbd05b6 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -17,6 +17,7 @@ */ #include "nvgpu/log.h" +#include "nvgpu/bitops.h" #include "gk20a/gk20a.h" @@ -26,6 +27,19 @@ #include +static u32 gv11b_ce_get_num_pce(struct gk20a *g) +{ + /* register contains a bitmask indicating which physical copy + * engines are present (and not floorswept). + */ + u32 num_pce; + u32 ce_pce_map = gk20a_readl(g, ce_pce_map_r()); + + num_pce = get_count_order(ce_pce_map) + 1; + nvgpu_log_info(g, "num PCE: %d", num_pce); + return num_pce; +} + static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) { u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); @@ -64,4 +78,5 @@ void gv11b_init_ce(struct gpu_ops *gops) { gp10b_init_ce(gops); gops->ce2.isr_stall = gv11b_ce_isr; + gops->ce2.get_num_pce = gv11b_ce_get_num_pce; } -- cgit v1.2.2 From 8a0221cfc735f79c94447ff5922e26c313e0f177 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 27 Jun 2017 16:36:48 -0700 Subject: gpu: nvgpu: gv11b: implement eng method buffer init/deinit When CE hits a page fault it needs to save out methods, it will save it out to a per runqueue per TSG method buffer. The method buffers (one per TSG runqueue) are allocated in BAR2 space during TSG creation All channels in a TSG that are mapped to the same runqueue will point to the same buffer. S/w will insert channel's method buffer pointer in the channel's instance block entries NV_RAMIN_ENG_METHOD_BUFFER_ADDR_LO and NV_RAMIN_ENG_METHOD_BUFFER_ADDR_HI. Method buffer in memory will be 32B aligned. Eng method buffer allocated per tsg will be de-allocated during tsg_release. JIRA GPUT19X-46 Change-Id: Ib480ae5840d9815d24fe2eadc169ac3102854cd0 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1509747 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 109 +++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 4 ++ 2 files changed, 113 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 1194663b..3e73a29e 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -48,6 +48,9 @@ #define CHANNEL_INFO_VEID0 0 #define PBDMA_SUBDEVICE_ID 1 +static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, + struct channel_gk20a *ch, struct nvgpu_mem *mem); + static inline void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) { struct fifo_gk20a *f = &g->fifo; @@ -180,6 +183,8 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, pbdma_set_channel_info_scg_type_graphics_compute0_f() | pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); + gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); + if (c->is_privileged_channel) { /* Set privilege level for channel */ nvgpu_mem_wr32(g, mem, ram_fc_config_w(), @@ -1470,6 +1475,106 @@ static unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, return rc_type; } +static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, + struct channel_gk20a *ch, struct nvgpu_mem *mem) +{ + struct tsg_gk20a *tsg; + struct nvgpu_mem *method_buffer_per_runque; + + tsg = tsg_gk20a_from_ch(ch); + if (tsg == NULL) { + nvgpu_err(g, "channel is not part of tsg"); + return; + } + if (tsg->eng_method_buffers == NULL) { + nvgpu_log_info(g, "eng method buffer NULL"); + return; + } + if (tsg->runlist_id == gk20a_fifo_get_fast_ce_runlist_id(g)) + method_buffer_per_runque = + &tsg->eng_method_buffers[ASYNC_CE_RUNQUE]; + else + method_buffer_per_runque = + &tsg->eng_method_buffers[GR_RUNQUE]; + + nvgpu_mem_wr32(g, mem, ram_in_eng_method_buffer_addr_lo_w(), + u64_lo32(method_buffer_per_runque->gpu_va)); + nvgpu_mem_wr32(g, mem, ram_in_eng_method_buffer_addr_hi_w(), + u64_hi32(method_buffer_per_runque->gpu_va)); + + nvgpu_log_info(g, "init ramfc with method buffer"); +} + +unsigned int gv11b_fifo_get_eng_method_buffer_size(struct gk20a *g) +{ + unsigned int buffer_size; + + buffer_size = ((9 + 1 + 3) * g->ops.ce2.get_num_pce(g)) + 2; + buffer_size = (27 * 5 * buffer_size); + buffer_size = roundup(buffer_size, PAGE_SIZE); + nvgpu_log_info(g, "method buffer size in bytes %d", buffer_size); + + return buffer_size; +} + +static void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, + struct tsg_gk20a *tsg) +{ + struct vm_gk20a *vm = g->mm.bar2.vm; + int err = 0; + unsigned int i, runque, method_buffer_size; + unsigned int num_pbdma = g->fifo.num_pbdma; + + if (tsg->eng_method_buffers != NULL) + return; + + method_buffer_size = gv11b_fifo_get_eng_method_buffer_size(g); + if (method_buffer_size == 0) { + nvgpu_info(g, "ce will hit MTHD_BUFFER_FAULT"); + return; + } + + tsg->eng_method_buffers = nvgpu_kzalloc(g, + num_pbdma * sizeof(struct nvgpu_mem)); + + for (runque = 0; runque < num_pbdma; runque++) { + err = nvgpu_dma_alloc_map_sys(vm, method_buffer_size, + &tsg->eng_method_buffers[runque]); + if (err) + break; + } + if (err) { + for (i = runque; i < runque; i--) + nvgpu_dma_unmap_free(vm, + &tsg->eng_method_buffers[runque]); + + nvgpu_kfree(g, tsg->eng_method_buffers); + tsg->eng_method_buffers = NULL; + nvgpu_err(g, "could not alloc eng method buffers"); + return; + } + nvgpu_log_info(g, "eng method buffers allocated"); + +} + +static void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, + struct tsg_gk20a *tsg) +{ + struct vm_gk20a *vm = g->mm.bar2.vm; + unsigned int runque; + + if (tsg->eng_method_buffers == NULL) + return; + + for (runque = 0; runque < g->fifo.num_pbdma; runque++) + nvgpu_dma_unmap_free(vm, &tsg->eng_method_buffers[runque]); + + nvgpu_kfree(g, tsg->eng_method_buffers); + tsg->eng_method_buffers = NULL; + + nvgpu_log_info(g, "eng method buffers de-allocated"); +} + #ifdef CONFIG_TEGRA_GK20A_NVHOST static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf) @@ -1633,6 +1738,10 @@ void gv11b_init_fifo(struct gpu_ops *gops) gv11b_fifo_handle_pbdma_intr_0; gops->fifo.handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1; + gops->fifo.init_eng_method_buffers = + gv11b_fifo_init_eng_method_buffers; + gops->fifo.deinit_eng_method_buffers = + gv11b_fifo_deinit_eng_method_buffers; #ifdef CONFIG_TEGRA_GK20A_NVHOST gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf; gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf; diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index ab56b876..94b7934f 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -31,6 +31,10 @@ */ #define SCHED_ERROR_CODE_BAD_TSG 0x00000020 +/* can be removed after runque support is added */ + +#define GR_RUNQUE 0 /* pbdma 0 */ +#define ASYNC_CE_RUNQUE 2 /* pbdma 2 */ struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); -- cgit v1.2.2 From 5cda5a3074e4c7dae1857e1dfdf55017b0450786 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 27 Jun 2017 22:10:49 -0700 Subject: gpu: nvgpu: gv11b: add a function to reset pbdma and eng faulted When Host receives a page fault signal from a CE, Host will immediately set _ENG_FAULTED bit in the NV_PCCSR_CHANNEL register for the channel and will trigger a preempt of the TSG/channel. A channel will only be scheduled when _ENABLED=1, _ENG_FAULTED=0 and _PBDMA_FAULTED=0 in pccsr_channel reg for the channel. If a TSG has a faulted channel, Host will not schedule the entire TSG agin until all _FAULTED bits from channels in the TSG are cleared by SW. This function will be required for ce page fault handling. JIRA GPUT19X-46 JIRA GPUT19X-12 Change-Id: Ib58dff7aa24aa144e970f11b5261877dec03f3e6 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1509776 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 38 +++++++++++++++++++++++++----------- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 3 +++ 2 files changed, 30 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 3e73a29e..a1f6d258 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -564,6 +564,29 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) up_read(&tsg->ch_list_lock); } +void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, + struct channel_gk20a *refch, + u32 faulted_pbdma, u32 faulted_engine) +{ + struct tsg_gk20a *tsg; + + nvgpu_log(g, gpu_dbg_intr, "reset faulted pbdma:0x%x eng:0x%x", + faulted_pbdma, faulted_engine); + + if (gk20a_is_channel_marked_as_tsg(refch)) { + tsg = &g->fifo.tsg[refch->tsgid]; + if (faulted_pbdma != FIFO_INVAL_PBDMA_ID) + gv11b_reset_pbdma_faulted_tsg(tsg); + if (faulted_engine != FIFO_INVAL_ENGINE_ID) + gv11b_reset_eng_faulted_tsg(tsg); + } else { + if (faulted_pbdma != FIFO_INVAL_PBDMA_ID) + gv11b_reset_pbdma_faulted_ch(g, refch->chid); + if (faulted_engine != FIFO_INVAL_ENGINE_ID) + gv11b_reset_eng_faulted_ch(g, refch->chid); + } +} + static u32 gv11b_fifo_get_runlists_mask(struct gk20a *g, u32 act_eng_bitmask, u32 id, unsigned int id_type, unsigned int rc_type, struct mmu_fault_info *mmfault) @@ -928,18 +951,11 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, if (rc_type == RC_TYPE_MMU_FAULT && mmfault && mmfault->refch) { refch = mmfault->refch; client_type = mmfault->client_type; - if (gk20a_is_channel_marked_as_tsg(refch)) { + if (gk20a_is_channel_marked_as_tsg(refch)) tsg = &g->fifo.tsg[refch->tsgid]; - if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) - gv11b_reset_pbdma_faulted_tsg(tsg); - if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) - gv11b_reset_eng_faulted_tsg(tsg); - } else { - if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) - gv11b_reset_pbdma_faulted_ch(g, refch->chid); - if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) - gv11b_reset_eng_faulted_ch(g, refch->chid); - } + gv11b_fifo_reset_pbdma_and_eng_faulted(g, refch, + mmfault->faulted_pbdma, + mmfault->faulted_engine); } else { if (id_type == ID_TYPE_TSG) tsg = &g->fifo.tsg[id]; diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 94b7934f..03cca839 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -38,4 +38,7 @@ struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); +void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, + struct channel_gk20a *refch, + u32 faulted_pbdma, u32 faulted_engine); #endif -- cgit v1.2.2 From f9c4f8b443c5394eb3ae5027c483d57ab0c5d515 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 4 Jul 2017 13:06:38 +0530 Subject: gpu: nvgpu: gv11b, rename gk20a_pmu_cmd_post() - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I1ce20cdd7190311535917058ad09a8896e505179 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1512972 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index ecc77e1b..fe468f19 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -197,7 +197,7 @@ static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; gv11b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM_INIT\n"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_param_msg, pmu, &seq, ~0); } else @@ -227,7 +227,7 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; gv11b_dbg_pmu("cmd post PMU_PG_CMD_SUB_FEATURE_MASK_UPDATE\n"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_sub_feature_msg, pmu, &seq, ~0); } else return -EINVAL; -- cgit v1.2.2 From a4439aee3a47ed9b966e5864a8e18a2bb13a9bb7 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 30 Jun 2017 11:19:24 -0700 Subject: gpu: nvgpu: gv11b: read from unicast register For updating broadcast register, read the current value from unicast register. JIRA GPUT19x-75 Change-Id: Ib4a3791304cabe77cf46543d4bec0312c6fcc0fb Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1511735 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 1291759f..5b1b41ce 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2448,7 +2448,7 @@ static int gv11b_gr_sm_trigger_suspend(struct gk20a *g) * the same state in dbg_control0. */ dbgr_control0 = - gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_control0_r()); + gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); dbgr_control0 |= gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(); /* broadcast write */ -- cgit v1.2.2 From 690d560e65af8096bc391064631c74a3dd14fa89 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 30 Jun 2017 11:45:16 -0700 Subject: gpu: nvgpu: gv11b: Use sm dbgr bpt and warp mask 0/1 Instead of assuming mask_0 and mask_1 as consecutive registers, use mask_1 and mask_0 registers for reading/writing sm dbgr warp and bpt mask registers JIRA GPUT19X-75 Change-Id: Ib6843d13828d899d4bd3f12bdf6701325ea760fd Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1511736 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 25 ++++++++++++---------- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 8 +++---- 2 files changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 5b1b41ce..6ac0c44f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1389,8 +1389,11 @@ static int gr_gv11b_dump_gr_sm_regs(struct gk20a *g, "NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0: 0x%x\n", gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_status0_r())); gk20a_debug_output(o, - "NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK: 0x%x\n", - gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_r())); + "NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK_0: 0x%x\n", + gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r())); + gk20a_debug_output(o, + "NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK_1: 0x%x\n", + gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r())); sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { @@ -2483,26 +2486,26 @@ static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) /* 64 bit read */ warps_valid = (u64)gk20a_readl(g, - gr_gpc0_tpc0_sm0_warp_valid_mask_r() + - offset + 4) << 32; + gr_gpc0_tpc0_sm0_warp_valid_mask_1_r() + + offset) << 32; warps_valid |= gk20a_readl(g, - gr_gpc0_tpc0_sm0_warp_valid_mask_r() + + gr_gpc0_tpc0_sm0_warp_valid_mask_0_r() + offset); /* 64 bit read */ warps_paused = (u64)gk20a_readl(g, - gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r() + - offset + 4) << 32; + gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r() + + offset) << 32; warps_paused |= gk20a_readl(g, - gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r() + + gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r() + offset); /* 64 bit read */ warps_trapped = (u64)gk20a_readl(g, - gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r() + - offset + 4) << 32; + gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r() + + offset) << 32; warps_trapped |= gk20a_readl(g, - gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r() + + gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r() + offset); w_state[sm_id].valid_warps[0] = warps_valid; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index daa4c08a..051961d2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3674,7 +3674,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; } -static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) { return 0x00504708; } @@ -3682,7 +3682,7 @@ static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) { return 0x0050470c; } -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) { return 0x00504710; } @@ -3690,7 +3690,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) { return 0x00504714; } -static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) { return 0x00504718; } @@ -3698,7 +3698,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) { return 0x0050471c; } -static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) { return 0x00419e90; } -- cgit v1.2.2 From edf87a42c3b18c2db8df07705ac26addc8c84df2 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 11:18:26 -0700 Subject: gpu: nvgpu: gv11b: init sm_debugger_attached gr ops Support gv11b sm register address changes. JIRA GPUT19X-75 Change-Id: I22562789ef7c064fa36c2d382224af6dc6a806c7 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512206 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 6ac0c44f..8e1f3af3 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2741,6 +2741,26 @@ static void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g) gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()); } +static bool gv11b_gr_sm_debugger_attached(struct gk20a *g) +{ + u32 debugger_mode; + u32 dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); + + /* check if sm debugger is attached. + * assumption: all SMs will have debug mode enabled/disabled + * uniformly. + */ + debugger_mode = + gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(dbgr_control0); + gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, + "SM Debugger Mode: %d", debugger_mode); + if (debugger_mode == + gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v()) + return true; + + return false; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2809,4 +2829,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode; gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask; + gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached; } -- cgit v1.2.2 From 30dcb317077a6a1651b856be56f714fb6016e21f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 15:31:03 -0700 Subject: gpu: nvgpu: gv11b: init suspend_single_sm gr ops Take care of SM register address changes. JIRA GPUT19X-75 Change-Id: I7fa68dbef014fb07a3656b2816d7d8d538a7cf52 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512207 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 40 +++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 8e1f3af3..4f17a33c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1780,7 +1780,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, "CILP: STOP_TRIGGER from " "gpc %d tpc %d sm %d", gpc, tpc, sm); - gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true); + g->ops.gr.suspend_single_sm(g, + gpc, tpc, sm, global_mask, true); } /* reset the HWW errors after locking down */ @@ -2761,6 +2762,42 @@ static bool gv11b_gr_sm_debugger_attached(struct gk20a *g) return false; } +static void gv11b_gr_suspend_single_sm(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, + u32 global_esr_mask, bool check_errors) +{ + int err; + u32 dbgr_control0; + u32 offset = gk20a_gr_gpc_offset(g, gpc) + + gk20a_gr_tpc_offset(g, tpc) + + gv11b_gr_sm_offset(g, sm); + + /* if an SM debugger isn't attached, skip suspend */ + if (!g->ops.gr.sm_debugger_attached(g)) { + nvgpu_err(g, + "SM debugger not attached, skipping suspend!"); + return; + } + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, + "suspending gpc:%d, tpc:%d, sm%d", gpc, tpc, sm); + + /* assert stop trigger. */ + dbgr_control0 = gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); + dbgr_control0 |= gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(); + gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset, + dbgr_control0); + + err = gk20a_gr_wait_for_sm_lock_down(g, gpc, tpc, + global_esr_mask, check_errors); + if (err) { + nvgpu_err(g, + "SuspendSm failed"); + return; + } +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2830,4 +2867,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask; gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached; + gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; } -- cgit v1.2.2 From cc698f6b9896342a4ab18a677fa05efd5d677bb6 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 16:20:19 -0700 Subject: gpu: nvgpu: gv11b: init suspend_all_sms gr ops This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: I46b7d58ed02710339aa27cd9db999aa60fbd4dd9 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512208 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 49 +++++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 4f17a33c..84ff1335 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1772,7 +1772,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, "CILP: Broadcasting STOP_TRIGGER from " "gpc %d tpc %d sm %d", gpc, tpc, sm); - gk20a_suspend_all_sms(g, global_mask, false); + g->ops.gr.suspend_all_sms(g, + global_mask, false); gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch); } else { @@ -2798,6 +2799,51 @@ static void gv11b_gr_suspend_single_sm(struct gk20a *g, } } +static void gv11b_gr_suspend_all_sms(struct gk20a *g, + u32 global_esr_mask, bool check_errors) +{ + struct gr_gk20a *gr = &g->gr; + u32 gpc, tpc, sm; + int err; + u32 dbgr_control0; + u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); + + /* if an SM debugger isn't attached, skip suspend */ + if (!g->ops.gr.sm_debugger_attached(g)) { + nvgpu_err(g, + "SM debugger not attached, skipping suspend!"); + return; + } + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "suspending all sms"); + + /* assert stop trigger. uniformity assumption: all SMs will have + * the same state in dbg_control0. + */ + dbgr_control0 = + gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); + dbgr_control0 |= gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(); + + /* broadcast write */ + gk20a_writel(g, + gr_gpcs_tpcs_sms_dbgr_control0_r(), dbgr_control0); + + for (gpc = 0; gpc < gr->gpc_count; gpc++) { + for (tpc = 0; tpc < gr_gk20a_get_tpc_count(gr, gpc); tpc++) { + for (sm = 0; sm < sm_per_tpc; sm++) { + err = gk20a_gr_wait_for_sm_lock_down(g, + gpc, tpc, + global_esr_mask, check_errors); + if (err) { + nvgpu_err(g, + "SuspendAllSms failed"); + return; + } + } + } + } +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2868,4 +2914,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask; gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached; gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; + gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms; } -- cgit v1.2.2 From 7185dcdbf8292bbdfceae49702107f0661397d21 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 16:52:18 -0700 Subject: gpu: nvgpu: gv11b: init resume_single_sm gr ops This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: I0ebbfdad73d6212997a21f9240f5d4bc2f28ab2f Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512209 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 71 +++++++++++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 84ff1335..f7d5eb62 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1815,7 +1815,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: resume for gpc %d tpc %d sm %d", gpc, tpc, sm); - gk20a_resume_single_sm(g, gpc, tpc); + g->ops.gr.resume_single_sm(g, gpc, tpc, sm); *ignore_debugger = true; gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, @@ -2844,6 +2844,74 @@ static void gv11b_gr_suspend_all_sms(struct gk20a *g, } } +static void gv11b_gr_resume_single_sm(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm) +{ + u32 dbgr_control0, dbgr_status0; + u32 offset; + /* + * The following requires some clarification. Despite the fact that both + * RUN_TRIGGER and STOP_TRIGGER have the word "TRIGGER" in their + * names, only one is actually a trigger, and that is the STOP_TRIGGER. + * Merely writing a 1(_TASK) to the RUN_TRIGGER is not sufficient to + * resume the gpu - the _STOP_TRIGGER must explicitly be set to 0 + * (_DISABLE) as well. + + * Advice from the arch group: Disable the stop trigger first, as a + * separate operation, in order to ensure that the trigger has taken + * effect, before enabling the run trigger. + */ + + offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc) + + gv11b_gr_sm_offset(g, sm); + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, + "resuming gpc:%d, tpc:%d, sm%d", gpc, tpc, sm); + dbgr_control0 = gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); + dbgr_status0 = gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_status0_r() + offset); + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, + "before stop trigger disable: " + "dbgr_control0 = 0x%x dbgr_status0: 0x%x", + dbgr_control0, dbgr_status0); + + /*De-assert stop trigger */ + dbgr_control0 = set_field(dbgr_control0, + gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(), + gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f()); + gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + + offset, dbgr_control0); + + dbgr_control0 = gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); + dbgr_status0 = gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_status0_r() + offset); + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, + "before run trigger: " + "dbgr_control0 = 0x%x dbgr_status0: 0x%x", + dbgr_control0, dbgr_status0); + /* Run trigger */ + dbgr_control0 |= + gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(); + gk20a_writel(g, + gr_gpc0_tpc0_sm0_dbgr_control0_r() + + offset, dbgr_control0); + + dbgr_control0 = gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); + dbgr_status0 = gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_status0_r() + offset); + /* run trigger is not sticky bit. SM clears it immediately */ + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, + "after run trigger: " + "dbgr_control0 = 0x%x dbgr_status0: 0x%x", + dbgr_control0, dbgr_status0); + +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2915,4 +2983,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached; gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms; + gops->gr.resume_single_sm = gv11b_gr_resume_single_sm; } -- cgit v1.2.2 From 8fb191aec01d0b4c83fbfe12310ed7827d87a873 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 17:11:46 -0700 Subject: gpu: nvgpu: gv11b: init resume_all_sms gr ops This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Ia5c0a3d1dead9c6094ca28716c06929dd3461814 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512210 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 66 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index f7d5eb62..0f331293 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2912,6 +2912,71 @@ static void gv11b_gr_resume_single_sm(struct gk20a *g, } +static void gv11b_gr_resume_all_sms(struct gk20a *g) +{ + u32 dbgr_control0, dbgr_status0; + /* + * The following requires some clarification. Despite the fact that both + * RUN_TRIGGER and STOP_TRIGGER have the word "TRIGGER" in their + * names, only one is actually a trigger, and that is the STOP_TRIGGER. + * Merely writing a 1(_TASK) to the RUN_TRIGGER is not sufficient to + * resume the gpu - the _STOP_TRIGGER must explicitly be set to 0 + * (_DISABLE) as well. + + * Advice from the arch group: Disable the stop trigger first, as a + * separate operation, in order to ensure that the trigger has taken + * effect, before enabling the run trigger. + */ + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "resuming all sms"); + + /* Read from unicast registers */ + dbgr_control0 = + gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); + dbgr_status0 = + gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_status0_r()); + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, + "before stop trigger disable: " + "dbgr_control0 = 0x%x dbgr_status0: 0x%x", + dbgr_control0, dbgr_status0); + + dbgr_control0 = set_field(dbgr_control0, + gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(), + gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f()); + /* Write to broadcast registers */ + gk20a_writel(g, + gr_gpcs_tpcs_sms_dbgr_control0_r(), dbgr_control0); + + /* Read from unicast registers */ + dbgr_control0 = + gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); + dbgr_status0 = + gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_status0_r()); + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, + "before run trigger: " + "dbgr_control0 = 0x%x dbgr_status0: 0x%x", + dbgr_control0, dbgr_status0); + /* Run trigger */ + dbgr_control0 |= + gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(); + /* Write to broadcast registers */ + gk20a_writel(g, + gr_gpcs_tpcs_sms_dbgr_control0_r(), dbgr_control0); + + /* Read from unicast registers */ + dbgr_control0 = + gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); + dbgr_status0 = + gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_status0_r()); + /* run trigger is not sticky bit. SM clears it immediately */ + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, + "after run trigger: " + "dbgr_control0 = 0x%x dbgr_status0: 0x%x", + dbgr_control0, dbgr_status0); +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -2984,4 +3049,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms; gops->gr.resume_single_sm = gv11b_gr_resume_single_sm; + gops->gr.resume_all_sms = gv11b_gr_resume_all_sms; } -- cgit v1.2.2 From f5b5099cf87a8d3219301c97189d581cafeaac4e Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 21 Jun 2017 16:28:19 -0700 Subject: gpu: nvgpu: gv11b: init resume_from_pause gr ops JIRA GPUT19X-75 Change-Id: Ie741bf50c771f21de3bf762ca506a36276f38437 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512211 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 0f331293..8094ea43 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2977,6 +2977,22 @@ static void gv11b_gr_resume_all_sms(struct gk20a *g) dbgr_control0, dbgr_status0); } +static int gv11b_gr_resume_from_pause(struct gk20a *g) +{ + int err = 0; + + /* Clear the pause mask to tell the GPU we want to resume everyone */ + gk20a_writel(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(), 0); + + /* explicitly re-enable forwarding of SM interrupts upon any resume */ + gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), + gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); + + g->ops.gr.resume_all_sms(g); + + return err; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3050,4 +3066,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms; gops->gr.resume_single_sm = gv11b_gr_resume_single_sm; gops->gr.resume_all_sms = gv11b_gr_resume_all_sms; + gops->gr.resume_from_pause = gv11b_gr_resume_from_pause; } -- cgit v1.2.2 From 37fa5128ec260bc9ebb2e902ac2dfe9baead4656 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 21 Jun 2017 16:34:10 -0700 Subject: gpu: nvgpu: gv11b: init get_sm_hww_warp_esr gr ops get sm hww_warp_esr reg val JIRA GPUT19X-75 Change-Id: I4ed04045e947c417291b7b1e2fc81bbe51f0b48c Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512212 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 8094ea43..2b083203 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1928,16 +1928,6 @@ static int gr_gv11b_handle_fecs_error(struct gk20a *g, return ret; } -static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) -{ - if (!(hww_warp_esr & gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m())) - hww_warp_esr = set_field(hww_warp_esr, - gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(), - gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f()); - - return hww_warp_esr; -} - static int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) { u32 map; @@ -2993,6 +2983,18 @@ static int gv11b_gr_resume_from_pause(struct gk20a *g) return err; } +static u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm) +{ + u32 offset = gk20a_gr_gpc_offset(g, gpc) + + gk20a_gr_tpc_offset(g, tpc) + + gv11b_gr_sm_offset(g, sm); + + u32 hww_warp_esr = gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset); + return hww_warp_esr; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3030,7 +3032,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; gops->gr.enable_exceptions = gr_gv11b_enable_exceptions; gops->gr.enable_hww_exceptions = gr_gv11b_enable_hww_exceptions; - gops->gr.mask_hww_warp_esr = gv11b_mask_hww_warp_esr; gops->gr.pre_process_sm_exception = gr_gv11b_pre_process_sm_exception; gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error; @@ -3067,4 +3068,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.resume_single_sm = gv11b_gr_resume_single_sm; gops->gr.resume_all_sms = gv11b_gr_resume_all_sms; gops->gr.resume_from_pause = gv11b_gr_resume_from_pause; + gops->gr.get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr; } -- cgit v1.2.2 From 6d758eb81bcbff4e50df5c9fa67a369a4e1f2074 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 29 Jun 2017 15:59:05 -0700 Subject: gpu: nvgpu: gv11b: support for full subcontext Changes to enable 64 subcontexts: 1 SYNC + 63 ASYNC Currently all subcontexts with in a tsg can have only single address space. Add support for NVGPU_TSG_IOCTL_BIND_CHANNEL_EX for selecting subctx id by client. Bug 1842197 Change-Id: Icf56a41303bd1ad7fc6f2a6fbc691bb7b4a01d22 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master/r/1511145 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/channel_t19x.h | 24 +++++++ drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c | 87 ++++++++++++++++++++++++ drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h | 21 ++++++ drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 16 +++-- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 4 +- drivers/gpu/nvgpu/gv11b/gv11b.c | 4 +- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 90 ++++++++++++++++--------- drivers/gpu/nvgpu/gv11b/subctx_gv11b.h | 2 +- drivers/gpu/nvgpu/tsg_t19x.h | 21 ++++++ include/uapi/linux/nvgpu-t19x.h | 22 +++++- 11 files changed, 249 insertions(+), 43 deletions(-) create mode 100644 drivers/gpu/nvgpu/channel_t19x.h create mode 100644 drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c create mode 100644 drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h create mode 100644 drivers/gpu/nvgpu/tsg_t19x.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 8a7c768e..33391a80 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -1,6 +1,7 @@ nvgpu-t19x := ../../../../nvgpu-t19x/drivers/gpu/nvgpu nvgpu-y += \ + $(nvgpu-t19x)/common/linux/ioctl_tsg_t19x.o \ $(nvgpu-t19x)/gv11b/gv11b.o \ $(nvgpu-t19x)/gv11b/bus_gv11b.o \ $(nvgpu-t19x)/gv11b/mc_gv11b.o \ diff --git a/drivers/gpu/nvgpu/channel_t19x.h b/drivers/gpu/nvgpu/channel_t19x.h new file mode 100644 index 00000000..bb324426 --- /dev/null +++ b/drivers/gpu/nvgpu/channel_t19x.h @@ -0,0 +1,24 @@ +/* + * NVIDIA T19x Channel info + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_CHANNEL_T19X_H_ +#define _NVGPU_CHANNEL_T19X_H_ + +struct channel_t19x { + u32 subctx_id; + u32 runqueue_sel; +}; + +#endif diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c new file mode 100644 index 00000000..bf6088ab --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c @@ -0,0 +1,87 @@ +/* + * GV11B TSG IOCTL Handler + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" + +#include "gv11b/fifo_gv11b.h" +#include "gv11b/subctx_gv11b.h" +#include "ioctl_tsg_t19x.h" + +static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g, + struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg) +{ + struct gk20a_sched_ctrl *sched = &g->sched_ctrl; + struct channel_gk20a *ch; + int err = 0; + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); + + nvgpu_mutex_acquire(&sched->control_lock); + if (sched->control_locked) { + err = -EPERM; + goto done; + } + err = gk20a_busy(g); + if (err) { + nvgpu_err(g, "failed to power on gpu"); + goto done; + } + + ch = gk20a_get_channel_from_file(arg->channel_fd); + if (!ch) + return -EINVAL; + if (arg->subcontext_id < gv11b_get_max_subctx_count(g)) + ch->t19x.subctx_id = arg->subcontext_id; + else + return -EINVAL; + nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d", + ch->chid, ch->t19x.subctx_id); + + /* Use runqueue selector 1 for all ASYNC ids */ + if (ch->t19x.subctx_id > CHANNEL_INFO_VEID0) + ch->t19x.runqueue_sel = 1; + + err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch); + gk20a_idle(g); +done: + nvgpu_mutex_release(&sched->control_lock); + return err; +} + +int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg, + unsigned int cmd, u8 *buf) +{ + int err = 0; + + nvgpu_log(g, gpu_dbg_fn, "t19x_tsg_ioctl_handler"); + + switch (cmd) { + case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX: + { + err = gv11b_tsg_ioctl_bind_channel_ex(g, tsg, + (struct nvgpu_tsg_bind_channel_ex_args *)buf); + break; + } + + default: + nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", + cmd); + err = -ENOTTY; + break; + } + return err; +} diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h new file mode 100644 index 00000000..3376ffce --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h @@ -0,0 +1,21 @@ +/* + * GV11B TSG IOCTL handler + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_IOCTL_TSG_T19X +#define _NVGPU_IOCTL_TSG_T19X + +int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg, + unsigned int cmd, u8 *arg); +#endif diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index a1f6d258..ace873e9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -45,7 +45,6 @@ #include "subctx_gv11b.h" #include "gr_gv11b.h" -#define CHANNEL_INFO_VEID0 0 #define PBDMA_SUBDEVICE_ID 1 static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, @@ -94,7 +93,8 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) /* Time being use 0 pbdma sequencer */ runlist_entry = ram_rl_entry_type_channel_v() | - ram_rl_entry_chan_runqueue_selector_f(0) | + ram_rl_entry_chan_runqueue_selector_f( + c->t19x.runqueue_sel) | ram_rl_entry_chan_userd_target_f( ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | ram_rl_entry_chan_inst_target_f( @@ -178,10 +178,14 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); - /* Until full subcontext is supported, always use VEID0 */ - nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), - pbdma_set_channel_info_scg_type_graphics_compute0_f() | - pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); + if (c->t19x.subctx_id == CHANNEL_INFO_VEID0) + nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), + pbdma_set_channel_info_scg_type_graphics_compute0_f() | + pbdma_set_channel_info_veid_f(c->t19x.subctx_id)); + else + nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), + pbdma_set_channel_info_scg_type_compute1_f() | + pbdma_set_channel_info_veid_f(c->t19x.subctx_id)); gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 03cca839..032342b2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -1,7 +1,7 @@ /* * GV11B Fifo * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -36,6 +36,8 @@ #define GR_RUNQUE 0 /* pbdma 0 */ #define ASYNC_CE_RUNQUE 2 /* pbdma 2 */ +#define CHANNEL_INFO_VEID0 0 + struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index 09628940..69fd0cf4 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c @@ -1,7 +1,7 @@ /* * GV11B Graphics * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,5 +23,7 @@ int gv11b_init_gpu_characteristics(struct gk20a *g) { gk20a_init_gpu_characteristics(g); + g->gpu_characteristics.flags |= + NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; return 0; } diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 79ed0d1e..cb042f87 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -31,12 +31,17 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block); +static void gv11b_subctx_commit_valid_mask(struct channel_gk20a *c, + struct nvgpu_mem *inst_block); +static void gv11b_subctx_commit_pdb(struct channel_gk20a *c, + struct nvgpu_mem *inst_block); + void gv11b_free_subctx_header(struct channel_gk20a *c) { struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; struct gk20a *g = c->g; - gk20a_dbg_fn(""); + nvgpu_log(g, gpu_dbg_fn, "gv11b_free_subctx_header"); if (ctx->mem.gpu_va) { nvgpu_gmmu_unmap(c->vm, &ctx->mem, ctx->mem.gpu_va); @@ -52,7 +57,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) struct gr_gk20a *gr = &g->gr; int ret = 0; - gk20a_dbg_fn(""); + nvgpu_log(g, gpu_dbg_fn, "gv11b_alloc_subctx_header"); if (ctx->mem.gpu_va == 0) { ret = nvgpu_dma_alloc_flags_sys(g, @@ -82,7 +87,6 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) nvgpu_mem_end(g, &ctx->mem); gv11b_init_subcontext_pdb(c, &c->inst_block); - } return ret; } @@ -91,37 +95,13 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block) { struct gk20a *g = c->g; - struct vm_gk20a *vm; - u64 pdb_addr, pdb_addr_lo, pdb_addr_hi; - u32 format_word; - u32 lo, hi; - gk20a_dbg_fn(""); - /* load main pdb as veid0 pdb also */ - vm = c->vm; - pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.priv.sgt->sgl, 0); - pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); - pdb_addr_hi = u64_hi32(pdb_addr); - format_word = ram_in_sc_page_dir_base_target_f( - ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | - ram_in_sc_page_dir_base_vol_f( - ram_in_sc_page_dir_base_vol_true_v(), 0) | - ram_in_sc_page_dir_base_fault_replay_tex_f(0, 0) | - ram_in_sc_page_dir_base_fault_replay_gcc_f(0, 0) | - ram_in_sc_use_ver2_pt_format_f(1, 0) | - ram_in_sc_big_page_size_f(1, 0) | - ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); - lo = ram_in_sc_page_dir_base_vol_0_w(); - hi = ram_in_sc_page_dir_base_hi_0_w(); - nvgpu_mem_wr32(g, inst_block, lo, format_word); - nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); - - /* make subcontext0 address space to valid */ - /* TODO fix proper hw register definations */ - nvgpu_mem_wr32(g, inst_block, 166, 0x1); - nvgpu_mem_wr32(g, inst_block, 167, 0); + gv11b_subctx_commit_pdb(c, inst_block); + gv11b_subctx_commit_valid_mask(c, inst_block); + + nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->t19x.subctx_id); nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), - ram_in_engine_wfi_veid_f(0)); + ram_in_engine_wfi_veid_f(c->t19x.subctx_id)); } @@ -149,7 +129,51 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) return ret; } -int gv11b_get_max_subctx_count(struct gk20a *g) +void gv11b_subctx_commit_valid_mask(struct channel_gk20a *c, + struct nvgpu_mem *inst_block) +{ + struct gk20a *g = c->g; + + /* Make all subctx pdbs valid */ + nvgpu_mem_wr32(g, inst_block, 166, 0xffffffff); + nvgpu_mem_wr32(g, inst_block, 167, 0xffffffff); +} + +void gv11b_subctx_commit_pdb(struct channel_gk20a *c, + struct nvgpu_mem *inst_block) +{ + struct gk20a *g = c->g; + u32 lo, hi; + u32 subctx_id = 0; + u32 format_word; + u32 pdb_addr_lo, pdb_addr_hi; + u64 pdb_addr; + + pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem.priv.sgt->sgl, 0); + pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); + pdb_addr_hi = u64_hi32(pdb_addr); + format_word = ram_in_sc_page_dir_base_target_f( + ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | + ram_in_sc_page_dir_base_vol_f( + ram_in_sc_page_dir_base_vol_true_v(), 0) | + ram_in_sc_page_dir_base_fault_replay_tex_f(0, 0) | + ram_in_sc_page_dir_base_fault_replay_gcc_f(0, 0) | + ram_in_sc_use_ver2_pt_format_f(1, 0) | + ram_in_sc_big_page_size_f(1, 0) | + ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); + nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", + format_word, pdb_addr_hi); + for (subctx_id = 0; subctx_id < gv11b_get_max_subctx_count(g); + subctx_id++) { + lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); + hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); + nvgpu_mem_wr32(g, inst_block, lo, format_word); + nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); + } +} + + +u32 gv11b_get_max_subctx_count(struct gk20a *g) { u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r()); diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h index fdfe9e3b..5e4e99f5 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h @@ -25,5 +25,5 @@ void gv11b_free_subctx_header(struct channel_gk20a *c); int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va); -int gv11b_get_max_subctx_count(struct gk20a *g); +u32 gv11b_get_max_subctx_count(struct gk20a *g); #endif /* __SUBCONTEXT_GV11B_H__ */ diff --git a/drivers/gpu/nvgpu/tsg_t19x.h b/drivers/gpu/nvgpu/tsg_t19x.h new file mode 100644 index 00000000..2f359668 --- /dev/null +++ b/drivers/gpu/nvgpu/tsg_t19x.h @@ -0,0 +1,21 @@ +/* + * NVIDIA T19x TSG + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_TSG_T19X_H_ +#define _NVGPU_TSG_T19X_H_ + +#include "common/linux/ioctl_tsg_t19x.h" + +#endif diff --git a/include/uapi/linux/nvgpu-t19x.h b/include/uapi/linux/nvgpu-t19x.h index 6a10fb77..96514a88 100644 --- a/include/uapi/linux/nvgpu-t19x.h +++ b/include/uapi/linux/nvgpu-t19x.h @@ -1,7 +1,7 @@ /* * NVGPU Public Interface Header * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -27,4 +27,24 @@ #define NVGPU_GPU_ARCH_GV110 0x00000150 #define NVGPU_GPU_IMPL_GV11B 0x0000000B +/* subcontexts are available */ +#define NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS (1ULL << 22) + +struct nvgpu_tsg_bind_channel_ex_args { + /* in: channel fd */ + __s32 channel_fd; + + /* in: VEID in Volta */ + __u32 subcontext_id; + + __u64 reserved[2]; +}; + +#define NVGPU_TSG_IOCTL_BIND_CHANNEL_EX \ + _IOWR(NVGPU_TSG_IOCTL_MAGIC, 11, struct nvgpu_tsg_bind_channel_ex_args) + +#define NVGPU_TSG_IOCTL_MAX NVGPU_TSG_IOCTL_BIND_CHANNEL_EX + +#define NVGPU_TSG_IOCTL_MAX_ARG sizeof(struct nvgpu_tsg_bind_channel_ex_args) + #endif /* _UAPI__LINUX_NVGPU_T19X_IOCTL_H_ */ -- cgit v1.2.2 From efd9ba3a797ee5b7edf4fb9464c802d3d5d29b68 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sun, 2 Jul 2017 12:59:28 -0700 Subject: gpu: nvgpu: gv11b: Use g->name instead of dev_name() Dump device name using g->name instead of dev_name(). dev_name() is Linux specific. Change-Id: I65eb89e41ca81ca6143fb247a10c306b4efc96ad Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master/r/1512176 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index ace873e9..b0d182dc 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -288,7 +288,7 @@ static void gv11b_dump_channel_status_ramfc(struct gk20a *g, inst_mem = &ch_state->inst_block[0]; gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", chid, - dev_name(g->dev), + g->name, ch_state->pid, ch_state->refs); gk20a_debug_output(o, "channel status: %s in use %s %s\n", @@ -333,7 +333,7 @@ static void gv11b_dump_eng_status(struct gk20a *g, u32 status = gk20a_readl(g, fifo_engine_status_r(i)); u32 ctx_status = fifo_engine_status_ctx_status_v(status); - gk20a_debug_output(o, "%s eng %d: ", dev_name(g->dev), i); + gk20a_debug_output(o, "%s eng %d: ", g->name, i); gk20a_debug_output(o, "id: %d (%s), next_id: %d (%s), ctx status: %s ", fifo_engine_status_id_v(status), -- cgit v1.2.2 From ce308666f55cd4699c9e118cac291879ddc066ed Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 5 Jul 2017 16:25:35 +0530 Subject: gpu: nvgpu: gv11b, use nvgpu_flcn_bootstrap() - Replaced falcon bootstrap code with nvgpu_flcn_bootstrap() method JIRA NVGPU-102 Change-Id: I5133419957c890847cac66c5ac018e8188db41e3 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1513647 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index fe468f19..d20b9c1a 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -18,6 +18,9 @@ #include +#include +#include + #include "gk20a/gk20a.h" #include "gp10b/pmu_gp10b.h" @@ -139,11 +142,7 @@ static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE)); } - gk20a_writel(g, pwr_falcon_bootvec_r(), - pwr_falcon_bootvec_vec_f(desc->bootloader_entry_point)); - - gk20a_writel(g, pwr_falcon_cpuctl_r(), - pwr_falcon_cpuctl_startcpu_f(1)); + nvgpu_flcn_bootstrap(pmu->flcn, desc->bootloader_entry_point); gk20a_writel(g, pwr_falcon_os_r(), desc->app_version); -- cgit v1.2.2 From c9b92595b2ac50dbfc2f6e2f9998d469b5ab4fbe Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 28 Jun 2017 16:00:52 -0700 Subject: gpu: nvgpu: gv11b: Reorg misc HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the lone function pointers of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I098559103ef280faca4e82708bb47b9b37057cfd Signed-off-by: Sunny He Reviewed-on: https://git-master/r/1510390 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 147 +++++++++++++++++++----------------- 1 file changed, 76 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0e874c8a..98350e4b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -52,75 +52,6 @@ #include -static const struct gpu_ops gv11b_ops = { - .ltc = { - .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, - .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, - .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, - .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, - .init_cbc = NULL, - .init_fs_state = gv11b_ltc_init_fs_state, - .init_comptags = gp10b_ltc_init_comptags, - .cbc_ctrl = gm20b_ltc_cbc_ctrl, - .isr = gv11b_ltc_isr, - .cbc_fix_config = gv11b_ltc_cbc_fix_config, - .flush = gm20b_flush_ltc, -#ifdef CONFIG_DEBUG_FS - .sync_debugfs = gp10b_ltc_sync_debugfs, -#endif - }, - .clock_gating = { - .slcg_bus_load_gating_prod = - gv11b_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gv11b_slcg_ce2_load_gating_prod, - .slcg_chiplet_load_gating_prod = - gv11b_slcg_chiplet_load_gating_prod, - .slcg_ctxsw_firmware_load_gating_prod = - gv11b_slcg_ctxsw_firmware_load_gating_prod, - .slcg_fb_load_gating_prod = - gv11b_slcg_fb_load_gating_prod, - .slcg_fifo_load_gating_prod = - gv11b_slcg_fifo_load_gating_prod, - .slcg_gr_load_gating_prod = - gr_gv11b_slcg_gr_load_gating_prod, - .slcg_ltc_load_gating_prod = - ltc_gv11b_slcg_ltc_load_gating_prod, - .slcg_perf_load_gating_prod = - gv11b_slcg_perf_load_gating_prod, - .slcg_priring_load_gating_prod = - gv11b_slcg_priring_load_gating_prod, - .slcg_pmu_load_gating_prod = - gv11b_slcg_pmu_load_gating_prod, - .slcg_therm_load_gating_prod = - gv11b_slcg_therm_load_gating_prod, - .slcg_xbar_load_gating_prod = - gv11b_slcg_xbar_load_gating_prod, - .blcg_bus_load_gating_prod = - gv11b_blcg_bus_load_gating_prod, - .blcg_ce_load_gating_prod = - gv11b_blcg_ce_load_gating_prod, - .blcg_ctxsw_firmware_load_gating_prod = - gv11b_blcg_ctxsw_firmware_load_gating_prod, - .blcg_fb_load_gating_prod = - gv11b_blcg_fb_load_gating_prod, - .blcg_fifo_load_gating_prod = - gv11b_blcg_fifo_load_gating_prod, - .blcg_gr_load_gating_prod = - gv11b_blcg_gr_load_gating_prod, - .blcg_ltc_load_gating_prod = - gv11b_blcg_ltc_load_gating_prod, - .blcg_pwr_csb_load_gating_prod = - gv11b_blcg_pwr_csb_load_gating_prod, - .blcg_pmu_load_gating_prod = - gv11b_blcg_pmu_load_gating_prod, - .blcg_xbar_load_gating_prod = - gv11b_blcg_xbar_load_gating_prod, - .pg_gr_load_gating_prod = - gr_gv11b_pg_gr_load_gating_prod, - } -}; - static int gv11b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; @@ -202,6 +133,77 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) return ret; } +static const struct gpu_ops gv11b_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = gv11b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gv11b_ltc_isr, + .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gp10b_ltc_sync_debugfs, +#endif + }, + .clock_gating = { + .slcg_bus_load_gating_prod = + gv11b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gv11b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gv11b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gv11b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gv11b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gv11b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gv11b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gv11b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gv11b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gv11b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gv11b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gv11b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gv11b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gv11b_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gv11b_blcg_ce_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gv11b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gv11b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gv11b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gv11b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gv11b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gv11b_blcg_pwr_csb_load_gating_prod, + .blcg_pmu_load_gating_prod = + gv11b_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gv11b_blcg_xbar_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gv11b_pg_gr_load_gating_prod, + }, + .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, + .get_litter_value = gv11b_get_litter_value, +}; + int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; @@ -210,6 +212,11 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; + /* Lone functions */ + gops->chip_init_gpu_characteristics = + gv11b_ops.chip_init_gpu_characteristics; + gops->get_litter_value = gv11b_ops.get_litter_value; + /* boot in non-secure modes for time beeing */ gops->privsecurity = 0; gops->securegpccs = 0; @@ -235,8 +242,6 @@ int gv11b_init_hal(struct gk20a *g) gk20a_init_css_ops(gops); #endif g->name = "gv11b"; - gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; - gops->get_litter_value = gv11b_get_litter_value; c->twod_class = FERMI_TWOD_A; c->threed_class = VOLTA_A; -- cgit v1.2.2 From d250adf53e836ea982193ad8a3e08084411d81a2 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 21 Jun 2017 20:47:25 -0700 Subject: gpu: nvgpu: gv11b: init gr ops get_sm_hww_global_esr Required for multiple SM support and sm register address changes JIRA GPUT19X-75 Change-Id: I3fb62a935636f3df050ed125ebe57d8469069591 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1514035 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 2b083203..0fcbd0d7 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1786,7 +1786,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, } /* reset the HWW errors after locking down */ - global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); + global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g, + gpc, tpc, sm); gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: HWWs cleared for " @@ -2995,6 +2996,19 @@ static u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, return hww_warp_esr; } +static u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm) +{ + u32 offset = gk20a_gr_gpc_offset(g, gpc) + + gk20a_gr_tpc_offset(g, tpc) + + gv11b_gr_sm_offset(g, sm); + + u32 hww_global_esr = gk20a_readl(g, + gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); + + return hww_global_esr; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3069,4 +3083,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.resume_all_sms = gv11b_gr_resume_all_sms; gops->gr.resume_from_pause = gv11b_gr_resume_from_pause; gops->gr.get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr; + gops->gr.get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr; } -- cgit v1.2.2 From bdf5207583a3c8f3bd4d844548d443f1454d26f5 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Jun 2017 10:37:09 -0700 Subject: gpu: nvgpu: gv11b: init get_sm_no_lock_down_hww_global_esr_mask gr ops Support SM register changes JIRA GPUT19X-75 Change-Id: I5d5e702d681398a8a8181d912e8c691c15e265d9 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1514036 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 0fcbd0d7..a726d058 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -3009,6 +3009,23 @@ static u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, return hww_global_esr; } +static u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) +{ + /* + * These three interrupts don't require locking down the SM. They can + * be handled by usermode clients as they aren't fatal. Additionally, + * usermode clients may wish to allow some warps to execute while others + * are at breakpoints, as opposed to fatal errors where all warps should + * halt. + */ + u32 global_esr_mask = + gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f() | + gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f() | + gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(); + + return global_esr_mask; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3084,4 +3101,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.resume_from_pause = gv11b_gr_resume_from_pause; gops->gr.get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr; gops->gr.get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr; + gops->gr.get_sm_no_lock_down_hww_global_esr_mask = + gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask; } -- cgit v1.2.2 From 013ead1587b47c296b0328ef076b0ee4628160aa Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Jun 2017 11:43:36 -0700 Subject: gpu: nvgpu: gv11b: init sm lock_down gr ops init lock_down_sm and wait_for_sm_lock_down gr ops Required to support multiple SM and register address changes JIRA GPUT19X-75 Change-Id: I992d1c0c5a1f559dc57bcef50025fa42913d6761 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1514037 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 158 ++++++++++++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index a726d058..63107cfc 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2781,7 +2781,7 @@ static void gv11b_gr_suspend_single_sm(struct gk20a *g, gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset, dbgr_control0); - err = gk20a_gr_wait_for_sm_lock_down(g, gpc, tpc, + err = g->ops.gr.wait_for_sm_lock_down(g, gpc, tpc, sm, global_esr_mask, check_errors); if (err) { nvgpu_err(g, @@ -2822,8 +2822,8 @@ static void gv11b_gr_suspend_all_sms(struct gk20a *g, for (gpc = 0; gpc < gr->gpc_count; gpc++) { for (tpc = 0; tpc < gr_gk20a_get_tpc_count(gr, gpc); tpc++) { for (sm = 0; sm < sm_per_tpc; sm++) { - err = gk20a_gr_wait_for_sm_lock_down(g, - gpc, tpc, + err = g->ops.gr.wait_for_sm_lock_down(g, + gpc, tpc, sm, global_esr_mask, check_errors); if (err) { nvgpu_err(g, @@ -3026,6 +3026,156 @@ static u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) return global_esr_mask; } +static void gv11b_gr_sm_dump_warp_bpt_pause_trap_mask_regs(struct gk20a *g, + u32 offset, bool timeout) +{ + u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0; + u32 dbgr_control0 = gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); + u32 dbgr_status0 = gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_status0_r() + offset); + /* 64 bit read */ + warps_valid = + (u64)gk20a_readl(g, gr_gpc0_tpc0_sm0_warp_valid_mask_1_r() + + offset) << 32; + warps_valid |= gk20a_readl(g, + gr_gpc0_tpc0_sm0_warp_valid_mask_0_r() + offset); + + /* 64 bit read */ + warps_paused = + (u64)gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r() + + offset) << 32; + warps_paused |= gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r() + offset); + + /* 64 bit read */ + warps_trapped = + (u64)gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r() + + offset) << 32; + warps_trapped |= gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r() + offset); + if (timeout) + nvgpu_err(g, + "STATUS0=0x%x CONTROL0=0x%x VALID_MASK=0x%llx " + "PAUSE_MASK=0x%llx TRAP_MASK=0x%llx\n", + dbgr_status0, dbgr_control0, warps_valid, + warps_paused, warps_trapped); + else + gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, + "STATUS0=0x%x CONTROL0=0x%x VALID_MASK=0x%llx " + "PAUSE_MASK=0x%llx TRAP_MASK=0x%llx\n", + dbgr_status0, dbgr_control0, warps_valid, + warps_paused, warps_trapped); +} + +static int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, + u32 global_esr_mask, bool check_errors) +{ + bool locked_down; + bool no_error_pending; + u32 delay = GR_IDLE_CHECK_DEFAULT; + bool mmu_debug_mode_enabled = g->ops.fb.is_debug_mode_enabled(g); + u32 dbgr_status0 = 0; + u32 warp_esr, global_esr; + struct nvgpu_timeout timeout; + u32 offset = gk20a_gr_gpc_offset(g, gpc) + + gk20a_gr_tpc_offset(g, tpc); + gv11b_gr_sm_offset(g, sm); + + gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, + "GPC%d TPC%d: locking down SM%d", gpc, tpc, sm); + + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + + /* wait for the sm to lock down */ + do { + global_esr = g->ops.gr.get_sm_hww_global_esr(g, gpc, tpc, sm); + dbgr_status0 = gk20a_readl(g, + gr_gpc0_tpc0_sm0_dbgr_status0_r() + offset); + + warp_esr = g->ops.gr.get_sm_hww_warp_esr(g, gpc, tpc, sm); + + locked_down = + (gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(dbgr_status0) == + gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v()); + no_error_pending = + check_errors && + (gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(warp_esr) == + gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v()) && + ((global_esr & ~global_esr_mask) == 0); + + if (locked_down) { + /* + * if SM reports locked down, it means that SM is idle and + * trapped and also that one of the these conditions are true + * 1) sm is nonempty and all valid warps are paused + * 2) sm is empty and held in trapped state due to stop trigger + * 3) sm is nonempty and some warps are not paused, but are + * instead held at RTT due to an "active" stop trigger + * Check for Paused warp mask != Valid + * warp mask after SM reports it is locked down in order to + * distinguish case 1 from case 3. When case 3 is detected, + * it implies a misprogrammed trap handler code, as all warps + * in the handler must promise to BPT.PAUSE instead of RTT + * whenever SR64 read in trap mode indicates stop trigger + * is asserted. + */ + gv11b_gr_sm_dump_warp_bpt_pause_trap_mask_regs(g, + offset, false); + } + + if (locked_down || no_error_pending) { + gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, + "GPC%d TPC%d: locked down SM%d", gpc, tpc, sm); + return 0; + } + + /* if an mmu fault is pending and mmu debug mode is not + * enabled, the sm will never lock down. + */ + if (!mmu_debug_mode_enabled && + (g->ops.mm.mmu_fault_pending(g))) { + nvgpu_err(g, + "GPC%d TPC%d: mmu fault pending," + " SM%d will never lock down!", gpc, tpc, sm); + return -EFAULT; + } + + nvgpu_usleep_range(delay, delay * 2); + delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired(&timeout)); + + nvgpu_err(g, "GPC%d TPC%d: timed out while trying to " + "lock down SM%d", gpc, tpc, sm); + gv11b_gr_sm_dump_warp_bpt_pause_trap_mask_regs(g, offset, true); + + return -ETIMEDOUT; +} + +static int gv11b_gr_lock_down_sm(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, + bool check_errors) +{ + u32 dbgr_control0; + u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc) + + gv11b_gr_sm_offset(g, sm); + + gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, + "GPC%d TPC%d SM%d: assert stop trigger", gpc, tpc, sm); + + /* assert stop trigger */ + dbgr_control0 = + gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); + dbgr_control0 |= gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(); + gk20a_writel(g, + gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset, dbgr_control0); + + return g->ops.gr.wait_for_sm_lock_down(g, gpc, tpc, sm, global_esr_mask, + check_errors); +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3103,4 +3253,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr; gops->gr.get_sm_no_lock_down_hww_global_esr_mask = gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask; + gops->gr.lock_down_sm = gv11b_gr_lock_down_sm; + gops->gr.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down; } -- cgit v1.2.2 From 99aeb5ae3b5606ffbeb168d25bec4adc541e1236 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Jun 2017 13:39:45 -0700 Subject: gpu: nvgpu: gv11b: init clear_sm_hww gr ops Required for multiple SM support and SM register address changes JIRA GPUT19X-75 Change-Id: I552bae890a416dc4a430b907641b5b3d09b638c7 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1514038 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 63107cfc..9da270ac 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1788,7 +1788,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, /* reset the HWW errors after locking down */ global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g, gpc, tpc, sm); - gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); + g->ops.gr.clear_sm_hww(g, + gpc, tpc, sm, global_esr_copy); gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: HWWs cleared for " "gpc %d tpc %d sm %d", @@ -3176,6 +3177,26 @@ static int gv11b_gr_lock_down_sm(struct gk20a *g, check_errors); } +static void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, + u32 global_esr) +{ + u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc) + + gv11b_gr_sm_offset(g, sm); + + gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, + global_esr); + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "Cleared HWW global esr, current reg val: 0x%x", + gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + + offset)); + + gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset, 0); + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "Cleared HWW warp esr, current reg val: 0x%x", + gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_warp_esr_r() + + offset)); +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3255,4 +3276,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask; gops->gr.lock_down_sm = gv11b_gr_lock_down_sm; gops->gr.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down; + gops->gr.clear_sm_hww = gv11b_gr_clear_sm_hww; } -- cgit v1.2.2 From 1f09340f82af277722deaa0e04e98a88f1e41044 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Jun 2017 14:06:18 -0700 Subject: gpu: nvgpu: gv11b: init handle_sm_exception gr ops gr_gk20a_handle_sm_exception is initialized to handle_sm_exception and new gr ops handle_tpc_sm_ecc_exception is initialized to gr_gv11b_handle_tpc_sm_ecc_exception to handle sm ecc errors per tpc. JIRA GPUT19X-75 JIRA GPUT19X-109 Change-Id: Iefa95b185b9eed23f9f54e231405fcd9fd83ccc0 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1514039 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 9da270ac..d61506c2 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -589,9 +589,10 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, } -static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, - u32 sm, bool *post_event, struct channel_gk20a *fault_ch, - u32 *hww_global_esr) +static int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, + u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr) { int ret = 0; @@ -3228,7 +3229,7 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.init_cyclestats = gr_gv11b_init_cyclestats; gops->gr.set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask; gops->gr.get_access_map = gr_gv11b_get_access_map; - gops->gr.handle_sm_exception = gr_gv11b_handle_sm_exception; + gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; gops->gr.handle_gcc_exception = gr_gv11b_handle_gcc_exception; gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; @@ -3277,4 +3278,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.lock_down_sm = gv11b_gr_lock_down_sm; gops->gr.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down; gops->gr.clear_sm_hww = gv11b_gr_clear_sm_hww; + gops->gr.handle_tpc_sm_ecc_exception = + gr_gv11b_handle_tpc_sm_ecc_exception; } -- cgit v1.2.2 From 6745200c6f5d5336bf3fbca6ed00794c2deec5ec Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 8 Jun 2017 15:05:19 -0700 Subject: gpu: nvgpu: Implement PD packing Necessary Volta changes for equivalent change in nvgpu. JIRA NVGPU-30 Change-Id: I541d6d6005bc7ea0bfb654d0f5f5554e46afc510 Signed-off-by: Alex Waterman Reviewed-on: https://git-master/r/1506611 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index cb042f87..68e969d0 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -149,7 +149,7 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, u32 pdb_addr_lo, pdb_addr_hi; u64 pdb_addr; - pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem.priv.sgt->sgl, 0); + pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem->priv.sgt->sgl, 0); pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); pdb_addr_hi = u64_hi32(pdb_addr); format_word = ram_in_sc_page_dir_base_target_f( -- cgit v1.2.2 From cca0510e477944e8781184592a95debd7742262d Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 3 Jul 2017 16:10:16 +0530 Subject: gpu: nvgpu: enable IO coherence support flag for gv11b Set flag NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE for gv11b to indicate IO coherence support is enabled Jira GPUT19X-17 Bug 1651331 Bug 200283998 Change-Id: If74db3de293e8ebd39e45d81cd1c0d1f7aa01d2d Signed-off-by: Deepak Nibade Reviewed-on: https://git-master/r/1512601 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index 69fd0cf4..d0fb41c3 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c @@ -24,6 +24,7 @@ int gv11b_init_gpu_characteristics(struct gk20a *g) { gk20a_init_gpu_characteristics(g); g->gpu_characteristics.flags |= - NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; + NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS | + NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE; return 0; } -- cgit v1.2.2 From afa31cdd8cc6bb04faeed30b2cc30f5e6be888b5 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 3 Jul 2017 16:40:44 +0530 Subject: gpu: nvgpu: add support for L3 cache allocation of buffers Add gv11b implementation of gpu_phys_addr() that checks the t19x GMMU attributes struct to determine if L3 allocation should be enabled. If L3 alloc is enabled then a special physical address bit is set. Add flag NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC to struct nvgpu_as_map_buffer_ex_args so that User space can add a hint to allocate buffer in L3 cache Jira GPUT19X-10 Bug 200279508 Change-Id: I1bb9876a670b252980922aa50e3e69b802be137f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master/r/1512602 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/common/mm/gmmu_t19x.c | 25 +++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 17 +++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h | 28 ++++++++++++++++++++++++++++ include/uapi/linux/nvgpu-t19x.h | 6 ++++++ 5 files changed, 77 insertions(+) create mode 100644 drivers/gpu/nvgpu/common/mm/gmmu_t19x.c create mode 100644 drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 33391a80..6fdabe62 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -1,6 +1,7 @@ nvgpu-t19x := ../../../../nvgpu-t19x/drivers/gpu/nvgpu nvgpu-y += \ + $(nvgpu-t19x)/common/mm/gmmu_t19x.o \ $(nvgpu-t19x)/common/linux/ioctl_tsg_t19x.o \ $(nvgpu-t19x)/gv11b/gv11b.o \ $(nvgpu-t19x)/gv11b/bus_gv11b.o \ diff --git a/drivers/gpu/nvgpu/common/mm/gmmu_t19x.c b/drivers/gpu/nvgpu/common/mm/gmmu_t19x.c new file mode 100644 index 00000000..05abec1b --- /dev/null +++ b/drivers/gpu/nvgpu/common/mm/gmmu_t19x.c @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include + +void nvgpu_gmmu_add_t19x_attrs(struct nvgpu_gmmu_attrs *attrs, u32 flags) +{ + attrs->t19x_attrs.l3_alloc = (bool)(flags & + NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC); +} diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 9d1e0f25..cc8dafa3 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -23,6 +23,8 @@ #include +#define NVGPU_L3_ALLOC_BIT 36 + static bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; @@ -61,6 +63,20 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) g->ops.mm.fb_flush(g); } +/* + * On Volta the GPU determines whether to do L3 allocation for a mapping by + * checking bit 36 of the phsyical address. So if a mapping should allocte lines + * in the L3 this bit must be set. + */ +u64 gv11b_gpu_phys_addr(struct gk20a *g, + struct nvgpu_gmmu_attrs *attrs, u64 phys) +{ + if (attrs->t19x_attrs.l3_alloc) + return phys | NVGPU_L3_ALLOC_BIT; + + return phys; +} + void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); @@ -69,4 +85,5 @@ void gv11b_init_mm(struct gpu_ops *gops) gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; gops->mm.l2_flush = gv11b_mm_l2_flush; + gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h new file mode 100644 index 00000000..8e1a4846 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVGPU_GMMU_T19X_H__ +#define __NVGPU_GMMU_T19X_H__ + +struct nvgpu_gmmu_attrs; + +struct nvgpu_gmmu_attrs_t19x { + bool l3_alloc; +}; + +void nvgpu_gmmu_add_t19x_attrs(struct nvgpu_gmmu_attrs *attrs, u32 flags); + +#endif diff --git a/include/uapi/linux/nvgpu-t19x.h b/include/uapi/linux/nvgpu-t19x.h index 96514a88..bc37bc7c 100644 --- a/include/uapi/linux/nvgpu-t19x.h +++ b/include/uapi/linux/nvgpu-t19x.h @@ -27,6 +27,12 @@ #define NVGPU_GPU_ARCH_GV110 0x00000150 #define NVGPU_GPU_IMPL_GV11B 0x0000000B +/* + * this flag is used in struct nvgpu_as_map_buffer_ex_args + * to provide L3 cache allocation hint + */ +#define NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC (1 << 7) + /* subcontexts are available */ #define NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS (1ULL << 22) -- cgit v1.2.2 From cf33b6c26bd054f5fe09be78ed754049821a8737 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 2 Jun 2017 09:06:42 -0700 Subject: gpu: nvgpu: gv11b: generated mmu fault fields/masks Generated h/w header for mmu fault handling JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I857ab6b67f6d9ac9a2c2ee982496dd0603bd010e Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1494842 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 268 ++++++++------------- .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 8 + .../nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h | 10 +- 3 files changed, 113 insertions(+), 173 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index e261ef14..fd5427ec 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -174,6 +174,10 @@ static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) { return 0x10; } +static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) +{ + return 0x20; +} static inline u32 fb_mmu_invalidate_sys_membar_s(void) { return 1; @@ -742,65 +746,65 @@ static inline u32 fb_niso_intr_r(void) { return 0x00100a20; } -static inline u32 fb_niso_intr_hub_access_counter_notify_f(u32 v) +static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) { - return (v & 0x1) << 0; + return 0x1 << 0; } static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) { return 0x1; } -static inline u32 fb_niso_intr_hub_access_counter_error_f(u32 v) +static inline u32 fb_niso_intr_hub_access_counter_error_m(void) { - return (v & 0x1) << 1; + return 0x1 << 1; } static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) { return 0x2; } -static inline u32 fb_niso_intr_mmu_replayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) { - return (v & 0x1) << 27; + return 0x1 << 27; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) { return 0x8000000; } -static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) { - return (v & 0x1) << 28; + return 0x1 << 28; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) { return 0x10000000; } -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) { - return (v & 0x1) << 29; + return 0x1 << 29; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) { return 0x20000000; } -static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) { - return (v & 0x1) << 30; + return 0x1 << 30; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) { return 0x40000000; } -static inline u32 fb_niso_intr_mmu_other_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) { - return (v & 0x1) << 31; + return 0x1 << 31; } static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) { return 0x80000000; } -static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_f(u32 v) +static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_m(void) { - return (v & 0x1) << 26; + return 0x1 << 26; } static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) { @@ -886,65 +890,65 @@ static inline u32 fb_niso_intr_en_set__size_1_v(void) { return 0x00000002; } -static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_f(u32 v) +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) { - return (v & 0x1) << 0; + return 0x1 << 0; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) { return 0x1; } -static inline u32 fb_niso_intr_en_set_hub_access_counter_error_f(u32 v) +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) { - return (v & 0x1) << 1; + return 0x1 << 1; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) { return 0x2; } -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) { - return (v & 0x1) << 27; + return 0x1 << 27; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) { return 0x8000000; } -static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) { - return (v & 0x1) << 28; + return 0x1 << 28; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) { return 0x10000000; } -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) { - return (v & 0x1) << 29; + return 0x1 << 29; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) { return 0x20000000; } -static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) { - return (v & 0x1) << 30; + return 0x1 << 30; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) { return 0x40000000; } -static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) { - return (v & 0x1) << 31; + return 0x1 << 31; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) { return 0x80000000; } -static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_f(u32 v) +static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(void) { - return (v & 0x1) << 26; + return 0x1 << 26; } static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) { @@ -958,65 +962,65 @@ static inline u32 fb_niso_intr_en_clr__size_1_v(void) { return 0x00000002; } -static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_f(u32 v) +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) { - return (v & 0x1) << 0; + return 0x1 << 0; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) { return 0x1; } -static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_f(u32 v) +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) { - return (v & 0x1) << 1; + return 0x1 << 1; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) { return 0x2; } -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) { - return (v & 0x1) << 27; + return 0x1 << 27; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) { return 0x8000000; } -static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) { - return (v & 0x1) << 28; + return 0x1 << 28; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) { return 0x10000000; } -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) { - return (v & 0x1) << 29; + return 0x1 << 29; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) { return 0x20000000; } -static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) { - return (v & 0x1) << 30; + return 0x1 << 30; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) { return 0x40000000; } -static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) { - return (v & 0x1) << 31; + return 0x1 << 31; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) { return 0x80000000; } -static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_f(u32 v) +static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(void) { - return (v & 0x1) << 26; + return 0x1 << 26; } static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) { @@ -1142,13 +1146,9 @@ static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) { return (v & 0x1) << 30; } -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_v(u32 r) +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) { - return (r >> 30) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_yes_v(void) -{ - return 0x00000001; + return 0x1 << 30; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) { @@ -1162,17 +1162,9 @@ static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) { return (v & 0x1) << 31; } -static inline u32 fb_mmu_fault_buffer_get_overflow_v(u32 r) +static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) { - return (r >> 31) & 0x1; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_yes_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_fault_buffer_get_overflow_yes_f(void) -{ - return 0x80000000; + return 0x1 << 31; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) { @@ -1290,6 +1282,10 @@ static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) { return (v & 0x1) << 31; } +static inline u32 fb_mmu_fault_buffer_size_enable_m(void) +{ + return 0x1 << 31; +} static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) { return (r >> 31) & 0x1; @@ -1430,13 +1426,9 @@ static inline u32 fb_mmu_fault_status_r(void) { return 0x00100e60; } -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_phys_v(u32 r) +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) { - return (r >> 0) & 0x1; + return 0x1 << 0; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) { @@ -1454,13 +1446,9 @@ static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) { return 0x1; } -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 fb_mmu_fault_status_dropped_bar1_virt_v(u32 r) +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) { - return (r >> 1) & 0x1; + return 0x1 << 1; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) { @@ -1478,13 +1466,9 @@ static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) { return 0x2; } -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_phys_v(u32 r) +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) { - return (r >> 2) & 0x1; + return 0x1 << 2; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) { @@ -1502,13 +1486,9 @@ static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) { return 0x4; } -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_f(u32 v) +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) { - return (v & 0x1) << 3; -} -static inline u32 fb_mmu_fault_status_dropped_bar2_virt_v(u32 r) -{ - return (r >> 3) & 0x1; + return 0x1 << 3; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) { @@ -1526,13 +1506,9 @@ static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) { return 0x8; } -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_phys_v(u32 r) +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) { - return (r >> 4) & 0x1; + return 0x1 << 4; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) { @@ -1550,13 +1526,9 @@ static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) { return 0x10; } -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_f(u32 v) +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) { - return (v & 0x1) << 5; -} -static inline u32 fb_mmu_fault_status_dropped_ifb_virt_v(u32 r) -{ - return (r >> 5) & 0x1; + return 0x1 << 5; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) { @@ -1574,13 +1546,9 @@ static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) { return 0x20; } -static inline u32 fb_mmu_fault_status_dropped_other_phys_f(u32 v) +static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) { - return (v & 0x1) << 6; -} -static inline u32 fb_mmu_fault_status_dropped_other_phys_v(u32 r) -{ - return (r >> 6) & 0x1; + return 0x1 << 6; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) { @@ -1598,13 +1566,9 @@ static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) { return 0x40; } -static inline u32 fb_mmu_fault_status_dropped_other_virt_f(u32 v) +static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) { - return (v & 0x1) << 7; -} -static inline u32 fb_mmu_fault_status_dropped_other_virt_v(u32 r) -{ - return (r >> 7) & 0x1; + return 0x1 << 7; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) { @@ -1622,13 +1586,9 @@ static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) { return 0x80; } -static inline u32 fb_mmu_fault_status_replayable_f(u32 v) +static inline u32 fb_mmu_fault_status_replayable_m(void) { - return (v & 0x1) << 8; -} -static inline u32 fb_mmu_fault_status_replayable_v(u32 r) -{ - return (r >> 8) & 0x1; + return 0x1 << 8; } static inline u32 fb_mmu_fault_status_replayable_set_v(void) { @@ -1642,13 +1602,9 @@ static inline u32 fb_mmu_fault_status_replayable_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_non_replayable_f(u32 v) -{ - return (v & 0x1) << 9; -} -static inline u32 fb_mmu_fault_status_non_replayable_v(u32 r) +static inline u32 fb_mmu_fault_status_non_replayable_m(void) { - return (r >> 9) & 0x1; + return 0x1 << 9; } static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) { @@ -1662,13 +1618,9 @@ static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_replayable_error_f(u32 v) +static inline u32 fb_mmu_fault_status_replayable_error_m(void) { - return (v & 0x1) << 10; -} -static inline u32 fb_mmu_fault_status_replayable_error_v(u32 r) -{ - return (r >> 10) & 0x1; + return 0x1 << 10; } static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) { @@ -1682,13 +1634,9 @@ static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_non_replayable_error_f(u32 v) -{ - return (v & 0x1) << 11; -} -static inline u32 fb_mmu_fault_status_non_replayable_error_v(u32 r) +static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) { - return (r >> 11) & 0x1; + return 0x1 << 11; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) { @@ -1702,13 +1650,9 @@ static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_replayable_overflow_f(u32 v) -{ - return (v & 0x1) << 12; -} -static inline u32 fb_mmu_fault_status_replayable_overflow_v(u32 r) +static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) { - return (r >> 12) & 0x1; + return 0x1 << 12; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) { @@ -1722,13 +1666,9 @@ static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_non_replayable_overflow_f(u32 v) +static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) { - return (v & 0x1) << 13; -} -static inline u32 fb_mmu_fault_status_non_replayable_overflow_v(u32 r) -{ - return (r >> 13) & 0x1; + return 0x1 << 13; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) { @@ -1742,13 +1682,9 @@ static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) { return 0x0; } -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_f(u32 v) +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) { - return (v & 0x1) << 14; -} -static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_v(u32 r) -{ - return (r >> 14) & 0x1; + return 0x1 << 14; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) { @@ -1758,13 +1694,9 @@ static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) { return 0x4000; } -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_f(u32 v) -{ - return (v & 0x1) << 15; -} -static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_v(u32 r) +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) { - return (r >> 15) & 0x1; + return 0x1 << 15; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) { @@ -1774,13 +1706,9 @@ static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void { return 0x8000; } -static inline u32 fb_mmu_fault_status_busy_f(u32 v) +static inline u32 fb_mmu_fault_status_busy_m(void) { - return (v & 0x1) << 30; -} -static inline u32 fb_mmu_fault_status_busy_v(u32 r) -{ - return (r >> 30) & 0x1; + return 0x1 << 30; } static inline u32 fb_mmu_fault_status_busy_true_v(void) { @@ -1790,13 +1718,9 @@ static inline u32 fb_mmu_fault_status_busy_true_f(void) { return 0x40000000; } -static inline u32 fb_mmu_fault_status_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_mmu_fault_status_valid_v(u32 r) +static inline u32 fb_mmu_fault_status_valid_m(void) { - return (r >> 31) & 0x1; + return 0x1 << 31; } static inline u32 fb_mmu_fault_status_valid_set_v(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index 22ad23bc..383f7773 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -1274,6 +1274,10 @@ static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) { return 0x0000001f; } +static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) +{ + return 0x0000000f; +} static inline u32 gmmu_fault_buf_size_v(void) { return 0x00000020; @@ -1458,6 +1462,10 @@ static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) { return 0x40000000; } +static inline u32 gmmu_fault_buf_entry_valid_m(void) +{ + return 0x1 << 31; +} static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) { return (r >> 31) & 0x1; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h index 2e2ff6ba..dbfc99b9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -94,6 +94,14 @@ static inline u32 top_num_ltcs_r(void) { return 0x00022454; } +static inline u32 top_num_ces_r(void) +{ + return 0x00022444; +} +static inline u32 top_num_ces_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} static inline u32 top_device_info_r(u32 i) { return 0x00022700 + i*4; -- cgit v1.2.2 From aa05648fd6038b69d1ed841f33b24cf1875efd83 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 2 Jun 2017 09:58:23 -0700 Subject: gpu: nvgpu: gv11b: set up for enabling/handling hub intr -implement mm ops init_mm_setup_hw This will also call *fault*setup* that will do s/w and h/w set up required to get mmu fault info -implement s/w set up for copying mmu faults Two shadow fault buffers are pre allocated which will be used to copy fault info. One for copying from fault snap registers/nonreplayable h/w fault buffers and one for replay h/w fault buffers -implement s/w set up for buffering mmu faults Replayable/Non-replayable fault buffers are mapped in BAR2 virtual/physical address space. These buffers are circular buffers in terms of address calculation. Currently there are num host channels buffers -configure h/w for buffering mmu faults if s/w set up is successful, configure h/w registers to enable buffered mode of mmu faults -if both s/w and h/w set up are successful, enable corresponding hub interrupts -implement new ops, fault_info_buf_deinit This will be called during gk20a_mm_destroy to disable hub intr and de-allocate shadow fault buf that is used to copy mmu fault info during mmu fault handling -implement mm ops remove_bar2_vm This will also unmap and free fault buffers mapped in BAR2 if fault buffers were allocated JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1492682 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 173 +++++++++++++++++++++++++++++--- drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 12 ++- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 19 ++-- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 198 +++++++++++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/mm_gv11b.h | 5 +- 5 files changed, 379 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 21d8cba3..da7c7d4a 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -15,6 +15,9 @@ #include +#include +#include + #include "gk20a/gk20a.h" #include "gk20a/kind_gk20a.h" @@ -26,6 +29,7 @@ #include #include #include +#include #include #include @@ -205,6 +209,90 @@ static void gv11b_init_kind_attr(void) } } +u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g, + unsigned int index) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fb_mmu_fault_buffer_size_r(index)); + return fb_mmu_fault_buffer_size_enable_v(reg_val); +} + +void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g, + unsigned int index, unsigned int state) +{ + u32 fault_status; + u32 reg_val; + + nvgpu_log_fn(g, " "); + + reg_val = gk20a_readl(g, fb_mmu_fault_buffer_size_r(index)); + if (state) { + if (gv11b_fb_is_fault_buf_enabled(g, index)) { + nvgpu_log_info(g, "fault buffer is already enabled"); + } else { + reg_val |= fb_mmu_fault_buffer_size_enable_true_f(); + gk20a_writel(g, fb_mmu_fault_buffer_size_r(index), + reg_val); + } + + } else { + struct nvgpu_timeout timeout; + u32 delay = GR_IDLE_CHECK_DEFAULT; + + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + + reg_val &= (~(fb_mmu_fault_buffer_size_enable_m())); + gk20a_writel(g, fb_mmu_fault_buffer_size_r(index), reg_val); + + fault_status = gk20a_readl(g, fb_mmu_fault_status_r()); + + do { + if (!(fault_status & fb_mmu_fault_status_busy_true_f())) + break; + /* + * Make sure fault buffer is disabled. + * This is to avoid accessing fault buffer by hw + * during the window BAR2 is being unmapped by s/w + */ + nvgpu_log_info(g, "fault status busy set, check again"); + fault_status = gk20a_readl(g, fb_mmu_fault_status_r()); + + nvgpu_usleep_range(delay, delay * 2); + delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired_msg(&timeout, + "fault status busy set")); + } +} + +void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index) +{ + u32 addr_lo; + u32 addr_hi; + + nvgpu_log_fn(g, " "); + + gv11b_fb_fault_buf_set_state_hw(g, index, + FAULT_BUF_DISABLED); + + addr_lo = u64_lo32(g->mm.hw_fault_buf[index].gpu_va >> + ram_in_base_shift_v()); + addr_hi = u64_hi32(g->mm.hw_fault_buf[index].gpu_va); + + gk20a_writel(g, fb_mmu_fault_buffer_lo_r(index), + fb_mmu_fault_buffer_lo_addr_f(addr_lo)); + + gk20a_writel(g, fb_mmu_fault_buffer_hi_r(index), + fb_mmu_fault_buffer_hi_addr_f(addr_hi)); + + gk20a_writel(g, fb_mmu_fault_buffer_size_r(index), + fb_mmu_fault_buffer_size_val_f(g->ops.fifo.get_num_fifos(g)) | + fb_mmu_fault_buffer_size_overflow_intr_enable_f()); + + gv11b_fb_fault_buf_set_state_hw(g, index, FAULT_BUF_ENABLED); +} + static void gv11b_fb_intr_en_set(struct gk20a *g, unsigned int index, u32 mask) { @@ -230,15 +318,32 @@ static u32 gv11b_fb_get_hub_intr_clr_mask(struct gk20a *g, { u32 mask = 0; - if (intr_type == HUB_INTR_TYPE_ALL) { + if (intr_type & HUB_INTR_TYPE_OTHER) { + mask |= + fb_niso_intr_en_clr_mmu_other_fault_notify_m(); + } + + if (intr_type & HUB_INTR_TYPE_NONREPLAY) { + mask |= + fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m() | + fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(); + } + + if (intr_type & HUB_INTR_TYPE_REPLAY) { mask |= - fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(); - return mask; + fb_niso_intr_en_clr_mmu_replayable_fault_notify_m() | + fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(); } if (intr_type & HUB_INTR_TYPE_ECC_UNCORRECTED) { mask |= - fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(); + fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(); + } + + if (intr_type & HUB_INTR_TYPE_ACCESS_COUNTER) { + mask |= + fb_niso_intr_en_clr_hub_access_counter_notify_m() | + fb_niso_intr_en_clr_hub_access_counter_error_m(); } return mask; @@ -249,15 +354,32 @@ static u32 gv11b_fb_get_hub_intr_en_mask(struct gk20a *g, { u32 mask = 0; - if (intr_type == HUB_INTR_TYPE_ALL) { + if (intr_type & HUB_INTR_TYPE_OTHER) { mask |= - fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(); - return mask; + fb_niso_intr_en_set_mmu_other_fault_notify_m(); + } + + if (intr_type & HUB_INTR_TYPE_NONREPLAY) { + mask |= + fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m() | + fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(); + } + + if (intr_type & HUB_INTR_TYPE_REPLAY) { + mask |= + fb_niso_intr_en_set_mmu_replayable_fault_notify_m() | + fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(); } if (intr_type & HUB_INTR_TYPE_ECC_UNCORRECTED) { mask |= - fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(); + fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(); + } + + if (intr_type & HUB_INTR_TYPE_ACCESS_COUNTER) { + mask |= + fb_niso_intr_en_set_hub_access_counter_notify_m() | + fb_niso_intr_en_set_hub_access_counter_error_m(); } return mask; @@ -469,14 +591,17 @@ static void gv11b_fb_hub_isr(struct gk20a *g) u32 status; u32 niso_intr = gk20a_readl(g, fb_niso_intr_r()); - nvgpu_info(g, "enter hub isr, niso_intr = 0x%x", niso_intr); + nvgpu_info(g, "enter hub isr, niso_intr = 0x%08x", niso_intr); + + nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); if (niso_intr & (fb_niso_intr_hub_access_counter_notify_pending_f() | fb_niso_intr_hub_access_counter_error_pending_f())) { nvgpu_info(g, "hub access counter notify/error"); - } else if (niso_intr & + } + if (niso_intr & fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f()) { nvgpu_info(g, "ecc uncorrected error notify"); @@ -501,9 +626,33 @@ static void gv11b_fb_hub_isr(struct gk20a *g) gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ECC_UNCORRECTED); - } else { - nvgpu_info(g, "mmu fault : TODO"); } + if (niso_intr & + (fb_niso_intr_mmu_other_fault_notify_m() | + fb_niso_intr_mmu_replayable_fault_notify_m() | + fb_niso_intr_mmu_replayable_fault_overflow_m() | + fb_niso_intr_mmu_nonreplayable_fault_notify_m() | + fb_niso_intr_mmu_nonreplayable_fault_overflow_m())) { + + nvgpu_info(g, "mmu fault : No handling in place"); + + } + + nvgpu_mutex_release(&g->mm.hub_isr_mutex); +} + +bool gv11b_fb_mmu_fault_pending(struct gk20a *g) +{ + if (gk20a_readl(g, fb_niso_intr_r()) & + (fb_niso_intr_mmu_other_fault_notify_m() | + fb_niso_intr_mmu_ecc_uncorrected_error_notify_m() | + fb_niso_intr_mmu_replayable_fault_notify_m() | + fb_niso_intr_mmu_replayable_fault_overflow_m() | + fb_niso_intr_mmu_nonreplayable_fault_notify_m() | + fb_niso_intr_mmu_nonreplayable_fault_overflow_m())) + return true; + + return false; } void gv11b_init_fb(struct gpu_ops *gops) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index eff3c25d..d8f5e145 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -40,9 +40,19 @@ struct gpu_ops; HUB_INTR_TYPE_ECC_UNCORRECTED | \ HUB_INTR_TYPE_ACCESS_COUNTER) +#define FAULT_TYPE_OTHER_AND_NONREPLAY 0 +#define FAULT_TYPE_REPLAY 1 + +void gv11b_init_fb(struct gpu_ops *gops); +u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g, + unsigned int index); +void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g, + unsigned int index, unsigned int state); +void gv11b_fb_nonreplay_fault_buf_configure_hw(struct gk20a *g); void gv11b_fb_enable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); void gv11b_fb_disable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); -void gv11b_init_fb(struct gpu_ops *gops); +void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index); +bool gv11b_fb_mmu_fault_pending(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 8b8fcea0..cc29f74a 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -30,6 +30,10 @@ static void mc_gv11b_intr_enable(struct gk20a *g) gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffff); + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffff); + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = mc_intr_pfifo_pending_f() | mc_intr_hub_pending_f() | @@ -38,20 +42,19 @@ static void mc_gv11b_intr_enable(struct gk20a *g) mc_intr_ltc_pending_f() | eng_intr_mask; - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); - - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = mc_intr_pfifo_pending_f() | eng_intr_mask; + + /* TODO: Enable PRI faults for HUB ECC err intr */ + gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types); + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); - /* TODO: Enable PRI faults for HUB ECC err intr */ - gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, - HUB_INTR_TYPE_ECC_UNCORRECTED); } static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index cc8dafa3..d6184cee 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -15,13 +15,21 @@ #include +#include +#include +#include + #include "gk20a/gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/mc_gp10b.h" #include "mm_gv11b.h" +#include "fb_gv11b.h" #include +#include #define NVGPU_L3_ALLOC_BIT 36 @@ -46,12 +54,187 @@ static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { - if (gk20a_readl(g, fb_niso_intr_r()) & - (fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f() | - fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f())) - return true; + return gv11b_fb_mmu_fault_pending(g); +} - return false; +static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) +{ + nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); + + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_OTHER | + HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY); + + nvgpu_kfree(g, g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY]); + + g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY] = NULL; + g->mm.fault_info[FAULT_TYPE_REPLAY] = NULL; + + nvgpu_mutex_release(&g->mm.hub_isr_mutex); + nvgpu_mutex_destroy(&g->mm.hub_isr_mutex); +} + +static int gv11b_mm_mmu_fault_info_buf_init(struct gk20a *g, + u32 *hub_intr_types) +{ + struct mmu_fault_info *fault_info_mem; + + fault_info_mem = nvgpu_kzalloc(g, sizeof(struct mmu_fault_info) * + FAULT_TYPE_NUM); + if (!fault_info_mem) { + nvgpu_log_info(g, "failed to alloc shadow fault info"); + return -ENOMEM; + } + /* shadow buffer for copying mmu fault info */ + g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY] = + &fault_info_mem[FAULT_TYPE_OTHER_AND_NONREPLAY]; + + g->mm.fault_info[FAULT_TYPE_REPLAY] = + &fault_info_mem[FAULT_TYPE_REPLAY]; + + *hub_intr_types |= HUB_INTR_TYPE_OTHER; + return 0; +} + +static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, + u32 *hub_intr_types) +{ + struct vm_gk20a *vm = g->mm.bar2.vm; + int err = 0; + size_t fb_size; + + /* Max entries take care of 1 entry used for full detection */ + fb_size = (g->ops.fifo.get_num_fifos(g) + 1) * + gmmu_fault_buf_size_v(); + + err = nvgpu_dma_alloc_map_sys(vm, fb_size, + &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); + if (err) { + nvgpu_err(g, + "Error in hw mmu fault buf [0] alloc in bar2 vm "); + /* Fault will be snapped in pri reg but not in buffer */ + return; + } + + g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_TRUE; + *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY; + + err = nvgpu_dma_alloc_map_sys(vm, fb_size, + &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); + if (err) { + nvgpu_err(g, + "Error in hw mmu fault buf [1] alloc in bar2 vm "); + /* Fault will be snapped in pri reg but not in buffer */ + return; + } + g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_TRUE; + *hub_intr_types |= HUB_INTR_TYPE_REPLAY; +} + +static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) +{ + struct vm_gk20a *vm = g->mm.bar2.vm; + + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_NONREPLAY | + HUB_INTR_TYPE_REPLAY); + + g->mm.hub_intr_types &= (~(HUB_INTR_TYPE_NONREPLAY | + HUB_INTR_TYPE_REPLAY)); + + if ((gv11b_fb_is_fault_buf_enabled(g, NONREPLAY_REG_INDEX))) { + gv11b_fb_fault_buf_set_state_hw(g, NONREPLAY_REG_INDEX, + FAULT_BUF_DISABLED); + } + + if ((gv11b_fb_is_fault_buf_enabled(g, REPLAY_REG_INDEX))) { + gv11b_fb_fault_buf_set_state_hw(g, REPLAY_REG_INDEX, + FAULT_BUF_DISABLED); + } + + if (g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + nvgpu_dma_unmap_free(vm, + &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); + g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + } + + if (g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + nvgpu_dma_unmap_free(vm, + &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); + g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + } +} + +static void gv11b_mm_remove_bar2_vm(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + + gv11b_mm_mmu_hw_fault_buf_deinit(g); + + gk20a_free_inst_block(g, &mm->bar2.inst_block); + nvgpu_vm_put(mm->bar2.vm); +} + +static void gv11b_mm_mmu_fault_setup_hw(struct gk20a *g) +{ + if (g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + gv11b_fb_fault_buf_configure_hw(g, NONREPLAY_REG_INDEX); + } + if (g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] == + HW_FAULT_BUF_STATUS_ALLOC_TRUE) { + gv11b_fb_fault_buf_configure_hw(g, REPLAY_REG_INDEX); + } +} + +static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) +{ + int err; + + nvgpu_mutex_init(&g->mm.hub_isr_mutex); + + g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + g->mm.hw_fault_buf_status[REPLAY_REG_INDEX] = + HW_FAULT_BUF_STATUS_ALLOC_FALSE; + + g->mm.hub_intr_types = HUB_INTR_TYPE_ECC_UNCORRECTED; + + err = gv11b_mm_mmu_fault_info_buf_init(g, &g->mm.hub_intr_types); + + if (!err) + gv11b_mm_mmu_hw_fault_buf_init(g, &g->mm.hub_intr_types); + + return err; +} + +static int gv11b_init_mm_setup_hw(struct gk20a *g) +{ + int err = 0; + + nvgpu_log_fn(g, "start"); + + g->ops.fb.set_mmu_page_size(g); + g->ops.fb.init_hw(g); + + err = g->ops.mm.init_bar2_mm_hw_setup(g); + if (err) + return err; + + if (gk20a_mm_fb_flush(g) || gk20a_mm_fb_flush(g)) + return -EBUSY; + + err = gv11b_mm_mmu_fault_setup_sw(g); + if (!err) + gv11b_mm_mmu_fault_setup_hw(g); + + nvgpu_log_fn(g, "end"); + + return err; } void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) @@ -82,8 +265,11 @@ void gv11b_init_mm(struct gpu_ops *gops) gp10b_init_mm(gops); gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; - gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; gops->mm.l2_flush = gv11b_mm_l2_flush; gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; + gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; + gops->mm.fault_info_mem_destroy = + gv11b_mm_fault_info_mem_destroy; + gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; } diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h index 4284b171..a887c7f4 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h @@ -1,6 +1,6 @@ /* * GV11B MM - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,6 +15,9 @@ #ifndef MM_GV11B_H #define MM_GV11B_H +#define HW_FAULT_BUF_STATUS_ALLOC_TRUE 1 +#define HW_FAULT_BUF_STATUS_ALLOC_FALSE 0 + struct gpu_ops; void gv11b_init_mm(struct gpu_ops *gops); -- cgit v1.2.2 From 2f6d321390a98ace1e52f21c6a399e06b3fe71e7 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 7 Mar 2017 12:16:07 -0800 Subject: gpu: nvgpu: gv11b: add mmu fault handling HUB reports following memory sub-system interrupts: a) ACCESS_COUNTER_NOTIFY: GET != PUT for access counter notify buffer b) ACCESS_COUNTER_ERROR: HUB received a NACK (BAR2 fault) when writing the notify buffer out to memory c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC error detected by HUB MMU d) MMU_REPLAYABLE_FAULT_NOTIFY: GET != PUT for replayable fault buffer e) MMU_REPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the replayable fault buffer f) MMU_NONREPLAYABLE_FAULT_NOTIFY: GET != PUT for non-replayable fault buffer g) MMU_NONREPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the non-replayable fault buffer h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU This change is to : -Detect other fault notify -Copy fault info from fault snap register for other fault notify interrupt -Detect and handle nonreplay/replay fault notify and fault overflow -Copy fault info from fault buffer for nonreplay/replay fault -Print fault info JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1493394 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 20 + drivers/gpu/nvgpu/gv11b/ce_gv11b.h | 1 + drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 748 ++++++++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 7 +- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 71 ++++ drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 3 + drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 10 +- 7 files changed, 847 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 0bbd05b6..af87f990 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -26,6 +26,7 @@ #include "ce_gv11b.h" #include +#include static u32 gv11b_ce_get_num_pce(struct gk20a *g) { @@ -74,6 +75,25 @@ static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) gp10b_ce_isr(g, inst_id, pri_base); } +void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) +{ + u32 reg_val, num_lce, lce, clear_intr; + + reg_val = gk20a_readl(g, top_num_ces_r()); + num_lce = top_num_ces_value_v(reg_val); + nvgpu_log_info(g, "num LCE: %d", num_lce); + + for (lce = 0; lce < num_lce; lce++) { + reg_val = gk20a_readl(g, ce_intr_status_r(lce)); + if (reg_val & ce_intr_status_mthd_buffer_fault_pending_f()) { + nvgpu_log(g, gpu_dbg_intr, + "ce: lce %d: mthd buffer fault", lce); + clear_intr = ce_intr_status_mthd_buffer_fault_reset_f(); + gk20a_writel(g, ce_intr_status_r(lce), clear_intr); + } + } +} + void gv11b_init_ce(struct gpu_ops *gops) { gp10b_init_ce(gops); diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h index 27dffa5d..09d18058 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h @@ -22,5 +22,6 @@ struct gpu_ops; void gv11b_init_ce(struct gpu_ops *gops); +void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g); #endif /*__CE2_GV11B_H__*/ diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index da7c7d4a..6d1fbca9 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -23,7 +23,9 @@ #include "gp10b/fb_gp10b.h" +#include "gv11b/fifo_gv11b.h" #include "gv11b/fb_gv11b.h" +#include "gv11b/ce_gv11b.h" #include #include @@ -160,6 +162,89 @@ static void gv11b_fb_reset(struct gk20a *g) } } +static const char * const invalid_str = "invalid"; + +static const char *const fault_type_descs_gv11b[] = { + "invalid pde", + "invalid pde size", + "invalid pte", + "limit violation", + "unbound inst block", + "priv violation", + "write", + "read", + "pitch mask violation", + "work creation", + "unsupported aperture", + "compression failure", + "unsupported kind", + "region violation", + "poison", + "atomic" +}; + +static const char *const fault_client_type_descs_gv11b[] = { + "gpc", + "hub", +}; + +static const char *const fault_access_type_descs_gv11b[] = { + "virt read", + "virt write", + "virt atomic strong", + "virt prefetch", + "virt atomic weak", + "xxx", + "xxx", + "xxx", + "phys read", + "phys write", + "phys atomic", + "phys prefetch", +}; + +static const char *const hub_client_descs_gv11b[] = { + "vip", "ce0", "ce1", "dniso", "fe", "fecs", "host", "host cpu", + "host cpu nb", "iso", "mmu", "nvdec", "nvenc1", "nvenc2", + "niso", "p2p", "pd", "perf", "pmu", "raster twod", "scc", + "scc nb", "sec", "ssync", "gr copy", "xv", "mmu nb", + "nvenc", "d falcon", "sked", "a falcon", "hsce0", "hsce1", + "hsce2", "hsce3", "hsce4", "hsce5", "hsce6", "hsce7", "hsce8", + "hsce9", "hshub", "ptp x0", "ptp x1", "ptp x2", "ptp x3", + "ptp x4", "ptp x5", "ptp x6", "ptp x7", "vpr scrubber0", + "vpr scrubber1", "dwbif", "fbfalcon", "ce shim", "gsp", + "dont care" +}; + +static const char *const gpc_client_descs_gv11b[] = { + "t1 0", "t1 1", "t1 2", "t1 3", + "t1 4", "t1 5", "t1 6", "t1 7", + "pe 0", "pe 1", "pe 2", "pe 3", + "pe 4", "pe 5", "pe 6", "pe 7", + "rast", "gcc", "gpccs", + "prop 0", "prop 1", "prop 2", "prop 3", + "gpm", + "ltp utlb 0", "ltp utlb 1", "ltp utlb 2", "ltp utlb 3", + "ltp utlb 4", "ltp utlb 5", "ltp utlb 6", "ltp utlb 7", + "utlb", + "t1 8", "t1 9", "t1 10", "t1 11", + "t1 12", "t1 13", "t1 14", "t1 15", + "tpccs 0", "tpccs 1", "tpccs 2", "tpccs 3", + "tpccs 4", "tpccs 5", "tpccs 6", "tpccs 7", + "pe 8", "pe 9", "tpccs 8", "tpccs 9", + "t1 16", "t1 17", "t1 18", "t1 19", + "pe 10", "pe 11", "tpccs 10", "tpccs 11", + "t1 20", "t1 21", "t1 22", "t1 23", + "pe 12", "pe 13", "tpccs 12", "tpccs 13", + "t1 24", "t1 25", "t1 26", "t1 27", + "pe 14", "pe 15", "tpccs 14", "tpccs 15", + "t1 28", "t1 29", "t1 30", "t1 31", + "pe 16", "pe 17", "tpccs 16", "tpccs 17", + "t1 32", "t1 33", "t1 34", "t1 35", + "pe 18", "pe 19", "tpccs 18", "tpccs 19", + "t1 36", "t1 37", "t1 38", "t1 39", +}; + static void gv11b_init_uncompressed_kind_map(void) { gk20a_uc_kind_map[gmmu_pte_kind_c32_ms2_4cbra_v()] = @@ -218,6 +303,84 @@ u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g, return fb_mmu_fault_buffer_size_enable_v(reg_val); } +static void gv11b_fb_fault_buffer_get_ptr_update(struct gk20a *g, + unsigned int index, u32 next) +{ + u32 reg_val; + + nvgpu_log(g, gpu_dbg_intr, "updating get index with = %d", next); + + reg_val = gk20a_readl(g, fb_mmu_fault_buffer_get_r(index)); + reg_val = set_field(reg_val, fb_mmu_fault_buffer_get_ptr_m(), + fb_mmu_fault_buffer_get_ptr_f(next)); + + /* while the fault is being handled it is possible for overflow + * to happen, + */ + if (reg_val & fb_mmu_fault_buffer_get_overflow_m()) + reg_val |= fb_mmu_fault_buffer_get_overflow_clear_f(); + + gk20a_writel(g, fb_mmu_fault_buffer_get_r(index), reg_val); + + /* make sure get ptr update is visible to everyone to avoid + * reading already read entry + */ + mb(); +} + +static u32 gv11b_fb_fault_buffer_get_index(struct gk20a *g, + unsigned int index) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fb_mmu_fault_buffer_get_r(index)); + return fb_mmu_fault_buffer_get_ptr_v(reg_val); +} + +static u32 gv11b_fb_fault_buffer_put_index(struct gk20a *g, + unsigned int index) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fb_mmu_fault_buffer_put_r(index)); + return fb_mmu_fault_buffer_put_ptr_v(reg_val); +} + +static u32 gv11b_fb_fault_buffer_size_val(struct gk20a *g, + unsigned int index) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fb_mmu_fault_buffer_size_r(index)); + return fb_mmu_fault_buffer_size_val_v(reg_val); +} + +static bool gv11b_fb_is_fault_buffer_empty(struct gk20a *g, + unsigned int index, u32 *get_idx) +{ + u32 put_idx; + + *get_idx = gv11b_fb_fault_buffer_get_index(g, index); + put_idx = gv11b_fb_fault_buffer_put_index(g, index); + + return *get_idx == put_idx; +} + +static bool gv11b_fb_is_fault_buffer_full(struct gk20a *g, + unsigned int index) +{ + u32 get_idx, put_idx, entries; + + + get_idx = gv11b_fb_fault_buffer_get_index(g, index); + + put_idx = gv11b_fb_fault_buffer_put_index(g, index); + + entries = gv11b_fb_fault_buffer_size_val(g, index); + + return get_idx == ((put_idx + 1) % entries); +} + void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g, unsigned int index, unsigned int state) { @@ -275,7 +438,6 @@ void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index) gv11b_fb_fault_buf_set_state_hw(g, index, FAULT_BUF_DISABLED); - addr_lo = u64_lo32(g->mm.hw_fault_buf[index].gpu_va >> ram_in_base_shift_v()); addr_hi = u64_hi32(g->mm.hw_fault_buf[index].gpu_va); @@ -586,18 +748,586 @@ static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0]); } -static void gv11b_fb_hub_isr(struct gk20a *g) +static void gv11b_fb_parse_mmfault(struct mmu_fault_info *mmfault) { - u32 status; - u32 niso_intr = gk20a_readl(g, fb_niso_intr_r()); + if (WARN_ON(mmfault->fault_type >= + ARRAY_SIZE(fault_type_descs_gv11b))) + mmfault->fault_type_desc = invalid_str; + else + mmfault->fault_type_desc = + fault_type_descs_gv11b[mmfault->fault_type]; - nvgpu_info(g, "enter hub isr, niso_intr = 0x%08x", niso_intr); + if (WARN_ON(mmfault->client_type >= + ARRAY_SIZE(fault_client_type_descs_gv11b))) + mmfault->client_type_desc = invalid_str; + else + mmfault->client_type_desc = + fault_client_type_descs_gv11b[mmfault->client_type]; + + mmfault->client_id_desc = invalid_str; + if (mmfault->client_type == + gmmu_fault_client_type_hub_v()) { + + if (!(WARN_ON(mmfault->client_id >= + ARRAY_SIZE(hub_client_descs_gv11b)))) + mmfault->client_id_desc = + hub_client_descs_gv11b[mmfault->client_id]; + } else if (mmfault->client_type == + gmmu_fault_client_type_gpc_v()) { + if (!(WARN_ON(mmfault->client_id >= + ARRAY_SIZE(gpc_client_descs_gv11b)))) + mmfault->client_id_desc = + gpc_client_descs_gv11b[mmfault->client_id]; + } + +} + +static void gv11b_fb_print_fault_info(struct gk20a *g, + struct mmu_fault_info *mmfault) +{ + if (mmfault && mmfault->valid) { + nvgpu_err(g, "[MMU FAULT] " + "mmu engine id: %d, " + "ch id: %d, " + "fault addr: 0x%llx, " + "fault addr aperture: %d, " + "fault type: %s, " + "access type: %s, ", + mmfault->mmu_engine_id, + mmfault->chid, + mmfault->fault_addr, + mmfault->fault_addr_aperture, + mmfault->fault_type_desc, + fault_access_type_descs_gv11b[mmfault->access_type]); + nvgpu_log(g, gpu_dbg_intr, "[MMU FAULT] " + "mmu engine id: %d, " + "faulted act eng id if any: 0x%x, " + "faulted veid if any: 0x%x, " + "faulted pbdma id if any: 0x%x, " + "fault addr: 0x%llx, ", + mmfault->mmu_engine_id, + mmfault->faulted_engine, + mmfault->faulted_subid, + mmfault->faulted_pbdma, + mmfault->fault_addr); + nvgpu_log(g, gpu_dbg_intr, "[MMU FAULT] " + "fault addr aperture: %d, " + "fault type: %s, " + "access type: %s, " + "inst ptr: 0x%llx, " + "inst ptr aperture: %d, ", + mmfault->fault_addr_aperture, + mmfault->fault_type_desc, + fault_access_type_descs_gv11b[mmfault->access_type], + mmfault->inst_ptr, + mmfault->inst_aperture); + nvgpu_log(g, gpu_dbg_intr, "[MMU FAULT] " + "ch id: %d, " + "timestamp hi:lo 0x%08x:0x%08x, " + "client type: %s, " + "client id: %s, " + "gpc id if client type is gpc: %d, ", + mmfault->chid, + mmfault->timestamp_hi, mmfault->timestamp_lo, + mmfault->client_type_desc, + mmfault->client_id_desc, + mmfault->gpc_id); + nvgpu_log(g, gpu_dbg_intr, "[MMU FAULT] " + "protected mode: %d, " + "replayable fault: %d, " + "replayable fault en: %d ", + mmfault->protected_mode, + mmfault->replayable_fault, + mmfault->replay_fault_en); + } +} + +/* + *Fault buffer format + * + * 31 28 24 23 16 15 8 7 4 0 + *.-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. + *| inst_lo |0 0|apr|0 0 0 0 0 0 0 0| + *`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + *| inst_hi | + *`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + *| addr_31_12 | |AP | + *`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + *| addr_63_32 | + *`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + *| timestamp_lo | + *`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + *| timestamp_hi | + *`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + *| (reserved) | engine_id | + *`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + *|V|R|P| gpc_id |0 0 0|t|0|acctp|0| client |RF0 0|faulttype| + */ + +static void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g, + struct nvgpu_mem *mem, u32 offset, struct mmu_fault_info *mmfault) +{ + u32 rd32_val; + u32 addr_lo, addr_hi; + u64 inst_ptr; + u32 chid = FIFO_INVAL_CHANNEL_ID; + struct channel_gk20a *refch; + + memset(mmfault, 0, sizeof(*mmfault)); + + rd32_val = nvgpu_mem_rd32(g, mem, offset + + gmmu_fault_buf_entry_inst_lo_w()); + addr_lo = gmmu_fault_buf_entry_inst_lo_v(rd32_val); + addr_lo = addr_lo << ram_in_base_shift_v(); + + addr_hi = nvgpu_mem_rd32(g, mem, offset + + gmmu_fault_buf_entry_inst_hi_w()); + addr_hi = gmmu_fault_buf_entry_inst_hi_v(addr_hi); + + inst_ptr = hi32_lo32_to_u64(addr_hi, addr_lo); + + /* refch will be put back after fault is handled */ + refch = gk20a_refch_from_inst_ptr(g, inst_ptr); + if (refch) + chid = refch->chid; + + /* it is ok to continue even if refch is NULL */ + mmfault->refch = refch; + mmfault->chid = chid; + mmfault->inst_ptr = inst_ptr; + mmfault->inst_aperture = gmmu_fault_buf_entry_inst_aperture_v(rd32_val); + + rd32_val = nvgpu_mem_rd32(g, mem, offset + + gmmu_fault_buf_entry_addr_lo_w()); + + mmfault->fault_addr_aperture = + gmmu_fault_buf_entry_addr_phys_aperture_v(rd32_val); + addr_lo = gmmu_fault_buf_entry_addr_lo_v(rd32_val); + addr_lo = addr_lo << ram_in_base_shift_v(); + + rd32_val = nvgpu_mem_rd32(g, mem, offset + + gmmu_fault_buf_entry_addr_hi_w()); + addr_hi = gmmu_fault_buf_entry_addr_hi_v(rd32_val); + mmfault->fault_addr = hi32_lo32_to_u64(addr_hi, addr_lo); + + rd32_val = nvgpu_mem_rd32(g, mem, offset + + gmmu_fault_buf_entry_timestamp_lo_w()); + mmfault->timestamp_lo = + gmmu_fault_buf_entry_timestamp_lo_v(rd32_val); + + rd32_val = nvgpu_mem_rd32(g, mem, offset + + gmmu_fault_buf_entry_timestamp_hi_w()); + mmfault->timestamp_hi = + gmmu_fault_buf_entry_timestamp_hi_v(rd32_val); + + rd32_val = nvgpu_mem_rd32(g, mem, offset + + gmmu_fault_buf_entry_engine_id_w()); + + mmfault->mmu_engine_id = + gmmu_fault_buf_entry_engine_id_v(rd32_val); + gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(g, mmfault->mmu_engine_id, + &mmfault->faulted_engine, &mmfault->faulted_subid, + &mmfault->faulted_pbdma); + + rd32_val = nvgpu_mem_rd32(g, mem, offset + + gmmu_fault_buf_entry_fault_type_w()); + mmfault->client_id = + gmmu_fault_buf_entry_client_v(rd32_val); + mmfault->replayable_fault = + gmmu_fault_buf_entry_replayable_fault_v(rd32_val); + + mmfault->fault_type = + gmmu_fault_buf_entry_fault_type_v(rd32_val); + mmfault->access_type = + gmmu_fault_buf_entry_access_type_v(rd32_val); + + mmfault->client_type = + gmmu_fault_buf_entry_mmu_client_type_v(rd32_val); + + mmfault->gpc_id = + gmmu_fault_buf_entry_gpc_id_v(rd32_val); + mmfault->protected_mode = + gmmu_fault_buf_entry_protected_mode_v(rd32_val); + + mmfault->replay_fault_en = + gmmu_fault_buf_entry_replayable_fault_en_v(rd32_val); + + mmfault->valid = gmmu_fault_buf_entry_valid_v(rd32_val); + + rd32_val = nvgpu_mem_rd32(g, mem, offset + + gmmu_fault_buf_entry_fault_type_w()); + rd32_val &= ~(gmmu_fault_buf_entry_valid_m()); + nvgpu_mem_wr32(g, mem, offset + gmmu_fault_buf_entry_valid_w(), + rd32_val); + + gv11b_fb_parse_mmfault(mmfault); +} + +static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, + struct mmu_fault_info *mmfault) +{ + if (!mmfault->valid) + return; + + gv11b_fb_print_fault_info(g, mmfault); + + if (mmfault->fault_type == gmmu_fault_type_unbound_inst_block_v()) { + /* + * Bug 1847172: When an engine faults due to an unbound + * instance block, the fault cannot be isolated to a + * single context so we need to reset the entire runlist + */ + nvgpu_log(g, gpu_dbg_intr, "UNBOUND INST"); + } + + if (mmfault->refch) { + gk20a_channel_put(mmfault->refch); + mmfault->refch = NULL; + } +} + +static void gv11b_fb_handle_mmu_nonreplay_replay_fault(struct gk20a *g, + u32 fault_status, unsigned int index) +{ + u32 get_indx, offset, rd32_val, entries; + struct nvgpu_mem *mem; + struct mmu_fault_info *mmfault; + + if (gv11b_fb_is_fault_buffer_empty(g, index, + &get_indx)) { + nvgpu_log(g, gpu_dbg_intr, "SPURIOUS fault"); + return; + } + nvgpu_log(g, gpu_dbg_intr, "get ptr = %d", get_indx); + + mem = &g->mm.hw_fault_buf[index]; + mmfault = g->mm.fault_info[index]; + + entries = gv11b_fb_fault_buffer_size_val(g, index); + nvgpu_log(g, gpu_dbg_intr, "buffer num entries = %d", entries); + + offset = (get_indx * gmmu_fault_buf_size_v()) / sizeof(u32); + nvgpu_log(g, gpu_dbg_intr, "starting word offset = 0x%x", offset); + + rd32_val = nvgpu_mem_rd32(g, mem, + offset + gmmu_fault_buf_entry_valid_w()); + nvgpu_log(g, gpu_dbg_intr, "entry valid offset val = 0x%x", rd32_val); + + while ((rd32_val & gmmu_fault_buf_entry_valid_m())) { + + nvgpu_log(g, gpu_dbg_intr, "entry valid = 0x%x", rd32_val); + + gv11b_fb_copy_from_hw_fault_buf(g, mem, offset, mmfault); + + /* Extra 1 in buffer size is to detect buffer full. + * Actual number of entries for faults to be snapped are + * one less than number in fault_buffer_size_val + */ + get_indx = (get_indx + 1) % (entries - 1); + nvgpu_log(g, gpu_dbg_intr, "new get index = %d", get_indx); + + gv11b_fb_fault_buffer_get_ptr_update(g, index, get_indx); + + gv11b_fb_handle_mmu_fault_common(g, mmfault); + + offset = (get_indx * gmmu_fault_buf_size_v()) / sizeof(u32); + nvgpu_log(g, gpu_dbg_intr, "next word offset = 0x%x", offset); + + rd32_val = nvgpu_mem_rd32(g, mem, + offset + gmmu_fault_buf_entry_valid_w()); + } +} + +static void gv11b_mm_copy_from_fault_snap_reg(struct gk20a *g, + u32 fault_status, struct mmu_fault_info *mmfault) +{ + u32 reg_val; + u32 addr_lo, addr_hi; + u64 inst_ptr; + int chid = FIFO_INVAL_CHANNEL_ID; + struct channel_gk20a *refch; + + memset(mmfault, 0, sizeof(*mmfault)); + + if (!(fault_status & fb_mmu_fault_status_valid_set_f())) { + + nvgpu_log(g, gpu_dbg_intr, "mmu fault status valid not set"); + return; + } + + reg_val = gk20a_readl(g, fb_mmu_fault_inst_lo_r()); + addr_lo = fb_mmu_fault_inst_lo_addr_v(reg_val); + addr_lo = addr_lo << ram_in_base_shift_v(); + + addr_hi = gk20a_readl(g, fb_mmu_fault_inst_hi_r()); + addr_hi = fb_mmu_fault_inst_hi_addr_v(addr_hi); + inst_ptr = hi32_lo32_to_u64(addr_hi, addr_lo); + + /* refch will be put back after fault is handled */ + refch = gk20a_refch_from_inst_ptr(g, inst_ptr); + if (refch) + chid = refch->chid; + + /* It is still ok to continue if refch is NULL */ + mmfault->refch = refch; + mmfault->chid = chid; + mmfault->inst_ptr = inst_ptr; + mmfault->inst_aperture = fb_mmu_fault_inst_lo_aperture_v(reg_val); + mmfault->mmu_engine_id = fb_mmu_fault_inst_lo_engine_id_v(reg_val); + + gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(g, mmfault->mmu_engine_id, + &mmfault->faulted_engine, &mmfault->faulted_subid, + &mmfault->faulted_pbdma); + + reg_val = gk20a_readl(g, fb_mmu_fault_addr_lo_r()); + addr_lo = fb_mmu_fault_addr_lo_addr_v(reg_val); + addr_lo = addr_lo << ram_in_base_shift_v(); + + mmfault->fault_addr_aperture = + fb_mmu_fault_addr_lo_phys_aperture_v(reg_val); + + addr_hi = gk20a_readl(g, fb_mmu_fault_addr_hi_r()); + addr_hi = fb_mmu_fault_addr_hi_addr_v(addr_hi); + mmfault->fault_addr = hi32_lo32_to_u64(addr_hi, addr_lo); + + reg_val = gk20a_readl(g, fb_mmu_fault_info_r()); + mmfault->fault_type = fb_mmu_fault_info_fault_type_v(reg_val); + mmfault->replayable_fault = + fb_mmu_fault_info_replayable_fault_v(reg_val); + mmfault->client_id = fb_mmu_fault_info_client_v(reg_val); + mmfault->access_type = fb_mmu_fault_info_access_type_v(reg_val); + mmfault->client_type = fb_mmu_fault_info_client_type_v(reg_val); + mmfault->gpc_id = fb_mmu_fault_info_gpc_id_v(reg_val); + mmfault->protected_mode = + fb_mmu_fault_info_protected_mode_v(reg_val); + mmfault->replay_fault_en = + fb_mmu_fault_info_replayable_fault_en_v(reg_val); + + mmfault->valid = fb_mmu_fault_info_valid_v(reg_val); + + fault_status &= ~(fb_mmu_fault_status_valid_m()); + gk20a_writel(g, fb_mmu_fault_status_r(), fault_status); + + gv11b_fb_parse_mmfault(mmfault); + +} + +static void gv11b_fb_handle_replay_fault_overflow(struct gk20a *g, + u32 fault_status) +{ + u32 reg_val; + unsigned int index = REPLAY_REG_INDEX; + + reg_val = gk20a_readl(g, fb_mmu_fault_buffer_get_r(index)); + + if (fault_status & + fb_mmu_fault_status_replayable_getptr_corrupted_m()) { + + nvgpu_err(g, "replayable getptr corrupted set"); + + gv11b_fb_fault_buf_configure_hw(g, index); + + reg_val = set_field(reg_val, + fb_mmu_fault_buffer_get_getptr_corrupted_m(), + fb_mmu_fault_buffer_get_getptr_corrupted_clear_f()); + } + + if (fault_status & + fb_mmu_fault_status_replayable_overflow_m()) { + bool buffer_full = gv11b_fb_is_fault_buffer_full(g, index); + + nvgpu_err(g, "replayable overflow: buffer full:%s", + buffer_full?"true":"false"); + + reg_val = set_field(reg_val, + fb_mmu_fault_buffer_get_overflow_m(), + fb_mmu_fault_buffer_get_overflow_clear_f()); + } + + gk20a_writel(g, fb_mmu_fault_buffer_get_r(index), reg_val); +} + +static void gv11b_fb_handle_nonreplay_fault_overflow(struct gk20a *g, + u32 fault_status) +{ + u32 reg_val; + unsigned int index = NONREPLAY_REG_INDEX; + + reg_val = gk20a_readl(g, fb_mmu_fault_buffer_get_r(index)); + + if (fault_status & + fb_mmu_fault_status_non_replayable_getptr_corrupted_m()) { + + nvgpu_err(g, "non replayable getptr corrupted set"); + + gv11b_fb_fault_buf_configure_hw(g, index); + + reg_val = set_field(reg_val, + fb_mmu_fault_buffer_get_getptr_corrupted_m(), + fb_mmu_fault_buffer_get_getptr_corrupted_clear_f()); + } + + if (fault_status & + fb_mmu_fault_status_non_replayable_overflow_m()) { + + bool buffer_full = gv11b_fb_is_fault_buffer_full(g, index); + + nvgpu_err(g, "non replayable overflow: buffer full:%s", + buffer_full?"true":"false"); + + reg_val = set_field(reg_val, + fb_mmu_fault_buffer_get_overflow_m(), + fb_mmu_fault_buffer_get_overflow_clear_f()); + } + + gk20a_writel(g, fb_mmu_fault_buffer_get_r(index), reg_val); +} + +static void gv11b_fb_handle_bar2_fault(struct gk20a *g, + struct mmu_fault_info *mmfault, u32 fault_status) +{ + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, + HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY); + + + if (fault_status & fb_mmu_fault_status_non_replayable_error_m()) { + if (gv11b_fb_is_fault_buf_enabled(g, NONREPLAY_REG_INDEX)) + gv11b_fb_fault_buf_configure_hw(g, NONREPLAY_REG_INDEX); + } + + if (fault_status & fb_mmu_fault_status_replayable_error_m()) { + if (gv11b_fb_is_fault_buf_enabled(g, REPLAY_REG_INDEX)) + gv11b_fb_fault_buf_configure_hw(g, REPLAY_REG_INDEX); + } + gv11b_ce_mthd_buffer_fault_in_bar2_fault(g); + + g->ops.mm.init_bar2_mm_hw_setup(g); + + if (mmfault->refch) { + gk20a_channel_put(mmfault->refch); + mmfault->refch = NULL; + } + gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, + HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY); +} + +static void gv11b_fb_handle_other_fault_notify(struct gk20a *g, + u32 fault_status) +{ + struct mmu_fault_info *mmfault; + + mmfault = g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY]; + + gv11b_mm_copy_from_fault_snap_reg(g, fault_status, mmfault); + + /* BAR2/Physical faults will not be snapped in hw fault buf */ + if (mmfault->mmu_engine_id == gmmu_fault_mmu_eng_id_bar2_v()) { + nvgpu_err(g, "BAR2 MMU FAULT"); + gv11b_fb_handle_bar2_fault(g, mmfault, fault_status); + + } else if (mmfault->mmu_engine_id == + gmmu_fault_mmu_eng_id_physical_v()) { + /* usually means VPR or out of bounds physical accesses */ + nvgpu_err(g, "PHYSICAL MMU FAULT"); + + } else { + gv11b_fb_handle_mmu_fault_common(g, mmfault); + } +} + +static void gv11b_fb_handle_dropped_mmu_fault(struct gk20a *g, u32 fault_status) +{ + u32 dropped_faults = 0; + + dropped_faults = fb_mmu_fault_status_dropped_bar1_phys_set_f() | + fb_mmu_fault_status_dropped_bar1_virt_set_f() | + fb_mmu_fault_status_dropped_bar2_phys_set_f() | + fb_mmu_fault_status_dropped_bar2_virt_set_f() | + fb_mmu_fault_status_dropped_ifb_phys_set_f() | + fb_mmu_fault_status_dropped_ifb_virt_set_f() | + fb_mmu_fault_status_dropped_other_phys_set_f()| + fb_mmu_fault_status_dropped_other_virt_set_f(); + + if (fault_status & dropped_faults) { + nvgpu_err(g, "dropped mmu fault (0x%08x)", + fault_status & dropped_faults); + gk20a_writel(g, fb_mmu_fault_status_r(), dropped_faults); + } +} + + +static void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr) +{ + u32 fault_status = gk20a_readl(g, fb_mmu_fault_status_r()); + + nvgpu_log(g, gpu_dbg_intr, "mmu_fault_status = 0x%08x", fault_status); + + if (niso_intr & + fb_niso_intr_mmu_other_fault_notify_m()) { + + gv11b_fb_handle_dropped_mmu_fault(g, fault_status); + + gv11b_fb_handle_other_fault_notify(g, fault_status); + } + + if (gv11b_fb_is_fault_buf_enabled(g, NONREPLAY_REG_INDEX)) { + + if (niso_intr & + fb_niso_intr_mmu_nonreplayable_fault_notify_m()) { + + gv11b_fb_handle_mmu_nonreplay_replay_fault(g, + fault_status, NONREPLAY_REG_INDEX); + + /* + * When all the faults are processed, + * GET and PUT will have same value and mmu fault status + * bit will be reset by HW + */ + } + if (niso_intr & + fb_niso_intr_mmu_nonreplayable_fault_overflow_m()) { + + gv11b_fb_handle_nonreplay_fault_overflow(g, + fault_status); + } + + } + + if (gv11b_fb_is_fault_buf_enabled(g, REPLAY_REG_INDEX)) { + + if (niso_intr & + fb_niso_intr_mmu_replayable_fault_notify_m()) { + + gv11b_fb_handle_mmu_nonreplay_replay_fault(g, + fault_status, REPLAY_REG_INDEX); + } + if (niso_intr & + fb_niso_intr_mmu_replayable_fault_overflow_m()) { + + gv11b_fb_handle_replay_fault_overflow(g, + fault_status); + } + + } + + nvgpu_log(g, gpu_dbg_intr, "clear mmu fault status"); + gk20a_writel(g, fb_mmu_fault_status_r(), + fb_mmu_fault_status_valid_clear_f()); +} + +static void gv11b_fb_hub_isr(struct gk20a *g) +{ + u32 status, niso_intr; nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); + niso_intr = gk20a_readl(g, fb_niso_intr_r()); + + nvgpu_info(g, "enter hub isr, niso_intr = 0x%08x", niso_intr); + if (niso_intr & - (fb_niso_intr_hub_access_counter_notify_pending_f() | - fb_niso_intr_hub_access_counter_error_pending_f())) { + (fb_niso_intr_hub_access_counter_notify_m() | + fb_niso_intr_hub_access_counter_error_m())) { nvgpu_info(g, "hub access counter notify/error"); } @@ -634,8 +1364,8 @@ static void gv11b_fb_hub_isr(struct gk20a *g) fb_niso_intr_mmu_nonreplayable_fault_notify_m() | fb_niso_intr_mmu_nonreplayable_fault_overflow_m())) { - nvgpu_info(g, "mmu fault : No handling in place"); - + nvgpu_info(g, "MMU Fault"); + gv11b_fb_handle_mmu_fault(g, niso_intr); } nvgpu_mutex_release(&g->mm.hub_isr_mutex); diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index d8f5e145..39cdfb77 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -15,7 +15,6 @@ #ifndef _NVGPU_GV11B_FB #define _NVGPU_GV11B_FB -struct gpu_ops; #define STALL_REG_INDEX 0 #define NONSTALL_REG_INDEX 1 @@ -26,8 +25,8 @@ struct gpu_ops; #define FAULT_BUF_DISABLED 0 #define FAULT_BUF_ENABLED 1 +#define FAULT_BUF_INVALID 0 #define FAULT_BUF_VALID 1 -#define CHECK_NEXT_FAULT_BUF 1 #define HUB_INTR_TYPE_OTHER 1 /* bit 0 */ #define HUB_INTR_TYPE_NONREPLAY 2 /* bit 1 */ @@ -43,12 +42,14 @@ struct gpu_ops; #define FAULT_TYPE_OTHER_AND_NONREPLAY 0 #define FAULT_TYPE_REPLAY 1 +struct gpu_ops; + void gv11b_init_fb(struct gpu_ops *gops); u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g, unsigned int index); void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g, unsigned int index, unsigned int state); -void gv11b_fb_nonreplay_fault_buf_configure_hw(struct gk20a *g); +void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index); void gv11b_fb_enable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); void gv11b_fb_disable_hub_intr(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b0d182dc..b0270150 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1720,6 +1720,77 @@ static int gv11b_init_fifo_setup_hw(struct gk20a *g) return 0; } +static u32 gv11b_mmu_fault_id_to_gr_veid(struct gk20a *g, u32 gr_eng_fault_id, + u32 mmu_fault_id) +{ + u32 num_subctx; + u32 veid = FIFO_INVAL_VEID; + + num_subctx = gv11b_get_max_subctx_count(g); + + if (mmu_fault_id >= gr_eng_fault_id && + mmu_fault_id < (gr_eng_fault_id + num_subctx)) + veid = mmu_fault_id - gr_eng_fault_id; + + return veid; +} + +static u32 gv11b_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g, + u32 mmu_fault_id, u32 *veid) +{ + u32 engine_id; + u32 active_engine_id; + struct fifo_engine_info_gk20a *engine_info; + struct fifo_gk20a *f = &g->fifo; + + + for (engine_id = 0; engine_id < f->num_engines; engine_id++) { + active_engine_id = f->active_engines_list[engine_id]; + engine_info = &g->fifo.engine_info[active_engine_id]; + + if (active_engine_id == ENGINE_GR_GK20A) { + /* get faulted subctx id */ + *veid = gv11b_mmu_fault_id_to_gr_veid(g, + engine_info->fault_id, mmu_fault_id); + if (*veid != FIFO_INVAL_VEID) + break; + } else { + if (engine_info->fault_id == mmu_fault_id) + break; + } + + active_engine_id = FIFO_INVAL_ENGINE_ID; + } + return active_engine_id; +} + +static u32 gv11b_mmu_fault_id_to_pbdma_id(struct gk20a *g, u32 mmu_fault_id) +{ + u32 num_pbdma, reg_val, fault_id_pbdma0; + + reg_val = gk20a_readl(g, fifo_cfg0_r()); + num_pbdma = fifo_cfg0_num_pbdma_v(reg_val); + fault_id_pbdma0 = fifo_cfg0_pbdma_fault_id_v(reg_val); + + if (mmu_fault_id >= fault_id_pbdma0 && + mmu_fault_id <= fault_id_pbdma0 + num_pbdma - 1) + return mmu_fault_id - fault_id_pbdma0; + + return FIFO_INVAL_PBDMA_ID; +} + +void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, + u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id) +{ + *active_engine_id = gv11b_mmu_fault_id_to_eng_id_and_veid(g, + mmu_fault_id, veid); + + if (*active_engine_id == FIFO_INVAL_ENGINE_ID) + *pbdma_id = gv11b_mmu_fault_id_to_pbdma_id(g, mmu_fault_id); + else + *pbdma_id = FIFO_INVAL_PBDMA_ID; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 032342b2..8a2b32f8 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -17,6 +17,7 @@ #define FIFO_GV11B_H #define FIFO_INVAL_PBDMA_ID ((u32)~0) +#define FIFO_INVAL_VEID ((u32)~0) /* engine context-switch request occurred while the engine was in reset */ #define SCHED_ERROR_CODE_ENGINE_RESET 0x00000005 @@ -43,4 +44,6 @@ void gv11b_init_fifo(struct gpu_ops *gops); void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, struct channel_gk20a *refch, u32 faulted_pbdma, u32 faulted_engine); +void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, + u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id); #endif diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index d6184cee..f4fc4db4 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -59,6 +59,8 @@ static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) { + nvgpu_log_fn(g, " "); + nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_OTHER | @@ -136,6 +138,8 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) { struct vm_gk20a *vm = g->mm.bar2.vm; + nvgpu_log_fn(g, " "); + gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY); @@ -173,6 +177,8 @@ static void gv11b_mm_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; + nvgpu_log_fn(g, " "); + gv11b_mm_mmu_hw_fault_buf_deinit(g); gk20a_free_inst_block(g, &mm->bar2.inst_block); @@ -195,6 +201,8 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) { int err; + nvgpu_log_fn(g, " "); + nvgpu_mutex_init(&g->mm.hub_isr_mutex); g->mm.hw_fault_buf_status[NONREPLAY_REG_INDEX] = @@ -216,7 +224,7 @@ static int gv11b_init_mm_setup_hw(struct gk20a *g) { int err = 0; - nvgpu_log_fn(g, "start"); + nvgpu_log_fn(g, " "); g->ops.fb.set_mmu_page_size(g); g->ops.fb.init_hw(g); -- cgit v1.2.2 From d9ee7aff0455ad79caf395cedd53c3e092d2538c Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 28 Mar 2017 14:36:02 -0700 Subject: gpu: nvgpu: gv11b: fifo recovery for nonreplay fault Host will no longer receive replayable or non-replayable fault requests. MMU will handle both types of fault reporting. This means that Host will no longer automatically disable scheduling or preempt a PBDMA when an engine page faults. After fault happens, engine will stall on its own fault and will not context switch until the fault is serviced JIRA GPUT19X-7 Change-Id: I8039e6f50d87f43e101d1372faa5ca6fb739036e Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1493417 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 6d1fbca9..f9532d66 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -966,6 +966,9 @@ static void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g, static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, struct mmu_fault_info *mmfault) { + unsigned int id_type; + u32 act_eng_bitmask = 0; + if (!mmfault->valid) return; @@ -977,13 +980,23 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, * instance block, the fault cannot be isolated to a * single context so we need to reset the entire runlist */ - nvgpu_log(g, gpu_dbg_intr, "UNBOUND INST"); + id_type = ID_TYPE_UNKNOWN; + nvgpu_log(g, gpu_dbg_intr, "UNBOUND INST BLOCK MMU FAULT"); + + } else if (mmfault->refch) { + if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) + id_type = ID_TYPE_TSG; + else + id_type = ID_TYPE_CHANNEL; + } else { + id_type = ID_TYPE_UNKNOWN; } - if (mmfault->refch) { - gk20a_channel_put(mmfault->refch); - mmfault->refch = NULL; - } + if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) + act_eng_bitmask = BIT(mmfault->faulted_engine); + + g->ops.fifo.teardown_ch_tsg(g, act_eng_bitmask, mmfault->chid, + id_type, RC_TYPE_MMU_FAULT, mmfault); } static void gv11b_fb_handle_mmu_nonreplay_replay_fault(struct gk20a *g, -- cgit v1.2.2 From cc940da42f34568d6327ee20653725d11b1a3258 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 9 Jul 2017 14:00:24 -0700 Subject: gpu: nvgpu: gv11b: enable and handle mpc exception Implement gr ops to handle MPC exception triggered per TPC JIRA GPUT19X-69 Change-Id: Ia92b1d51ad896116b25d71e07ed26f1539475be8 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1515915 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 40 ++++++++++++++++++++-- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 32 +++++++++++++++++ 2 files changed, 69 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index d61506c2..2c3b0820 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -885,7 +885,8 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) u32 tpc_mask; gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), - gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); + gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f() | + gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f()); tpc_mask = gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); @@ -2973,13 +2974,16 @@ static void gv11b_gr_resume_all_sms(struct gk20a *g) static int gv11b_gr_resume_from_pause(struct gk20a *g) { int err = 0; + u32 reg_val; /* Clear the pause mask to tell the GPU we want to resume everyone */ gk20a_writel(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(), 0); /* explicitly re-enable forwarding of SM interrupts upon any resume */ - gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), - gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); + reg_val = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_en_r()); + reg_val |= gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(); + + gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), reg_val); g->ops.gr.resume_all_sms(g); @@ -3198,6 +3202,34 @@ static void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, offset)); } +static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, + u32 gpc, u32 tpc, bool *post_event) +{ + u32 esr; + u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); + u32 tpc_exception = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_r() + + offset); + + if (!(tpc_exception & gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m())) + return 0; + + nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, + "GPC%d TPC%d MPC exception", gpc, tpc); + + esr = gk20a_readl(g, gr_gpc0_tpc0_mpc_hww_esr_r() + offset); + nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, "mpc hww esr 0x%08x", esr); + + esr = gk20a_readl(g, gr_gpc0_tpc0_mpc_hww_esr_info_r() + offset); + nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, + "mpc hww esr info: veid 0x%08x", + gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(esr)); + + gk20a_writel(g, gr_gpc0_tpc0_mpc_hww_esr_r() + offset, + gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f()); + + return 0; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3280,4 +3312,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.clear_sm_hww = gv11b_gr_clear_sm_hww; gops->gr.handle_tpc_sm_ecc_exception = gr_gv11b_handle_tpc_sm_ecc_exception; + gops->gr.handle_tpc_mpc_exception = + gr_gv11b_handle_tpc_mpc_exception; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 051961d2..53dc7c87 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -902,6 +902,22 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) { return 0x2; } +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) +{ + return 0x00504430; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) +{ + return 0x00504434; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) +{ + return (r >> 0) & 0x3f; +} static inline u32 gr_pri_be0_crop_status1_r(void) { return 0x00410134; @@ -3470,6 +3486,10 @@ static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) { return 0x1; } +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) +{ + return 0x10; +} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { return 0x0050450c; @@ -3482,6 +3502,10 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) { return 0x2; } +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) +{ + return 0x10; +} static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) { return 0x0041ac94; @@ -3618,6 +3642,14 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) +{ + return 0x10; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) { return 0x00504704; -- cgit v1.2.2 From cdae0f137923b5996bf544eb676394e0e51e993f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sat, 8 Jul 2017 23:14:58 -0700 Subject: gpu: nvgpu: gv11b: check bar2 bind_status This is needed as BAR1 support is removed and there is no way to know if gpu successfully accessed memory. JIRA GPUT19X-115 Change-Id: I5d18b6bf73e11b103d1951d2e28fb1f895e72c85 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1515813 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 52 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index f4fc4db4..9430f576 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -30,6 +30,7 @@ #include #include +#include #define NVGPU_L3_ALLOC_BIT 36 @@ -268,6 +269,56 @@ u64 gv11b_gpu_phys_addr(struct gk20a *g, return phys; } +static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + struct nvgpu_mem *inst_block = &mm->bar2.inst_block; + u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block); + u32 reg_val; + struct nvgpu_timeout timeout; + u32 delay = GR_IDLE_CHECK_DEFAULT; + + nvgpu_log_fn(g, " "); + + g->ops.fb.set_mmu_page_size(g); + + inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v()); + nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", (u32)inst_pa); + + gk20a_writel(g, bus_bar2_block_r(), + nvgpu_aperture_mask(g, inst_block, + bus_bar2_block_target_sys_mem_ncoh_f(), + bus_bar2_block_target_vid_mem_f()) | + bus_bar2_block_mode_virtual_f() | + bus_bar2_block_ptr_f(inst_pa)); + + /* This is needed as BAR1 support is removed and there is no way + * to know if gpu successfully accessed memory. + * To avoid deadlocks and non-deterministic virtual address translation + * behavior, after writing BAR2_BLOCK to bind BAR2 to a virtual address + * space, SW must ensure that the bind has completed prior to issuing + * any further BAR2 requests by polling for both + * BUS_BIND_STATUS_BAR2_PENDING to return to EMPTY and + * BUS_BIND_STATUS_BAR2_OUTSTANDING to return to FALSE + */ + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + nvgpu_log_info(g, "check bar2 bind status"); + do { + reg_val = gk20a_readl(g, bus_bind_status_r()); + + if (!((reg_val & bus_bind_status_bar2_pending_busy_f()) || + (reg_val & bus_bind_status_bar2_outstanding_true_f()))) + return 0; + + nvgpu_usleep_range(delay, delay * 2); + delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired_msg(&timeout, "bar2 bind timedout")); + + nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); + return -EBUSY; +} + void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); @@ -280,4 +331,5 @@ void gv11b_init_mm(struct gpu_ops *gops) gops->mm.fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy; gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; + gops->mm.init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup; } -- cgit v1.2.2 From 971c90e3b6b7f1e3f5dff67ccd701c99c1b0f7b5 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 11 May 2017 09:42:44 -0700 Subject: gpu: nvgpu: gv11b: set replay fault for tex and gcc This is to enable replay fault from tex and gcc engines JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I0cc8a59499da9eb056d19ee8d6cd33a94e3f0835 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1493407 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 68e969d0..bda36216 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -156,8 +156,8 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | ram_in_sc_page_dir_base_vol_f( ram_in_sc_page_dir_base_vol_true_v(), 0) | - ram_in_sc_page_dir_base_fault_replay_tex_f(0, 0) | - ram_in_sc_page_dir_base_fault_replay_gcc_f(0, 0) | + ram_in_sc_page_dir_base_fault_replay_tex_f(1, 0) | + ram_in_sc_page_dir_base_fault_replay_gcc_f(1, 0) | ram_in_sc_use_ver2_pt_format_f(1, 0) | ram_in_sc_big_page_size_f(1, 0) | ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); -- cgit v1.2.2 From 66fb130bfdf12175c117f36737503b1b5f33d42e Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 15 May 2017 16:33:41 -0700 Subject: gpu: nvgpu: gv11b: recover from replay and ce mmu fault Fix pte valid bit for replayable fault and ce fault JIRA GPUT19X-12 Change-Id: I77a7a452d9b5b304f182e120e8d75959d46d4422 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1515538 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 13 ++- drivers/gpu/nvgpu/gv11b/ce_gv11b.h | 3 +- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 218 +++++++++++++++++++++++++++++++++---- 3 files changed, 210 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index af87f990..9716c6d6 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -75,14 +75,23 @@ static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) gp10b_ce_isr(g, inst_id, pri_base); } -void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) +u32 gv11b_ce_get_num_lce(struct gk20a *g) { - u32 reg_val, num_lce, lce, clear_intr; + u32 reg_val, num_lce; reg_val = gk20a_readl(g, top_num_ces_r()); num_lce = top_num_ces_value_v(reg_val); nvgpu_log_info(g, "num LCE: %d", num_lce); + return num_lce; +} + +void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) +{ + u32 reg_val, num_lce, lce, clear_intr; + + num_lce = gv11b_ce_get_num_lce(g); + for (lce = 0; lce < num_lce; lce++) { reg_val = gk20a_readl(g, ce_intr_status_r(lce)); if (reg_val & ce_intr_status_mthd_buffer_fault_pending_f()) { diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h index 09d18058..23053199 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h @@ -2,7 +2,7 @@ * * Volta GPU series copy engine * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,5 +23,6 @@ struct gpu_ops; void gv11b_init_ce(struct gpu_ops *gops); void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g); +u32 gv11b_ce_get_num_lce(struct gk20a *g); #endif /*__CE2_GV11B_H__*/ diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index f9532d66..0ec6c9dd 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -17,9 +17,12 @@ #include #include +#include +#include #include "gk20a/gk20a.h" #include "gk20a/kind_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gp10b/fb_gp10b.h" @@ -33,8 +36,12 @@ #include #include -#include -#include + +static int gv11b_fb_fix_page_fault(struct gk20a *g, + struct mmu_fault_info *mmfault); + +static int gv11b_fb_mmu_invalidate_replay(struct gk20a *g, + u32 invalidate_replay_val); static void gv11b_init_nvlink_soc_credits(struct gk20a *g) { @@ -964,17 +971,43 @@ static void gv11b_fb_copy_from_hw_fault_buf(struct gk20a *g, } static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, - struct mmu_fault_info *mmfault) + struct mmu_fault_info *mmfault, u32 *invalidate_replay_val) { unsigned int id_type; - u32 act_eng_bitmask = 0; + u32 num_lce, act_eng_bitmask = 0; + int err = 0; if (!mmfault->valid) return; gv11b_fb_print_fault_info(g, mmfault); - if (mmfault->fault_type == gmmu_fault_type_unbound_inst_block_v()) { + num_lce = gv11b_ce_get_num_lce(g); + if ((mmfault->mmu_engine_id >= + gmmu_fault_mmu_eng_id_ce0_v()) && + (mmfault->mmu_engine_id < + gmmu_fault_mmu_eng_id_ce0_v() + num_lce)) { + /* CE page faults are not reported as replayable */ + nvgpu_log(g, gpu_dbg_intr, "CE Faulted"); + err = gv11b_fb_fix_page_fault(g, mmfault); + gv11b_fifo_reset_pbdma_and_eng_faulted(g, mmfault->refch, + mmfault->faulted_pbdma, mmfault->faulted_engine); + if (!err) { + nvgpu_log(g, gpu_dbg_intr, "CE Page Fault Fixed"); + *invalidate_replay_val = 0; + /* refch in mmfault is assigned at the time of copying + * fault info from snap reg or bar2 fault buf + */ + gk20a_channel_put(mmfault->refch); + return; + } + /* Do recovery. Channel recovery needs refch */ + nvgpu_log(g, gpu_dbg_intr, "CE Page Fault Not Fixed"); + } + + if (!mmfault->replayable_fault) { + if (mmfault->fault_type == + gmmu_fault_type_unbound_inst_block_v()) { /* * Bug 1847172: When an engine faults due to an unbound * instance block, the fault cannot be isolated to a @@ -983,20 +1016,56 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, id_type = ID_TYPE_UNKNOWN; nvgpu_log(g, gpu_dbg_intr, "UNBOUND INST BLOCK MMU FAULT"); - } else if (mmfault->refch) { - if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) - id_type = ID_TYPE_TSG; - else - id_type = ID_TYPE_CHANNEL; + } else if (mmfault->refch) { + if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) + id_type = ID_TYPE_TSG; + else + id_type = ID_TYPE_CHANNEL; + } else { + id_type = ID_TYPE_UNKNOWN; + } + if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) + act_eng_bitmask = BIT(mmfault->faulted_engine); + + g->ops.fifo.teardown_ch_tsg(g, act_eng_bitmask, + mmfault->chid, id_type, RC_TYPE_MMU_FAULT, mmfault); } else { - id_type = ID_TYPE_UNKNOWN; + err = gv11b_fb_fix_page_fault(g, mmfault); + if (err) { + *invalidate_replay_val |= + fb_mmu_invalidate_replay_cancel_global_f(); + } else { + *invalidate_replay_val |= + fb_mmu_invalidate_replay_start_ack_all_f(); + } + /* refch in mmfault is assigned at the time of copying + * fault info from snap reg or bar2 fault buf + */ + gk20a_channel_put(mmfault->refch); } +} - if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) - act_eng_bitmask = BIT(mmfault->faulted_engine); +static void gv11b_fb_replay_or_cancel_faults(struct gk20a *g, + u32 invalidate_replay_val) +{ + int err = 0; - g->ops.fifo.teardown_ch_tsg(g, act_eng_bitmask, mmfault->chid, - id_type, RC_TYPE_MMU_FAULT, mmfault); + nvgpu_log_fn(g, " "); + + if (invalidate_replay_val & + fb_mmu_invalidate_replay_cancel_global_f()) { + /* + * cancel faults so that next time it faults as + * replayable faults and channel recovery can be done + */ + err = gv11b_fb_mmu_invalidate_replay(g, + fb_mmu_invalidate_replay_cancel_global_f()); + } else if (invalidate_replay_val & + fb_mmu_invalidate_replay_start_ack_all_f()) { + /* pte valid is fixed. replay faulting request */ + err = gv11b_fb_mmu_invalidate_replay(g, + fb_mmu_invalidate_replay_start_ack_all_f()); + } } static void gv11b_fb_handle_mmu_nonreplay_replay_fault(struct gk20a *g, @@ -1005,10 +1074,13 @@ static void gv11b_fb_handle_mmu_nonreplay_replay_fault(struct gk20a *g, u32 get_indx, offset, rd32_val, entries; struct nvgpu_mem *mem; struct mmu_fault_info *mmfault; + u32 invalidate_replay_val = 0; + u64 prev_fault_addr = 0; + u64 next_fault_addr = 0; - if (gv11b_fb_is_fault_buffer_empty(g, index, - &get_indx)) { - nvgpu_log(g, gpu_dbg_intr, "SPURIOUS fault"); + if (gv11b_fb_is_fault_buffer_empty(g, index, &get_indx)) { + nvgpu_log(g, gpu_dbg_intr, + "SPURIOUS mmu fault: reg index:%d", index); return; } nvgpu_log(g, gpu_dbg_intr, "get ptr = %d", get_indx); @@ -1041,14 +1113,29 @@ static void gv11b_fb_handle_mmu_nonreplay_replay_fault(struct gk20a *g, gv11b_fb_fault_buffer_get_ptr_update(g, index, get_indx); - gv11b_fb_handle_mmu_fault_common(g, mmfault); - offset = (get_indx * gmmu_fault_buf_size_v()) / sizeof(u32); nvgpu_log(g, gpu_dbg_intr, "next word offset = 0x%x", offset); rd32_val = nvgpu_mem_rd32(g, mem, offset + gmmu_fault_buf_entry_valid_w()); + + if (index == REPLAY_REG_INDEX) { + prev_fault_addr = next_fault_addr; + next_fault_addr = mmfault->fault_addr; + if (prev_fault_addr == next_fault_addr) { + if (mmfault->refch) + gk20a_channel_put(mmfault->refch); + /* pte already fixed for this addr */ + continue; + } + } + + gv11b_fb_handle_mmu_fault_common(g, mmfault, + &invalidate_replay_val); + } + if (index == REPLAY_REG_INDEX && invalidate_replay_val) + gv11b_fb_replay_or_cancel_faults(g, invalidate_replay_val); } static void gv11b_mm_copy_from_fault_snap_reg(struct gk20a *g, @@ -1228,6 +1315,7 @@ static void gv11b_fb_handle_other_fault_notify(struct gk20a *g, u32 fault_status) { struct mmu_fault_info *mmfault; + u32 invalidate_replay_val = 0; mmfault = g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY]; @@ -1244,7 +1332,12 @@ static void gv11b_fb_handle_other_fault_notify(struct gk20a *g, nvgpu_err(g, "PHYSICAL MMU FAULT"); } else { - gv11b_fb_handle_mmu_fault_common(g, mmfault); + gv11b_fb_handle_mmu_fault_common(g, mmfault, + &invalidate_replay_val); + + if (invalidate_replay_val) + gv11b_fb_replay_or_cancel_faults(g, + invalidate_replay_val); } } @@ -1398,6 +1491,89 @@ bool gv11b_fb_mmu_fault_pending(struct gk20a *g) return false; } +static int gv11b_fb_mmu_invalidate_replay(struct gk20a *g, + u32 invalidate_replay_val) +{ + int err = -ETIMEDOUT; + u32 reg_val; + struct nvgpu_timeout timeout; + + gk20a_dbg_fn(""); + + nvgpu_mutex_acquire(&g->mm.tlb_lock); + + reg_val = gk20a_readl(g, fb_mmu_invalidate_r()); + + reg_val |= fb_mmu_invalidate_all_va_true_f() | + fb_mmu_invalidate_all_pdb_true_f() | + invalidate_replay_val | + fb_mmu_invalidate_trigger_true_f(); + + gk20a_writel(g, fb_mmu_invalidate_r(), reg_val); + + /* retry 200 times */ + nvgpu_timeout_init(g, &timeout, 200, NVGPU_TIMER_RETRY_TIMER); + do { + reg_val = gk20a_readl(g, fb_mmu_ctrl_r()); + if (fb_mmu_ctrl_pri_fifo_empty_v(reg_val) != + fb_mmu_ctrl_pri_fifo_empty_false_f()) { + err = 0; + break; + } + nvgpu_udelay(5); + } while (!nvgpu_timeout_expired_msg(&timeout, + "invalidate replay failed on 0x%llx")); + if (err) + nvgpu_err(g, "invalidate replay timedout"); + + nvgpu_mutex_release(&g->mm.tlb_lock); + + return err; +} + +static int gv11b_fb_fix_page_fault(struct gk20a *g, + struct mmu_fault_info *mmfault) +{ + int err = 0; + u32 pte[2]; + + if (mmfault->refch == NULL) { + nvgpu_log(g, gpu_dbg_intr, "refch from mmu_fault_info is NULL"); + return -EINVAL; + } + + err = __nvgpu_get_pte(g, + mmfault->refch->vm, mmfault->fault_addr, &pte[0]); + if (err) { + nvgpu_log(g, gpu_dbg_intr | gpu_dbg_pte, "pte not found"); + return err; + } + nvgpu_log(g, gpu_dbg_intr | gpu_dbg_pte, + "pte: %#08x %#08x", pte[1], pte[0]); + + pte[0] |= gmmu_new_pte_valid_true_f(); + if (pte[0] & gmmu_new_pte_read_only_true_f()) + pte[0] &= ~(gmmu_new_pte_read_only_true_f()); + nvgpu_log(g, gpu_dbg_intr | gpu_dbg_pte, + "new pte: %#08x %#08x", pte[1], pte[0]); + + err = __nvgpu_set_pte(g, + mmfault->refch->vm, mmfault->fault_addr, &pte[0]); + if (err) { + nvgpu_log(g, gpu_dbg_intr | gpu_dbg_pte, "pte not fixed"); + return err; + } + /* invalidate tlb so that GMMU does not use old cached translation */ + g->ops.fb.tlb_invalidate(g, mmfault->refch->vm->pdb.mem); + + err = __nvgpu_get_pte(g, + mmfault->refch->vm, mmfault->fault_addr, &pte[0]); + nvgpu_log(g, gpu_dbg_intr | gpu_dbg_pte, + "pte after tlb invalidate: %#08x %#08x", + pte[1], pte[0]); + return err; +} + void gv11b_init_fb(struct gpu_ops *gops) { gp10b_init_fb(gops); -- cgit v1.2.2 From df022d27ddf2f66bff04170bb454fa26db8d51b1 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sat, 8 Jul 2017 17:20:26 -0700 Subject: gpu: nvgpu: gv11b: support SET_SKEDCHECK s/w methods Support sw method NVC397_SET_SKEDCHECK and NVC3C0_SET_SKEDCHECK data fields are data:0 SKEDCHECK_18_DISABLE data:1 SKEDCHECK_18_ENABLE Bug 200315442 Change-Id: I0652434ab0b4d6e49dab94be329072861e99c38c Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1515772 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 40 ++++++++++++++++++++++++++++---------- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 8 ++++++++ 2 files changed, 38 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 2c3b0820..6f3b5f0f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -299,8 +299,6 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) { - u32 val; - /* enable exceptions */ gk20a_writel(g, gr_fe_hww_esr_r(), gr_fe_hww_esr_en_enable_f() | @@ -308,14 +306,6 @@ static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) gk20a_writel(g, gr_memfmt_hww_esr_r(), gr_memfmt_hww_esr_en_enable_f() | gr_memfmt_hww_esr_reset_active_f()); - /* WAR for 200315442 */ - val = gk20a_readl(g, gr_sked_hww_esr_en_r()); - val = set_field(val, - gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), - gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f() - ); - nvgpu_log_info(g, "sked_hww_esr_en = 0x%x", val); - gk20a_writel(g, gr_sked_hww_esr_en_r(), val); } static void gr_gv11b_enable_exceptions(struct gk20a *g) @@ -1108,6 +1098,30 @@ static void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data) gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); } +static void gr_gv11b_set_skedcheck(struct gk20a *g, u32 data) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, gr_sked_hww_esr_en_r()); + + if ((data & NVC397_SET_SKEDCHECK_18_MASK) == + NVC397_SET_SKEDCHECK_18_DISABLE) { + reg_val = set_field(reg_val, + gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), + gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f() + ); + } else if ((data & NVC397_SET_SKEDCHECK_18_MASK) == + NVC397_SET_SKEDCHECK_18_ENABLE) { + reg_val = set_field(reg_val, + gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(), + gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f() + ); + } + nvgpu_log_info(g, "sked_hww_esr_en = 0x%x", reg_val); + gk20a_writel(g, gr_sked_hww_esr_en_r(), reg_val); + +} + static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) { gk20a_dbg_fn(""); @@ -1132,6 +1146,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, case NVC0C0_SET_SHADER_EXCEPTIONS: gv11b_gr_set_shader_exceptions(g, data); break; + case NVC3C0_SET_SKEDCHECK: + gr_gv11b_set_skedcheck(g, data); + break; default: goto fail; } @@ -1157,6 +1174,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, case NVC397_SET_TEX_IN_DBG: gr_gv11b_set_tex_in_dbg(g, data); break; + case NVC397_SET_SKEDCHECK: + gr_gv11b_set_skedcheck(g, data); + break; default: goto fail; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index ff5782d9..1e060bd0 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -40,11 +40,19 @@ enum { #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c #define NVC397_SET_TEX_IN_DBG 0x10bc +#define NVC397_SET_SKEDCHECK 0x10c0 #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4 +#define NVC397_SET_SKEDCHECK_18_MASK 0x3 +#define NVC397_SET_SKEDCHECK_18_DEFAULT 0x0 +#define NVC397_SET_SKEDCHECK_18_DISABLE 0x1 +#define NVC397_SET_SKEDCHECK_18_ENABLE 0x2 + +#define NVC3C0_SET_SKEDCHECK 0x23c + #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 void gv11b_init_gr(struct gpu_ops *ops); -- cgit v1.2.2 From aade61eff9962b4671802b0d88523e6ccccde6b0 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 28 Jun 2017 17:57:39 -0700 Subject: gpu: nvgpu: gv11b: Reorg falcon HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the falcon sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: If980fcd2605a445bd623a5fcca8262826ce289c4 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514013 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 98350e4b..0a508ddf 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -200,6 +200,10 @@ static const struct gpu_ops gv11b_ops = { .pg_gr_load_gating_prod = gr_gv11b_pg_gr_load_gating_prod, }, + + .falcon = { + .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, + }, .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; @@ -211,6 +215,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; + gops->falcon = gv11b_ops.falcon; /* Lone functions */ gops->chip_init_gpu_characteristics = @@ -231,7 +236,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); - gk20a_falcon_init_hal(gops); gv11b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); gk20a_init_dbg_session_ops(gops); -- cgit v1.2.2 From 4e290320fdfe56cc2fe849720d6a01b44cace1a7 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 27 Jun 2017 14:05:15 -0700 Subject: gpu: nvgpu: gv11b: Reorg mc HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I1a5abde46bf079c206dfdf9f8ee35df048565c49 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1509603 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 22 ++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 11 ++--------- drivers/gpu/nvgpu/gv11b/mc_gv11b.h | 5 +++-- 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0a508ddf..d7f00d2f 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -21,6 +21,7 @@ #include "gk20a/gk20a.h" #include "gk20a/css_gr_gk20a.h" +#include "gk20a/mc_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -29,6 +30,7 @@ #include "gm20b/gr_gm20b.h" #include "gp10b/ltc_gp10b.h" +#include "gp10b/mc_gp10b.h" #include "gp10b/priv_ring_gp10b.h" #include "hal_gv11b.h" @@ -200,7 +202,23 @@ static const struct gpu_ops gv11b_ops = { .pg_gr_load_gating_prod = gr_gv11b_pg_gr_load_gating_prod, }, - + .mc = { + .intr_enable = mc_gv11b_intr_enable, + .intr_unit_config = mc_gp10b_intr_unit_config, + .isr_stall = mc_gp10b_isr_stall, + .intr_stall = mc_gp10b_intr_stall, + .intr_stall_pause = mc_gp10b_intr_stall_pause, + .intr_stall_resume = mc_gp10b_intr_stall_resume, + .intr_nonstall = mc_gp10b_intr_nonstall, + .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, + .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .enable = gk20a_mc_enable, + .disable = gk20a_mc_disable, + .reset = gk20a_mc_reset, + .boot_0 = gk20a_mc_boot_0, + .is_intr1_pending = mc_gp10b_is_intr1_pending, + .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, + }, .falcon = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, @@ -215,6 +233,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; + gops->mc = gv11b_ops.mc; gops->falcon = gv11b_ops.falcon; /* Lone functions */ @@ -227,7 +246,6 @@ int gv11b_init_hal(struct gk20a *g) gops->securegpccs = 0; gv11b_init_bus(gops); - gv11b_init_mc(gops); gp10b_init_priv_ring(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index cc29f74a..81e6381f 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -24,7 +24,7 @@ #include -static void mc_gv11b_intr_enable(struct gk20a *g) +void mc_gv11b_intr_enable(struct gk20a *g) { u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); @@ -57,14 +57,7 @@ static void mc_gv11b_intr_enable(struct gk20a *g) } -static bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) +bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) { return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false); } - -void gv11b_init_mc(struct gpu_ops *gops) -{ - gp10b_init_mc(gops); - gops->mc.intr_enable = mc_gv11b_intr_enable; - gops->mc.is_intr_hub_pending = gv11b_mc_is_intr_hub_pending; -} diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/mc_gv11b.h index 6cb2cde0..53f25a39 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,5 +15,6 @@ #define MC_GV11B_H struct gk20a; -void gv11b_init_mc(struct gpu_ops *gops); +void mc_gv11b_intr_enable(struct gk20a *g); +bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0); #endif -- cgit v1.2.2 From 2f0838af1b8a73dc976837dfa568281d47628a37 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 27 Jun 2017 14:30:57 -0700 Subject: gpu: nvgpu: gv11b: Move gops.mc's non-fp members Move non-function pointer members out of the mc substruct of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. gops.mc.intr_mask_restore is now mc_intr_mask_restore Jira NVGPU-74 Change-Id: I789087704fb5e6338f6010f18457948d0ee6c630 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1509604 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 81e6381f..59263e54 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -34,7 +34,7 @@ void mc_gv11b_intr_enable(struct gk20a *g) 0xffffffff); gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = mc_intr_pfifo_pending_f() | mc_intr_hub_pending_f() | mc_intr_priv_ring_pending_f() | @@ -42,7 +42,7 @@ void mc_gv11b_intr_enable(struct gk20a *g) mc_intr_ltc_pending_f() | eng_intr_mask; - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = mc_intr_pfifo_pending_f() | eng_intr_mask; @@ -50,10 +50,10 @@ void mc_gv11b_intr_enable(struct gk20a *g) gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types); gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); } -- cgit v1.2.2 From 4074484f756734d9f1902944dc80966f3659bb39 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Thu, 29 Jun 2017 11:14:52 -0700 Subject: gpu: nvgpu: gv11b: Reorg debug HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the debug and dbg_session_ops sub-modules of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I23cda2fbb47fb41975a4a938e352a7427853be94 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514820 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index d7f00d2f..18cd686e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,6 +25,7 @@ #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" +#include "gk20a/regops_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" @@ -219,6 +220,21 @@ static const struct gpu_ops gv11b_ops = { .is_intr1_pending = mc_gp10b_is_intr1_pending, .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, }, + .debug = { + .show_dump = gk20a_debug_show_dump, + }, + .dbg_session_ops = { + .exec_reg_ops = exec_regops_gk20a, + .dbg_set_powergate = dbg_set_powergate, + .check_and_set_global_reservation = + nvgpu_check_and_set_global_reservation, + .check_and_set_context_reservation = + nvgpu_check_and_set_context_reservation, + .release_profiler_reservation = + nvgpu_release_profiler_reservation, + .perfbuffer_enable = gk20a_perfbuf_enable_locked, + .perfbuffer_disable = gk20a_perfbuf_disable_locked, + }, .falcon = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, @@ -234,6 +250,8 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; gops->mc = gv11b_ops.mc; + gops->debug = gv11b_ops.debug; + gops->dbg_session_ops = gv11b_ops.dbg_session_ops; gops->falcon = gv11b_ops.falcon; /* Lone functions */ @@ -255,8 +273,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(gops); - gk20a_init_debug_ops(gops); - gk20a_init_dbg_session_ops(gops); gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); -- cgit v1.2.2 From 2272cedfbacf271a0faacfd054240fea3027423d Mon Sep 17 00:00:00 2001 From: Lauri Peltonen Date: Mon, 10 Jul 2017 15:06:31 +0300 Subject: gpu: nvgu: Support SET_BES_CROP_DEBUG3 sw method The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is used by the user space driver to disable enough ROP optimizations to maintain ZBC state of target tiles. Bug 1942454 Change-Id: I3109fb4120674b15db4998693d0aa65bf0c3c8b5 Signed-off-by: Lauri Peltonen Reviewed-on: https://git-master.nvidia.com/r/1516205 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 3 +++ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 + .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 24 ++++++++++++++++++++++ 3 files changed, 28 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 6f3b5f0f..f44c60b0 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1177,6 +1177,9 @@ static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, case NVC397_SET_SKEDCHECK: gr_gv11b_set_skedcheck(g, data); break; + case NVC397_SET_BES_CROP_DEBUG3: + g->ops.gr.set_bes_crop_debug3(g, data); + break; default: goto fail; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 1e060bd0..e6149b37 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -41,6 +41,7 @@ enum { #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c #define NVC397_SET_TEX_IN_DBG 0x10bc #define NVC397_SET_SKEDCHECK 0x10c0 +#define NVC397_SET_BES_CROP_DEBUG3 0x10c4 #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 53dc7c87..c9dbee52 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3918,6 +3918,30 @@ static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) { return 0x1 << 31; } +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) +{ + return 0x4; +} static inline u32 gr_bes_crop_settings_r(void) { return 0x00408958; -- cgit v1.2.2 From 81274038a4ac4404d4697cf54278da0a5154f353 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 11 Jul 2017 12:59:33 -0700 Subject: gpu: nvgpu: gv11b: updated clock gating prod settings Updated clock gating prod settings for HW CL 38810810 Change-Id: Ie0769edb41b46e323b042a654e6002a4f7044030 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1517514 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c index 390d89c2..3b55eb41 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c @@ -94,13 +94,6 @@ static const struct gating_desc gv11b_slcg_gr[] = { {.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe}, {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, - {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, - {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, - {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, - {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, - {.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe}, - {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, - {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, -- cgit v1.2.2 From 68b65f642ab49e8d30a17da04c053673e49e6d24 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sat, 8 Jul 2017 15:51:17 -0700 Subject: gpu: nvgpu: gv11b: h/w header updated for CL 38810810 H/w header updates for FPGA SNAP_0617 Change-Id: I6d3fe0b5b36de5999b09b9aa65e6dde2817634b5 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1515766 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 12 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 122 ++++++++++++++++++++- 2 files changed, 125 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index bd2f628c..e98c9f76 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -266,10 +266,6 @@ static inline u32 fifo_intr_sched_error_code_f(u32 v) { return (v & 0xff) << 0; } -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000a; -} static inline u32 fifo_intr_chsw_error_r(void) { return 0x0000256c; @@ -308,7 +304,7 @@ static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 14) & 0x3; } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) { @@ -324,15 +320,15 @@ static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) } static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) { - return (r >> 4) & 0xfff; + return (r >> 0) & 0x3fff; } static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) { - return (r >> 16) & 0xfff; + return (r >> 16) & 0x3fff; } static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 30) & 0x3; } static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 965f8663..6c6dea4a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -78,6 +78,10 @@ static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) { return 0x40; } +static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) +{ + return 0x800; +} static inline u32 pwr_falcon_irqmode_r(void) { return 0x0010a00c; @@ -118,6 +122,38 @@ static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) { return (v & 0x1) << 7; } +static inline u32 pwr_falcon_irqmset_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v) +{ + return (v & 0x1) << 15; +} static inline u32 pwr_falcon_irqmclr_r(void) { return 0x0010a014; @@ -158,6 +194,34 @@ static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) { return (v & 0xff) << 8; } +static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v) +{ + return (v & 0x1) << 15; +} static inline u32 pwr_falcon_irqmask_r(void) { return 0x0010a018; @@ -202,6 +266,34 @@ static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) { return (v & 0xff) << 8; } +static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v) +{ + return (v & 0x1) << 15; +} static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) { return (v & 0x1) << 16; @@ -238,6 +330,34 @@ static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) { return (v & 0xff) << 24; } +static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v) +{ + return (v & 0x1) << 31; +} static inline u32 pwr_falcon_curctx_r(void) { return 0x0010a050; -- cgit v1.2.2 From 4df5427c15e28a3bd131a4bdaed413de2a9a5e99 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 6 Jun 2017 22:56:11 -0700 Subject: gpu: nvgpu: gv11b: init perf related gr ops Implement gv11b specific perf gr ops JIRA GPUT19X-49 Bug 200311674 Change-Id: Ia65fe84df6e38e25f87d2c1b21c04b518c334d42 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1497402 GVS: Gerrit_Virtual_Submit Reviewed-by: Tushar Kashalikar Tested-by: Tushar Kashalikar Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 86 ++++++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 152 +++++++++++++++++++++ 2 files changed, 238 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index f44c60b0..eefbdf3b 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -3253,6 +3253,87 @@ static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, return 0; } +static const u32 _num_ovr_perf_regs = 20; +static u32 _ovr_perf_regs[20] = { 0, }; + +static void gv11b_gr_init_ovr_sm_dsm_perf(void) +{ + if (_ovr_perf_regs[0] != 0) + return; + + _ovr_perf_regs[0] = gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(); + _ovr_perf_regs[1] = gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(); + _ovr_perf_regs[2] = gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(); + _ovr_perf_regs[3] = gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(); + _ovr_perf_regs[4] = gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(); + _ovr_perf_regs[5] = gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(); + _ovr_perf_regs[6] = gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(); + _ovr_perf_regs[7] = gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(); + _ovr_perf_regs[8] = gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(); + _ovr_perf_regs[9] = gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(); + _ovr_perf_regs[10] = gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(); + _ovr_perf_regs[11] = gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(); + _ovr_perf_regs[12] = gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(); + _ovr_perf_regs[13] = gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(); + _ovr_perf_regs[14] = gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(); + _ovr_perf_regs[15] = gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(); + + _ovr_perf_regs[16] = gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(); + _ovr_perf_regs[17] = gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(); + _ovr_perf_regs[18] = gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(); + _ovr_perf_regs[19] = gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(); +} + +/* Following are the blocks of registers that the ucode + * stores in the extended region. + */ +/* == ctxsw_extended_sm_dsm_perf_counter_register_stride_v() ? */ +static const u32 _num_sm_dsm_perf_regs; +/* == ctxsw_extended_sm_dsm_perf_counter_control_register_stride_v() ?*/ +static const u32 _num_sm_dsm_perf_ctrl_regs = 2; +static u32 *_sm_dsm_perf_regs; +static u32 _sm_dsm_perf_ctrl_regs[2]; + +static void gv11b_gr_init_sm_dsm_reg_info(void) +{ + if (_sm_dsm_perf_ctrl_regs[0] != 0) + return; + + _sm_dsm_perf_ctrl_regs[0] = + gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(); + _sm_dsm_perf_ctrl_regs[1] = + gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(); +} + +static void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, + u32 *num_sm_dsm_perf_regs, + u32 **sm_dsm_perf_regs, + u32 *perf_register_stride) +{ + *num_sm_dsm_perf_regs = _num_sm_dsm_perf_regs; + *sm_dsm_perf_regs = _sm_dsm_perf_regs; + *perf_register_stride = + ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); +} + +static void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, + u32 *num_sm_dsm_perf_ctrl_regs, + u32 **sm_dsm_perf_ctrl_regs, + u32 *ctrl_register_stride) +{ + *num_sm_dsm_perf_ctrl_regs = _num_sm_dsm_perf_ctrl_regs; + *sm_dsm_perf_ctrl_regs = _sm_dsm_perf_ctrl_regs; + *ctrl_register_stride = + ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); +} + +static void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, + u32 **ovr_perf_regs) +{ + *num_ovr_perf_regs = _num_ovr_perf_regs; + *ovr_perf_regs = _ovr_perf_regs; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3337,4 +3418,9 @@ void gv11b_init_gr(struct gpu_ops *gops) gr_gv11b_handle_tpc_sm_ecc_exception; gops->gr.handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception; + gops->gr.init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf; + gops->gr.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info; + gops->gr.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs; + gops->gr.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs; + gops->gr.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index c9dbee52..153aef2f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -3998,6 +3998,158 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) { return 0x1 << 10; } +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) +{ + return 0x00584200; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void) +{ + return 0x00584204; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void) +{ + return 0x00584208; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void) +{ + return 0x00584210; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void) +{ + return 0x00584214; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void) +{ + return 0x00584218; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void) +{ + return 0x0058421c; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void) +{ + return 0x0058420c; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void) +{ + return 0x00584220; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void) +{ + return 0x00584224; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void) +{ + return 0x00584228; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void) +{ + return 0x0058422c; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void) +{ + return 0x00584230; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void) +{ + return 0x00584234; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void) +{ + return 0x00584238; +} +static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void) +{ + return 0x0058423c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void) +{ + return 0x00584600; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void) +{ + return 0x00584604; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void) +{ + return 0x00584624; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void) +{ + return 0x00584628; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void) +{ + return 0x0058462c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void) +{ + return 0x00584630; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void) +{ + return 0x00584634; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void) +{ + return 0x00584638; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void) +{ + return 0x0058463c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void) +{ + return 0x00584640; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void) +{ + return 0x00584644; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void) +{ + return 0x00584648; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void) +{ + return 0x0058464c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void) +{ + return 0x00584650; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void) +{ + return 0x00584654; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void) +{ + return 0x00584658; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void) +{ + return 0x0058465c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void) +{ + return 0x00584660; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void) +{ + return 0x00584614; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void) +{ + return 0x00584618; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void) +{ + return 0x0058461c; +} +static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void) +{ + return 0x00584620; +} static inline u32 gr_fe_pwr_mode_r(void) { return 0x00404170; -- cgit v1.2.2 From c7d48710b09dcd64c55f7ae4f264499c2bbc866c Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 17 Jul 2017 14:45:35 -0700 Subject: gpu: nvgpu: gv11b: init access_smpc_reg gr ops This is needed to support t19x smpc register addresses JIRA GPUT19X-49 Bug 200311674 Change-Id: I67146d997d96eeca4344ed0fb4cabbc216461c6c Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1508543 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 45 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index eefbdf3b..00bfde6b 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -30,6 +30,7 @@ #include "gk20a/gr_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/regops_gk20a.h" +#include "gk20a/gr_pri_gk20a.h" #include "gm20b/gr_gm20b.h" @@ -3334,6 +3335,49 @@ static void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, *ovr_perf_regs = _ovr_perf_regs; } +static void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset) +{ + u32 reg_val; + u32 quad_ctrl; + u32 half_ctrl; + u32 tpc, gpc; + u32 gpc_tpc_addr; + u32 gpc_tpc_stride; + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, + GPU_LIT_TPC_IN_GPC_STRIDE); + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "offset=0x%x", offset); + + gpc = pri_get_gpc_num(g, offset); + gpc_tpc_addr = pri_gpccs_addr_mask(offset); + tpc = g->ops.gr.get_tpc_num(g, gpc_tpc_addr); + + quad_ctrl = quad & 0x1; /* first bit tells us quad */ + half_ctrl = (quad >> 1) & 0x1; /* second bit tells us half */ + + gpc_tpc_stride = gpc * gpc_stride + tpc * tpc_in_gpc_stride; + gpc_tpc_addr = gr_gpc0_tpc0_sm_halfctl_ctrl_r() + gpc_tpc_stride; + + /* read from unicast reg */ + reg_val = gk20a_readl(g, gpc_tpc_addr); + reg_val = set_field(reg_val, + gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(), + gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(quad_ctrl)); + + /* write to broadcast reg */ + gk20a_writel(g, gr_gpcs_tpcs_sm_halfctl_ctrl_r(), reg_val); + + gpc_tpc_addr = gr_gpc0_tpc0_sm_debug_sfe_control_r() + gpc_tpc_stride; + reg_val = gk20a_readl(g, gpc_tpc_addr); + reg_val = set_field(reg_val, + gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(), + gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(half_ctrl)); + + /* write to broadcast reg */ + gk20a_writel(g, gr_gpcs_tpcs_sm_debug_sfe_control_r(), reg_val); +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3423,4 +3467,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs; gops->gr.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs; gops->gr.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs; + gops->gr.access_smpc_reg = gv11b_gr_access_smpc_reg; } -- cgit v1.2.2 From 7ab28a41842df2045533b0836233db3563cd531f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 6 Jun 2017 12:04:46 -0700 Subject: gpu: nvgpu: gv11b: support egpc and etpc context regoptype - implement is_egpc_addr, is_etpc_addr and get_egpc_etpc_num gr ops - implement decode and create priv addr for egpc/etpc JIRA GPUT19X-49 Bug 200311674 Signed-off-by: Seema Khowala Change-Id: Ia0cef51b2064df28460711185cd90b60aac03e4f Reviewed-on: https://git-master.nvidia.com/r/1522450 GVS: Gerrit_Virtual_Submit Reviewed-by: Tushar Kashalikar Tested-by: Tushar Kashalikar Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 196 +++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 + 2 files changed, 199 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 00bfde6b..fab2ae9a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -3378,6 +3378,196 @@ static void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset) gk20a_writel(g, gr_gpcs_tpcs_sm_debug_sfe_control_r(), reg_val); } +static bool pri_is_egpc_addr_shared(struct gk20a *g, u32 addr) +{ + u32 egpc_shared_base = EGPC_PRI_SHARED_BASE; + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + + return (addr >= egpc_shared_base) && + (addr < egpc_shared_base + gpc_stride); +} + +static bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr) +{ + u32 egpc_base = g->ops.gr.get_egpc_base(g); + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); + + return ((addr >= egpc_base) && + (addr < egpc_base + num_gpcs * gpc_stride)) || + pri_is_egpc_addr_shared(g, addr); +} + +static bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr) +{ + u32 egpc_addr = 0; + + if (g->ops.gr.is_egpc_addr(g, addr)) { + egpc_addr = pri_gpccs_addr_mask(addr); + if (g->ops.gr.is_tpc_addr(g, egpc_addr)) + return true; + } + + return false; +} + +static u32 pri_get_egpc_num(struct gk20a *g, u32 addr) +{ + u32 i, start; + u32 egpc_base = g->ops.gr.get_egpc_base(g); + u32 num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + + for (i = 0; i < num_gpcs; i++) { + start = egpc_base + (i * gpc_stride); + if ((addr >= start) && (addr < (start + gpc_stride))) + return i; + } + return 0; +} + +static u32 pri_egpc_addr(struct gk20a *g, u32 addr, u32 gpc) +{ + u32 egpc_base = g->ops.gr.get_egpc_base(g); + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + + return egpc_base + (gpc * gpc_stride) + addr; +} + +static u32 pri_etpc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 tpc) +{ + u32 egpc_base = g->ops.gr.get_egpc_base(g); + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 tpc_in_gpc_base = nvgpu_get_litter_value(g, + GPU_LIT_TPC_IN_GPC_BASE); + u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, + GPU_LIT_TPC_IN_GPC_STRIDE); + + return egpc_base + (gpc * gpc_stride) + + tpc_in_gpc_base + (tpc * tpc_in_gpc_stride) + + addr; +} + +static void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, + u32 *egpc_num, u32 *etpc_num) +{ + u32 egpc_addr = 0; + + *egpc_num = pri_get_egpc_num(g, addr); + egpc_addr = pri_gpccs_addr_mask(addr); + *etpc_num = g->ops.gr.get_tpc_num(g, egpc_addr); + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, + "egpc_num = %d etpc_num = %d", *egpc_num, *etpc_num); +} + +static int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, + u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags) +{ + u32 gpc_addr; + + if (g->ops.gr.is_egpc_addr(g, addr)) { + nvgpu_log_info(g, "addr=0x%x is egpc", addr); + + *addr_type = CTXSW_ADDR_TYPE_EGPC; + gpc_addr = pri_gpccs_addr_mask(addr); + if (pri_is_egpc_addr_shared(g, addr)) { + *broadcast_flags |= PRI_BROADCAST_FLAGS_EGPC; + *gpc_num = 0; + nvgpu_log_info(g, "shared egpc"); + } else { + *gpc_num = pri_get_egpc_num(g, addr); + nvgpu_log_info(g, "gpc=0x%x", *gpc_num); + } + if (g->ops.gr.is_tpc_addr(g, gpc_addr)) { + nvgpu_log_info(g, "addr=0x%x is etpc", addr); + *addr_type = CTXSW_ADDR_TYPE_ETPC; + if (pri_is_tpc_addr_shared(g, gpc_addr)) { + *broadcast_flags |= PRI_BROADCAST_FLAGS_ETPC; + *tpc_num = 0; + nvgpu_log_info(g, "shared etpc"); + } else { + *tpc_num = g->ops.gr.get_tpc_num(g, gpc_addr); + nvgpu_log_info(g, "tpc=0x%x", *tpc_num); + } + } + + nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, + "addr_type = %d, broadcast_flags = %#08x", + *addr_type, *broadcast_flags); + return 0; + } + return -EINVAL; +} + +static void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, + u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t) +{ + u32 gpc_num, tpc_num; + + nvgpu_log_info(g, "addr=0x%x", addr); + + /* The GPC/TPC unicast registers are included in the compressed PRI + * tables. Convert a GPC/TPC broadcast address to unicast addresses so + * that we can look up the offsets. + */ + if (broadcast_flags & PRI_BROADCAST_FLAGS_EGPC) { + nvgpu_log_info(g, "broadcast flags egpc"); + for (gpc_num = 0; gpc_num < g->gr.gpc_count; gpc_num++) { + + if (broadcast_flags & PRI_BROADCAST_FLAGS_ETPC) { + nvgpu_log_info(g, "broadcast flags etpc"); + for (tpc_num = 0; + tpc_num < g->gr.gpc_tpc_count[gpc_num]; + tpc_num++) { + priv_addr_table[*t] = + pri_etpc_addr(g, + pri_tpccs_addr_mask(addr), + gpc_num, tpc_num); + nvgpu_log_info(g, + "priv_addr_table[%d]:%#08x", + *t, priv_addr_table[*t]); + (*t)++; + } + } else { + priv_addr_table[*t] = + pri_egpc_addr(g, + pri_gpccs_addr_mask(addr), + gpc_num); + nvgpu_log_info(g, "priv_addr_table[%d]:%#08x", + *t, priv_addr_table[*t]); + (*t)++; + } + } + } else if (!(broadcast_flags & PRI_BROADCAST_FLAGS_EGPC)) { + if (broadcast_flags & PRI_BROADCAST_FLAGS_ETPC) { + nvgpu_log_info(g, "broadcast flags etpc but not egpc"); + for (tpc_num = 0; + tpc_num < g->gr.gpc_tpc_count[gpc]; + tpc_num++) { + priv_addr_table[*t] = + pri_etpc_addr(g, + pri_tpccs_addr_mask(addr), + gpc, tpc_num); + nvgpu_log_info(g, + "priv_addr_table[%d]:%#08x", + *t, priv_addr_table[*t]); + (*t)++; + } + } else { + priv_addr_table[*t] = addr; + nvgpu_log_info(g, "priv_addr_table[%d]:%#08x", + *t, priv_addr_table[*t]); + (*t)++; + } + } +} + +static u32 gv11b_gr_get_egpc_base(struct gk20a *g) +{ + return EGPC_PRI_BASE; +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3468,4 +3658,10 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs; gops->gr.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs; gops->gr.access_smpc_reg = gv11b_gr_access_smpc_reg; + gops->gr.decode_egpc_addr = gv11b_gr_decode_egpc_addr; + gops->gr.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table; + gops->gr.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num; + gops->gr.get_egpc_base = gv11b_gr_get_egpc_base; + gops->gr.is_egpc_addr = gv11b_gr_pri_is_egpc_addr; + gops->gr.is_etpc_addr = gv11b_gr_pri_is_etpc_addr; } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index e6149b37..0793dae5 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -16,6 +16,9 @@ #ifndef _NVGPU_GR_GV11B_H_ #define _NVGPU_GR_GV11B_H_ +#define EGPC_PRI_BASE 0x580000 +#define EGPC_PRI_SHARED_BASE 0x480000 + #define GV11B_ZBC_TYPE_STENCIL T19X_ZBC #define ZBC_STENCIL_CLEAR_FMT_INVAILD 0 #define ZBC_STENCIL_CLEAR_FMT_U8 1 -- cgit v1.2.2 From 357e3d4d388bef0556239412ab46dd01c3bbac2e Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 18 Jul 2017 15:17:22 -0700 Subject: gpu: nvgpu: gv11b: fix for replay fault addr equal to 0 fault_addr "0" is not supposed to be fixed ever. For the first time when prev = 0, next = 0 and fault addr is also 0 then handle_mmu_fault_common will not be called. Fix by checking fault_addr not equal to 0 Bug 200277163 Change-Id: I532bca54a85e540415b9f5f5e71daec9cf0e0619 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1522653 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 0ec6c9dd..6626344c 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -1075,14 +1075,17 @@ static void gv11b_fb_handle_mmu_nonreplay_replay_fault(struct gk20a *g, struct nvgpu_mem *mem; struct mmu_fault_info *mmfault; u32 invalidate_replay_val = 0; - u64 prev_fault_addr = 0; - u64 next_fault_addr = 0; + u64 prev_fault_addr = 0ULL; + u64 next_fault_addr = 0ULL; if (gv11b_fb_is_fault_buffer_empty(g, index, &get_indx)) { nvgpu_log(g, gpu_dbg_intr, "SPURIOUS mmu fault: reg index:%d", index); return; } + nvgpu_info(g, "%s MMU FAULT" , + index == REPLAY_REG_INDEX ? "REPLAY" : "NON-REPLAY"); + nvgpu_log(g, gpu_dbg_intr, "get ptr = %d", get_indx); mem = &g->mm.hw_fault_buf[index]; @@ -1119,10 +1122,16 @@ static void gv11b_fb_handle_mmu_nonreplay_replay_fault(struct gk20a *g, rd32_val = nvgpu_mem_rd32(g, mem, offset + gmmu_fault_buf_entry_valid_w()); - if (index == REPLAY_REG_INDEX) { + if (index == REPLAY_REG_INDEX && mmfault->fault_addr != 0ULL) { + /* fault_addr "0" is not supposed to be fixed ever. + * For the first time when prev = 0, next = 0 and + * fault addr is also 0 then handle_mmu_fault_common will + * not be called. Fix by checking fault_addr not equal to 0 + */ prev_fault_addr = next_fault_addr; next_fault_addr = mmfault->fault_addr; if (prev_fault_addr == next_fault_addr) { + nvgpu_log(g, gpu_dbg_intr, "pte is fixed"); if (mmfault->refch) gk20a_channel_put(mmfault->refch); /* pte already fixed for this addr */ -- cgit v1.2.2 From 8b571de4563b83352097474c5f7157ea6623a97f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 11 Jul 2017 21:53:00 -0700 Subject: gpu: nvgpu: gv11b: implement init_gpc_mmu - Created HAL to configure gpc mmu unit for gv11b. - Earlier chips needs writes to NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS register to know supported number of LTCS by reading NUM_ACTIVE_LTCS but gv11b support auto update from fuse upon reset, so skipped LTCS update for GPCS & skipping helps to fix compression failure issue. Bug 1950234 Change-Id: I628af7d1399e4fe3126895e3a703a19147f7a12f Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1517733 Reviewed-by: Mahantesh Kumbar Tested-by: Mahantesh Kumbar Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index fab2ae9a..3450bf05 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -45,10 +45,10 @@ #include #include #include -#include #include #include #include +#include static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) { @@ -3568,6 +3568,39 @@ static u32 gv11b_gr_get_egpc_base(struct gk20a *g) return EGPC_PRI_BASE; } +static void gr_gv11b_init_gpc_mmu(struct gk20a *g) +{ + u32 temp; + + nvgpu_log_info(g, "initialize gpc mmu"); + + if (!g->ops.privsecurity) { + /* Bypass MMU check for non-secure boot. For + * secure-boot,this register write has no-effect */ + gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); + } + temp = gk20a_readl(g, fb_mmu_ctrl_r()); + temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | + gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | + gr_gpcs_pri_mmu_ctrl_vol_fault_m() | + gr_gpcs_pri_mmu_ctrl_comp_fault_m() | + gr_gpcs_pri_mmu_ctrl_miss_gran_m() | + gr_gpcs_pri_mmu_ctrl_cache_mode_m() | + gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() | + gr_gpcs_pri_mmu_ctrl_mmu_vol_m() | + gr_gpcs_pri_mmu_ctrl_mmu_disable_m(); + gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp); + gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0); + gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); + + gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), + gk20a_readl(g, fb_mmu_debug_ctrl_r())); + gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(), + gk20a_readl(g, fb_mmu_debug_wr_r())); + gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), + gk20a_readl(g, fb_mmu_debug_rd_r())); +} + void gv11b_init_gr(struct gpu_ops *gops) { gp10b_init_gr(gops); @@ -3664,4 +3697,5 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.get_egpc_base = gv11b_gr_get_egpc_base; gops->gr.is_egpc_addr = gv11b_gr_pri_is_egpc_addr; gops->gr.is_etpc_addr = gv11b_gr_pri_is_etpc_addr; + gops->gr.init_gpc_mmu = gr_gv11b_init_gpc_mmu; } -- cgit v1.2.2 From 3b7d50ee12b7ed93f908338dc321bf71023d4b49 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 5 Jul 2017 15:20:14 -0700 Subject: gpu: nvgpu: gv11b: Reorg css HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the css sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Change-Id: I04177d6c9eb4f3c433d493c815ad15cf7b755910 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514206 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 18cd686e..4f993494 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -235,6 +235,16 @@ static const struct gpu_ops gv11b_ops = { .perfbuffer_enable = gk20a_perfbuf_enable_locked, .perfbuffer_disable = gk20a_perfbuf_disable_locked, }, +#if defined(CONFIG_GK20A_CYCLE_STATS) + .css = { + .enable_snapshot = css_hw_enable_snapshot, + .disable_snapshot = css_hw_disable_snapshot, + .check_data_available = css_hw_check_data_available, + .set_handled_snapshots = css_hw_set_handled_snapshots, + .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, + .release_perfmon_ids = css_gr_release_perfmon_ids, + }, +#endif .falcon = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, @@ -252,6 +262,9 @@ int gv11b_init_hal(struct gk20a *g) gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; +#if defined(CONFIG_GK20A_CYCLE_STATS) + gops->css = gv11b_ops.css; +#endif gops->falcon = gv11b_ops.falcon; /* Lone functions */ @@ -276,9 +289,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); -#if defined(CONFIG_GK20A_CYCLE_STATS) - gk20a_init_css_ops(gops); -#endif + g->name = "gv11b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From e932982853d779b62bc328eb3e9e506dad590f64 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 5 Jul 2017 19:05:45 -0700 Subject: gpu: nvgpu: gv11b: Reorg bus HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the bus sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I469113b204cb693a6b1cbf34a9ca53b62e34ec20 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514661 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/Makefile | 1 - drivers/gpu/nvgpu/gv11b/bus_gv11b.c | 26 -------------------------- drivers/gpu/nvgpu/gv11b/bus_gv11b.h | 21 --------------------- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 9 +++++++-- 4 files changed, 7 insertions(+), 50 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gv11b/bus_gv11b.c delete mode 100644 drivers/gpu/nvgpu/gv11b/bus_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 6fdabe62..7e96dcf3 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -4,7 +4,6 @@ nvgpu-y += \ $(nvgpu-t19x)/common/mm/gmmu_t19x.o \ $(nvgpu-t19x)/common/linux/ioctl_tsg_t19x.o \ $(nvgpu-t19x)/gv11b/gv11b.o \ - $(nvgpu-t19x)/gv11b/bus_gv11b.o \ $(nvgpu-t19x)/gv11b/mc_gv11b.o \ $(nvgpu-t19x)/gv11b/ltc_gv11b.o \ $(nvgpu-t19x)/gv11b/hal_gv11b.o \ diff --git a/drivers/gpu/nvgpu/gv11b/bus_gv11b.c b/drivers/gpu/nvgpu/gv11b/bus_gv11b.c deleted file mode 100644 index 9a70b41c..00000000 --- a/drivers/gpu/nvgpu/gv11b/bus_gv11b.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * GV11B BUS - * - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "bus_gv11b.h" -#include "gk20a/gk20a.h" -#include "gk20a/bus_gk20a.h" - -void gv11b_init_bus(struct gpu_ops *gops) -{ - gops->bus.init_hw = gk20a_bus_init_hw; - gops->bus.isr = gk20a_bus_isr; - gops->bus.read_ptimer = gk20a_read_ptimer; - gops->bus.bar1_bind = NULL; -} diff --git a/drivers/gpu/nvgpu/gv11b/bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/bus_gv11b.h deleted file mode 100644 index fde0b14b..00000000 --- a/drivers/gpu/nvgpu/gv11b/bus_gv11b.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * GV11B BUS - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef BUS_GV11B_H -#define BUS_GV11B_H - -struct gpu_ops; - -void gv11b_init_bus(struct gpu_ops *gops); -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4f993494..51fe6b0a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -35,7 +35,6 @@ #include "gp10b/priv_ring_gp10b.h" #include "hal_gv11b.h" -#include "bus_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" #include "ltc_gv11b.h" @@ -235,6 +234,12 @@ static const struct gpu_ops gv11b_ops = { .perfbuffer_enable = gk20a_perfbuf_enable_locked, .perfbuffer_disable = gk20a_perfbuf_disable_locked, }, + .bus = { + .init_hw = gk20a_bus_init_hw, + .isr = gk20a_bus_isr, + .read_ptimer = gk20a_read_ptimer, + .bar1_bind = NULL, + }, #if defined(CONFIG_GK20A_CYCLE_STATS) .css = { .enable_snapshot = css_hw_enable_snapshot, @@ -262,6 +267,7 @@ int gv11b_init_hal(struct gk20a *g) gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; + gops->bus = gv11b_ops.bus; #if defined(CONFIG_GK20A_CYCLE_STATS) gops->css = gv11b_ops.css; #endif @@ -276,7 +282,6 @@ int gv11b_init_hal(struct gk20a *g) gops->privsecurity = 0; gops->securegpccs = 0; - gv11b_init_bus(gops); gp10b_init_priv_ring(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); -- cgit v1.2.2 From d9f906c1e0f06f54e545727817d227a0bac46a0a Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 28 Jun 2017 17:42:59 -0700 Subject: gpu: nvgpu: gv11b: Reorg priv_ring HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the priv_ring sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Idee9e8a3a5bfa65b350f0e9fb14c4364c4d6f1d2 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514103 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 51fe6b0a..8dc9900a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -253,6 +253,9 @@ static const struct gpu_ops gv11b_ops = { .falcon = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, + .priv_ring = { + .isr = gp10b_priv_ring_isr, + }, .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; @@ -272,6 +275,7 @@ int gv11b_init_hal(struct gk20a *g) gops->css = gv11b_ops.css; #endif gops->falcon = gv11b_ops.falcon; + gops->priv_ring = gv11b_ops.priv_ring; /* Lone functions */ gops->chip_init_gpu_characteristics = @@ -282,7 +286,6 @@ int gv11b_init_hal(struct gk20a *g) gops->privsecurity = 0; gops->securegpccs = 0; - gp10b_init_priv_ring(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); -- cgit v1.2.2 From 8140c51e6cd212517fc343e6f8f8694bbad98f3b Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 30 Jun 2017 15:54:03 -0700 Subject: gpu: nvgpu: gv11b: Reorg fifo HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7c81edfa785a4ecafef41aae7b82d6b1707d294e Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1522554 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 119 ++++++++++------------------------- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 58 ++++++++++++++++- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 76 +++++++++++++++++++++- 3 files changed, 163 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b0270150..e210d40d 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -59,7 +59,7 @@ static inline void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); } -static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) +void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { u32 runlist_entry_0 = ram_rl_entry_type_tsg_v(); @@ -85,7 +85,7 @@ static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) } -static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) +void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) { struct gk20a *g = c->g; u32 addr_lo, addr_hi; @@ -126,7 +126,7 @@ static void gv11b_userd_writeback_config(struct gk20a *g) } -static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, +int channel_gv11b_setup_ramfc(struct channel_gk20a *c, u64 gpfifo_base, u32 gpfifo_entries, unsigned long acquire_timeout, u32 flags) { @@ -219,7 +219,7 @@ static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) usermode_notify_channel_pending_id_f(hw_chid)); } -static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) +u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); @@ -228,7 +228,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) offset + ram_userd_gp_get_w()); } -static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) +u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); @@ -238,7 +238,7 @@ static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) return ((u64)hi << 32) | lo; } -static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) +void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); @@ -251,24 +251,24 @@ static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) gv11b_ring_channel_doorbell(c); } -static void channel_gv11b_unbind(struct channel_gk20a *ch) +void channel_gv11b_unbind(struct channel_gk20a *ch) { gk20a_dbg_fn(""); gk20a_fifo_channel_unbind(ch); } -static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) +u32 gv11b_fifo_get_num_fifos(struct gk20a *g) { return ccsr_channel__size_1_v(); } -static bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) +bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) { return (engine_subid == gmmu_fault_client_type_gpc_v()); } -static void gv11b_dump_channel_status_ramfc(struct gk20a *g, +void gv11b_dump_channel_status_ramfc(struct gk20a *g, struct gk20a_debug_output *o, u32 chid, struct ch_state *ch_state) @@ -322,7 +322,7 @@ static void gv11b_dump_channel_status_ramfc(struct gk20a *g, gk20a_debug_output(o, "\n"); } -static void gv11b_dump_eng_status(struct gk20a *g, +void gv11b_dump_eng_status(struct gk20a *g, struct gk20a_debug_output *o) { u32 i, host_num_engines; @@ -355,7 +355,7 @@ static void gv11b_dump_eng_status(struct gk20a *g, gk20a_debug_output(o, "\n"); } -static u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g) +u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g) { u32 intr_0_error_mask = fifo_intr_0_bind_error_pending_f() | @@ -698,7 +698,7 @@ static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g, return ret; } -static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, +int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type) { struct fifo_gk20a *f = &g->fifo; @@ -747,7 +747,7 @@ static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, return ret; } -static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid) +int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid) { struct fifo_gk20a *f = &g->fifo; u32 tsgid; @@ -784,7 +784,7 @@ static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) return ret; } -static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) +int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) { struct fifo_gk20a *f = &g->fifo; u32 ret = 0; @@ -868,7 +868,7 @@ static int __locked_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, } -static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, +int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type) { struct fifo_gk20a *f = &g->fifo; @@ -906,7 +906,7 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, } -static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, +void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, u32 id, unsigned int id_type, unsigned int rc_type, struct mmu_fault_info *mmfault) { @@ -1058,7 +1058,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, nvgpu_pmu_enable_elpg(g); } -static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) +void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) { /* * These are all errors which indicate something really wrong @@ -1118,7 +1118,7 @@ static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g) return intr_0_en_mask; } -static int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) +int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) { u32 intr_stall; u32 mask; @@ -1232,7 +1232,7 @@ static const char *const gv11b_sched_error_str[] = { "bad_tsg", }; -static bool gv11b_fifo_handle_sched_error(struct gk20a *g) +bool gv11b_fifo_handle_sched_error(struct gk20a *g) { u32 sched_error; @@ -1348,7 +1348,7 @@ static u32 gv11b_fifo_ctxsw_timeout_info(struct gk20a *g, u32 active_eng_id) return tsgid; } -static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) +bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) { bool ret = false; u32 tsgid = FIFO_INVAL_TSG_ID; @@ -1411,7 +1411,7 @@ static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) return ret; } -static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, +unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0, u32 *handled, u32 *error_notifier) { @@ -1460,7 +1460,7 @@ static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, * will have to be destroyed. */ -static unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, +unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1, u32 *handled, u32 *error_notifier) { @@ -1537,7 +1537,7 @@ unsigned int gv11b_fifo_get_eng_method_buffer_size(struct gk20a *g) return buffer_size; } -static void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, +void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, struct tsg_gk20a *tsg) { struct vm_gk20a *vm = g->mm.bar2.vm; @@ -1577,7 +1577,7 @@ static void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, } -static void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, +void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, struct tsg_gk20a *tsg) { struct vm_gk20a *vm = g->mm.bar2.vm; @@ -1596,7 +1596,7 @@ static void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, } #ifdef CONFIG_TEGRA_GK20A_NVHOST -static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, +int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf) { struct page **pages; @@ -1631,14 +1631,14 @@ static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, return err; } -static void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, +void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, struct nvgpu_mem *syncpt_buf) { nvgpu_gmmu_unmap(c->vm, syncpt_buf, syncpt_buf->gpu_va); nvgpu_dma_free(c->g, syncpt_buf); } -static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, +void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, struct priv_cmd_entry *cmd, u32 off, u32 id, u32 thresh, u64 gpu_va_base) { @@ -1668,12 +1668,12 @@ static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12)); } -static u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) +u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) { return 8; } -static void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, +void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, bool wfi_cmd, struct priv_cmd_entry *cmd, u32 id, u64 gpu_va_base) { @@ -1706,13 +1706,13 @@ static void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, nvgpu_mem_wr32(g, cmd->mem, off++, 0); } -static u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) +u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) { return 9; } #endif /* CONFIG_TEGRA_GK20A_NVHOST */ -static int gv11b_init_fifo_setup_hw(struct gk20a *g) +int gv11b_init_fifo_setup_hw(struct gk20a *g) { struct fifo_gk20a *f = &g->fifo; @@ -1790,58 +1790,3 @@ void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, else *pbdma_id = FIFO_INVAL_PBDMA_ID; } - -void gv11b_init_fifo(struct gpu_ops *gops) -{ - gp10b_init_fifo(gops); - /* for gv11b no need to do any thing special for fifo hw setup */ - gops->fifo.init_fifo_setup_hw = gv11b_init_fifo_setup_hw; - gops->fifo.runlist_entry_size = ram_rl_entry_size_v; - gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry; - gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry; - gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos; - gops->fifo.userd_gp_get = gv11b_userd_gp_get; - gops->fifo.userd_gp_put = gv11b_userd_gp_put; - gops->fifo.userd_pb_get = gv11b_userd_pb_get; - gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; - gops->fifo.resetup_ramfc = NULL; - gops->fifo.unbind_channel = channel_gv11b_unbind; - gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; - gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; - gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; - gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; - gops->fifo.trigger_mmu_fault = NULL; - gops->fifo.get_mmu_fault_info = NULL; - gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; - gops->fifo.dump_eng_status = gv11b_dump_eng_status; - gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; - gops->fifo.intr_0_error_mask = gv11b_fifo_intr_0_error_mask; - gops->fifo.preempt_channel = gv11b_fifo_preempt_channel; - gops->fifo.preempt_tsg = gv11b_fifo_preempt_tsg; - gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending; - gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; - gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; - gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw; - gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg; - gops->fifo.handle_sched_error = gv11b_fifo_handle_sched_error; - gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; - gops->fifo.handle_pbdma_intr_0 = - gv11b_fifo_handle_pbdma_intr_0; - gops->fifo.handle_pbdma_intr_1 = - gv11b_fifo_handle_pbdma_intr_1; - gops->fifo.init_eng_method_buffers = - gv11b_fifo_init_eng_method_buffers; - gops->fifo.deinit_eng_method_buffers = - gv11b_fifo_deinit_eng_method_buffers; -#ifdef CONFIG_TEGRA_GK20A_NVHOST - gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf; - gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf; - gops->fifo.add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd; - gops->fifo.get_syncpt_wait_cmd_size = - gv11b_fifo_get_syncpt_wait_cmd_size; - gops->fifo.add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd; - gops->fifo.get_syncpt_incr_cmd_size = - gv11b_fifo_get_syncpt_incr_cmd_size; -#endif - -} diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 8a2b32f8..3fb2f6e9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -40,10 +40,66 @@ #define CHANNEL_INFO_VEID0 0 struct gpu_ops; -void gv11b_init_fifo(struct gpu_ops *gops); + void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, struct channel_gk20a *refch, u32 faulted_pbdma, u32 faulted_engine); void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id); + +void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist); +void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist); +int channel_gv11b_setup_ramfc(struct channel_gk20a *c, + u64 gpfifo_base, u32 gpfifo_entries, + unsigned long acquire_timeout, u32 flags); +u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c); +u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c); +void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c); +void channel_gv11b_unbind(struct channel_gk20a *ch); +u32 gv11b_fifo_get_num_fifos(struct gk20a *g); +bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid); +void gv11b_dump_channel_status_ramfc(struct gk20a *g, + struct gk20a_debug_output *o, + u32 chid, + struct ch_state *ch_state); +void gv11b_dump_eng_status(struct gk20a *g, + struct gk20a_debug_output *o); +u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g); +int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, + unsigned int id_type, unsigned int timeout_rc_type); +int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid); +int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); +int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, + unsigned int id_type, unsigned int timeout_rc_type); +void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, + u32 id, unsigned int id_type, unsigned int rc_type, + struct mmu_fault_info *mmfault); +void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); +int gv11b_init_fifo_reset_enable_hw(struct gk20a *g); +bool gv11b_fifo_handle_sched_error(struct gk20a *g); +bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr); +unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_0, + u32 *handled, u32 *error_notifier); +unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_1, + u32 *handled, u32 *error_notifier); +void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, + struct tsg_gk20a *tsg); +void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, + struct tsg_gk20a *tsg); +int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf); +void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, + struct nvgpu_mem *syncpt_buf); +void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, + struct priv_cmd_entry *cmd, u32 off, + u32 id, u32 thresh, u64 gpu_va_base); +u32 gv11b_fifo_get_syncpt_wait_cmd_size(void); +void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, + bool wfi_cmd, struct priv_cmd_entry *cmd, + u32 id, u64 gpu_va_base); +u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); +int gv11b_init_fifo_setup_hw(struct gk20a *g); + #endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 8dc9900a..b6c17c7d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -20,6 +20,7 @@ #include #include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" @@ -29,10 +30,12 @@ #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" +#include "gm20b/fifo_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/priv_ring_gp10b.h" +#include "gp10b/fifo_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -49,10 +52,14 @@ #include "fifo_gv11b.h" #include "gv11b_gating_reglist.h" #include "regops_gv11b.h" +#include "subctx_gv11b.h" #include #include +#include +#include +#include static int gv11b_get_litter_value(struct gk20a *g, int value) { @@ -202,6 +209,72 @@ static const struct gpu_ops gv11b_ops = { .pg_gr_load_gating_prod = gr_gv11b_pg_gr_load_gating_prod, }, + .fifo = { + .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, + .bind_channel = channel_gm20b_bind, + .unbind_channel = channel_gv11b_unbind, + .disable_channel = gk20a_fifo_disable_channel, + .enable_channel = gk20a_fifo_enable_channel, + .alloc_inst = gk20a_fifo_alloc_inst, + .free_inst = gk20a_fifo_free_inst, + .setup_ramfc = channel_gv11b_setup_ramfc, + .channel_set_priority = gk20a_fifo_set_priority, + .channel_set_timeslice = gk20a_fifo_set_timeslice, + .default_timeslice_us = gk20a_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gv11b_userd_gp_get, + .userd_gp_put = gv11b_userd_gp_put, + .userd_pb_get = gv11b_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = gv11b_fifo_preempt_channel, + .preempt_tsg = gv11b_fifo_preempt_tsg, + .update_runlist = gk20a_fifo_update_runlist, + .trigger_mmu_fault = NULL, + .get_mmu_fault_info = NULL, + .wait_engine_idle = gk20a_fifo_wait_engine_idle, + .get_num_fifos = gv11b_fifo_get_num_fifos, + .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, + .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, + .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, + .force_reset_ch = gk20a_fifo_force_reset_ch, + .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, + .device_info_data_parse = gp10b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = gk20a_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, + .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gv11b_dump_eng_status, + .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, + .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, + .is_preempt_pending = gv11b_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, + .handle_sched_error = gv11b_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, + .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, + .deinit_eng_method_buffers = + gv11b_fifo_deinit_eng_method_buffers, + .tsg_bind_channel = gk20a_tsg_bind_channel, + .tsg_unbind_channel = gk20a_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, +#endif + .resetup_ramfc = NULL, + .device_info_fault_id = top_device_info_data_fault_id_enum_v, + .free_channel_ctx_header = gv11b_free_subctx_header, + .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -267,6 +340,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; + gops->fifo = gv11b_ops.fifo; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; @@ -289,14 +363,12 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); - gv11b_init_fifo(gops); gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(gops); gv11b_init_regops(gops); gv11b_init_therm_ops(gops); - gk20a_init_tsg_ops(gops); g->name = "gv11b"; -- cgit v1.2.2 From a5d6970df79ab712a7db76e7a02bceaa590ae1d9 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 28 Jun 2017 14:17:59 -0700 Subject: gpu: nvgpu: gv11b: Remove securegpccs from gpu_ops Replace securegpccs boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_SECUREGPCCS Jira NVGPU-74 Change-Id: I487aa5e8545027a3b5bbe33ce68b2715cc2eb39a Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514096 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index b6c17c7d..2c20bd04 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -55,6 +55,7 @@ #include "subctx_gv11b.h" #include +#include #include #include @@ -358,7 +359,7 @@ int gv11b_init_hal(struct gk20a *g) /* boot in non-secure modes for time beeing */ gops->privsecurity = 0; - gops->securegpccs = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); -- cgit v1.2.2 From 2b98e1308d49b9c941d8fa6fc87f67108d6d9370 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 24 Jul 2017 12:19:53 -0700 Subject: gpu: nvgpu: gv11b: Remove privsecurity from gpu_ops Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4c11e3a89a76abe137cf61b69ad0fbcd665554b7 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1525714 Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 9 ++++++--- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 4 ++-- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 6 +++--- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 7 +++++-- drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 6 ++++-- 5 files changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 3450bf05..1ba0c523 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" @@ -3574,7 +3575,7 @@ static void gr_gv11b_init_gpc_mmu(struct gk20a *g) nvgpu_log_info(g, "initialize gpc mmu"); - if (!g->ops.privsecurity) { + if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { /* Bypass MMU check for non-secure boot. For * secure-boot,this register write has no-effect */ gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); @@ -3601,9 +3602,11 @@ static void gr_gv11b_init_gpc_mmu(struct gk20a *g) gk20a_readl(g, fb_mmu_debug_rd_r())); } -void gv11b_init_gr(struct gpu_ops *gops) +void gv11b_init_gr(struct gk20a *g) { - gp10b_init_gr(gops); + struct gpu_ops *gops = &g->ops; + + gp10b_init_gr(g); gops->gr.init_preemption_state = NULL; gops->gr.init_fs_state = gr_gv11b_init_fs_state; gops->gr.detect_sm_arch = gr_gv11b_detect_sm_arch; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 0793dae5..69148554 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -29,7 +29,7 @@ struct zbc_s_table { u32 ref_cnt; }; -struct gpu_ops; +struct gk20a; enum { VOLTA_CHANNEL_GPFIFO_A = 0xC36F, @@ -59,7 +59,7 @@ enum { #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 -void gv11b_init_gr(struct gpu_ops *ops); +void gv11b_init_gr(struct gk20a *g); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct nvgpu_mem *mem); /*zcull*/ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2c20bd04..3ebeb205 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -358,16 +358,16 @@ int gv11b_init_hal(struct gk20a *g) gops->get_litter_value = gv11b_ops.get_litter_value; /* boot in non-secure modes for time beeing */ - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - gv11b_init_gr(gops); + gv11b_init_gr(g); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); - gv11b_init_pmu_ops(gops); + gv11b_init_pmu_ops(g); gv11b_init_regops(gops); gv11b_init_therm_ops(gops); diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index d20b9c1a..35719dff 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -20,6 +20,7 @@ #include #include +#include #include "gk20a/gk20a.h" @@ -234,9 +235,11 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) return 0; } -void gv11b_init_pmu_ops(struct gpu_ops *gops) +void gv11b_init_pmu_ops(struct gk20a *g) { - gp10b_init_pmu_ops(gops); + struct gpu_ops *gops = &g->ops; + + gp10b_init_pmu_ops(g); gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; gops->pmu.reset_engine = gp106_pmu_engine_reset; diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h index c99923e7..ce10c4cb 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h @@ -1,7 +1,7 @@ /* * GV11B PMU * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,6 +16,8 @@ #ifndef __PMU_GV11B_H_ #define __PMU_GV11B_H_ -void gv11b_init_pmu_ops(struct gpu_ops *gops); +struct gk20a; + +void gv11b_init_pmu_ops(struct gk20a *g); #endif /*__PMU_GV11B_H_*/ -- cgit v1.2.2 From 3c556c5e9573ffa69bfe64ed1401ed4a9141acb3 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 27 Jun 2017 15:09:58 -0700 Subject: gpu: nvgpu: gv11b: Reorg ce2 HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ce2 sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ia2d715a471d7e23420691a461e9442780176ea13 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1509633 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 11 ++--------- drivers/gpu/nvgpu/gv11b/ce_gv11b.h | 5 +++-- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 8 +++++++- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 9716c6d6..8bf636b1 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -28,7 +28,7 @@ #include #include -static u32 gv11b_ce_get_num_pce(struct gk20a *g) +u32 gv11b_ce_get_num_pce(struct gk20a *g) { /* register contains a bitmask indicating which physical copy * engines are present (and not floorswept). @@ -41,7 +41,7 @@ static u32 gv11b_ce_get_num_pce(struct gk20a *g) return num_pce; } -static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) { u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); u32 clear_intr = 0; @@ -102,10 +102,3 @@ void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) } } } - -void gv11b_init_ce(struct gpu_ops *gops) -{ - gp10b_init_ce(gops); - gops->ce2.isr_stall = gv11b_ce_isr; - gops->ce2.get_num_pce = gv11b_ce_get_num_pce; -} diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h index 23053199..ce60ad3e 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h @@ -19,10 +19,11 @@ #ifndef __CE_GV11B_H__ #define __CE_GV11B_H__ -struct gpu_ops; +struct gk20a; -void gv11b_init_ce(struct gpu_ops *gops); void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g); u32 gv11b_ce_get_num_lce(struct gk20a *g); +u32 gv11b_ce_get_num_pce(struct gk20a *g); +void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base); #endif /*__CE2_GV11B_H__*/ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 3ebeb205..e585e9b1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -34,6 +34,7 @@ #include "gp10b/ltc_gp10b.h" #include "gp10b/mc_gp10b.h" +#include "gp10b/ce_gp10b.h" #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" @@ -160,6 +161,11 @@ static const struct gpu_ops gv11b_ops = { .sync_debugfs = gp10b_ltc_sync_debugfs, #endif }, + .ce2 = { + .isr_stall = gv11b_ce_isr, + .isr_nonstall = gp10b_ce_nonstall_isr, + .get_num_pce = gv11b_ce_get_num_pce, + }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, @@ -340,6 +346,7 @@ int gv11b_init_hal(struct gk20a *g) struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; gops->ltc = gv11b_ops.ltc; + gops->ce2 = gv11b_ops.ce2; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->mc = gv11b_ops.mc; @@ -364,7 +371,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_gr(g); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); - gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); -- cgit v1.2.2 From afa29933e45b2c3054db67065a0a68606bbc1f52 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 10:45:38 -0700 Subject: gpu: nvgpu: gv11b: Reorg gr_ctx HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr_ctx sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Icc6b0f968f2e3209de190d445c878a4b20bfcf4a Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1527418 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c | 12 +++--------- drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h | 3 ++- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 7 ++++++- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c index 6cb42baa..920e4c16 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c @@ -2,7 +2,7 @@ * * GV11B Graphics Context * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -22,7 +22,7 @@ #include "gr_ctx_gv11b.h" -static int gr_gv11b_get_netlist_name(struct gk20a *g, int index, char *name) +int gr_gv11b_get_netlist_name(struct gk20a *g, int index, char *name) { switch (index) { #ifdef GV11B_NETLIST_IMAGE_FW_NAME @@ -57,7 +57,7 @@ static int gr_gv11b_get_netlist_name(struct gk20a *g, int index, char *name) return -1; } -static bool gr_gv11b_is_firmware_defined(void) +bool gr_gv11b_is_firmware_defined(void) { #ifdef GV11B_NETLIST_IMAGE_FW_NAME return true; @@ -65,9 +65,3 @@ static bool gr_gv11b_is_firmware_defined(void) return false; #endif } - -void gv11b_init_gr_ctx(struct gpu_ops *gops) { - gops->gr_ctx.get_netlist_name = gr_gv11b_get_netlist_name; - gops->gr_ctx.is_fw_defined = gr_gv11b_is_firmware_defined; - gops->gr_ctx.use_dma_for_fw_bootstrap = false; -} diff --git a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h index 0a046eb4..8feb15fd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h @@ -25,6 +25,7 @@ * Define netlist for silicon only * #define GV11B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A */ -void gv11b_init_gr_ctx(struct gpu_ops *gops); +int gr_gv11b_get_netlist_name(struct gk20a *g, int index, char *name); +bool gr_gv11b_is_firmware_defined(void); #endif /*__GR_CTX_GV11B_H__*/ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e585e9b1..f5191da7 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -282,6 +282,10 @@ static const struct gpu_ops gv11b_ops = { .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, }, + .gr_ctx = { + .get_netlist_name = gr_gv11b_get_netlist_name, + .is_fw_defined = gr_gv11b_is_firmware_defined, + }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -349,6 +353,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ce2 = gv11b_ops.ce2; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; + gops->gr_ctx = gv11b_ops.gr_ctx; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; @@ -365,13 +370,13 @@ int gv11b_init_hal(struct gk20a *g) gops->get_litter_value = gv11b_ops.get_litter_value; /* boot in non-secure modes for time beeing */ + __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); - gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_regops(gops); -- cgit v1.2.2 From 8aa0370005a81a7e26ae7c86585626d3261aa4d3 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 11:14:21 -0700 Subject: gpu: nvgpu: gv11b: Reorg fecs_trace HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fecs_trace sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43932a8eac2a9f791e967a8ed736f76350889a51 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1527420 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 1 - drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c | 31 ------------------------------ drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h | 23 ---------------------- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 24 +++++++++++++++++++++-- 4 files changed, 22 insertions(+), 57 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c delete mode 100644 drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 7e96dcf3..4b0aa321 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -9,7 +9,6 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/hal_gv11b.o \ $(nvgpu-t19x)/gv11b/gv11b_gating_reglist.o \ $(nvgpu-t19x)/gv11b/gr_gv11b.o \ - $(nvgpu-t19x)/gv11b/fecs_trace_gv11b.o \ $(nvgpu-t19x)/gv11b/fb_gv11b.o \ $(nvgpu-t19x)/gv11b/fifo_gv11b.o \ $(nvgpu-t19x)/gv11b/mm_gv11b.o \ diff --git a/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c b/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c deleted file mode 100644 index 92357980..00000000 --- a/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * GV11B GPU FECS traces - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "gp10b/fecs_trace_gp10b.h" - -#include "gv11b/fecs_trace_gv11b.h" - -#ifdef CONFIG_GK20A_CTXSW_TRACE -int gv11b_init_fecs_trace_ops(struct gpu_ops *ops) -{ - gp10b_init_fecs_trace_ops(ops); - return 0; -} -#else -int gv11b_init_fecs_trace_ops(struct gpu_ops *ops) -{ - return 0; -} -#endif /* CONFIG_GK20A_CTXSW_TRACE */ diff --git a/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h b/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h deleted file mode 100644 index 607d715b..00000000 --- a/drivers/gpu/nvgpu/gv11b/fecs_trace_gv11b.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * GV11B GPU FECS traces - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _NVGPU_FECS_TRACE_GV11B_H_ -#define _NVGPU_FECS_TRACE_GV11B_H_ - -struct gpu_ops; - -int gv11b_init_fecs_trace_ops(struct gpu_ops *); - -#endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f5191da7..04712409 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -21,6 +21,8 @@ #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" +#include "gk20a/ctxsw_trace_gk20a.h" +#include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" @@ -37,12 +39,12 @@ #include "gp10b/ce_gp10b.h" #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" +#include "gp10b/fecs_trace_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" #include "ltc_gv11b.h" -#include "fecs_trace_gv11b.h" #include "gv11b.h" #include "ce_gv11b.h" #include "gr_ctx_gv11b.h" @@ -286,6 +288,24 @@ static const struct gpu_ops gv11b_ops = { .get_netlist_name = gr_gv11b_get_netlist_name, .is_fw_defined = gr_gv11b_is_firmware_defined, }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, + .free_user_buffer = gk20a_ctxsw_dev_ring_free, + .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, + .init = gk20a_fecs_trace_init, + .deinit = gk20a_fecs_trace_deinit, + .enable = gk20a_fecs_trace_enable, + .disable = gk20a_fecs_trace_disable, + .is_enabled = gk20a_fecs_trace_is_enabled, + .reset = gk20a_fecs_trace_reset, + .flush = gp10b_fecs_trace_flush, + .poll = gk20a_fecs_trace_poll, + .bind_channel = gk20a_fecs_trace_bind_channel, + .unbind_channel = gk20a_fecs_trace_unbind_channel, + .max_entries = gk20a_gr_max_entries, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -354,6 +374,7 @@ int gv11b_init_hal(struct gk20a *g) gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; + gops->fecs_trace = gv11b_ops.fecs_trace; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; @@ -375,7 +396,6 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); -- cgit v1.2.2 From f457e808f0d1097cec02a022eb42c77a075ef881 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 18:09:07 -0700 Subject: gpu: nvgpu: gv11b: Reorg therm HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the therm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic297792c4d47ffbe64cc0bd95a659a6b7f383743 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1527423 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 1 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 8 ++++++-- drivers/gpu/nvgpu/gv11b/therm_gv11b.c | 25 ------------------------- drivers/gpu/nvgpu/gv11b/therm_gv11b.h | 19 ------------------- 4 files changed, 6 insertions(+), 47 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gv11b/therm_gv11b.c delete mode 100644 drivers/gpu/nvgpu/gv11b/therm_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 4b0aa321..1d2feba4 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -15,7 +15,6 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/ce_gv11b.o \ $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \ $(nvgpu-t19x)/gv11b/pmu_gv11b.o \ - $(nvgpu-t19x)/gv11b/therm_gv11b.o \ $(nvgpu-t19x)/gv11b/subctx_gv11b.o \ $(nvgpu-t19x)/gv11b/regops_gv11b.o diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 04712409..f6121f94 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -35,6 +35,7 @@ #include "gm20b/fifo_gm20b.h" #include "gp10b/ltc_gp10b.h" +#include "gp10b/therm_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/ce_gp10b.h" #include "gp10b/priv_ring_gp10b.h" @@ -50,7 +51,6 @@ #include "gr_ctx_gv11b.h" #include "mm_gv11b.h" #include "pmu_gv11b.h" -#include "therm_gv11b.h" #include "fb_gv11b.h" #include "fifo_gv11b.h" #include "gv11b_gating_reglist.h" @@ -306,6 +306,10 @@ static const struct gpu_ops gv11b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .therm = { + .init_therm_setup_hw = gp10b_init_therm_setup_hw, + .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, + }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -375,6 +379,7 @@ int gv11b_init_hal(struct gk20a *g) gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; gops->fecs_trace = gv11b_ops.fecs_trace; + gops->therm = gv11b_ops.therm; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; @@ -400,7 +405,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_regops(gops); - gv11b_init_therm_ops(gops); g->name = "gv11b"; diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.c b/drivers/gpu/nvgpu/gv11b/therm_gv11b.c deleted file mode 100644 index 89520ead..00000000 --- a/drivers/gpu/nvgpu/gv11b/therm_gv11b.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * GV11B Therm - * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "gk20a/gk20a.h" - -#include "gp10b/therm_gp10b.h" - -#include "therm_gv11b.h" - -void gv11b_init_therm_ops(struct gpu_ops *gops) -{ - gp10b_init_therm_ops(gops); -} diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/therm_gv11b.h deleted file mode 100644 index 2710285a..00000000 --- a/drivers/gpu/nvgpu/gv11b/therm_gv11b.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef THERM_GV11B_H -#define THERM_GV11B_H - -struct gpu_ops; -void gv11b_init_therm_ops(struct gpu_ops *gops); - -#endif /* THERM_GV11B_H */ -- cgit v1.2.2 From b859393ffee2b9e29fd3a18f6fc78594fed7eda1 Mon Sep 17 00:00:00 2001 From: Sandarbh Jain Date: Thu, 27 Jul 2017 00:43:37 -0700 Subject: gpu: nvgpu: gv11b: fix no_of_sm Number of sm is being reported incorrectly. This is because we are not taking into account that each TPC have 2 sm. Bug 1951026 Change-Id: I7c666aa2a0470a14aad29ab1a80ae9d23958a743 Signed-off-by: Sandarbh Jain Reviewed-on: https://git-master.nvidia.com/r/1527771 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Lewkowicz Tested-by: Alexander Lewkowicz Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 1ba0c523..850315f7 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2113,24 +2113,29 @@ static void gr_gv11b_detect_sm_arch(struct gk20a *g) static void gr_gv11b_init_sm_id_table(struct gk20a *g) { - u32 gpc, tpc; + u32 gpc, tpc, sm; u32 sm_id = 0; + u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); /* TODO populate smids based on power efficiency */ for (tpc = 0; tpc < g->gr.max_tpc_per_gpc_count; tpc++) { for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { - if (tpc < g->gr.gpc_tpc_count[gpc]) { + if (tpc >= g->gr.gpc_tpc_count[gpc]) + continue; + + for (sm = 0; sm < sm_per_tpc; sm++) { g->gr.sm_to_cluster[sm_id].tpc_index = tpc; g->gr.sm_to_cluster[sm_id].gpc_index = gpc; g->gr.sm_to_cluster[sm_id].sm_index = sm_id % 2; g->gr.sm_to_cluster[sm_id].global_tpc_index = - sm_id; + tpc; sm_id++; } } } g->gr.no_of_sm = sm_id; + nvgpu_log_info(g, " total number of sm = %d", g->gr.no_of_sm); } static void gr_gv11b_program_sm_id_numbering(struct gk20a *g, @@ -2156,7 +2161,7 @@ static int gr_gv11b_load_smid_config(struct gk20a *g) u32 *tpc_sm_id; u32 i, j; u32 tpc_index, gpc_index, tpc_id; - u32 sms_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); + u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); int num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); tpc_sm_id = kcalloc(gr_cwd_sm_id__size_1_v(), sizeof(u32), GFP_KERNEL); @@ -2174,7 +2179,7 @@ static int gr_gv11b_load_smid_config(struct gk20a *g) u32 bits; tpc_id = (i << 2) + j; - sm_id = tpc_id * sms_per_tpc; + sm_id = tpc_id * sm_per_tpc; if (sm_id >= g->gr.no_of_sm) break; -- cgit v1.2.2 From 7c2b4d70ec98f9da123744ffddb413a606cbbd2b Mon Sep 17 00:00:00 2001 From: Ashish Srivastava Date: Thu, 27 Jul 2017 18:59:03 +0530 Subject: gpu: nvgpu: gv11b: fix get ptr update for mmu fault buffer Skipping the last entry makes get ptr 0. This causes HW to think that buffer overflow has happened, but it really hasn't. Due to this issue no further progress is possible as all FB entries beyond get ptr are invalid. Bug 200300788 Change-Id: I7373dfa087cdb7c307aacacf62ef4ca8a0214cf2 Signed-off-by: Ashish Srivastava Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1528070 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 6626344c..fd63e9ff 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -1107,11 +1107,7 @@ static void gv11b_fb_handle_mmu_nonreplay_replay_fault(struct gk20a *g, gv11b_fb_copy_from_hw_fault_buf(g, mem, offset, mmfault); - /* Extra 1 in buffer size is to detect buffer full. - * Actual number of entries for faults to be snapped are - * one less than number in fault_buffer_size_val - */ - get_indx = (get_indx + 1) % (entries - 1); + get_indx = (get_indx + 1) % entries; nvgpu_log(g, gpu_dbg_intr, "new get index = %d", get_indx); gv11b_fb_fault_buffer_get_ptr_update(g, index, get_indx); -- cgit v1.2.2 From ea381959d973f013a2a2b2ae6fe694f1f569683c Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 31 Jul 2017 13:09:06 +0530 Subject: gpu: nvgpu: fix L3 alloc bit Last minute rebase of commit afa31cdd8cc6bb04faeed30b2cc30f5e6be888b5 on top of reworked memory infrastucture introduced a bug where we actually need to set BIT(36) in physical address but we ended up ORing the address by "36" Fix this by by adding correct value BIT(36) instead of 36 Jira GPUT19X-10 Bug 200279508 Change-Id: Ib587849c75f57dda5ad802b8389b7563b8b690ed Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1529511 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 9430f576..9be8352a 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -32,7 +32,7 @@ #include #include -#define NVGPU_L3_ALLOC_BIT 36 +#define NVGPU_L3_ALLOC_BIT BIT(36) static bool gv11b_mm_is_bar1_supported(struct gk20a *g) { -- cgit v1.2.2 From f87007829f176baa5d3e784c71f3bceb082a29eb Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 28 Jul 2017 18:37:49 -0700 Subject: gpu: nvgpu: gv11b: Reorg regops HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the regops sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ibf9f64ca445691e252b72c2b8fc59edb84e226ce Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1530136 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Tested-by: Alex Waterman Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 25 +++++++++++++- drivers/gpu/nvgpu/gv11b/regops_gv11b.c | 63 +++++++--------------------------- drivers/gpu/nvgpu/gv11b/regops_gv11b.h | 14 +++++++- 3 files changed, 50 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f6121f94..963f78c6 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -310,6 +310,29 @@ static const struct gpu_ops gv11b_ops = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, }, + .regops = { + .get_global_whitelist_ranges = + gv11b_get_global_whitelist_ranges, + .get_global_whitelist_ranges_count = + gv11b_get_global_whitelist_ranges_count, + .get_context_whitelist_ranges = + gv11b_get_context_whitelist_ranges, + .get_context_whitelist_ranges_count = + gv11b_get_context_whitelist_ranges_count, + .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist, + .get_runcontrol_whitelist_count = + gv11b_get_runcontrol_whitelist_count, + .get_runcontrol_whitelist_ranges = + gv11b_get_runcontrol_whitelist_ranges, + .get_runcontrol_whitelist_ranges_count = + gv11b_get_runcontrol_whitelist_ranges_count, + .get_qctl_whitelist = gv11b_get_qctl_whitelist, + .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count, + .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges, + .get_qctl_whitelist_ranges_count = + gv11b_get_qctl_whitelist_ranges_count, + .apply_smpc_war = gv11b_apply_smpc_war, + }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -380,6 +403,7 @@ int gv11b_init_hal(struct gk20a *g) gops->gr_ctx = gv11b_ops.gr_ctx; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; + gops->regops = gv11b_ops.regops; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; @@ -404,7 +428,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_fb(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); - gv11b_init_regops(gops); g->name = "gv11b"; diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c index 75923b6a..5e98f9f1 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c @@ -1327,105 +1327,68 @@ static const struct regop_offset_range gv11b_qctl_whitelist_ranges[] = { static const u32 gv11b_qctl_whitelist_ranges_count = ARRAY_SIZE(gv11b_qctl_whitelist_ranges); -static const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void) +const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void) { return gv11b_global_whitelist_ranges; } -static int gv11b_get_global_whitelist_ranges_count(void) +int gv11b_get_global_whitelist_ranges_count(void) { return gv11b_global_whitelist_ranges_count; } -static const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void) +const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void) { return gv11b_global_whitelist_ranges; } -static int gv11b_get_context_whitelist_ranges_count(void) +int gv11b_get_context_whitelist_ranges_count(void) { return gv11b_global_whitelist_ranges_count; } -static const u32 *gv11b_get_runcontrol_whitelist(void) +const u32 *gv11b_get_runcontrol_whitelist(void) { return gv11b_runcontrol_whitelist; } -static int gv11b_get_runcontrol_whitelist_count(void) +int gv11b_get_runcontrol_whitelist_count(void) { return gv11b_runcontrol_whitelist_count; } -static const -struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void) +const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void) { return gv11b_runcontrol_whitelist_ranges; } -static int gv11b_get_runcontrol_whitelist_ranges_count(void) +int gv11b_get_runcontrol_whitelist_ranges_count(void) { return gv11b_runcontrol_whitelist_ranges_count; } -static const u32 *gv11b_get_qctl_whitelist(void) +const u32 *gv11b_get_qctl_whitelist(void) { return gv11b_qctl_whitelist; } -static int gv11b_get_qctl_whitelist_count(void) +int gv11b_get_qctl_whitelist_count(void) { return gv11b_qctl_whitelist_count; } -static const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void) +const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void) { return gv11b_qctl_whitelist_ranges; } -static int gv11b_get_qctl_whitelist_ranges_count(void) +int gv11b_get_qctl_whitelist_ranges_count(void) { return gv11b_qctl_whitelist_ranges_count; } -static int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) +int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) { /* Not needed on gv11b */ return 0; } - -void gv11b_init_regops(struct gpu_ops *gops) -{ - gops->regops.get_global_whitelist_ranges = - gv11b_get_global_whitelist_ranges; - gops->regops.get_global_whitelist_ranges_count = - gv11b_get_global_whitelist_ranges_count; - - gops->regops.get_context_whitelist_ranges = - gv11b_get_context_whitelist_ranges; - gops->regops.get_context_whitelist_ranges_count = - gv11b_get_context_whitelist_ranges_count; - - gops->regops.get_runcontrol_whitelist = - gv11b_get_runcontrol_whitelist; - gops->regops.get_runcontrol_whitelist_count = - gv11b_get_runcontrol_whitelist_count; - - gops->regops.get_runcontrol_whitelist_ranges = - gv11b_get_runcontrol_whitelist_ranges; - gops->regops.get_runcontrol_whitelist_ranges_count = - gv11b_get_runcontrol_whitelist_ranges_count; - - gops->regops.get_qctl_whitelist = - gv11b_get_qctl_whitelist; - gops->regops.get_qctl_whitelist_count = - gv11b_get_qctl_whitelist_count; - - gops->regops.get_qctl_whitelist_ranges = - gv11b_get_qctl_whitelist_ranges; - gops->regops.get_qctl_whitelist_ranges_count = - gv11b_get_qctl_whitelist_ranges_count; - - gops->regops.apply_smpc_war = - gv11b_apply_smpc_war; -} diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h index b7250818..dada9a7e 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h @@ -19,6 +19,18 @@ #ifndef __REGOPS_GV11B_H_ #define __REGOPS_GV11B_H_ -void gv11b_init_regops(struct gpu_ops *gops); +const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void); +int gv11b_get_global_whitelist_ranges_count(void); +const struct regop_offset_range *gv11b_get_context_whitelist_ranges(void); +int gv11b_get_context_whitelist_ranges_count(void); +const u32 *gv11b_get_runcontrol_whitelist(void); +int gv11b_get_runcontrol_whitelist_count(void); +const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void); +int gv11b_get_runcontrol_whitelist_ranges_count(void); +const u32 *gv11b_get_qctl_whitelist(void); +int gv11b_get_qctl_whitelist_count(void); +const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void); +int gv11b_get_qctl_whitelist_ranges_count(void); +int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s); #endif /* __REGOPS_GV11B_H_ */ -- cgit v1.2.2 From 3e3c1920404ddec1ddbcf8adad93067f384a3e59 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 27 Jul 2017 13:00:46 -0700 Subject: gpu: nvgpu: gv11b: Make LTC disabling common code Refactor the sync_debugfs LTC HAL op so that the logic to enable or disable LTC goes to common code nvgpu_ltc_sync_enabled() and the LTC HAL set_enabled only performs the hardware register access. Create a new common function nvgpu_init_ltc_support() to initialize the LTC software variable, and move hardware initialization of LTC to be called from it. JIRA NVGPU-62 Change-Id: I7b73625bccd45aefa5694989adbf4a0bbac75fc4 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1529054 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 963f78c6..12ec4841 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -159,9 +159,7 @@ static const struct gpu_ops gv11b_ops = { .isr = gv11b_ltc_isr, .cbc_fix_config = gv11b_ltc_cbc_fix_config, .flush = gm20b_flush_ltc, -#ifdef CONFIG_DEBUG_FS - .sync_debugfs = gp10b_ltc_sync_debugfs, -#endif + .set_enabled = gp10b_ltc_set_enabled, }, .ce2 = { .isr_stall = gv11b_ce_isr, -- cgit v1.2.2 From 5a5792d911d99a08663c59f74c552883804780f3 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 8 Jun 2017 15:05:19 -0700 Subject: gpu: nvgpu: Remove mm.get_iova_addr Volta changes for equivalent change on nvgpu. JIRA NVGPU-30 Change-Id: I78e84ce67468dfe3556232ddb25e824f6b84835c Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1530863 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 4 ++-- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 7 ++++--- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 3 ++- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index fd63e9ff..51ee55f8 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -101,8 +101,8 @@ static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); else - compbit_store_iova = g->ops.mm.get_iova_addr(g, - gr->compbit_store.mem.priv.sgt->sgl, 0); + compbit_store_iova = nvgpu_mem_get_addr(g, + &gr->compbit_store.mem); compbit_base_post_divide64 = compbit_store_iova >> fb_mmu_cbc_base_address_alignment_shift_v(); diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 9be8352a..7ba8f74f 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -260,10 +260,10 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) * checking bit 36 of the phsyical address. So if a mapping should allocte lines * in the L3 this bit must be set. */ -u64 gv11b_gpu_phys_addr(struct gk20a *g, - struct nvgpu_gmmu_attrs *attrs, u64 phys) +static u64 gv11b_gpu_phys_addr(struct gk20a *g, + struct nvgpu_gmmu_attrs *attrs, u64 phys) { - if (attrs->t19x_attrs.l3_alloc) + if (attrs && attrs->t19x_attrs.l3_alloc) return phys | NVGPU_L3_ALLOC_BIT; return phys; @@ -322,6 +322,7 @@ static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) void gv11b_init_mm(struct gpu_ops *gops) { gp10b_init_mm(gops); + gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; gops->mm.init_inst_block = gv11b_init_inst_block; gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index bda36216..72a66530 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -143,13 +143,14 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block) { struct gk20a *g = c->g; + struct vm_gk20a *vm = c->vm; u32 lo, hi; u32 subctx_id = 0; u32 format_word; u32 pdb_addr_lo, pdb_addr_hi; u64 pdb_addr; - pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem->priv.sgt->sgl, 0); + pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); pdb_addr_hi = u64_hi32(pdb_addr); format_word = ram_in_sc_page_dir_base_target_f( -- cgit v1.2.2 From 026d1f8efec6f88a6a910820b761ba1b335edc72 Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 4 Aug 2017 10:44:41 -0700 Subject: gpu: nvgpu: update gv11b_get_litter_value Update gv11b_get_litter_value: - add PPC_IN_GPC_BASE - set all FBPA values to 0, since gv11b does not have an FBPA unit - error/bug if we fall through to default, for easier debugging JIRA EVLR-1712 Change-Id: I9a388d6f525e101d4742ade07f972410ec3b2591 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1533192 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 12ec4841..282aa228 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -105,6 +105,9 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_TPC_IN_GPC_SHARED_BASE: ret = proj_tpc_in_gpc_shared_base_v(); break; + case GPU_LIT_PPC_IN_GPC_BASE: + ret = proj_ppc_in_gpc_base_v(); + break; case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; @@ -129,17 +132,23 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_LTS_STRIDE: ret = proj_lts_stride_v(); break; - case GPU_LIT_NUM_FBPAS: - ret = proj_scal_litter_num_fbpas_v(); - break; - case GPU_LIT_FBPA_STRIDE: - ret = proj_fbpa_stride_v(); - break; case GPU_LIT_SM_PRI_STRIDE: ret = proj_sm_stride_v(); break; + /* GV11B does not have a FBPA unit, despite what's listed in the + * hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS, + * so hardcode all values to 0. + */ + case GPU_LIT_NUM_FBPAS: + case GPU_LIT_FBPA_STRIDE: + case GPU_LIT_FBPA_BASE: + case GPU_LIT_FBPA_SHARED_BASE: + ret = 0; + break; default: + nvgpu_err(g, "Missing definition %d", value); + BUG(); break; } -- cgit v1.2.2 From de8e057f7eebcfe676278826ab457bf86b1b36fd Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 3 Aug 2017 21:43:50 -0700 Subject: gpu: nvgpu: GV100 support Adds support of GV100 up to devinit. JIRA: EVLR-1693 Change-Id: Ic7aa5f1c20714e05954139f143abb6a3459858fc Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1532747 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 6 +- drivers/gpu/nvgpu/gv100/fb_gv100.c | 58 + drivers/gpu/nvgpu/gv100/fb_gv100.h | 22 + drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c | 38 + drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h | 28 + drivers/gpu/nvgpu/gv100/gv100.h | 26 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 441 +++ drivers/gpu/nvgpu/gv100/hal_gv100.h | 21 + drivers/gpu/nvgpu/gv100/mm_gv100.c | 41 + drivers/gpu/nvgpu/gv100/mm_gv100.h | 23 + .../nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | 217 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 133 + .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h | 101 + .../include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h | 449 +++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | 1469 ++++++++ .../nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h | 545 +++ .../nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h | 181 + .../nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h | 137 + .../nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h | 1281 +++++++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 3905 ++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h | 613 +++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | 245 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | 645 ++++ .../nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h | 205 + .../nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h | 57 + .../nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h | 161 + .../nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h | 73 + .../nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h | 85 + .../nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | 161 + .../nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h | 929 +++++ .../nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | 761 ++++ .../nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h | 293 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h | 109 + .../nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h | 229 ++ .../include/nvgpu/hw/gv100/hw_usermode_gv100.h | 89 + .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h | 137 + .../nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h | 201 + drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h | 9 + include/uapi/linux/nvgpu-t19x.h | 2 + 39 files changed, 14125 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/gv100/fb_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/fb_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/hal_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/hal_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/mm_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/mm_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 1d2feba4..e91b4e69 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -16,7 +16,11 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \ $(nvgpu-t19x)/gv11b/pmu_gv11b.o \ $(nvgpu-t19x)/gv11b/subctx_gv11b.o \ - $(nvgpu-t19x)/gv11b/regops_gv11b.o + $(nvgpu-t19x)/gv11b/regops_gv11b.o \ + $(nvgpu-t19x)/gv100/mm_gv100.o \ + $(nvgpu-t19x)/gv100/gr_ctx_gv100.o \ + $(nvgpu-t19x)/gv100/fb_gv100.o \ + $(nvgpu-t19x)/gv100/hal_gv100.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += $(nvgpu-t19x)/common/linux/nvhost_t19x.o diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c new file mode 100644 index 00000000..a3785266 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -0,0 +1,58 @@ +/* + * GV100 FB + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gv11b/fb_gv11b.h" +#include "gv100/fb_gv100.h" + +#include + +#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ +#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ + +static void gv100_fb_reset(struct gk20a *g) +{ + u32 val; + int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT; + + nvgpu_info(g, "reset gv100 fb"); + + /* wait for memory to be accessible */ + do { + u32 w = gk20a_readl(g, fb_niso_scrub_status_r()); + if (fb_niso_scrub_status_flag_v(w)) { + nvgpu_info(g, "done"); + break; + } + nvgpu_udelay(HW_SCRUB_TIMEOUT_DEFAULT); + } while (--retries); + + val = gk20a_readl(g, fb_mmu_priv_level_mask_r()); + val &= ~fb_mmu_priv_level_mask_write_violation_m(); + gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); +} + +void gv100_init_fb(struct gpu_ops *gops) +{ + gv11b_init_fb(gops); + gops->fb.reset = gv100_fb_reset; +} diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h new file mode 100644 index 00000000..b234fa13 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h @@ -0,0 +1,22 @@ +/* + * GV100 FB + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_GV100_FB +#define _NVGPU_GV100_FB + +struct gpu_ops; + +void gv100_init_fb(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c new file mode 100644 index 00000000..2e605cce --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c @@ -0,0 +1,38 @@ +/* + * GV100 Graphics Context + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gr_ctx_gv100.h" + +int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name) +{ + u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; + + switch (ver) { + case NVGPU_GPUID_GV100: + sprintf(name, "%s/%s", "gv100", + GV100_NETLIST_IMAGE_FW_NAME); + break; + default: + nvgpu_err(g, "no support for GPUID %x", ver); + } + + return 0; +} + +bool gr_gv100_is_firmware_defined(void) +{ + return true; +} diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h new file mode 100644 index 00000000..122e750f --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __GR_CTX_GV100_H__ +#define __GR_CTX_GV100_H__ + +#include "gk20a/gr_ctx_gk20a.h" +#include "nvgpu_gpuid_t19x.h" + +/* production netlist, one and only one from below */ +#define GV100_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D + +int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name); +bool gr_gv100_is_firmware_defined(void); + +#endif /*__GR_CTX_GV100_H__*/ diff --git a/drivers/gpu/nvgpu/gv100/gv100.h b/drivers/gpu/nvgpu/gv100/gv100.h new file mode 100644 index 00000000..eeea64a4 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gv100.h @@ -0,0 +1,26 @@ +/* + * GV100 Graphics + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef GV100_H +#define GV100_H + +#include "gk20a/gk20a.h" + +int gv100_init_gpu_characteristics(struct gk20a *g); + +#endif /* GV11B_H */ diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c new file mode 100644 index 00000000..337c607f --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -0,0 +1,441 @@ +/* + * GV100 Tegra HAL interface + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include +#include + +#include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" +#include "gk20a/ctxsw_trace_gk20a.h" +#include "gk20a/fecs_trace_gk20a.h" +#include "gk20a/css_gr_gk20a.h" +#include "gk20a/mc_gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/bus_gk20a.h" +#include "gk20a/pramin_gk20a.h" +#include "gk20a/flcn_gk20a.h" +#include "gk20a/regops_gk20a.h" + +#include "gm20b/ltc_gm20b.h" +#include "gm20b/gr_gm20b.h" +#include "gm20b/fifo_gm20b.h" + +#include "gp106/clk_gp106.h" +#include "gp106/clk_arb_gp106.h" +#include "gp106/pmu_gp106.h" + +#include "gm206/bios_gm206.h" +#include "gp106/therm_gp106.h" +#include "gp106/xve_gp106.h" +#include "gp106/clk_gp106.h" +#include "gp106/flcn_gp106.h" +#include "gp10b/ltc_gp10b.h" +#include "gp10b/therm_gp10b.h" +#include "gp10b/mc_gp10b.h" +#include "gp10b/ce_gp10b.h" +#include "gp10b/priv_ring_gp10b.h" +#include "gp10b/fifo_gp10b.h" +#include "gp10b/fecs_trace_gp10b.h" + +#include "gv11b/hal_gv11b.h" +#include "gv11b/gr_gv11b.h" +#include "gv11b/mc_gv11b.h" +#include "gv11b/ltc_gv11b.h" +#include "gv11b/gv11b.h" +#include "gv11b/ce_gv11b.h" +#include "gv100/gr_ctx_gv100.h" +#include "gv100/mm_gv100.h" +#include "gv11b/pmu_gv11b.h" +#include "gv100/fb_gv100.h" +#include "gv11b/fifo_gv11b.h" +#include "gv11b/gv11b_gating_reglist.h" +#include "gv11b/regops_gv11b.h" +#include "gv11b/subctx_gv11b.h" + +#include "gv100.h" +#include "hal_gv100.h" + +#include +#include + +#include +#include +#include +#include +#include + +static int gv100_get_litter_value(struct gk20a *g, int value) +{ + int ret = EINVAL; + switch (value) { + case GPU_LIT_NUM_GPCS: + ret = proj_scal_litter_num_gpcs_v(); + break; + case GPU_LIT_NUM_PES_PER_GPC: + ret = proj_scal_litter_num_pes_per_gpc_v(); + break; + case GPU_LIT_NUM_ZCULL_BANKS: + ret = proj_scal_litter_num_zcull_banks_v(); + break; + case GPU_LIT_NUM_TPC_PER_GPC: + ret = proj_scal_litter_num_tpc_per_gpc_v(); + break; + case GPU_LIT_NUM_SM_PER_TPC: + ret = proj_scal_litter_num_sm_per_tpc_v(); + break; + case GPU_LIT_NUM_FBPS: + ret = proj_scal_litter_num_fbps_v(); + break; + case GPU_LIT_GPC_BASE: + ret = proj_gpc_base_v(); + break; + case GPU_LIT_GPC_STRIDE: + ret = proj_gpc_stride_v(); + break; + case GPU_LIT_GPC_SHARED_BASE: + ret = proj_gpc_shared_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_BASE: + ret = proj_tpc_in_gpc_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_STRIDE: + ret = proj_tpc_in_gpc_stride_v(); + break; + case GPU_LIT_TPC_IN_GPC_SHARED_BASE: + ret = proj_tpc_in_gpc_shared_base_v(); + break; + case GPU_LIT_PPC_IN_GPC_BASE: + ret = proj_ppc_in_gpc_base_v(); + case GPU_LIT_PPC_IN_GPC_STRIDE: + ret = proj_ppc_in_gpc_stride_v(); + break; + case GPU_LIT_ROP_BASE: + ret = proj_rop_base_v(); + break; + case GPU_LIT_ROP_STRIDE: + ret = proj_rop_stride_v(); + break; + case GPU_LIT_ROP_SHARED_BASE: + ret = proj_rop_shared_base_v(); + break; + case GPU_LIT_HOST_NUM_ENGINES: + ret = proj_host_num_engines_v(); + break; + case GPU_LIT_HOST_NUM_PBDMA: + ret = proj_host_num_pbdma_v(); + break; + case GPU_LIT_LTC_STRIDE: + ret = proj_ltc_stride_v(); + break; + case GPU_LIT_LTS_STRIDE: + ret = proj_lts_stride_v(); + break; + case GPU_LIT_NUM_FBPAS: + ret = proj_scal_litter_num_fbpas_v(); + break; + case GPU_LIT_FBPA_STRIDE: + ret = proj_fbpa_stride_v(); + break; + case GPU_LIT_SM_PRI_STRIDE: + ret = proj_sm_stride_v(); + break; + + default: + break; + } + + return ret; +} + +int gv100_init_gpu_characteristics(struct gk20a *g) +{ + struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; + + int err; + + err = gk20a_init_gpu_characteristics(g); + if (err) + return err; + + gpu->flags |= + NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; + + return 0; +} + + + +static const struct gpu_ops gv100_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = gv11b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gv11b_ltc_isr, + .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, + .set_enabled = gp10b_ltc_set_enabled, + }, + .ce2 = { + .isr_stall = gv11b_ce_isr, + .isr_nonstall = gp10b_ce_nonstall_isr, + .get_num_pce = gv11b_ce_get_num_pce, + }, + .fifo = { + .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, + .bind_channel = channel_gm20b_bind, + .unbind_channel = channel_gv11b_unbind, + .disable_channel = gk20a_fifo_disable_channel, + .enable_channel = gk20a_fifo_enable_channel, + .alloc_inst = gk20a_fifo_alloc_inst, + .free_inst = gk20a_fifo_free_inst, + .setup_ramfc = channel_gv11b_setup_ramfc, + .channel_set_priority = gk20a_fifo_set_priority, + .channel_set_timeslice = gk20a_fifo_set_timeslice, + .default_timeslice_us = gk20a_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gv11b_userd_gp_get, + .userd_gp_put = gv11b_userd_gp_put, + .userd_pb_get = gv11b_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = gv11b_fifo_preempt_channel, + .preempt_tsg = gv11b_fifo_preempt_tsg, + .update_runlist = gk20a_fifo_update_runlist, + .trigger_mmu_fault = NULL, + .get_mmu_fault_info = NULL, + .wait_engine_idle = gk20a_fifo_wait_engine_idle, + .get_num_fifos = gv11b_fifo_get_num_fifos, + .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, + .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, + .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, + .force_reset_ch = gk20a_fifo_force_reset_ch, + .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, + .device_info_data_parse = gp10b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = gk20a_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, + .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gv11b_dump_eng_status, + .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, + .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, + .is_preempt_pending = gv11b_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, + .handle_sched_error = gv11b_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, + .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, + .deinit_eng_method_buffers = + gv11b_fifo_deinit_eng_method_buffers, + .tsg_bind_channel = gk20a_tsg_bind_channel, + .tsg_unbind_channel = gk20a_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, +#endif + .resetup_ramfc = NULL, + .device_info_fault_id = top_device_info_data_fault_id_enum_v, + .free_channel_ctx_header = gv11b_free_subctx_header, + .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + }, + .gr_ctx = { + .get_netlist_name = gr_gv100_get_netlist_name, + .is_fw_defined = gr_gv100_is_firmware_defined, + }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, + .free_user_buffer = gk20a_ctxsw_dev_ring_free, + .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, + .init = gk20a_fecs_trace_init, + .deinit = gk20a_fecs_trace_deinit, + .enable = gk20a_fecs_trace_enable, + .disable = gk20a_fecs_trace_disable, + .is_enabled = gk20a_fecs_trace_is_enabled, + .reset = gk20a_fecs_trace_reset, + .flush = gp10b_fecs_trace_flush, + .poll = gk20a_fecs_trace_poll, + .bind_channel = gk20a_fecs_trace_bind_channel, + .unbind_channel = gk20a_fecs_trace_unbind_channel, + .max_entries = gk20a_gr_max_entries, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ + .pramin = { + .enter = gk20a_pramin_enter, + .exit = gk20a_pramin_exit, + .data032_r = pram_data032_r, + }, + .clk = { + .init_clk_support = gp106_init_clk_support, + .get_crystal_clk_hz = gp106_crystal_clk_hz, + .measure_freq = gp106_clk_measure_freq, + .suspend_clk_support = gp106_suspend_clk_support, + }, + .clk_arb = { + .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, + .get_arbiter_clk_range = gp106_get_arbiter_clk_range, + .get_arbiter_clk_default = gp106_get_arbiter_clk_default, + .get_current_pstate = nvgpu_clk_arb_get_current_pstate, + }, + .mc = { + .intr_enable = mc_gv11b_intr_enable, + .intr_unit_config = mc_gp10b_intr_unit_config, + .isr_stall = mc_gp10b_isr_stall, + .intr_stall = mc_gp10b_intr_stall, + .intr_stall_pause = mc_gp10b_intr_stall_pause, + .intr_stall_resume = mc_gp10b_intr_stall_resume, + .intr_nonstall = mc_gp10b_intr_nonstall, + .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, + .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .enable = gk20a_mc_enable, + .disable = gk20a_mc_disable, + .reset = gk20a_mc_reset, + .boot_0 = gk20a_mc_boot_0, + .is_intr1_pending = mc_gp10b_is_intr1_pending, + .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, + }, + .debug = { + .show_dump = gk20a_debug_show_dump, + }, + .dbg_session_ops = { + .exec_reg_ops = exec_regops_gk20a, + .dbg_set_powergate = dbg_set_powergate, + .check_and_set_global_reservation = + nvgpu_check_and_set_global_reservation, + .check_and_set_context_reservation = + nvgpu_check_and_set_context_reservation, + .release_profiler_reservation = + nvgpu_release_profiler_reservation, + .perfbuffer_enable = gk20a_perfbuf_enable_locked, + .perfbuffer_disable = gk20a_perfbuf_disable_locked, + }, + .bus = { + .init_hw = gk20a_bus_init_hw, + .isr = gk20a_bus_isr, + .read_ptimer = gk20a_read_ptimer, + .bar1_bind = NULL, + }, +#if defined(CONFIG_GK20A_CYCLE_STATS) + .css = { + .enable_snapshot = css_hw_enable_snapshot, + .disable_snapshot = css_hw_disable_snapshot, + .check_data_available = css_hw_check_data_available, + .set_handled_snapshots = css_hw_set_handled_snapshots, + .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, + .release_perfmon_ids = css_gr_release_perfmon_ids, + }, +#endif + .xve = { + .sw_init = xve_sw_init_gp106, + .get_speed = xve_get_speed_gp106, + .set_speed = xve_set_speed_gp106, + .available_speeds = xve_available_speeds_gp106, + .xve_readl = xve_xve_readl_gp106, + .xve_writel = xve_xve_writel_gp106, + .disable_aspm = xve_disable_aspm_gp106, + .reset_gpu = xve_reset_gpu_gp106, +#if defined(CONFIG_PCI_MSI) + .rearm_msi = xve_rearm_msi_gp106, +#endif + .enable_shadow_rom = xve_enable_shadow_rom_gp106, + .disable_shadow_rom = xve_disable_shadow_rom_gp106, + }, + .falcon = { + .falcon_hal_sw_init = gp106_falcon_hal_sw_init, + }, + .priv_ring = { + .isr = gp10b_priv_ring_isr, + }, + .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, + .get_litter_value = gv100_get_litter_value, + .bios_init = gm206_bios_init, +}; + +int gv100_init_hal(struct gk20a *g) +{ + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + + gops->ltc = gv100_ops.ltc; + gops->ce2 = gv100_ops.ce2; + gops->clock_gating = gv100_ops.clock_gating; + gops->fifo = gv100_ops.fifo; + gops->gr_ctx = gv100_ops.gr_ctx; + gops->fecs_trace = gv100_ops.fecs_trace; + gops->pramin = gv100_ops.pramin; + gops->therm = gv100_ops.therm; + gops->mc = gv100_ops.mc; + gops->debug = gv100_ops.debug; + gops->dbg_session_ops = gv100_ops.dbg_session_ops; + gops->bus = gv100_ops.bus; +#if defined(CONFIG_GK20A_CYCLE_STATS) + gops->css = gv100_ops.css; +#endif + gops->xve = gv100_ops.xve; + gops->falcon = gv100_ops.falcon; + gops->priv_ring = gv100_ops.priv_ring; + + /* clocks */ + gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; + gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz; + gops->clk.measure_freq = gv100_ops.clk.measure_freq; + gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support; + + /* Lone functions */ + gops->chip_init_gpu_characteristics = + gv100_ops.chip_init_gpu_characteristics; + gops->get_litter_value = gv100_ops.get_litter_value; + gops->bios_init = gv100_ops.bios_init; + + __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + /* for now */ + __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); + + g->bootstrap_owner = LSF_FALCON_ID_SEC2; + + gv11b_init_gr(g); + gv100_init_fb(gops); + gv100_init_mm(gops); + gp106_init_pmu_ops(g); + + g->name = "gv10x"; + + c->twod_class = FERMI_TWOD_A; + c->threed_class = VOLTA_A; + c->compute_class = VOLTA_COMPUTE_A; + c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = VOLTA_DMA_COPY_A; + + return 0; +} diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h new file mode 100644 index 00000000..a7c74db0 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h @@ -0,0 +1,21 @@ +/* + * GV100 Tegra HAL interface + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_HAL_GV11B_H +#define _NVGPU_HAL_GV11B_H +struct gk20a; + +int gv100_init_hal(struct gk20a *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c new file mode 100644 index 00000000..fbc5df79 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c @@ -0,0 +1,41 @@ +/* + * GV100 memory management + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gv11b/mm_gv11b.h" +#include "gv100/mm_gv100.h" + +#include + +static size_t gv100_mm_get_vidmem_size(struct gk20a *g) +{ + u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r()); + u32 mag = fb_mmu_local_memory_range_lower_mag_v(range); + u32 scale = fb_mmu_local_memory_range_lower_scale_v(range); + u32 ecc = fb_mmu_local_memory_range_ecc_mode_v(range); + size_t bytes = ((size_t)mag << scale) * SZ_1M; + + if (ecc) + bytes = bytes / 16 * 15; + + return bytes; +} + +void gv100_init_mm(struct gpu_ops *gops) +{ + gv11b_init_mm(gops); + gops->mm.get_vidmem_size = gv100_mm_get_vidmem_size; + gops->mm.get_physical_addr_bits = NULL; +} diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h new file mode 100644 index 00000000..ff1bc3df --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h @@ -0,0 +1,23 @@ +/* + * GV100 memory management + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef MM_GV100_H +#define MM_GV100_H + +struct gpu_ops; + +void gv100_init_mm(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h new file mode 100644 index 00000000..c95d5af4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_bus_gv100_h_ +#define _hw_bus_gv100_h_ + +static inline u32 bus_bar0_window_r(void) +{ + return 0x00001700; +} +static inline u32 bus_bar0_window_base_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 bus_bar0_window_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) +{ + return 0x2000000; +} +static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) +{ + return 0x3000000; +} +static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) +{ + return 0x00000010; +} +static inline u32 bus_bar1_block_r(void) +{ + return 0x00001704; +} +static inline u32 bus_bar1_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar1_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 bus_bar1_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar2_block_r(void) +{ + return 0x00001714; +} +static inline u32 bus_bar2_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar2_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 bus_bar2_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar1_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bar2_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_bind_status_r(void) +{ + return 0x00001710; +} +static inline u32 bus_bind_status_bar1_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 bus_bind_status_bar1_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 bus_bind_status_bar1_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar1_outstanding_true_f(void) +{ + return 0x2; +} +static inline u32 bus_bind_status_bar2_pending_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 bus_bind_status_bar2_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_pending_busy_f(void) +{ + return 0x4; +} +static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 bus_bind_status_bar2_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 bus_bind_status_bar2_outstanding_true_f(void) +{ + return 0x8; +} +static inline u32 bus_intr_0_r(void) +{ + return 0x00001100; +} +static inline u32 bus_intr_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +static inline u32 bus_intr_en_0_r(void) +{ + return 0x00001140; +} +static inline u32 bus_intr_en_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_en_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_en_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h new file mode 100644 index 00000000..f64f542c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ccsr_gv100_h_ +#define _hw_ccsr_gv100_h_ + +static inline u32 ccsr_channel_inst_r(u32 i) +{ + return 0x00800000 + i*8; +} +static inline u32 ccsr_channel_inst__size_1_v(void) +{ + return 0x00001000; +} +static inline u32 ccsr_channel_inst_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 ccsr_channel_inst_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 ccsr_channel_inst_bind_false_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_bind_true_f(void) +{ + return 0x80000000; +} +static inline u32 ccsr_channel_r(u32 i) +{ + return 0x00800004 + i*8; +} +static inline u32 ccsr_channel__size_1_v(void) +{ + return 0x00001000; +} +static inline u32 ccsr_channel_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ccsr_channel_enable_set_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ccsr_channel_enable_set_true_f(void) +{ + return 0x400; +} +static inline u32 ccsr_channel_enable_clr_true_f(void) +{ + return 0x800; +} +static inline u32 ccsr_channel_status_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) +{ + return 0x400000; +} +static inline u32 ccsr_channel_eng_faulted_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 ccsr_channel_eng_faulted_reset_f(void) +{ + return 0x800000; +} +static inline u32 ccsr_channel_busy_v(u32 r) +{ + return (r >> 28) & 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h new file mode 100644 index 00000000..26971f3f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce_gv100_h_ +#define _hw_ce_gv100_h_ + +static inline u32 ce_intr_status_r(u32 i) +{ + return 0x00104410 + i*128; +} +static inline u32 ce_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +static inline u32 ce_intr_status_invalid_config_pending_f(void) +{ + return 0x8; +} +static inline u32 ce_intr_status_invalid_config_reset_f(void) +{ + return 0x8; +} +static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) +{ + return 0x10; +} +static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) +{ + return 0x10; +} +static inline u32 ce_pce_map_r(void) +{ + return 0x00104028; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h new file mode 100644 index 00000000..f5593095 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ctxsw_prog_gv100_h_ +#define _hw_ctxsw_prog_gv100_h_ + +static inline u32 ctxsw_prog_fecs_header_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) +{ + return 0x00000011; +} +static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) +{ + return 0x00000012; +} +static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) +{ + return 0x00000021; +} +static inline u32 ctxsw_prog_main_image_patch_count_o(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_context_id_o(void) +{ + return 0x000000f0; +} +static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) +{ + return 0x00000014; +} +static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) +{ + return 0x00000018; +} +static inline u32 ctxsw_prog_main_image_zcull_o(void) +{ + return 0x0000001c; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) +{ + return 0x00000001; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_pm_o(void) +{ + return 0x00000028; +} +static inline u32 ctxsw_prog_main_image_pm_mode_m(void) +{ + return 0x7 << 0; +} +static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) +{ + return 0x7 << 3; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) +{ + return 0x8; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) +{ + return 0x0000002c; +} +static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) +{ + return 0x000000d0; +} +static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) +{ + return 0x000000d4; +} +static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) +{ + return 0x000000d8; +} +static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) +{ + return 0x000000dc; +} +static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) +{ + return 0x00000060; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) +{ + return 0x00000094; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) +{ + return 0x00000064; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) +{ + return 0x00000068; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) +{ + return 0x00000070; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) +{ + return 0x00000074; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) +{ + return 0x00000078; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) +{ + return 0x0000007c; +} +static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) +{ + return 0x600dc0de; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) +{ + return 0x000000b8; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) +{ + return 0x000000bc; +} +static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) +{ + return 0x000000c0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) +{ + return 0x000000c4; +} +static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) +{ + return 0x000000c8; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) +{ + return 0x000000cc; +} +static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) +{ + return 0x000000e0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) +{ + return 0x000000e4; +} +static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ctxsw_prog_local_image_ppc_info_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_local_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) +{ + return 0xad0becab; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) +{ + return 0x000000ec; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) +{ + return 0x000000a0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) +{ + return 2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) +{ + return 0x3 << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) +{ + return 0x2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) +{ + return 0x000000a4; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) +{ + return 0x000000a8; +} +static inline u32 ctxsw_prog_main_image_misc_options_o(void) +{ + return 0x0000003c; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) +{ + return 0x1 << 3; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) +{ + return 0x00000080; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) +{ + return 0x00000084; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) +{ + return 0x2; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h new file mode 100644 index 00000000..ce726633 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -0,0 +1,1469 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fb_gv100_h_ +#define _hw_fb_gv100_h_ + +static inline u32 fb_fbhub_num_active_ltcs_r(void) +{ + return 0x00100800; +} +static inline u32 fb_mmu_ctrl_r(void) +{ + return 0x00100c80; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) +{ + return 0x0; +} +static inline u32 fb_priv_mmu_phy_secure_r(void) +{ + return 0x00100ce4; +} +static inline u32 fb_mmu_invalidate_pdb_r(void) +{ + return 0x00100cb8; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_invalidate_r(void) +{ + return 0x00100cbc; +} +static inline u32 fb_mmu_invalidate_all_va_true_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_invalidate_replay_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_replay_f(u32 v) +{ + return (v & 0x7) << 3; +} +static inline u32 fb_mmu_invalidate_replay_m(void) +{ + return 0x7 << 3; +} +static inline u32 fb_mmu_invalidate_replay_v(u32 r) +{ + return (r >> 3) & 0x7; +} +static inline u32 fb_mmu_invalidate_replay_none_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_replay_start_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_invalidate_sys_membar_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_m(void) +{ + return 0x1 << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_invalidate_ack_s(void) +{ + return 2; +} +static inline u32 fb_mmu_invalidate_ack_f(u32 v) +{ + return (v & 0x3) << 7; +} +static inline u32 fb_mmu_invalidate_ack_m(void) +{ + return 0x3 << 7; +} +static inline u32 fb_mmu_invalidate_ack_v(u32 r) +{ + return (r >> 7) & 0x3; +} +static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) +{ + return 6; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) +{ + return (v & 0x3f) << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) +{ + return 0x3f << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) +{ + return (r >> 9) & 0x3f; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) +{ + return 5; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) +{ + return 0x1f << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) +{ + return 0x1 << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) +{ + return 0x100000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) +{ + return 0x7 << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) +{ + return (r >> 24) & 0x7; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) +{ + return 0x1000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) +{ + return 0x2000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) +{ + return 0x3000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) +{ + return 0x4000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) +{ + return 0x5000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) +{ + return 0x6000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) +{ + return 0x7000000; +} +static inline u32 fb_mmu_invalidate_trigger_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_trigger_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_invalidate_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_invalidate_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_invalidate_trigger_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_debug_wr_r(void) +{ + return 0x00100cc8; +} +static inline u32 fb_mmu_debug_wr_aperture_s(void) +{ + return 2; +} +static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_m(void) +{ + return 0x3 << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_debug_wr_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_wr_vol_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_debug_wr_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_rd_r(void) +{ + return 0x00100ccc; +} +static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_debug_rd_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_ctrl_r(void) +{ + return 0x00100cc4; +} +static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 fb_mmu_debug_ctrl_debug_m(void) +{ + return 0x1 << 16; +} +static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_r(void) +{ + return 0x00100cd0; +} +static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_vpr_info_fetch_false_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_fetch_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_niso_flush_sysmem_addr_r(void) +{ + return 0x00100c10; +} +static inline u32 fb_niso_intr_r(void) +{ + return 0x00100a20; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) +{ + return 0x1 << 27; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) +{ + return 0x1 << 28; +} +static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) +{ + return 0x1 << 29; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_r(u32 i) +{ + return 0x00100a24 + i*4; +} +static inline u32 fb_niso_intr_en__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_set_r(u32 i) +{ + return 0x00100a2c + i*4; +} +static inline u32 fb_niso_intr_en_set__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) +{ + return 0x1 << 27; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) +{ + return 0x1 << 28; +} +static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) +{ + return 0x1 << 29; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_r(u32 i) +{ + return 0x00100a34 + i*4; +} +static inline u32 fb_niso_intr_en_clr__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) +{ + return 0x1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) +{ + return 0x2; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) +{ + return 0x1 << 27; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) +{ + return 0x8000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) +{ + return 0x1 << 28; +} +static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) +{ + return 0x10000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) +{ + return 0x1 << 29; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) +{ + return 0x20000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) +{ + return 0x40000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) +{ + return 0x00000000; +} +static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) +{ + return 0x00100e24 + i*20; +} +static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 1; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) +{ + return (r >> 1) & 0x3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x6; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) +{ + return 0x00100e28 + i*20; +} +static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_buffer_get_r(u32 i) +{ + return 0x00100e2c + i*20; +} +static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) +{ + return 0xfffff << 0; +} +static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_put_r(u32 i) +{ + return 0x00100e30 + i*20; +} +static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_buffer_size_r(u32 i) +{ + return 0x00100e34 + i*20; +} +static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) +{ + return 0x20000000; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_fault_buffer_size_enable_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_addr_lo_r(void) +{ + return 0x00100e4c; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) +{ + return 0x3; +} +static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_addr_hi_r(void) +{ + return 0x00100e50; +} +static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_inst_lo_r(void) +{ + return 0x00100e54; +} +static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) +{ + return (r >> 10) & 0x3; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) +{ + return 0x00000003; +} +static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) +{ + return (r >> 12) & 0xfffff; +} +static inline u32 fb_mmu_fault_inst_hi_r(void) +{ + return 0x00100e58; +} +static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 fb_mmu_fault_info_r(void) +{ + return 0x00100e5c; +} +static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 fb_mmu_fault_info_client_v(u32 r) +{ + return (r >> 8) & 0x7f; +} +static inline u32 fb_mmu_fault_info_access_type_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 fb_mmu_fault_info_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_mmu_fault_info_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_fault_status_r(void) +{ + return 0x00100e60; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) +{ + return 0x1 << 0; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) +{ + return 0x1 << 1; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) +{ + return 0x1 << 3; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) +{ + return 0x1 << 4; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) +{ + return 0x1 << 5; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) +{ + return 0x1 << 6; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) +{ + return 0x1 << 7; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_fault_status_replayable_m(void) +{ + return 0x1 << 8; +} +static inline u32 fb_mmu_fault_status_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_set_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_fault_status_replayable_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_non_replayable_m(void) +{ + return 0x1 << 9; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) +{ + return 0x200; +} +static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_replayable_error_m(void) +{ + return 0x1 << 10; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) +{ + return 0x400; +} +static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) +{ + return 0x1 << 11; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) +{ + return 0x1 << 12; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) +{ + return 0x1000; +} +static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) +{ + return 0x1 << 13; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) +{ + return 0x2000; +} +static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) +{ + return 0x1 << 14; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) +{ + return 0x4000; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) +{ + return 0x1 << 15; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) +{ + return 0x8000; +} +static inline u32 fb_mmu_fault_status_busy_m(void) +{ + return 0x1 << 30; +} +static inline u32 fb_mmu_fault_status_busy_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_busy_true_f(void) +{ + return 0x40000000; +} +static inline u32 fb_mmu_fault_status_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_fault_status_valid_set_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_set_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_fault_status_valid_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_fault_status_valid_clear_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_local_memory_range_r(void) +{ + return 0x00100ce0; +} +static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) +{ + return (r >> 4) & 0x3f; +} +static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fb_niso_scrub_status_r(void) +{ + return 0x00100b20; +} +static inline u32 fb_niso_scrub_status_flag_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fb_mmu_priv_level_mask_r(void) +{ + return 0x00100cdc; +} +static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) +{ + return 0x1 << 7; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h new file mode 100644 index 00000000..9466a695 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h @@ -0,0 +1,545 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fifo_gv100_h_ +#define _hw_fifo_gv100_h_ + +static inline u32 fifo_bar1_base_r(void) +{ + return 0x00002254; +} +static inline u32 fifo_bar1_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_bar1_base_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 fifo_bar1_base_valid_false_f(void) +{ + return 0x0; +} +static inline u32 fifo_bar1_base_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_userd_writeback_r(void) +{ + return 0x0000225c; +} +static inline u32 fifo_userd_writeback_timer_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_userd_writeback_timer_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_userd_writeback_timer_shorter_v(void) +{ + return 0x00000003; +} +static inline u32 fifo_userd_writeback_timer_100us_v(void) +{ + return 0x00000064; +} +static inline u32 fifo_userd_writeback_timescale_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 fifo_userd_writeback_timescale_0_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_runlist_base_r(void) +{ + return 0x00002270; +} +static inline u32 fifo_runlist_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_runlist_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 fifo_runlist_r(void) +{ + return 0x00002274; +} +static inline u32 fifo_runlist_engine_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 fifo_eng_runlist_base_r(u32 i) +{ + return 0x00002280 + i*8; +} +static inline u32 fifo_eng_runlist_base__size_1_v(void) +{ + return 0x0000000d; +} +static inline u32 fifo_eng_runlist_r(u32 i) +{ + return 0x00002284 + i*8; +} +static inline u32 fifo_eng_runlist__size_1_v(void) +{ + return 0x0000000d; +} +static inline u32 fifo_eng_runlist_length_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fifo_eng_runlist_length_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 fifo_eng_runlist_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_pb_timeslice_r(u32 i) +{ + return 0x00002350 + i*4; +} +static inline u32 fifo_pb_timeslice_timeout_16_f(void) +{ + return 0x10; +} +static inline u32 fifo_pb_timeslice_timescale_0_f(void) +{ + return 0x0; +} +static inline u32 fifo_pb_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_pbdma_map_r(u32 i) +{ + return 0x00002390 + i*4; +} +static inline u32 fifo_intr_0_r(void) +{ + return 0x00002100; +} +static inline u32 fifo_intr_0_bind_error_pending_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_bind_error_reset_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_sched_error_pending_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_sched_error_reset_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_chsw_error_pending_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_chsw_error_reset_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_lb_error_pending_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_lb_error_reset_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_intr_0_runlist_event_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fifo_intr_0_channel_intr_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fifo_intr_en_0_r(void) +{ + return 0x00002140; +} +static inline u32 fifo_intr_en_0_sched_error_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fifo_intr_en_0_sched_error_m(void) +{ + return 0x1 << 8; +} +static inline u32 fifo_intr_en_1_r(void) +{ + return 0x00002528; +} +static inline u32 fifo_intr_bind_error_r(void) +{ + return 0x0000252c; +} +static inline u32 fifo_intr_sched_error_r(void) +{ + return 0x0000254c; +} +static inline u32 fifo_intr_sched_error_code_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_intr_chsw_error_r(void) +{ + return 0x0000256c; +} +static inline u32 fifo_intr_pbdma_id_r(void) +{ + return 0x000025a0; +} +static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 fifo_intr_runlist_r(void) +{ + return 0x00002a00; +} +static inline u32 fifo_fb_timeout_r(void) +{ + return 0x00002a04; +} +static inline u32 fifo_fb_timeout_period_m(void) +{ + return 0x3fffffff << 0; +} +static inline u32 fifo_fb_timeout_period_max_f(void) +{ + return 0x3fffffff; +} +static inline u32 fifo_fb_timeout_period_init_f(void) +{ + return 0x3c00; +} +static inline u32 fifo_sched_disable_r(void) +{ + return 0x00002630; +} +static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_sched_disable_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_sched_disable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_runlist_preempt_r(void) +{ + return 0x00002638; +} +static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_runlist_preempt_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_runlist_preempt_runlist_pending_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_preempt_r(void) +{ + return 0x00002634; +} +static inline u32 fifo_preempt_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_preempt_type_channel_f(void) +{ + return 0x0; +} +static inline u32 fifo_preempt_type_tsg_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_preempt_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_preempt_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_engine_status_r(u32 i) +{ + return 0x00002640 + i*8; +} +static inline u32 fifo_engine_status__size_1_v(void) +{ + return 0x0000000f; +} +static inline u32 fifo_engine_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_engine_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_engine_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_engine_status_ctx_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_engine_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_engine_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_engine_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_eng_reload_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 fifo_engine_status_faulted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fifo_engine_status_faulted_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_engine_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fifo_engine_status_engine_idle_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_engine_busy_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) +{ + return 0x8000; +} +static inline u32 fifo_pbdma_status_r(u32 i) +{ + return 0x00003080 + i*4; +} +static inline u32 fifo_pbdma_status__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 fifo_pbdma_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_pbdma_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_pbdma_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_pbdma_status_chan_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_pbdma_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_chsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_cfg0_r(void) +{ + return 0x00002004; +} +static inline u32 fifo_cfg0_num_pbdma_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 fifo_fb_iface_r(void) +{ + return 0x000026f0; +} +static inline u32 fifo_fb_iface_control_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fifo_fb_iface_control_enable_f(void) +{ + return 0x1; +} +static inline u32 fifo_fb_iface_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 fifo_fb_iface_status_enabled_f(void) +{ + return 0x10; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h new file mode 100644 index 00000000..c9b592bf --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_flush_gv100_h_ +#define _hw_flush_gv100_h_ + +static inline u32 flush_l2_system_invalidate_r(void) +{ + return 0x00070004; +} +static inline u32 flush_l2_system_invalidate_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_system_invalidate_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_system_invalidate_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_r(void) +{ + return 0x00070010; +} +static inline u32 flush_l2_flush_dirty_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_flush_dirty_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_r(void) +{ + return 0x0007000c; +} +static inline u32 flush_l2_clean_comptags_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_clean_comptags_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_clean_comptags_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_r(void) +{ + return 0x00070000; +} +static inline u32 flush_fb_flush_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_fb_flush_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_fb_flush_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_fb_flush_outstanding_true_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h new file mode 100644 index 00000000..b2b52ff2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fuse_gv100_h_ +#define _hw_fuse_gv100_h_ + +static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) +{ + return 0x00021c38 + i*4; +} +static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) +{ + return 0x00021838 + i*4; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) +{ + return 0x00021944; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) +{ + return 0xff << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) +{ + return 0x00021948; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) +{ + return 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) +{ + return 0x0; +} +static inline u32 fuse_status_opt_fbio_r(void) +{ + return 0x00021c14; +} +static inline u32 fuse_status_opt_fbio_data_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fuse_status_opt_fbio_data_m(void) +{ + return 0xffff << 0; +} +static inline u32 fuse_status_opt_fbio_data_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) +{ + return 0x00021d70 + i*4; +} +static inline u32 fuse_status_opt_fbp_r(void) +{ + return 0x00021d38; +} +static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) +{ + return (r >> (0 + i*1)) & 0x1; +} +static inline u32 fuse_opt_ecc_en_r(void) +{ + return 0x00021228; +} +static inline u32 fuse_opt_feature_fuses_override_disable_r(void) +{ + return 0x000213f0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h new file mode 100644 index 00000000..15bdde6c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h @@ -0,0 +1,1281 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gmmu_gv100_h_ +#define _hw_gmmu_gv100_h_ + +static inline u32 gmmu_new_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_aperture_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_pde_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pde_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pde_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_pde__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_dual_pde_vol_small_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_vol_big_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) +{ + return 2; +} +static inline u32 gmmu_new_dual_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde__size_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_new_pte__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_pte_valid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_valid_true_f(void) +{ + return 0x1; +} +static inline u32 gmmu_new_pte_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_privilege_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_privilege_true_f(void) +{ + return 0x20; +} +static inline u32 gmmu_new_pte_privilege_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_address_vid_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pte_address_vid_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pte_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_aperture_video_memory_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) +{ + return 0x4; +} +static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) +{ + return 0x6; +} +static inline u32 gmmu_new_pte_read_only_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_read_only_true_f(void) +{ + return 0x40; +} +static inline u32 gmmu_new_pte_comptagline_f(u32 v) +{ + return (v & 0x3ffff) << 4; +} +static inline u32 gmmu_new_pte_comptagline_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_kind_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gmmu_new_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_new_pte_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_f(u32 v) +{ + return (v & 0xff) << 4; +} +static inline u32 gmmu_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_kind_invalid_v(void) +{ + return 0x000000ff; +} +static inline u32 gmmu_pte_kind_pitch_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_pte_kind_z16_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_pte_kind_z16_2c_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) +{ + return 0x00000006; +} +static inline u32 gmmu_pte_kind_z16_2z_v(void) +{ + return 0x00000007; +} +static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) +{ + return 0x00000009; +} +static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) +{ + return 0x0000000a; +} +static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) +{ + return 0x0000000b; +} +static inline u32 gmmu_pte_kind_z16_2cz_v(void) +{ + return 0x00000036; +} +static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) +{ + return 0x00000037; +} +static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) +{ + return 0x00000038; +} +static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) +{ + return 0x00000039; +} +static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) +{ + return 0x0000005f; +} +static inline u32 gmmu_pte_kind_s8z24_v(void) +{ + return 0x00000011; +} +static inline u32 gmmu_pte_kind_s8z24_1z_v(void) +{ + return 0x00000012; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) +{ + return 0x00000013; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) +{ + return 0x00000014; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) +{ + return 0x00000015; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) +{ + return 0x00000016; +} +static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) +{ + return 0x00000017; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) +{ + return 0x00000018; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) +{ + return 0x00000019; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) +{ + return 0x0000001a; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) +{ + return 0x0000001b; +} +static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) +{ + return 0x0000001c; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) +{ + return 0x0000001d; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) +{ + return 0x0000001e; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) +{ + return 0x00000021; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) +{ + return 0x00000022; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) +{ + return 0x00000023; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) +{ + return 0x00000024; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) +{ + return 0x00000025; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) +{ + return 0x00000026; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) +{ + return 0x00000027; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) +{ + return 0x00000028; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) +{ + return 0x00000029; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) +{ + return 0x0000002e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) +{ + return 0x0000002f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) +{ + return 0x00000030; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) +{ + return 0x00000031; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) +{ + return 0x00000032; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) +{ + return 0x00000033; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) +{ + return 0x00000034; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) +{ + return 0x00000035; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) +{ + return 0x0000003a; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) +{ + return 0x0000003b; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) +{ + return 0x0000003c; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) +{ + return 0x0000003d; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) +{ + return 0x0000003e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) +{ + return 0x0000003f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) +{ + return 0x00000040; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) +{ + return 0x00000041; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) +{ + return 0x00000042; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) +{ + return 0x00000043; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) +{ + return 0x00000044; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) +{ + return 0x00000045; +} +static inline u32 gmmu_pte_kind_z24s8_v(void) +{ + return 0x00000046; +} +static inline u32 gmmu_pte_kind_z24s8_1z_v(void) +{ + return 0x00000047; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) +{ + return 0x00000048; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) +{ + return 0x00000049; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) +{ + return 0x0000004a; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) +{ + return 0x0000004b; +} +static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) +{ + return 0x0000004c; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) +{ + return 0x0000004d; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) +{ + return 0x0000004e; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) +{ + return 0x0000004f; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) +{ + return 0x00000050; +} +static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) +{ + return 0x00000051; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) +{ + return 0x00000052; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) +{ + return 0x00000053; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) +{ + return 0x00000054; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) +{ + return 0x00000055; +} +static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) +{ + return 0x00000056; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) +{ + return 0x00000057; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) +{ + return 0x00000058; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) +{ + return 0x00000059; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) +{ + return 0x0000005a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) +{ + return 0x0000005b; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) +{ + return 0x0000005c; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) +{ + return 0x0000005d; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) +{ + return 0x0000005e; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) +{ + return 0x00000063; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) +{ + return 0x00000064; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) +{ + return 0x00000065; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) +{ + return 0x00000066; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) +{ + return 0x00000067; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) +{ + return 0x00000068; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) +{ + return 0x00000069; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) +{ + return 0x0000006a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) +{ + return 0x0000006f; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) +{ + return 0x00000070; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) +{ + return 0x00000071; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) +{ + return 0x00000072; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) +{ + return 0x00000073; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) +{ + return 0x00000074; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) +{ + return 0x00000075; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) +{ + return 0x00000076; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) +{ + return 0x00000077; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) +{ + return 0x00000078; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) +{ + return 0x00000079; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) +{ + return 0x0000007a; +} +static inline u32 gmmu_pte_kind_zf32_v(void) +{ + return 0x0000007b; +} +static inline u32 gmmu_pte_kind_zf32_1z_v(void) +{ + return 0x0000007c; +} +static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) +{ + return 0x0000007d; +} +static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) +{ + return 0x0000007e; +} +static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) +{ + return 0x0000007f; +} +static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) +{ + return 0x00000080; +} +static inline u32 gmmu_pte_kind_zf32_2cs_v(void) +{ + return 0x00000081; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) +{ + return 0x00000082; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) +{ + return 0x00000083; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) +{ + return 0x00000084; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) +{ + return 0x00000085; +} +static inline u32 gmmu_pte_kind_zf32_2cz_v(void) +{ + return 0x00000086; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) +{ + return 0x00000087; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) +{ + return 0x00000088; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) +{ + return 0x00000089; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) +{ + return 0x0000008a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) +{ + return 0x0000008b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) +{ + return 0x0000008c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) +{ + return 0x0000008d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) +{ + return 0x0000008e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x0000008f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x00000090; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x00000091; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x00000092; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x00000097; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x00000098; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x00000099; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x0000009a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x0000009b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x0000009c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x0000009d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x0000009e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x0000009f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000a0; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000a1; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000a2; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000a3; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000a4; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000a5; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000a6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) +{ + return 0x000000a7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) +{ + return 0x000000a8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) +{ + return 0x000000a9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) +{ + return 0x000000aa; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x000000ab; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x000000ac; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x000000ad; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x000000ae; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x000000b3; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x000000b4; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x000000b5; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x000000b6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x000000b7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x000000b8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x000000b9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x000000ba; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x000000bb; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000bc; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000bd; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000be; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000bf; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000c0; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000c1; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000c2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) +{ + return 0x000000c3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) +{ + return 0x000000c4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) +{ + return 0x000000c5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) +{ + return 0x000000c6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) +{ + return 0x000000c7; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) +{ + return 0x000000c8; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) +{ + return 0x000000ce; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) +{ + return 0x000000cf; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) +{ + return 0x000000d0; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) +{ + return 0x000000d1; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) +{ + return 0x000000d2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) +{ + return 0x000000d3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) +{ + return 0x000000d4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) +{ + return 0x000000d5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) +{ + return 0x000000d6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) +{ + return 0x000000d7; +} +static inline u32 gmmu_pte_kind_generic_16bx2_v(void) +{ + return 0x000000fe; +} +static inline u32 gmmu_pte_kind_c32_2c_v(void) +{ + return 0x000000d8; +} +static inline u32 gmmu_pte_kind_c32_2cbr_v(void) +{ + return 0x000000d9; +} +static inline u32 gmmu_pte_kind_c32_2cba_v(void) +{ + return 0x000000da; +} +static inline u32 gmmu_pte_kind_c32_2cra_v(void) +{ + return 0x000000db; +} +static inline u32 gmmu_pte_kind_c32_2bra_v(void) +{ + return 0x000000dc; +} +static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) +{ + return 0x000000dd; +} +static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) +{ + return 0x000000de; +} +static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) +{ + return 0x000000cc; +} +static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) +{ + return 0x000000df; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) +{ + return 0x000000e0; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) +{ + return 0x000000e1; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) +{ + return 0x000000e2; +} +static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) +{ + return 0x000000e3; +} +static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) +{ + return 0x0000002c; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) +{ + return 0x000000e4; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) +{ + return 0x000000e5; +} +static inline u32 gmmu_pte_kind_c64_2c_v(void) +{ + return 0x000000e6; +} +static inline u32 gmmu_pte_kind_c64_2cbr_v(void) +{ + return 0x000000e7; +} +static inline u32 gmmu_pte_kind_c64_2cba_v(void) +{ + return 0x000000e8; +} +static inline u32 gmmu_pte_kind_c64_2cra_v(void) +{ + return 0x000000e9; +} +static inline u32 gmmu_pte_kind_c64_2bra_v(void) +{ + return 0x000000ea; +} +static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) +{ + return 0x000000eb; +} +static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) +{ + return 0x000000ec; +} +static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) +{ + return 0x000000cd; +} +static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) +{ + return 0x000000ed; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) +{ + return 0x000000ee; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) +{ + return 0x000000ef; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) +{ + return 0x000000f0; +} +static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) +{ + return 0x000000f1; +} +static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) +{ + return 0x0000002d; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) +{ + return 0x000000f2; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) +{ + return 0x000000f3; +} +static inline u32 gmmu_pte_kind_c128_2c_v(void) +{ + return 0x000000f4; +} +static inline u32 gmmu_pte_kind_c128_2cr_v(void) +{ + return 0x000000f5; +} +static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) +{ + return 0x000000f6; +} +static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) +{ + return 0x000000f7; +} +static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) +{ + return 0x000000f8; +} +static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) +{ + return 0x000000f9; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) +{ + return 0x000000fa; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) +{ + return 0x000000fb; +} +static inline u32 gmmu_pte_kind_x8c24_v(void) +{ + return 0x000000fc; +} +static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) +{ + return 0x000000fd; +} +static inline u32 gmmu_pte_kind_smsked_message_v(void) +{ + return 0x000000ca; +} +static inline u32 gmmu_pte_kind_smhost_message_v(void) +{ + return 0x000000cb; +} +static inline u32 gmmu_pte_kind_s8_v(void) +{ + return 0x0000002a; +} +static inline u32 gmmu_pte_kind_s8_2s_v(void) +{ + return 0x0000002b; +} +static inline u32 gmmu_fault_client_type_gpc_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_fault_client_type_hub_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_fault_type_unbound_inst_block_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) +{ + return 0x0000000f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h new file mode 100644 index 00000000..af1915b2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -0,0 +1,3905 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gr_gv100_h_ +#define _hw_gr_gv100_h_ + +static inline u32 gr_intr_r(void) +{ + return 0x00400100; +} +static inline u32 gr_intr_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_notify_reset_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_semaphore_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_semaphore_reset_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_illegal_method_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_method_reset_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_notify_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_illegal_notify_reset_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_firmware_method_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_intr_firmware_method_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_firmware_method_reset_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_illegal_class_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_illegal_class_reset_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_fecs_error_pending_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_fecs_error_reset_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_class_error_pending_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_class_error_reset_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_exception_pending_f(void) +{ + return 0x200000; +} +static inline u32 gr_intr_exception_reset_f(void) +{ + return 0x200000; +} +static inline u32 gr_fecs_intr_r(void) +{ + return 0x00400144; +} +static inline u32 gr_class_error_r(void) +{ + return 0x00400110; +} +static inline u32 gr_class_error_code_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_intr_nonstall_r(void) +{ + return 0x00400120; +} +static inline u32 gr_intr_nonstall_trap_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_en_r(void) +{ + return 0x0040013c; +} +static inline u32 gr_exception_r(void) +{ + return 0x00400108; +} +static inline u32 gr_exception_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception_sked_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_exception1_r(void) +{ + return 0x00400118; +} +static inline u32 gr_exception1_gpc_0_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_exception2_r(void) +{ + return 0x0040011c; +} +static inline u32 gr_exception_en_r(void) +{ + return 0x00400138; +} +static inline u32 gr_exception_en_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception_en_fe_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_exception_en_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception_en_gpc_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 gr_exception_en_memfmt_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_exception_en_memfmt_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_exception_en_ds_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_exception_en_ds_enabled_f(void) +{ + return 0x10; +} +static inline u32 gr_exception1_en_r(void) +{ + return 0x00400130; +} +static inline u32 gr_exception2_en_r(void) +{ + return 0x00400134; +} +static inline u32 gr_gpfifo_ctl_r(void) +{ + return 0x00400500; +} +static inline u32 gr_gpfifo_ctl_access_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpfifo_ctl_access_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpfifo_ctl_access_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpfifo_status_r(void) +{ + return 0x00400504; +} +static inline u32 gr_trapped_addr_r(void) +{ + return 0x00400704; +} +static inline u32 gr_trapped_addr_mthd_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 gr_trapped_addr_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 gr_trapped_data_lo_r(void) +{ + return 0x00400708; +} +static inline u32 gr_trapped_data_hi_r(void) +{ + return 0x0040070c; +} +static inline u32 gr_status_r(void) +{ + return 0x00400700; +} +static inline u32 gr_status_fe_method_upper_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_status_fe_method_lower_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_status_fe_method_lower_idle_v(void) +{ + return 0x00000000; +} +static inline u32 gr_status_fe_gi_v(u32 r) +{ + return (r >> 21) & 0x1; +} +static inline u32 gr_status_mask_r(void) +{ + return 0x00400610; +} +static inline u32 gr_status_1_r(void) +{ + return 0x00400604; +} +static inline u32 gr_status_2_r(void) +{ + return 0x00400608; +} +static inline u32 gr_engine_status_r(void) +{ + return 0x0040060c; +} +static inline u32 gr_engine_status_value_busy_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_be0_becs_be_exception_r(void) +{ + return 0x00410204; +} +static inline u32 gr_pri_be0_becs_be_exception_en_r(void) +{ + return 0x00410208; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) +{ + return 0x00502c94; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_activity_0_r(void) +{ + return 0x00400380; +} +static inline u32 gr_activity_1_r(void) +{ + return 0x00400384; +} +static inline u32 gr_activity_2_r(void) +{ + return 0x00400388; +} +static inline u32 gr_activity_4_r(void) +{ + return 0x00400390; +} +static inline u32 gr_activity_4_gpc0_s(void) +{ + return 3; +} +static inline u32 gr_activity_4_gpc0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_activity_4_gpc0_m(void) +{ + return 0x7 << 0; +} +static inline u32 gr_activity_4_gpc0_v(u32 r) +{ + return (r >> 0) & 0x7; +} +static inline u32 gr_activity_4_gpc0_empty_v(void) +{ + return 0x00000000; +} +static inline u32 gr_activity_4_gpc0_preempted_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pri_gpc0_gcc_dbg_r(void) +{ + return 0x00501000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_r(void) +{ + return 0x00419000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) +{ + return 0x0050433c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) +{ + return 0x00419b3c; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_sked_activity_r(void) +{ + return 0x00407054; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) +{ + return 0x00502c80; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) +{ + return 0x00502c84; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) +{ + return 0x00502c88; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) +{ + return 0x00502c8c; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x00504500; +} +static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x00504d00; +} +static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00501d00; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) +{ + return 0x0041ac80; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) +{ + return 0x0041ac84; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) +{ + return 0x0041ac88; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) +{ + return 0x0041ac8c; +} +static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x0041c500; +} +static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x0041cd00; +} +static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00419d00; +} +static inline u32 gr_pri_be0_becs_be_activity0_r(void) +{ + return 0x00410200; +} +static inline u32 gr_pri_be1_becs_be_activity0_r(void) +{ + return 0x00410600; +} +static inline u32 gr_pri_bes_becs_be_activity0_r(void) +{ + return 0x00408a00; +} +static inline u32 gr_pri_ds_mpipe_status_r(void) +{ + return 0x00405858; +} +static inline u32 gr_pri_fe_go_idle_info_r(void) +{ + return 0x00404194; +} +static inline u32 gr_pri_fe_chip_def_info_r(void) +{ + return 0x00404030; +} +static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) +{ + return 0x00000040; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) +{ + return 0x00504238; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) +{ + return 0x00504358; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) +{ + return 0x1 << 13; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) +{ + return 0x1 << 14; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) +{ + return 0x1 << 15; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 26) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) +{ + return 0x0050435c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) +{ + return 0x00504360; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) +{ + return 0x0050436c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) +{ + return 0x00504370; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) +{ + return 0x00504374; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) +{ + return 0x00504638; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) +{ + return (r >> 18) & 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) +{ + return 0x0050463c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) +{ + return 0x00504640; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) +{ + return 0x005042c4; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) +{ + return 0x0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) +{ + return 0x00504430; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) +{ + return 0x00504434; +} +static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_pri_be0_crop_status1_r(void) +{ + return 0x00410134; +} +static inline u32 gr_pri_bes_crop_status1_r(void) +{ + return 0x00408934; +} +static inline u32 gr_pri_be0_zrop_status_r(void) +{ + return 0x00410048; +} +static inline u32 gr_pri_be0_zrop_status2_r(void) +{ + return 0x0041004c; +} +static inline u32 gr_pri_bes_zrop_status_r(void) +{ + return 0x00408848; +} +static inline u32 gr_pri_bes_zrop_status2_r(void) +{ + return 0x0040884c; +} +static inline u32 gr_pipe_bundle_address_r(void) +{ + return 0x00400200; +} +static inline u32 gr_pipe_bundle_address_value_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pipe_bundle_address_veid_f(u32 v) +{ + return (v & 0x3f) << 20; +} +static inline u32 gr_pipe_bundle_address_veid_w(void) +{ + return 0; +} +static inline u32 gr_pipe_bundle_data_r(void) +{ + return 0x00400204; +} +static inline u32 gr_pipe_bundle_config_r(void) +{ + return 0x00400208; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fe_hww_esr_r(void) +{ + return 0x00404000; +} +static inline u32 gr_fe_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_fe_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) +{ + return 0x00419eac; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) +{ + return 0x0050472c; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) +{ + return 0x00419eb4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) +{ + return 0x00504734; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_fe_go_idle_timeout_r(void) +{ + return 0x00404154; +} +static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) +{ + return 0x1800; +} +static inline u32 gr_fe_object_table_r(u32 i) +{ + return 0x00404200 + i*4; +} +static inline u32 gr_fe_object_table_nvclass_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fe_tpc_fs_r(u32 i) +{ + return 0x0040a200 + i*4; +} +static inline u32 gr_pri_mme_shadow_raw_index_r(void) +{ + return 0x00404488; +} +static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pri_mme_shadow_raw_data_r(void) +{ + return 0x0040448c; +} +static inline u32 gr_mme_hww_esr_r(void) +{ + return 0x00404490; +} +static inline u32 gr_mme_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_mme_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_memfmt_hww_esr_r(void) +{ + return 0x00404600; +} +static inline u32 gr_memfmt_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_memfmt_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fecs_cpuctl_r(void) +{ + return 0x00409100; +} +static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_cpuctl_alias_r(void) +{ + return 0x00409130; +} +static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_dmactl_r(void) +{ + return 0x0040910c; +} +static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_fecs_os_r(void) +{ + return 0x00409080; +} +static inline u32 gr_fecs_idlestate_r(void) +{ + return 0x0040904c; +} +static inline u32 gr_fecs_mailbox0_r(void) +{ + return 0x00409040; +} +static inline u32 gr_fecs_mailbox1_r(void) +{ + return 0x00409044; +} +static inline u32 gr_fecs_irqstat_r(void) +{ + return 0x00409008; +} +static inline u32 gr_fecs_irqmode_r(void) +{ + return 0x0040900c; +} +static inline u32 gr_fecs_irqmask_r(void) +{ + return 0x00409018; +} +static inline u32 gr_fecs_irqdest_r(void) +{ + return 0x0040901c; +} +static inline u32 gr_fecs_curctx_r(void) +{ + return 0x00409050; +} +static inline u32 gr_fecs_nxtctx_r(void) +{ + return 0x00409054; +} +static inline u32 gr_fecs_engctl_r(void) +{ + return 0x004090a4; +} +static inline u32 gr_fecs_debug1_r(void) +{ + return 0x00409090; +} +static inline u32 gr_fecs_debuginfo_r(void) +{ + return 0x00409094; +} +static inline u32 gr_fecs_icd_cmd_r(void) +{ + return 0x00409200; +} +static inline u32 gr_fecs_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 gr_fecs_icd_rdata_r(void) +{ + return 0x0040920c; +} +static inline u32 gr_fecs_imemc_r(u32 i) +{ + return 0x00409180 + i*16; +} +static inline u32 gr_fecs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_imemd_r(u32 i) +{ + return 0x00409184 + i*16; +} +static inline u32 gr_fecs_imemt_r(u32 i) +{ + return 0x00409188 + i*16; +} +static inline u32 gr_fecs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_dmemc_r(u32 i) +{ + return 0x004091c0 + i*8; +} +static inline u32 gr_fecs_dmemc_offs_s(void) +{ + return 6; +} +static inline u32 gr_fecs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 gr_fecs_dmemc_offs_v(u32 r) +{ + return (r >> 2) & 0x3f; +} +static inline u32 gr_fecs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_dmemd_r(u32 i) +{ + return 0x004091c4 + i*8; +} +static inline u32 gr_fecs_dmatrfbase_r(void) +{ + return 0x00409110; +} +static inline u32 gr_fecs_dmatrfmoffs_r(void) +{ + return 0x00409114; +} +static inline u32 gr_fecs_dmatrffboffs_r(void) +{ + return 0x0040911c; +} +static inline u32 gr_fecs_dmatrfcmd_r(void) +{ + return 0x00409118; +} +static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_fecs_bootvec_r(void) +{ + return 0x00409104; +} +static inline u32 gr_fecs_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_falcon_hwcfg_r(void) +{ + return 0x00409108; +} +static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) +{ + return 0x0041a108; +} +static inline u32 gr_fecs_falcon_rm_r(void) +{ + return 0x00409084; +} +static inline u32 gr_fecs_current_ctx_r(void) +{ + return 0x00409b00; +} +static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_current_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_current_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_current_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_current_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) +{ + return 0x20000000; +} +static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 gr_fecs_current_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_current_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_current_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_current_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_current_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_method_data_r(void) +{ + return 0x00409500; +} +static inline u32 gr_fecs_method_push_r(void) +{ + return 0x00409504; +} +static inline u32 gr_fecs_method_push_adr_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) +{ + return 0x00000003; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) +{ + return 0x3; +} +static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) +{ + return 0x00000009; +} +static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) +{ + return 0x00000015; +} +static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) +{ + return 0x00000016; +} +static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) +{ + return 0x00000025; +} +static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) +{ + return 0x00000030; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) +{ + return 0x00000031; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) +{ + return 0x00000032; +} +static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) +{ + return 0x00000038; +} +static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) +{ + return 0x00000039; +} +static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) +{ + return 0x21; +} +static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) +{ + return 0x0000001a; +} +static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) +{ + return 0x00000004; +} +static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) +{ + return 0x0000003a; +} +static inline u32 gr_fecs_host_int_status_r(void) +{ + return 0x00409c18; +} +static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_host_int_clear_r(void) +{ + return 0x00409c20; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_r(void) +{ + return 0x00409c24; +} +static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) +{ + return 0x10000; +} +static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) +{ + return 0x20000; +} +static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) +{ + return 0x40000; +} +static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) +{ + return 0x80000; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) +{ + return 0x00409614; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) +{ + return 0x10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) +{ + return 0x20; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) +{ + return 0x40; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) +{ + return 0x100; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) +{ + return 0x200; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) +{ + return 0x400; +} +static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) +{ + return 0x0040960c; +} +static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) +{ + return 0x00409800 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) +{ + return 0x00000001; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) +{ + return 0x00000002; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) +{ + return 0x004098c0 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) +{ + return 0x00409840 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_fs_r(void) +{ + return 0x00409604; +} +static inline u32 gr_fecs_fs_num_available_gpcs_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_fs_num_available_fbps_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_m(void) +{ + return 0x1f << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_fecs_cfg_r(void) +{ + return 0x00409620; +} +static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_fecs_rc_lanes_r(void) +{ + return 0x00409880; +} +static inline u32 gr_fecs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_fecs_ctxsw_status_1_r(void) +{ + return 0x00409400; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_adr_r(void) +{ + return 0x00409a24; +} +static inline u32 gr_fecs_new_ctx_r(void) +{ + return 0x00409b04; +} +static inline u32 gr_fecs_new_ctx_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_new_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_new_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_new_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_new_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_new_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_new_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_new_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_new_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_ptr_r(void) +{ + return 0x00409a0c; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_arb_ctx_cmd_r(void) +{ + return 0x00409a10; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) +{ + return 5; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) +{ + return 0x00409c00; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) +{ + return 0x00502c04; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) +{ + return 0x00502400; +} +static inline u32 gr_fecs_ctxsw_idlestate_r(void) +{ + return 0x00409420; +} +static inline u32 gr_fecs_feature_override_ecc_r(void) +{ + return 0x00409658; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) +{ + return 0x00502420; +} +static inline u32 gr_rstr2d_gpc_map_r(u32 i) +{ + return 0x0040780c + i*4; +} +static inline u32 gr_rstr2d_map_table_cfg_r(void) +{ + return 0x004078bc; +} +static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_hww_esr_r(void) +{ + return 0x00406018; +} +static inline u32 gr_pd_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pd_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) +{ + return 0x00406028 + i*4; +} +static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) +{ + return (v & 0xf) << 24; +} +static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) +{ + return (v & 0xf) << 28; +} +static inline u32 gr_pd_ab_dist_cfg0_r(void) +{ + return 0x004064c0; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) +{ + return 0x0; +} +static inline u32 gr_pd_ab_dist_cfg1_r(void) +{ + return 0x004064c4; +} +static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) +{ + return 0xffff; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) +{ + return 0x00000080; +} +static inline u32 gr_pd_ab_dist_cfg2_r(void) +{ + return 0x004064c8; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) +{ + return (v & 0x1fff) << 0; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) +{ + return 0x00001680; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) +{ + return (v & 0x1fff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) +{ + return 0x00001680; +} +static inline u32 gr_pd_dist_skip_table_r(u32 i) +{ + return 0x004064d0 + i*4; +} +static inline u32 gr_pd_dist_skip_table__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_ds_debug_r(void) +{ + return 0x00405800; +} +static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) +{ + return 0x8000000; +} +static inline u32 gr_ds_zbc_color_r_r(void) +{ + return 0x00405804; +} +static inline u32 gr_ds_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_g_r(void) +{ + return 0x00405808; +} +static inline u32 gr_ds_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_b_r(void) +{ + return 0x0040580c; +} +static inline u32 gr_ds_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_a_r(void) +{ + return 0x00405810; +} +static inline u32 gr_ds_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_r(void) +{ + return 0x00405814; +} +static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) +{ + return (v & 0x7f) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) +{ + return 0x00000002; +} +static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) +{ + return 0x00000004; +} +static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) +{ + return 0x00000028; +} +static inline u32 gr_ds_zbc_z_r(void) +{ + return 0x00405818; +} +static inline u32 gr_ds_zbc_z_val_s(void) +{ + return 32; +} +static inline u32 gr_ds_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_z_val_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_ds_zbc_z_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_ds_zbc_z_val__init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_ds_zbc_z_val__init_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_r(void) +{ + return 0x0040581c; +} +static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_tbl_index_r(void) +{ + return 0x00405820; +} +static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_ds_zbc_tbl_ld_r(void) +{ + return 0x00405824; +} +static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_tga_constraintlogic_beta_r(void) +{ + return 0x00405830; +} +static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) +{ + return 0x0040585c; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_ds_hww_esr_r(void) +{ + return 0x00405840; +} +static inline u32 gr_ds_hww_esr_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_esr_2_r(void) +{ + return 0x00405848; +} +static inline u32 gr_ds_hww_esr_2_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_2_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_2_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_report_mask_r(void) +{ + return 0x00405844; +} +static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) +{ + return 0x2; +} +static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) +{ + return 0x8; +} +static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) +{ + return 0x10; +} +static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) +{ + return 0x20; +} +static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) +{ + return 0x40; +} +static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) +{ + return 0x80; +} +static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) +{ + return 0x100; +} +static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) +{ + return 0x200; +} +static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) +{ + return 0x400; +} +static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) +{ + return 0x800; +} +static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) +{ + return 0x1000; +} +static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) +{ + return 0x20000; +} +static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) +{ + return 0x80000; +} +static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) +{ + return 0x100000; +} +static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) +{ + return 0x200000; +} +static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_ds_hww_report_mask_2_r(void) +{ + return 0x0040584c; +} +static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) +{ + return 0x00405870 + i*4; +} +static inline u32 gr_scc_bundle_cb_base_r(void) +{ + return 0x00408004; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_bundle_cb_size_r(void) +{ + return 0x00408008; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) +{ + return 0x00000030; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_pagepool_base_r(void) +{ + return 0x0040800c; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_pagepool_r(void) +{ + return 0x00408010; +} +static inline u32 gr_scc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) +{ + return 0x00000200; +} +static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_pagepool_max_valid_pages_s(void) +{ + return 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) +{ + return (v & 0x3ff) << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_m(void) +{ + return 0x3ff << 10; +} +static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) +{ + return (r >> 10) & 0x3ff; +} +static inline u32 gr_scc_pagepool_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_init_r(void) +{ + return 0x0040802c; +} +static inline u32 gr_scc_init_ram_trigger_f(void) +{ + return 0x1; +} +static inline u32 gr_scc_hww_esr_r(void) +{ + return 0x00408030; +} +static inline u32 gr_scc_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_scc_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_sked_hww_esr_r(void) +{ + return 0x00407020; +} +static inline u32 gr_sked_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_sked_hww_esr_en_r(void) +{ + return 0x00407024; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) +{ + return 0x1 << 25; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 gr_cwd_fs_r(void) +{ + return 0x00405b00; +} +static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) +{ + return 0x00405b60 + i*4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) +{ + return 4; +} +static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_cwd_sm_id_r(u32 i) +{ + return 0x00405ba0 + i*4; +} +static inline u32 gr_cwd_sm_id__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpc0_fs_gpc_r(void) +{ + return 0x00502608; +} +static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_gpc0_cfg_r(void) +{ + return 0x00502620; +} +static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpccs_rc_lanes_r(void) +{ + return 0x00502880; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_rc_lane_size_r(void) +{ + return 0x00502910; +} +static inline u32 gr_gpccs_rc_lane_size_v_s(void) +{ + return 24; +} +static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_m(void) +{ + return 0xffffff << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_zcull_fs_r(void) +{ + return 0x00500910; +} +static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_gpc0_zcull_ram_addr_r(void) +{ + return 0x00500914; +} +static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) +{ + return 0x00500918; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) +{ + return 0x00800000; +} +static inline u32 gr_gpc0_zcull_total_ram_size_r(void) +{ + return 0x00500920; +} +static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) +{ + return 0x00500a04 + i*32; +} +static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) +{ + return 0x00000040; +} +static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) +{ + return 0x00000010; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) +{ + return 0x00500c10 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) +{ + return 0x00500c30 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) +{ + return 0x00504088; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) +{ + return 0x00504608; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_r(void) +{ + return 0x00504330; +} +static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) +{ + return (r >> 8) & 0xfff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) +{ + return (r >> 20) & 0xfff; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) +{ + return 0x00503018; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) +{ + return 0x005030c0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) +{ + return 0x00000480; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) +{ + return 0x00000d10; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) +{ + return 0x005030f4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) +{ + return 0x005030e4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) +{ + return 0x005030f8; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) +{ + return 0x005030f0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) +{ + return 0x00000480; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) +{ + return 0x00419e00; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) +{ + return 0x00419e04; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) +{ + return 21; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) +{ + return (v & 0x1fffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) +{ + return 0x1fffff << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) +{ + return (r >> 0) & 0x1fffff; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) +{ + return 0x80; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpccs_falcon_addr_r(void) +{ + return 0x0041a0ac; +} +static inline u32 gr_gpccs_falcon_addr_lsb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_msb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_m(void) +{ + return 0x3f << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) +{ + return (r >> 6) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_ext_s(void) +{ + return 12; +} +static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_m(void) +{ + return 0xfff << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_gpccs_cpuctl_r(void) +{ + return 0x0041a100; +} +static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpccs_dmactl_r(void) +{ + return 0x0041a10c; +} +static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpccs_imemc_r(u32 i) +{ + return 0x0041a180 + i*16; +} +static inline u32 gr_gpccs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_imemd_r(u32 i) +{ + return 0x0041a184 + i*16; +} +static inline u32 gr_gpccs_imemt_r(u32 i) +{ + return 0x0041a188 + i*16; +} +static inline u32 gr_gpccs_imemt__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_gpccs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpccs_dmemc_r(u32 i) +{ + return 0x0041a1c0 + i*8; +} +static inline u32 gr_gpccs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_dmemd_r(u32 i) +{ + return 0x0041a1c4 + i*8; +} +static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) +{ + return 0x0041a800 + i*4; +} +static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) +{ + return 0x00418e24; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) +{ + return 32; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) +{ + return 0x00418e28; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) +{ + return 11; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) +{ + return 0x7ff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) +{ + return (r >> 0) & 0x7ff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) +{ + return 0x00000030; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) +{ + return 0x30; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) +{ + return 0x005001dc; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) +{ + return 0x000004b0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) +{ + return 0x005001d8; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) +{ + return 0x004181e4; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) +{ + return 0x0041befc; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) +{ + return 0x00418ea0 + i*4; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) +{ + return 0x00418010 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) +{ + return 0x0041804c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) +{ + return 0x00418088 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) +{ + return 0x004180c4 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) +{ + return 0x00418100; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) +{ + return 0x00418110 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) +{ + return 0x0041814c; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) +{ + return 0x0041815c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) +{ + return 0x00418198; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) +{ + return 0x00418810; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) +{ + return 0x0000000c; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_crstr_gpc_map_r(u32 i) +{ + return 0x00418b08 + i*4; +} +static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) +{ + return (v & 0x1f) << 5; +} +static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) +{ + return (v & 0x1f) << 10; +} +static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) +{ + return (v & 0x1f) << 20; +} +static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) +{ + return (v & 0x1f) << 25; +} +static inline u32 gr_crstr_map_table_cfg_r(void) +{ + return 0x00418bb8; +} +static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) +{ + return 0x00418980 + i*4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_gpm_pd_cfg_r(void) +{ + return 0x00418c6c; +} +static inline u32 gr_gpcs_gcc_pagepool_base_r(void) +{ + return 0x00419004; +} +static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_gcc_pagepool_r(void) +{ + return 0x00419008; +} +static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) +{ + return 0x0041980c; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) +{ + return 0x00419848; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) +{ + return 0x00419c00; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) +{ + return 0x00419c2c; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) +{ + return 0x00419ea8; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) +{ + return 0x00504728; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +{ + return 0x200; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +{ + return 0x800; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) +{ + return 0x00419d0c; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) +{ + return 0x0041ac94; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) +{ + return 0x00504704; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) +{ + return 0x00504708; +} +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) +{ + return 0x0050470c; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) +{ + return 0x00504710; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00504714; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) +{ + return 0x00504718; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) +{ + return 0x0050471c; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) +{ + return 0x00419e90; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00419e94; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) +{ + return 0x00419e80; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) +{ + return 0x00504700; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) +{ + return 0x00504730; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) +{ + return 0xff << 16; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) +{ + return 0xf << 24; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) +{ + return 0x0050460c; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) +{ + return 0x00504738; +} +static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) +{ + return 0x005043a0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) +{ + return 0x00419ba0; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) +{ + return 0x005043b0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) +{ + return 0x00419bb0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) +{ + return 0x0041be08; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) +{ + return 0x4; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) +{ + return 0x0041bf00 + i*4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) +{ + return 0x0041bfd0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) +{ + return (v & 0x7) << 21; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) +{ + return 0x0041bfd4; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) +{ + return 0x0041bfb0 + i*4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) +{ + return 0x00000005; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_bes_zrop_settings_r(void) +{ + return 0x00408850; +} +static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_be0_crop_debug3_r(void) +{ + return 0x00410108; +} +static inline u32 gr_bes_crop_debug3_r(void) +{ + return 0x00408908; +} +static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) +{ + return 0x4; +} +static inline u32 gr_bes_crop_settings_r(void) +{ + return 0x00408958; +} +static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) +{ + return 0x000000c0; +} +static inline u32 gr_zcull_subregion_qty_v(void) +{ + return 0x00000010; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) +{ + return 0x00419a00; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) +{ + return 0x1 << 19; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) +{ + return 0x00419bf0; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fe_pwr_mode_r(void) +{ + return 0x00404170; +} +static inline u32 gr_fe_pwr_mode_mode_auto_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) +{ + return 0x2; +} +static inline u32 gr_fe_pwr_mode_req_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_fe_pwr_mode_req_send_f(void) +{ + return 0x10; +} +static inline u32 gr_fe_pwr_mode_req_done_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) +{ + return 0x00418880; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) +{ + return 0x3 << 3; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) +{ + return 0x3 << 5; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) +{ + return 0x00418890; +} +static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) +{ + return 0x00418894; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) +{ + return 0x004188b0; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) +{ + return 0x004188b4; +} +static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) +{ + return 0x004188b8; +} +static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) +{ + return 0x004188ac; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) +{ + return 0x00419e84; +} +static inline u32 gr_fe_gfxp_wfi_timeout_r(void) +{ + return 0x004041c0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) +{ + return 0x00419bd8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) +{ + return 0x7 << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) +{ + return 0x00419ba4; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) +{ + return 0x3 << 11; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) +{ + return 0x1000; +} +static inline u32 gr_gpcs_tc_debug0_r(void) +{ + return 0x00418708; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) +{ + return 0x1ff << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h new file mode 100644 index 00000000..f1d977d4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h @@ -0,0 +1,613 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ltc_gv100_h_ +#define _hw_ltc_gv100_h_ + +static inline u32 ltc_pltcg_base_v(void) +{ + return 0x00140000; +} +static inline u32 ltc_pltcg_extent_v(void) +{ + return 0x0017ffff; +} +static inline u32 ltc_ltc0_ltss_v(void) +{ + return 0x00140200; +} +static inline u32 ltc_ltc0_lts0_v(void) +{ + return 0x00140400; +} +static inline u32 ltc_ltcs_ltss_v(void) +{ + return 0x0017e200; +} +static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) +{ + return 0x00140518; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) +{ + return 0x0017e318; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) +{ + return 0x1 << 15; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) +{ + return 0x00140494; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) +{ + return (r >> 16) & 0x3; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) +{ + return 0x00000000; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) +{ + return 0x00000002; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) +{ + return 0x0017e26c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) +{ + return 0x2; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) +{ + return 0x4; +} +static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) +{ + return 0x0017e270; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) +{ + return 0x0017e274; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) +{ + return (v & 0x3ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) +{ + return 0x0003ffff; +} +static inline u32 ltc_ltcs_ltss_cbc_base_r(void) +{ + return 0x0017e278; +} +static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) +{ + return (r >> 0) & 0x3ffffff; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) +{ + return 0x0017e27c; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) +{ + return (r >> 25) & 0x1; +} +static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) +{ + return 0x0017e000; +} +static inline u32 ltc_ltcs_ltss_cbc_param_r(void) +{ + return 0x0017e280; +} +static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) +{ + return (r >> 28) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) +{ + return 0x0017e3f4; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) +{ + return 0x0017e2ac; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) +{ + return 0x0017e338; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) +{ + return 0x0017e33c + i*4; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) +{ + return 0x0017e34c; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) +{ + return 32; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) +{ + return 0x0017e204; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) +{ + return 8; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) +{ + return 0x0017e2b0; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_g_elpg_r(void) +{ + return 0x0017e214; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_r(void) +{ + return 0x00140214; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_r(void) +{ + return 0x00142214; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_intr_r(void) +{ + return 0x0017e20c; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) +{ + return 0x100; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) +{ + return 0x200; +} +static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) +{ + return 0x1 << 20; +} +static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) +{ + return 0x1 << 30; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) +{ + return 0x2000000; +} +static inline u32 ltc_ltc0_lts0_intr_r(void) +{ + return 0x0014040c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) +{ + return 0x0014051c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) +{ + return 0xff << 16; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) +{ + return 0x0017e2a0; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) +{ + return 0x0017e2a4; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) +{ + return 0x10000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) +{ + return 0x001402a0; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) +{ + return 0x001402a4; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) +{ + return 0x001422a0; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) +{ + return 0x001422a4; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) +{ + return 0x0014058c; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h new file mode 100644 index 00000000..0cd59c3b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_mc_gv100_h_ +#define _hw_mc_gv100_h_ + +static inline u32 mc_boot_0_r(void) +{ + return 0x00000000; +} +static inline u32 mc_boot_0_architecture_v(u32 r) +{ + return (r >> 24) & 0x1f; +} +static inline u32 mc_boot_0_implementation_v(u32 r) +{ + return (r >> 20) & 0xf; +} +static inline u32 mc_boot_0_major_revision_v(u32 r) +{ + return (r >> 4) & 0xf; +} +static inline u32 mc_boot_0_minor_revision_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 mc_intr_r(u32 i) +{ + return 0x00000100 + i*4; +} +static inline u32 mc_intr_pfifo_pending_f(void) +{ + return 0x100; +} +static inline u32 mc_intr_hub_pending_f(void) +{ + return 0x200; +} +static inline u32 mc_intr_pgraph_pending_f(void) +{ + return 0x1000; +} +static inline u32 mc_intr_pmu_pending_f(void) +{ + return 0x1000000; +} +static inline u32 mc_intr_ltc_pending_f(void) +{ + return 0x2000000; +} +static inline u32 mc_intr_priv_ring_pending_f(void) +{ + return 0x40000000; +} +static inline u32 mc_intr_pbus_pending_f(void) +{ + return 0x10000000; +} +static inline u32 mc_intr_en_r(u32 i) +{ + return 0x00000140 + i*4; +} +static inline u32 mc_intr_en_set_r(u32 i) +{ + return 0x00000160 + i*4; +} +static inline u32 mc_intr_en_clear_r(u32 i) +{ + return 0x00000180 + i*4; +} +static inline u32 mc_enable_r(void) +{ + return 0x00000200; +} +static inline u32 mc_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_enable_l2_enabled_f(void) +{ + return 0x8; +} +static inline u32 mc_enable_pmedia_s(void) +{ + return 1; +} +static inline u32 mc_enable_pmedia_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 mc_enable_pmedia_m(void) +{ + return 0x1 << 4; +} +static inline u32 mc_enable_pmedia_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 mc_enable_ce0_m(void) +{ + return 0x1 << 6; +} +static inline u32 mc_enable_pfifo_enabled_f(void) +{ + return 0x100; +} +static inline u32 mc_enable_pgraph_enabled_f(void) +{ + return 0x1000; +} +static inline u32 mc_enable_pwr_v(u32 r) +{ + return (r >> 13) & 0x1; +} +static inline u32 mc_enable_pwr_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 mc_enable_pwr_enabled_f(void) +{ + return 0x2000; +} +static inline u32 mc_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_enable_ce2_m(void) +{ + return 0x1 << 21; +} +static inline u32 mc_enable_ce2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 mc_enable_blg_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 mc_enable_perfmon_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 mc_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 mc_intr_ltc_r(void) +{ + return 0x000001c0; +} +static inline u32 mc_enable_pb_r(void) +{ + return 0x00000204; +} +static inline u32 mc_enable_pb_0_s(void) +{ + return 1; +} +static inline u32 mc_enable_pb_0_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 mc_enable_pb_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 mc_enable_pb_0_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 mc_enable_pb_0_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 mc_elpg_enable_r(void) +{ + return 0x0000020c; +} +static inline u32 mc_elpg_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_elpg_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_elpg_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 mc_elpg_enable_l2_enabled_f(void) +{ + return 0x8; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h new file mode 100644 index 00000000..ab363e94 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h @@ -0,0 +1,645 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pbdma_gv100_h_ +#define _hw_pbdma_gv100_h_ + +static inline u32 pbdma_gp_entry1_r(void) +{ + return 0x10000004; +} +static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pbdma_gp_entry1_length_f(u32 v) +{ + return (v & 0x1fffff) << 10; +} +static inline u32 pbdma_gp_entry1_length_v(u32 r) +{ + return (r >> 10) & 0x1fffff; +} +static inline u32 pbdma_gp_base_r(u32 i) +{ + return 0x00040048 + i*8192; +} +static inline u32 pbdma_gp_base__size_1_v(void) +{ + return 0x0000000e; +} +static inline u32 pbdma_gp_base_offset_f(u32 v) +{ + return (v & 0x1fffffff) << 3; +} +static inline u32 pbdma_gp_base_rsvd_s(void) +{ + return 3; +} +static inline u32 pbdma_gp_base_hi_r(u32 i) +{ + return 0x0004004c + i*8192; +} +static inline u32 pbdma_gp_base_hi_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 pbdma_gp_fetch_r(u32 i) +{ + return 0x00040050 + i*8192; +} +static inline u32 pbdma_gp_get_r(u32 i) +{ + return 0x00040014 + i*8192; +} +static inline u32 pbdma_gp_put_r(u32 i) +{ + return 0x00040000 + i*8192; +} +static inline u32 pbdma_pb_fetch_r(u32 i) +{ + return 0x00040054 + i*8192; +} +static inline u32 pbdma_pb_fetch_hi_r(u32 i) +{ + return 0x00040058 + i*8192; +} +static inline u32 pbdma_get_r(u32 i) +{ + return 0x00040018 + i*8192; +} +static inline u32 pbdma_get_hi_r(u32 i) +{ + return 0x0004001c + i*8192; +} +static inline u32 pbdma_put_r(u32 i) +{ + return 0x0004005c + i*8192; +} +static inline u32 pbdma_put_hi_r(u32 i) +{ + return 0x00040060 + i*8192; +} +static inline u32 pbdma_pb_header_r(u32 i) +{ + return 0x00040084 + i*8192; +} +static inline u32 pbdma_pb_header_priv_user_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_method_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_subchannel_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_level_main_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_pb_header_type_inc_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_pb_header_type_non_inc_f(void) +{ + return 0x60000000; +} +static inline u32 pbdma_hdr_shadow_r(u32 i) +{ + return 0x00040118 + i*8192; +} +static inline u32 pbdma_subdevice_r(u32 i) +{ + return 0x00040094 + i*8192; +} +static inline u32 pbdma_subdevice_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 pbdma_subdevice_status_active_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_subdevice_channel_dma_enable_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_method0_r(u32 i) +{ + return 0x000400c0 + i*8192; +} +static inline u32 pbdma_method0_fifo_size_v(void) +{ + return 0x00000004; +} +static inline u32 pbdma_method0_addr_f(u32 v) +{ + return (v & 0xfff) << 2; +} +static inline u32 pbdma_method0_addr_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 pbdma_method0_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 pbdma_method0_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_method0_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_method1_r(u32 i) +{ + return 0x000400c8 + i*8192; +} +static inline u32 pbdma_method2_r(u32 i) +{ + return 0x000400d0 + i*8192; +} +static inline u32 pbdma_method3_r(u32 i) +{ + return 0x000400d8 + i*8192; +} +static inline u32 pbdma_data0_r(u32 i) +{ + return 0x000400c4 + i*8192; +} +static inline u32 pbdma_acquire_r(u32 i) +{ + return 0x00040030 + i*8192; +} +static inline u32 pbdma_acquire_retry_man_2_f(void) +{ + return 0x2; +} +static inline u32 pbdma_acquire_retry_exp_2_f(void) +{ + return 0x100; +} +static inline u32 pbdma_acquire_timeout_exp_f(u32 v) +{ + return (v & 0xf) << 11; +} +static inline u32 pbdma_acquire_timeout_exp_max_v(void) +{ + return 0x0000000f; +} +static inline u32 pbdma_acquire_timeout_exp_max_f(void) +{ + return 0x7800; +} +static inline u32 pbdma_acquire_timeout_man_f(u32 v) +{ + return (v & 0xffff) << 15; +} +static inline u32 pbdma_acquire_timeout_man_max_v(void) +{ + return 0x0000ffff; +} +static inline u32 pbdma_acquire_timeout_man_max_f(void) +{ + return 0x7fff8000; +} +static inline u32 pbdma_acquire_timeout_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_acquire_timeout_en_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_status_r(u32 i) +{ + return 0x00040100 + i*8192; +} +static inline u32 pbdma_channel_r(u32 i) +{ + return 0x00040120 + i*8192; +} +static inline u32 pbdma_signature_r(u32 i) +{ + return 0x00040010 + i*8192; +} +static inline u32 pbdma_signature_hw_valid_f(void) +{ + return 0xface; +} +static inline u32 pbdma_signature_sw_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_r(u32 i) +{ + return 0x00040008 + i*8192; +} +static inline u32 pbdma_userd_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 pbdma_userd_addr_f(u32 v) +{ + return (v & 0x7fffff) << 9; +} +static inline u32 pbdma_config_r(u32 i) +{ + return 0x000400f4 + i*8192; +} +static inline u32 pbdma_config_l2_evict_first_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_l2_evict_normal_f(void) +{ + return 0x1; +} +static inline u32 pbdma_config_l2_evict_last_f(void) +{ + return 0x2; +} +static inline u32 pbdma_config_ce_split_enable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_ce_split_disable_f(void) +{ + return 0x10; +} +static inline u32 pbdma_config_auth_level_non_privileged_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_auth_level_privileged_f(void) +{ + return 0x100; +} +static inline u32 pbdma_config_userd_writeback_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_config_userd_writeback_enable_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_userd_hi_r(u32 i) +{ + return 0x0004000c + i*8192; +} +static inline u32 pbdma_userd_hi_addr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_hce_ctrl_r(u32 i) +{ + return 0x000400e4 + i*8192; +} +static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_r(u32 i) +{ + return 0x00040108 + i*8192; +} +static inline u32 pbdma_intr_0_memreq_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pbdma_intr_0_memreq_pending_f(void) +{ + return 0x1; +} +static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) +{ + return 0x2; +} +static inline u32 pbdma_intr_0_memack_extra_pending_f(void) +{ + return 0x4; +} +static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) +{ + return 0x8; +} +static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) +{ + return 0x10; +} +static inline u32 pbdma_intr_0_memflush_pending_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_memop_pending_f(void) +{ + return 0x40; +} +static inline u32 pbdma_intr_0_lbconnect_pending_f(void) +{ + return 0x80; +} +static inline u32 pbdma_intr_0_lbreq_pending_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) +{ + return 0x200; +} +static inline u32 pbdma_intr_0_lback_extra_pending_f(void) +{ + return 0x400; +} +static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) +{ + return 0x800; +} +static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_intr_0_gpfifo_pending_f(void) +{ + return 0x2000; +} +static inline u32 pbdma_intr_0_gpptr_pending_f(void) +{ + return 0x4000; +} +static inline u32 pbdma_intr_0_gpentry_pending_f(void) +{ + return 0x8000; +} +static inline u32 pbdma_intr_0_gpcrc_pending_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_intr_0_pbptr_pending_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_intr_0_pbentry_pending_f(void) +{ + return 0x40000; +} +static inline u32 pbdma_intr_0_pbcrc_pending_f(void) +{ + return 0x80000; +} +static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) +{ + return 0x100000; +} +static inline u32 pbdma_intr_0_method_pending_f(void) +{ + return 0x200000; +} +static inline u32 pbdma_intr_0_methodcrc_pending_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_intr_0_device_pending_f(void) +{ + return 0x800000; +} +static inline u32 pbdma_intr_0_eng_reset_pending_f(void) +{ + return 0x1000000; +} +static inline u32 pbdma_intr_0_semaphore_pending_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_intr_0_acquire_pending_f(void) +{ + return 0x4000000; +} +static inline u32 pbdma_intr_0_pri_pending_f(void) +{ + return 0x8000000; +} +static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_intr_0_pbseg_pending_f(void) +{ + return 0x40000000; +} +static inline u32 pbdma_intr_0_signature_pending_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_intr_1_r(u32 i) +{ + return 0x00040148 + i*8192; +} +static inline u32 pbdma_intr_1_ctxnotvalid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_intr_en_0_r(u32 i) +{ + return 0x0004010c + i*8192; +} +static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_en_1_r(u32 i) +{ + return 0x0004014c + i*8192; +} +static inline u32 pbdma_intr_stall_r(u32 i) +{ + return 0x0004013c + i*8192; +} +static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_stall_1_r(u32 i) +{ + return 0x00040140 + i*8192; +} +static inline u32 pbdma_udma_nop_r(void) +{ + return 0x00000008; +} +static inline u32 pbdma_runlist_timeslice_r(u32 i) +{ + return 0x000400f8 + i*8192; +} +static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) +{ + return 0x80; +} +static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) +{ + return 0x3000; +} +static inline u32 pbdma_runlist_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_target_r(u32 i) +{ + return 0x000400ac + i*8192; +} +static inline u32 pbdma_target_engine_sw_f(void) +{ + return 0x1f; +} +static inline u32 pbdma_target_eng_ctx_valid_true_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_target_eng_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_ce_ctx_valid_true_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_target_ce_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) +{ + return 0x1000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) +{ + return 0x3000000; +} +static inline u32 pbdma_target_should_send_tsg_event_true_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_target_should_send_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_r(u32 i) +{ + return 0x000400fc + i*8192; +} +static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) +{ + return 0x0; +} +static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) +{ + return 0x1; +} +static inline u32 pbdma_set_channel_info_veid_f(u32 v) +{ + return (v & 0x3f) << 8; +} +static inline u32 pbdma_timeout_r(u32 i) +{ + return 0x0004012c + i*8192; +} +static inline u32 pbdma_timeout_period_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 pbdma_timeout_period_max_f(void) +{ + return 0xffffffff; +} +static inline u32 pbdma_timeout_period_init_f(void) +{ + return 0x10000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h new file mode 100644 index 00000000..f8e7c2a4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_perf_gv100_h_ +#define _hw_perf_gv100_h_ + +static inline u32 perf_pmasys_control_r(void) +{ + return 0x0024a000; +} +static inline u32 perf_pmasys_control_membuf_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) +{ + return 0x10; +} +static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) +{ + return 0x20; +} +static inline u32 perf_pmasys_mem_block_r(void) +{ + return 0x0024a070; +} +static inline u32 perf_pmasys_mem_block_base_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 perf_pmasys_mem_block_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 perf_pmasys_mem_block_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 perf_pmasys_mem_block_target_lfb_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_target_lfb_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 perf_pmasys_mem_block_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 perf_pmasys_mem_block_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 perf_pmasys_mem_block_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_mem_block_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_outbase_r(void) +{ + return 0x0024a074; +} +static inline u32 perf_pmasys_outbase_ptr_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_outbaseupper_r(void) +{ + return 0x0024a078; +} +static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 perf_pmasys_outsize_r(void) +{ + return 0x0024a07c; +} +static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_mem_bytes_r(void) +{ + return 0x0024a084; +} +static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_mem_bump_r(void) +{ + return 0x0024a088; +} +static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_enginestatus_r(void) +{ + return 0x0024a0a4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) +{ + return 0x10; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h new file mode 100644 index 00000000..88c70f53 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pram_gv100_h_ +#define _hw_pram_gv100_h_ + +static inline u32 pram_data032_r(u32 i) +{ + return 0x00700000 + i*4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h new file mode 100644 index 00000000..197fe550 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringmaster_gv100_h_ +#define _hw_pri_ringmaster_gv100_h_ + +static inline u32 pri_ringmaster_command_r(void) +{ + return 0x0012004c; +} +static inline u32 pri_ringmaster_command_cmd_m(void) +{ + return 0x3f << 0; +} +static inline u32 pri_ringmaster_command_cmd_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) +{ + return 0x00000000; +} +static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) +{ + return 0x2; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) +{ + return 0x3; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_command_data_r(void) +{ + return 0x00120048; +} +static inline u32 pri_ringmaster_start_results_r(void) +{ + return 0x00120050; +} +static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) +{ + return 0x00000001; +} +static inline u32 pri_ringmaster_intr_status0_r(void) +{ + return 0x00120058; +} +static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 pri_ringmaster_intr_status1_r(void) +{ + return 0x0012005c; +} +static inline u32 pri_ringmaster_global_ctl_r(void) +{ + return 0x00120060; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_enum_fbp_r(void) +{ + return 0x00120074; +} +static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_gpc_r(void) +{ + return 0x00120078; +} +static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_ltc_r(void) +{ + return 0x0012006c; +} +static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h new file mode 100644 index 00000000..eb77b4c0 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_gpc_gv100_h_ +#define _hw_pri_ringstation_gpc_gv100_h_ + +static inline u32 pri_ringstation_gpc_master_config_r(u32 i) +{ + return 0x00128300 + i*4; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) +{ + return 0x00128120; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) +{ + return 0x00128124; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) +{ + return 0x00128128; +} +static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) +{ + return 0x0012812c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h new file mode 100644 index 00000000..27feb5e9 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_sys_gv100_h_ +#define _hw_pri_ringstation_sys_gv100_h_ + +static inline u32 pri_ringstation_sys_master_config_r(u32 i) +{ + return 0x00122300 + i*4; +} +static inline u32 pri_ringstation_sys_decode_config_r(void) +{ + return 0x00122204; +} +static inline u32 pri_ringstation_sys_decode_config_ring_m(void) +{ + return 0x7 << 0; +} +static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) +{ + return 0x1; +} +static inline u32 pri_ringstation_sys_priv_error_adr_r(void) +{ + return 0x00122120; +} +static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) +{ + return 0x00122124; +} +static inline u32 pri_ringstation_sys_priv_error_info_r(void) +{ + return 0x00122128; +} +static inline u32 pri_ringstation_sys_priv_error_code_r(void) +{ + return 0x0012212c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h new file mode 100644 index 00000000..44e804e7 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_proj_gv100_h_ +#define _hw_proj_gv100_h_ + +static inline u32 proj_gpc_base_v(void) +{ + return 0x00500000; +} +static inline u32 proj_gpc_shared_base_v(void) +{ + return 0x00418000; +} +static inline u32 proj_gpc_stride_v(void) +{ + return 0x00008000; +} +static inline u32 proj_ltc_stride_v(void) +{ + return 0x00002000; +} +static inline u32 proj_lts_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_fbpa_stride_v(void) +{ + return 0x00004000; +} +static inline u32 proj_ppc_in_gpc_base_v(void) +{ + return 0x00003000; +} +static inline u32 proj_ppc_in_gpc_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_rop_base_v(void) +{ + return 0x00410000; +} +static inline u32 proj_rop_shared_base_v(void) +{ + return 0x00408800; +} +static inline u32 proj_rop_stride_v(void) +{ + return 0x00000400; +} +static inline u32 proj_tpc_in_gpc_base_v(void) +{ + return 0x00004000; +} +static inline u32 proj_tpc_in_gpc_stride_v(void) +{ + return 0x00000800; +} +static inline u32 proj_tpc_in_gpc_shared_base_v(void) +{ + return 0x00001800; +} +static inline u32 proj_host_num_engines_v(void) +{ + return 0x0000000f; +} +static inline u32 proj_host_num_pbdma_v(void) +{ + return 0x0000000e; +} +static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) +{ + return 0x00000007; +} +static inline u32 proj_scal_litter_num_fbps_v(void) +{ + return 0x00000008; +} +static inline u32 proj_scal_litter_num_fbpas_v(void) +{ + return 0x00000010; +} +static inline u32 proj_scal_litter_num_gpcs_v(void) +{ + return 0x00000006; +} +static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) +{ + return 0x00000003; +} +static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) +{ + return 0x00000003; +} +static inline u32 proj_scal_litter_num_zcull_banks_v(void) +{ + return 0x00000004; +} +static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_max_gpcs_v(void) +{ + return 0x00000020; +} +static inline u32 proj_scal_max_tpc_per_gpc_v(void) +{ + return 0x00000008; +} +static inline u32 proj_sm_stride_v(void) +{ + return 0x00000080; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h new file mode 100644 index 00000000..7d83b4ae --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h @@ -0,0 +1,929 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pwr_gv100_h_ +#define _hw_pwr_gv100_h_ + +static inline u32 pwr_falcon_irqsset_r(void) +{ + return 0x0010a000; +} +static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqsclr_r(void) +{ + return 0x0010a004; +} +static inline u32 pwr_falcon_irqstat_r(void) +{ + return 0x0010a008; +} +static inline u32 pwr_falcon_irqstat_halt_true_f(void) +{ + return 0x10; +} +static inline u32 pwr_falcon_irqstat_exterr_true_f(void) +{ + return 0x20; +} +static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) +{ + return 0x800; +} +static inline u32 pwr_falcon_irqmode_r(void) +{ + return 0x0010a00c; +} +static inline u32 pwr_falcon_irqmset_r(void) +{ + return 0x0010a010; +} +static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmset_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqmclr_r(void) +{ + return 0x0010a014; +} +static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqmask_r(void) +{ + return 0x0010a018; +} +static inline u32 pwr_falcon_irqdest_r(void) +{ + return 0x0010a01c; +} +static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) +{ + return (v & 0x1) << 27; +} +static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) +{ + return (v & 0x1) << 29; +} +static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_falcon_curctx_r(void) +{ + return 0x0010a050; +} +static inline u32 pwr_falcon_nxtctx_r(void) +{ + return 0x0010a054; +} +static inline u32 pwr_falcon_mailbox0_r(void) +{ + return 0x0010a040; +} +static inline u32 pwr_falcon_mailbox1_r(void) +{ + return 0x0010a044; +} +static inline u32 pwr_falcon_itfen_r(void) +{ + return 0x0010a048; +} +static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1; +} +static inline u32 pwr_falcon_idlestate_r(void) +{ + return 0x0010a04c; +} +static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1) & 0x7fff; +} +static inline u32 pwr_falcon_os_r(void) +{ + return 0x0010a080; +} +static inline u32 pwr_falcon_engctl_r(void) +{ + return 0x0010a0a4; +} +static inline u32 pwr_falcon_cpuctl_r(void) +{ + return 0x0010a100; +} +static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1 << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1 << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_alias_r(void) +{ + return 0x0010a130; +} +static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_pmu_scpctl_stat_r(void) +{ + return 0x0010ac08; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) +{ + return 0x1 << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 pwr_falcon_imemc_r(u32 i) +{ + return 0x0010a180 + i*16; +} +static inline u32 pwr_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_imemd_r(u32 i) +{ + return 0x0010a184 + i*16; +} +static inline u32 pwr_falcon_imemt_r(u32 i) +{ + return 0x0010a188 + i*16; +} +static inline u32 pwr_falcon_sctl_r(void) +{ + return 0x0010a240; +} +static inline u32 pwr_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4; +} +static inline u32 pwr_falcon_bootvec_r(void) +{ + return 0x0010a104; +} +static inline u32 pwr_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_falcon_dmactl_r(void) +{ + return 0x0010a10c; +} +static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_falcon_hwcfg_r(void) +{ + return 0x0010a108; +} +static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9) & 0x1ff; +} +static inline u32 pwr_falcon_dmatrfbase_r(void) +{ + return 0x0010a110; +} +static inline u32 pwr_falcon_dmatrfbase1_r(void) +{ + return 0x0010a128; +} +static inline u32 pwr_falcon_dmatrfmoffs_r(void) +{ + return 0x0010a114; +} +static inline u32 pwr_falcon_dmatrfcmd_r(void) +{ + return 0x0010a118; +} +static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 pwr_falcon_dmatrffboffs_r(void) +{ + return 0x0010a11c; +} +static inline u32 pwr_falcon_exterraddr_r(void) +{ + return 0x0010a168; +} +static inline u32 pwr_falcon_exterrstat_r(void) +{ + return 0x0010a16c; +} +static inline u32 pwr_falcon_exterrstat_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 pwr_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 pwr_pmu_falcon_icd_cmd_r(void) +{ + return 0x0010a200; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 pwr_pmu_falcon_icd_rdata_r(void) +{ + return 0x0010a20c; +} +static inline u32 pwr_falcon_dmemc_r(u32 i) +{ + return 0x0010a1c0 + i*8; +} +static inline u32 pwr_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 pwr_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_dmemc_blk_m(void) +{ + return 0xff << 8; +} +static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_dmemd_r(u32 i) +{ + return 0x0010a1c4 + i*8; +} +static inline u32 pwr_pmu_new_instblk_r(void) +{ + return 0x0010a480; +} +static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 pwr_pmu_new_instblk_target_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_pmu_mutex_id_r(void) +{ + return 0x0010a488; +} +static inline u32 pwr_pmu_mutex_id_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_id_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) +{ + return 0x000000ff; +} +static inline u32 pwr_pmu_mutex_id_release_r(void) +{ + return 0x0010a48c; +} +static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_m(void) +{ + return 0xff << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_mutex_r(u32 i) +{ + return 0x0010a580 + i*4; +} +static inline u32 pwr_pmu_mutex__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 pwr_pmu_mutex_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_queue_head_r(u32 i) +{ + return 0x0010a800 + i*4; +} +static inline u32 pwr_pmu_queue_head__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 pwr_pmu_queue_head_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_head_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_queue_tail_r(u32 i) +{ + return 0x0010a820 + i*4; +} +static inline u32 pwr_pmu_queue_tail__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 pwr_pmu_queue_tail_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_tail_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_head_r(void) +{ + return 0x0010a4c8; +} +static inline u32 pwr_pmu_msgq_head_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_head_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_tail_r(void) +{ + return 0x0010a4cc; +} +static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_idle_mask_r(u32 i) +{ + return 0x0010a504 + i*16; +} +static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) +{ + return 0x1; +} +static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 pwr_pmu_idle_count_r(u32 i) +{ + return 0x0010a508 + i*16; +} +static inline u32 pwr_pmu_idle_count_value_f(u32 v) +{ + return (v & 0x7fffffff) << 0; +} +static inline u32 pwr_pmu_idle_count_value_v(u32 r) +{ + return (r >> 0) & 0x7fffffff; +} +static inline u32 pwr_pmu_idle_count_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pwr_pmu_idle_ctrl_r(u32 i) +{ + return 0x0010a50c + i*16; +} +static inline u32 pwr_pmu_idle_ctrl_value_m(void) +{ + return 0x3 << 0; +} +static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) +{ + return 0x2; +} +static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) +{ + return 0x3; +} +static inline u32 pwr_pmu_idle_ctrl_filter_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) +{ + return 0x0010a9f0 + i*8; +} +static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) +{ + return 0x0010a9f4 + i*8; +} +static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) +{ + return 0x0010aa30 + i*8; +} +static inline u32 pwr_pmu_debug_r(u32 i) +{ + return 0x0010a5c0 + i*4; +} +static inline u32 pwr_pmu_debug__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_mailbox_r(u32 i) +{ + return 0x0010a450 + i*4; +} +static inline u32 pwr_pmu_mailbox__size_1_v(void) +{ + return 0x0000000c; +} +static inline u32 pwr_pmu_bar0_addr_r(void) +{ + return 0x0010a7a0; +} +static inline u32 pwr_pmu_bar0_data_r(void) +{ + return 0x0010a7a4; +} +static inline u32 pwr_pmu_bar0_ctl_r(void) +{ + return 0x0010a7ac; +} +static inline u32 pwr_pmu_bar0_timeout_r(void) +{ + return 0x0010a7a8; +} +static inline u32 pwr_pmu_bar0_fecs_error_r(void) +{ + return 0x0010a988; +} +static inline u32 pwr_pmu_bar0_error_status_r(void) +{ + return 0x0010a7b0; +} +static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) +{ + return 0x0010a6c0 + i*4; +} +static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) +{ + return 0x0010a6e8 + i*4; +} +static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) +{ + return 0x0010a710 + i*4; +} +static inline u32 pwr_pmu_pg_intren_r(u32 i) +{ + return 0x0010a760 + i*4; +} +static inline u32 pwr_fbif_transcfg_r(u32 i) +{ + return 0x0010ae00 + i*4; +} +static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) +{ + return 0x1; +} +static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) +{ + return 0x2; +} +static inline u32 pwr_fbif_transcfg_mem_type_s(void) +{ + return 1; +} +static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h new file mode 100644 index 00000000..7fff981b --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h @@ -0,0 +1,761 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ram_gv100_h_ +#define _hw_ram_gv100_h_ + +static inline u32 ram_in_ramfc_s(void) +{ + return 4096; +} +static inline u32 ram_in_ramfc_w(void) +{ + return 0; +} +static inline u32 ram_in_page_dir_base_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_page_dir_base_target_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) +{ + return 0x2; +} +static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) +{ + return 0x3; +} +static inline u32 ram_in_page_dir_base_vol_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_vol_true_f(void) +{ + return 0x4; +} +static inline u32 ram_in_page_dir_base_vol_false_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) +{ + return 0x10; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) +{ + return 0x20; +} +static inline u32 ram_in_big_page_size_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 ram_in_big_page_size_w(void) +{ + return 128; +} +static inline u32 ram_in_big_page_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 ram_in_big_page_size_64kb_f(void) +{ + return 0x800; +} +static inline u32 ram_in_page_dir_base_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_page_dir_base_lo_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_page_dir_base_hi_w(void) +{ + return 129; +} +static inline u32 ram_in_engine_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_cs_wfi_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_engine_cs_fg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_cs_fg_f(void) +{ + return 0x8; +} +static inline u32 ram_in_engine_wfi_mode_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_engine_wfi_mode_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_mode_physical_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_mode_virtual_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_wfi_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_engine_wfi_target_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_engine_wfi_target_local_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_engine_wfi_ptr_lo_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_engine_wfi_ptr_hi_w(void) +{ + return 133; +} +static inline u32 ram_in_engine_wfi_veid_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 ram_in_engine_wfi_veid_w(void) +{ + return 134; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) +{ + return 136; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) +{ + return 137; +} +static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) +{ + return (v & 0x3) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) +{ + return (v & 0x1) << (2 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) +{ + return (v & 0x1) << (4 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) +{ + return (v & 0x1) << (5 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) +{ + return (v & 0x1) << (10 + i*0); +} +static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) +{ + return (v & 0x1) << (11 + i*0); +} +static inline u32 ram_in_sc_big_page_size__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_big_page_size_64kb_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) +{ + return (v & 0xfffff) << (12 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) +{ + return (v & 0xffffffff) << (0 + i*0); +} +static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_sc_page_dir_base_target_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_big_page_size_0_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_sc_big_page_size_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) +{ + return 168; +} +static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) +{ + return 169; +} +static inline u32 ram_in_base_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_in_alloc_size_v(void) +{ + return 0x00001000; +} +static inline u32 ram_fc_size_val_v(void) +{ + return 0x00000200; +} +static inline u32 ram_fc_gp_put_w(void) +{ + return 0; +} +static inline u32 ram_fc_userd_w(void) +{ + return 2; +} +static inline u32 ram_fc_userd_hi_w(void) +{ + return 3; +} +static inline u32 ram_fc_signature_w(void) +{ + return 4; +} +static inline u32 ram_fc_gp_get_w(void) +{ + return 5; +} +static inline u32 ram_fc_pb_get_w(void) +{ + return 6; +} +static inline u32 ram_fc_pb_get_hi_w(void) +{ + return 7; +} +static inline u32 ram_fc_pb_top_level_get_w(void) +{ + return 8; +} +static inline u32 ram_fc_pb_top_level_get_hi_w(void) +{ + return 9; +} +static inline u32 ram_fc_acquire_w(void) +{ + return 12; +} +static inline u32 ram_fc_sem_addr_hi_w(void) +{ + return 14; +} +static inline u32 ram_fc_sem_addr_lo_w(void) +{ + return 15; +} +static inline u32 ram_fc_sem_payload_lo_w(void) +{ + return 16; +} +static inline u32 ram_fc_sem_payload_hi_w(void) +{ + return 39; +} +static inline u32 ram_fc_sem_execute_w(void) +{ + return 17; +} +static inline u32 ram_fc_gp_base_w(void) +{ + return 18; +} +static inline u32 ram_fc_gp_base_hi_w(void) +{ + return 19; +} +static inline u32 ram_fc_gp_fetch_w(void) +{ + return 20; +} +static inline u32 ram_fc_pb_fetch_w(void) +{ + return 21; +} +static inline u32 ram_fc_pb_fetch_hi_w(void) +{ + return 22; +} +static inline u32 ram_fc_pb_put_w(void) +{ + return 23; +} +static inline u32 ram_fc_pb_put_hi_w(void) +{ + return 24; +} +static inline u32 ram_fc_pb_header_w(void) +{ + return 33; +} +static inline u32 ram_fc_pb_count_w(void) +{ + return 34; +} +static inline u32 ram_fc_subdevice_w(void) +{ + return 37; +} +static inline u32 ram_fc_target_w(void) +{ + return 43; +} +static inline u32 ram_fc_hce_ctrl_w(void) +{ + return 57; +} +static inline u32 ram_fc_chid_w(void) +{ + return 58; +} +static inline u32 ram_fc_chid_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_fc_chid_id_w(void) +{ + return 0; +} +static inline u32 ram_fc_config_w(void) +{ + return 61; +} +static inline u32 ram_fc_runlist_timeslice_w(void) +{ + return 62; +} +static inline u32 ram_fc_set_channel_info_w(void) +{ + return 63; +} +static inline u32 ram_userd_base_shift_v(void) +{ + return 0x00000009; +} +static inline u32 ram_userd_chan_size_v(void) +{ + return 0x00000200; +} +static inline u32 ram_userd_put_w(void) +{ + return 16; +} +static inline u32 ram_userd_get_w(void) +{ + return 17; +} +static inline u32 ram_userd_ref_w(void) +{ + return 18; +} +static inline u32 ram_userd_put_hi_w(void) +{ + return 19; +} +static inline u32 ram_userd_ref_threshold_w(void) +{ + return 20; +} +static inline u32 ram_userd_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_userd_get_hi_w(void) +{ + return 24; +} +static inline u32 ram_userd_gp_get_w(void) +{ + return 34; +} +static inline u32 ram_userd_gp_put_w(void) +{ + return 35; +} +static inline u32 ram_userd_gp_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_gp_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_rl_entry_size_v(void) +{ + return 0x00000010; +} +static inline u32 ram_rl_entry_type_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 ram_rl_entry_type_channel_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_type_tsg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) +{ + return (v & 0x3) << 4; +} +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) +{ + return (v & 0x3) << 6; +} +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) +{ + return 0x00000002; +} +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) +{ + return 0x00000003; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_rl_entry_tsg_length_init_v(void) +{ + return 0x00000000; +} +static inline u32 ram_rl_entry_tsg_length_min_v(void) +{ + return 0x00000001; +} +static inline u32 ram_rl_entry_tsg_length_max_v(void) +{ + return 0x00000080; +} +static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h new file mode 100644 index 00000000..d98002c0 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_therm_gv100_h_ +#define _hw_therm_gv100_h_ + +static inline u32 therm_weight_1_r(void) +{ + return 0x00020024; +} +static inline u32 therm_config1_r(void) +{ + return 0x00020050; +} +static inline u32 therm_config2_r(void) +{ + return 0x00020130; +} +static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 therm_config2_grad_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 therm_gate_ctrl_r(u32 i) +{ + return 0x00020200 + i*4; +} +static inline u32 therm_gate_ctrl_eng_clk_m(void) +{ + return 0x3 << 0; +} +static inline u32 therm_gate_ctrl_eng_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) +{ + return 0x1; +} +static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) +{ + return 0x2; +} +static inline u32 therm_gate_ctrl_blk_clk_m(void) +{ + return 0x3 << 2; +} +static inline u32 therm_gate_ctrl_blk_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) +{ + return 0x4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_m(void) +{ + return 0x1 << 4; +} +static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) +{ + return 0x10; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) +{ + return 0x1f << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) +{ + return (v & 0x7) << 13; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) +{ + return 0x7 << 13; +} +static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_before_m(void) +{ + return 0xf << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 therm_gate_ctrl_eng_delay_after_m(void) +{ + return 0xf << 20; +} +static inline u32 therm_fecs_idle_filter_r(void) +{ + return 0x00020288; +} +static inline u32 therm_fecs_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_hubmmu_idle_filter_r(void) +{ + return 0x0002028c; +} +static inline u32 therm_hubmmu_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_clk_slowdown_r(u32 i) +{ + return 0x00020160 + i*4; +} +static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) +{ + return (v & 0x3f) << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_m(void) +{ + return 0x3f << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) +{ + return (r >> 16) & 0x3f; +} +static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) +{ + return 0x0; +} +static inline u32 therm_grad_stepping_table_r(u32 i) +{ + return 0x000202c8 + i*4; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) +{ + return 0x3f << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) +{ + return 0x2; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) +{ + return 0x6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) +{ + return 0xe; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) +{ + return 0x3f << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) +{ + return (v & 0x3f) << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) +{ + return 0x3f << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) +{ + return (v & 0x3f) << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) +{ + return 0x3f << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) +{ + return 0x3f << 24; +} +static inline u32 therm_grad_stepping0_r(void) +{ + return 0x000202c0; +} +static inline u32 therm_grad_stepping0_feature_s(void) +{ + return 1; +} +static inline u32 therm_grad_stepping0_feature_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 therm_grad_stepping0_feature_m(void) +{ + return 0x1 << 0; +} +static inline u32 therm_grad_stepping0_feature_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 therm_grad_stepping0_feature_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping1_r(void) +{ + return 0x000202c4; +} +static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 therm_clk_timing_r(u32 i) +{ + return 0x000203c0 + i*4; +} +static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_m(void) +{ + return 0x1 << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) +{ + return 0x10000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h new file mode 100644 index 00000000..c71e9a7d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_timer_gv100_h_ +#define _hw_timer_gv100_h_ + +static inline u32 timer_pri_timeout_r(void) +{ + return 0x00009080; +} +static inline u32 timer_pri_timeout_period_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 timer_pri_timeout_period_m(void) +{ + return 0xffffff << 0; +} +static inline u32 timer_pri_timeout_period_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 timer_pri_timeout_en_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 timer_pri_timeout_en_m(void) +{ + return 0x1 << 31; +} +static inline u32 timer_pri_timeout_en_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 timer_pri_timeout_en_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 timer_pri_timeout_en_en_disabled_f(void) +{ + return 0x0; +} +static inline u32 timer_pri_timeout_save_0_r(void) +{ + return 0x00009084; +} +static inline u32 timer_pri_timeout_save_1_r(void) +{ + return 0x00009088; +} +static inline u32 timer_pri_timeout_fecs_errcode_r(void) +{ + return 0x0000908c; +} +static inline u32 timer_time_0_r(void) +{ + return 0x00009400; +} +static inline u32 timer_time_1_r(void) +{ + return 0x00009410; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h new file mode 100644 index 00000000..d993bddc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_top_gv100_h_ +#define _hw_top_gv100_h_ + +static inline u32 top_num_gpcs_r(void) +{ + return 0x00022430; +} +static inline u32 top_num_gpcs_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_tpc_per_gpc_r(void) +{ + return 0x00022434; +} +static inline u32 top_tpc_per_gpc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_fbps_r(void) +{ + return 0x00022438; +} +static inline u32 top_num_fbps_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_ltc_per_fbp_r(void) +{ + return 0x00022450; +} +static inline u32 top_ltc_per_fbp_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_slices_per_ltc_r(void) +{ + return 0x0002245c; +} +static inline u32 top_slices_per_ltc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_ltcs_r(void) +{ + return 0x00022454; +} +static inline u32 top_num_ces_r(void) +{ + return 0x00022444; +} +static inline u32 top_num_ces_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_device_info_r(u32 i) +{ + return 0x00022700 + i*4; +} +static inline u32 top_device_info__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 top_device_info_chain_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 top_device_info_chain_enable_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_engine_enum_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_runlist_enum_v(u32 r) +{ + return (r >> 21) & 0xf; +} +static inline u32 top_device_info_intr_enum_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 top_device_info_reset_enum_v(u32 r) +{ + return (r >> 9) & 0x1f; +} +static inline u32 top_device_info_type_enum_v(u32 r) +{ + return (r >> 2) & 0x1fffffff; +} +static inline u32 top_device_info_type_enum_graphics_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_type_enum_graphics_f(void) +{ + return 0x0; +} +static inline u32 top_device_info_type_enum_copy2_v(void) +{ + return 0x00000003; +} +static inline u32 top_device_info_type_enum_copy2_f(void) +{ + return 0xc; +} +static inline u32 top_device_info_type_enum_lce_v(void) +{ + return 0x00000013; +} +static inline u32 top_device_info_type_enum_lce_f(void) +{ + return 0x4c; +} +static inline u32 top_device_info_engine_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 top_device_info_runlist_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 top_device_info_intr_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 top_device_info_reset_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_entry_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 top_device_info_entry_not_valid_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_entry_enum_v(void) +{ + return 0x00000002; +} +static inline u32 top_device_info_entry_data_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_data_type_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 top_device_info_data_type_enum2_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_data_inst_id_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_data_pri_base_v(u32 r) +{ + return (r >> 12) & 0xfff; +} +static inline u32 top_device_info_data_pri_base_align_v(void) +{ + return 0x0000000c; +} +static inline u32 top_device_info_data_fault_id_enum_v(u32 r) +{ + return (r >> 3) & 0x7f; +} +static inline u32 top_device_info_data_fault_id_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 top_device_info_data_fault_id_valid_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h new file mode 100644 index 00000000..86045e51 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_usermode_gv100_h_ +#define _hw_usermode_gv100_h_ + +static inline u32 usermode_cfg0_r(void) +{ + return 0x00810000; +} +static inline u32 usermode_cfg0_class_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 usermode_cfg0_class_id_value_v(void) +{ + return 0x0000c361; +} +static inline u32 usermode_time_0_r(void) +{ + return 0x00810080; +} +static inline u32 usermode_time_0_nsec_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 usermode_time_1_r(void) +{ + return 0x00810084; +} +static inline u32 usermode_time_1_nsec_f(u32 v) +{ + return (v & 0x1fffffff) << 0; +} +static inline u32 usermode_notify_channel_pending_r(void) +{ + return 0x00810090; +} +static inline u32 usermode_notify_channel_pending_id_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h new file mode 100644 index 00000000..4f15b39d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_xp_gv100_h_ +#define _hw_xp_gv100_h_ + +static inline u32 xp_dl_mgr_r(u32 i) +{ + return 0x0008b8c0 + i*4; +} +static inline u32 xp_dl_mgr_safe_timing_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 xp_pl_link_config_r(u32 i) +{ + return 0x0008c040 + i*4; +} +static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) +{ + return 0x00000000; +} +static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 xp_pl_link_config_ltssm_directive_m(void) +{ + return 0xf << 0; +} +static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) +{ + return 0x00000000; +} +static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) +{ + return 0x00000001; +} +static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) +{ + return (v & 0x3) << 18; +} +static inline u32 xp_pl_link_config_max_link_rate_m(void) +{ + return 0x3 << 18; +} +static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) +{ + return 0x00000002; +} +static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) +{ + return 0x00000001; +} +static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) +{ + return 0x00000000; +} +static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 xp_pl_link_config_target_tx_width_m(void) +{ + return 0x7 << 20; +} +static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) +{ + return 0x00000007; +} +static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) +{ + return 0x00000006; +} +static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) +{ + return 0x00000005; +} +static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) +{ + return 0x00000004; +} +static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) +{ + return 0x00000000; +} +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h new file mode 100644 index 00000000..f082fdc7 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_xve_gv100_h_ +#define _hw_xve_gv100_h_ + +static inline u32 xve_rom_ctrl_r(void) +{ + return 0x00000050; +} +static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) +{ + return 0x0; +} +static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) +{ + return 0x1; +} +static inline u32 xve_link_control_status_r(void) +{ + return 0x00000088; +} +static inline u32 xve_link_control_status_link_speed_m(void) +{ + return 0xf << 16; +} +static inline u32 xve_link_control_status_link_speed_v(u32 r) +{ + return (r >> 16) & 0xf; +} +static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) +{ + return 0x00000001; +} +static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) +{ + return 0x00000002; +} +static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) +{ + return 0x00000003; +} +static inline u32 xve_link_control_status_link_width_m(void) +{ + return 0x3f << 20; +} +static inline u32 xve_link_control_status_link_width_v(u32 r) +{ + return (r >> 20) & 0x3f; +} +static inline u32 xve_link_control_status_link_width_x1_v(void) +{ + return 0x00000001; +} +static inline u32 xve_link_control_status_link_width_x2_v(void) +{ + return 0x00000002; +} +static inline u32 xve_link_control_status_link_width_x4_v(void) +{ + return 0x00000004; +} +static inline u32 xve_link_control_status_link_width_x8_v(void) +{ + return 0x00000008; +} +static inline u32 xve_link_control_status_link_width_x16_v(void) +{ + return 0x00000010; +} +static inline u32 xve_priv_xv_r(void) +{ + return 0x00000150; +} +static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 xve_priv_xv_cya_l0s_enable_m(void) +{ + return 0x1 << 7; +} +static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 xve_priv_xv_cya_l1_enable_m(void) +{ + return 0x1 << 8; +} +static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 xve_cya_2_r(void) +{ + return 0x00000704; +} +static inline u32 xve_reset_r(void) +{ + return 0x00000718; +} +static inline u32 xve_reset_reset_m(void) +{ + return 0x1 << 0; +} +static inline u32 xve_reset_gpu_on_sw_reset_m(void) +{ + return 0x1 << 1; +} +static inline u32 xve_reset_counter_en_m(void) +{ + return 0x1 << 2; +} +static inline u32 xve_reset_counter_val_f(u32 v) +{ + return (v & 0x7ff) << 4; +} +static inline u32 xve_reset_counter_val_m(void) +{ + return 0x7ff << 4; +} +static inline u32 xve_reset_counter_val_v(u32 r) +{ + return (r >> 4) & 0x7ff; +} +static inline u32 xve_reset_clock_on_sw_reset_m(void) +{ + return 0x1 << 15; +} +static inline u32 xve_reset_clock_counter_en_m(void) +{ + return 0x1 << 16; +} +static inline u32 xve_reset_clock_counter_val_f(u32 v) +{ + return (v & 0x7ff) << 17; +} +static inline u32 xve_reset_clock_counter_val_m(void) +{ + return 0x7ff << 17; +} +static inline u32 xve_reset_clock_counter_val_v(u32 r) +{ + return (r >> 17) & 0x7ff; +} +#endif diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h index 63901445..71841484 100644 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h +++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h @@ -17,16 +17,25 @@ #define NVGPU_GPUID_GV11B \ GK20A_GPUID(NVGPU_GPU_ARCH_GV110, NVGPU_GPU_IMPL_GV11B) +#define NVGPU_GPUID_GV100 \ + GK20A_GPUID(NVGPU_GPU_ARCH_GV100, NVGPU_GPU_IMPL_GV100) + #define NVGPU_COMPAT_TEGRA_GV11B "nvidia,gv11b" #define NVGPU_COMPAT_GENERIC_GV11B "nvidia,generic-gv11b" + #define TEGRA_19x_GPUID NVGPU_GPUID_GV11B #define TEGRA_19x_GPUID_HAL gv11b_init_hal #define TEGRA_19x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GV11B #define TEGRA_19x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GV11B + +#define BIGGPU_19x_GPUID NVGPU_GPUID_GV100 +#define BIGGPU_19x_GPUID_HAL gv100_init_hal + struct gpu_ops; extern int gv11b_init_hal(struct gk20a *); +extern int gv100_init_hal(struct gk20a *); extern struct gk20a_platform t19x_gpu_tegra_platform; #endif diff --git a/include/uapi/linux/nvgpu-t19x.h b/include/uapi/linux/nvgpu-t19x.h index bc37bc7c..f56bc9d7 100644 --- a/include/uapi/linux/nvgpu-t19x.h +++ b/include/uapi/linux/nvgpu-t19x.h @@ -25,7 +25,9 @@ #define _UAPI__LINUX_NVGPU_T19X_IOCTL_H_ #define NVGPU_GPU_ARCH_GV110 0x00000150 +#define NVGPU_GPU_ARCH_GV100 0x00000140 #define NVGPU_GPU_IMPL_GV11B 0x0000000B +#define NVGPU_GPU_IMPL_GV100 0x00000000 /* * this flag is used in struct nvgpu_as_map_buffer_ex_args -- cgit v1.2.2 From 3197a918d5052c71ad854f6b22fdb35bfe7cebe2 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 10 Aug 2017 16:34:16 -0700 Subject: gpu: nvgpu: gv11b: add max_subctx_count to g->fifo.t19x - For better performance. It used to read register every time referencing max_subctx_count. - Avoid reading registers for vgpu. Jira VFND-3797 Change-Id: Id6e6b15a0d9a035795e8a9a2c6bb63524c5eb544 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1537009 Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c | 2 +- drivers/gpu/nvgpu/fifo_t19x.h | 1 + drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 7 ++++++- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 13 ++----------- drivers/gpu/nvgpu/gv11b/subctx_gv11b.h | 1 - 6 files changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c index bf6088ab..b0b1f9c4 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c @@ -44,7 +44,7 @@ static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g, ch = gk20a_get_channel_from_file(arg->channel_fd); if (!ch) return -EINVAL; - if (arg->subcontext_id < gv11b_get_max_subctx_count(g)) + if (arg->subcontext_id < g->fifo.t19x.max_subctx_count) ch->t19x.subctx_id = arg->subcontext_id; else return -EINVAL; diff --git a/drivers/gpu/nvgpu/fifo_t19x.h b/drivers/gpu/nvgpu/fifo_t19x.h index 531c6f34..25d5f41d 100644 --- a/drivers/gpu/nvgpu/fifo_t19x.h +++ b/drivers/gpu/nvgpu/fifo_t19x.h @@ -16,6 +16,7 @@ struct fifo_t19x { void __iomem *usermode_regs; + u32 max_subctx_count; }; #endif diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index e210d40d..bd769f75 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -40,6 +40,7 @@ #include #include #include +#include #include "fifo_gv11b.h" #include "subctx_gv11b.h" @@ -1717,16 +1718,20 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g) struct fifo_gk20a *f = &g->fifo; f->t19x.usermode_regs = g->regs + usermode_cfg0_r(); + f->t19x.max_subctx_count = + gr_pri_fe_chip_def_info_max_veid_count_v( + gk20a_readl(g, gr_pri_fe_chip_def_info_r())); return 0; } static u32 gv11b_mmu_fault_id_to_gr_veid(struct gk20a *g, u32 gr_eng_fault_id, u32 mmu_fault_id) { + struct fifo_gk20a *f = &g->fifo; u32 num_subctx; u32 veid = FIFO_INVAL_VEID; - num_subctx = gv11b_get_max_subctx_count(g); + num_subctx = f->t19x.max_subctx_count; if (mmu_fault_id >= gr_eng_fault_id && mmu_fault_id < (gr_eng_fault_id + num_subctx)) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 850315f7..b95152eb 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2021,7 +2021,7 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) u32 j; u32 num_subctx, err = 0; - num_subctx = gv11b_get_max_subctx_count(g); + num_subctx = g->fifo.t19x.max_subctx_count; for (j = 0; j < num_subctx; j++) { diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 72a66530..4f64843c 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -26,7 +26,6 @@ #include #include -#include static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block); @@ -143,6 +142,7 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, struct nvgpu_mem *inst_block) { struct gk20a *g = c->g; + struct fifo_gk20a *f = &g->fifo; struct vm_gk20a *vm = c->vm; u32 lo, hi; u32 subctx_id = 0; @@ -164,19 +164,10 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", format_word, pdb_addr_hi); - for (subctx_id = 0; subctx_id < gv11b_get_max_subctx_count(g); - subctx_id++) { + for (subctx_id = 0; subctx_id < f->t19x.max_subctx_count; subctx_id++) { lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); nvgpu_mem_wr32(g, inst_block, lo, format_word); nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); } } - - -u32 gv11b_get_max_subctx_count(struct gk20a *g) -{ - u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r()); - - return gr_pri_fe_chip_def_info_max_veid_count_v(data); -} diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h index 5e4e99f5..d199711d 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h @@ -25,5 +25,4 @@ void gv11b_free_subctx_header(struct channel_gk20a *c); int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va); -u32 gv11b_get_max_subctx_count(struct gk20a *g); #endif /* __SUBCONTEXT_GV11B_H__ */ -- cgit v1.2.2 From 2660d1d881d1536c1b723d9737ae9a04321d69f3 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 31 Jul 2017 16:05:22 -0700 Subject: gpu: nvgpu: gv11b: remove kind map inheritance Currently, the kind map initialization inherits from earlier chips' kind map definitions and simply adds on newly supported features. This is dangerous as changes in older architectures may affect newer architectures in unpredictable ways. This patch removes inheritance between subsequent architectures' kind map initializations. Jira NVGPU-74 Change-Id: I894e08da9acd288a4ea36282a2c7dc0b03bf9161 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1533353 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 421 +++++++++++++++++++++++++++++++++++-- 1 file changed, 405 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 51ee55f8..35227576 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -30,12 +30,11 @@ #include "gv11b/fb_gv11b.h" #include "gv11b/ce_gv11b.h" -#include #include #include #include #include - +#include static int gv11b_fb_fix_page_fault(struct gk20a *g, struct mmu_fault_info *mmfault); @@ -252,50 +251,440 @@ static const char *const gpc_client_descs_gv11b[] = { "t1 36", "t1 37", "t1 38", "t1 39", }; -static void gv11b_init_uncompressed_kind_map(void) +static noinline_for_stack void gv11b_init_uncompressed_kind_map(void) { + int i; + + for (i = 0; i < 256; i++) + gk20a_uc_kind_map[i] = gmmu_pte_kind_invalid_v(); + + /* From gv11b */ gk20a_uc_kind_map[gmmu_pte_kind_c32_ms2_4cbra_v()] = gk20a_uc_kind_map[gmmu_pte_kind_c64_ms2_4cbra_v()] = gmmu_pte_kind_generic_16bx2_v(); + + /* From gp10b */ + gk20a_uc_kind_map[gmmu_pte_kind_z16_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms16_2cz_v()] = + gmmu_pte_kind_z16_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_4cbra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_4cbra_v()] = + gmmu_pte_kind_generic_16bx2_v(); + + /* From gm20b */ + gk20a_uc_kind_map[gmmu_pte_kind_s8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8_2s_v()] = + gmmu_pte_kind_s8_v(); + + /* From gk20a */ + gk20a_uc_kind_map[gmmu_pte_kind_z16_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_2z_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2z_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2z_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2z_v()] = + gmmu_pte_kind_z16_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms2_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms4_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms8_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms2_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms8_2cs_v()] = + gmmu_pte_kind_s8z24_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2zv_v()] = + gmmu_pte_kind_v8z24_ms4_vc4_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2zv_v()] = + gmmu_pte_kind_v8z24_ms8_vc8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2zv_v()] = + gmmu_pte_kind_v8z24_ms4_vc12_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2zv_v()] = + gmmu_pte_kind_v8z24_ms8_vc24_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms2_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms2_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms4_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms8_2cz_v()] = + gmmu_pte_kind_z24s8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms2_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms2_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms4_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms8_2cz_v()] = + gmmu_pte_kind_zf32_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v()] = + gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v()] = + gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v()] = + gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()] = + gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v()] = + gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v()] = + gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v()] = + gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()] = + gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_2cszv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms2_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms8_2cs_v()] = + gmmu_pte_kind_zf32_x24s8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_c32_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_2cba_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_2bra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms2_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cbr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cba_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2bra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms8_ms16_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms8_ms16_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_2cbr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_2cba_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_2bra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms2_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cbr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cba_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2bra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms8_ms16_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms8_ms16_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_2cr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms2_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms2_2cr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms4_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms4_2cr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms8_ms16_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms8_ms16_2cr_v()] = + gmmu_pte_kind_generic_16bx2_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2zv_v()] = + gmmu_pte_kind_z24v8_ms4_vc4_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2zv_v()] = + gmmu_pte_kind_z24v8_ms4_vc12_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2zv_v()] = + gmmu_pte_kind_z24v8_ms8_vc8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2zv_v()] = + gmmu_pte_kind_z24v8_ms8_vc24_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_x8c24_v()] = + gmmu_pte_kind_x8c24_v(); +} + +static noinline_for_stack bool gv11b_kind_supported(u8 k) +{ + return /* From gv11b */ + k == gmmu_pte_kind_c32_ms2_4cbra_v() + || k == gmmu_pte_kind_c64_ms2_4cbra_v() + /* From gp10b */ + || (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) + || k == gmmu_pte_kind_z16_ms16_2cz_v() + || k == gmmu_pte_kind_c32_ms4_4cbra_v() + || k == gmmu_pte_kind_c64_ms4_4cbra_v() + /* From gm20b */ + || (k == gmmu_pte_kind_smsked_message_v()) + || (k >= gmmu_pte_kind_s8_v() && + k <= gmmu_pte_kind_s8_2s_v()) + /* From gk20a */ + || gk20a_kind_work_creation(k) + || (k == gmmu_pte_kind_invalid_v()) + || (k == gmmu_pte_kind_pitch_v()) + || (k >= gmmu_pte_kind_z16_v() && + k <= gmmu_pte_kind_z16_ms8_2c_v()) + || (k >= gmmu_pte_kind_z16_2z_v() && + k <= gmmu_pte_kind_z16_ms8_2z_v()) + || (k == gmmu_pte_kind_s8z24_v()) + || (k >= gmmu_pte_kind_s8z24_2cz_v() && + k <= gmmu_pte_kind_s8z24_ms8_2cz_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_2zv_v()) + || (k == gmmu_pte_kind_z24s8_v()) + || (k >= gmmu_pte_kind_z24s8_2cz_v() && + k <= gmmu_pte_kind_z24s8_ms8_2cz_v()) + || (k == gmmu_pte_kind_zf32_v()) + || (k >= gmmu_pte_kind_zf32_2cz_v() && + k <= gmmu_pte_kind_zf32_ms8_2cz_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v() && + k <= gmmu_pte_kind_zf32_x24s8_v()) + || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && + k <= gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v()) + || (k == gmmu_pte_kind_generic_16bx2_v()) + || (k == gmmu_pte_kind_c32_2c_v()) + || (k == gmmu_pte_kind_c32_2cra_v()) + || (k == gmmu_pte_kind_c32_ms2_2c_v()) + || (k >= gmmu_pte_kind_c32_ms4_2c_v() && + k <= gmmu_pte_kind_c32_ms4_2cbr_v()) + || (k >= gmmu_pte_kind_c32_ms4_2cra_v() && + k <= gmmu_pte_kind_c64_2c_v()) + || (k == gmmu_pte_kind_c64_2cra_v()) + || (k == gmmu_pte_kind_c64_ms2_2c_v()) + || (k >= gmmu_pte_kind_c64_ms4_2c_v() && + k <= gmmu_pte_kind_c64_ms4_2cbr_v()) + || (k >= gmmu_pte_kind_c64_ms4_2cra_v() && + k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()) + || (k == gmmu_pte_kind_pitch_no_swizzle_v()); } -static bool gv11b_kind_supported(u8 k) +static noinline_for_stack bool gv11b_kind_z(u8 k) { - return (k == gmmu_pte_kind_c32_ms2_4cbra_v() - || k == gmmu_pte_kind_c64_ms2_4cbra_v()); + return /* From gv11b */ + (k == gmmu_pte_kind_c32_ms2_4cbra_v()) + || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) + /* From gp10b */ + || (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) + || (k == gmmu_pte_kind_z16_ms16_2cz_v()) + /* From gm20b */ + || (k >= gmmu_pte_kind_s8_v() && + k <= gmmu_pte_kind_s8_2s_v()) + /* From gk20a */ + || (k >= gmmu_pte_kind_z16_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()); } -static bool gv11b_kind_z(u8 k) +static noinline_for_stack bool gv11b_kind_c(u8 k) { - return (k == gmmu_pte_kind_c32_ms2_4cbra_v() - || k == gmmu_pte_kind_c64_ms2_4cbra_v()); + return gk20a_kind_work_creation(k) + || (k == gmmu_pte_kind_pitch_v()) + || (k == gmmu_pte_kind_generic_16bx2_v()) + || (k >= gmmu_pte_kind_c32_2c_v() && + k <= gmmu_pte_kind_c32_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c32_ms4_2c_v() && + k <= gmmu_pte_kind_c64_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c64_ms4_2c_v() && + k <= gmmu_pte_kind_pitch_no_swizzle_v()); } -static bool gv11b_kind_compressible(u8 k) +static noinline_for_stack bool gv11b_kind_compressible(u8 k) { - return (k == gmmu_pte_kind_c32_ms2_4cbra_v() - || k == gmmu_pte_kind_c64_ms2_4cbra_v()); + return /* From gv11b */ + (k == gmmu_pte_kind_c32_ms2_4cbra_v()) + || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) + /* From gp10b */ + || (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) + || (k == gmmu_pte_kind_z16_ms16_2cz_v()) + || (k == gmmu_pte_kind_c32_ms4_4cbra_v()) + || (k == gmmu_pte_kind_c64_ms4_4cbra_v()) + /* From gm20b */ + || (k >= gmmu_pte_kind_s8_v() && + k <= gmmu_pte_kind_s8_2s_v()) + /* From gk20a */ + || (k >= gmmu_pte_kind_s8z24_1z_v() && + k <= gmmu_pte_kind_s8z24_ms16_4cszv_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v()) + || (k >= gmmu_pte_kind_z24s8_1z_v() && + k <= gmmu_pte_kind_z24s8_ms16_4cszv_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v()) + || (k >= gmmu_pte_kind_zf32_1z_v() && + k <= gmmu_pte_kind_zf32_ms16_2cz_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()) + || (k >= gmmu_pte_kind_zf32_x24s8_1cs_v() && + k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()) + || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && + k <= gmmu_pte_kind_c32_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c32_ms4_2c_v() && + k <= gmmu_pte_kind_c64_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c64_ms4_2c_v() && + k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); } -static bool gv11b_kind_zbc(u8 k) +static noinline_for_stack bool gv11b_kind_zbc(u8 k) { - return (k == gmmu_pte_kind_c32_ms2_4cbra_v() - || k == gmmu_pte_kind_c64_ms2_4cbra_v()); + return /* From gv11b */ + (k == gmmu_pte_kind_c32_ms2_4cbra_v()) + || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) + /* From gp10b */ + || (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) + || (k == gmmu_pte_kind_z16_ms16_2cz_v()) + || (k == gmmu_pte_kind_c32_ms4_4cbra_v()) + || (k == gmmu_pte_kind_c64_ms4_4cbra_v()) + /* From gm20b */ + || (k >= gmmu_pte_kind_s8_v() && + k <= gmmu_pte_kind_s8_2s_v()) + /* From gk20a */ + || (k >= gmmu_pte_kind_z16_2c_v() && + k <= gmmu_pte_kind_z16_ms16_2c_v()) + || (k >= gmmu_pte_kind_s8z24_2cz_v() && + k <= gmmu_pte_kind_s8z24_ms16_4cszv_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2cs_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_2czv_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v()) + || (k >= gmmu_pte_kind_z24s8_2cs_v() && + k <= gmmu_pte_kind_z24s8_ms16_4cszv_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2cs_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_2czv_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v()) + || (k >= gmmu_pte_kind_zf32_2cs_v() && + k <= gmmu_pte_kind_zf32_ms16_2cz_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()) + || (k >= gmmu_pte_kind_zf32_x24s8_1cs_v() && + k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()) + || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && + k <= gmmu_pte_kind_c32_2cra_v()) + || (k >= gmmu_pte_kind_c32_ms2_2c_v() && + k <= gmmu_pte_kind_c32_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c32_ms4_2c_v() && + k <= gmmu_pte_kind_c32_ms4_2cra_v()) + || (k >= gmmu_pte_kind_c32_ms8_ms16_2c_v() && + k <= gmmu_pte_kind_c64_2cra_v()) + || (k >= gmmu_pte_kind_c64_ms2_2c_v() && + k <= gmmu_pte_kind_c64_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c64_ms4_2c_v() && + k <= gmmu_pte_kind_c64_ms4_2cra_v()) + || (k >= gmmu_pte_kind_c64_ms8_ms16_2c_v() && + k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); } static void gv11b_init_kind_attr(void) { u16 k; - for (k = 0; k < 256; k++) { + for (k = 0; k < NV_KIND_ATTR_SIZE; k++) { if (gv11b_kind_supported((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED; if (gv11b_kind_compressible((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE; if (gv11b_kind_z((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z; + if (gv11b_kind_c((u8)k)) + gk20a_kind_attr[k] |= GK20A_KIND_ATTR_C; if (gv11b_kind_zbc((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC; } -- cgit v1.2.2 From da8e67f042760d54f3d6b5f84abbd9981d9fcd54 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 31 Jul 2017 14:40:46 -0700 Subject: gpu: nvgpu: gv11b: Reorg fb HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I896d90e0dcffc0e133e6902ff9c3eab39c53080d Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1533354 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 25 ++++++------------------- drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 11 +++++++++-- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 25 ++++++++++++++++++++++++- 3 files changed, 39 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 35227576..384dfb20 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -75,7 +75,7 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) } -static void gv11b_fb_init_fs_state(struct gk20a *g) +void gv11b_fb_init_fs_state(struct gk20a *g) { nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb"); @@ -87,7 +87,7 @@ static void gv11b_fb_init_fs_state(struct gk20a *g) gk20a_readl(g, fb_mmu_num_active_ltcs_r()))); } -static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) +void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) { u32 max_size = gr->max_comptag_mem; /* one tag line covers 64KB */ @@ -137,7 +137,7 @@ static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) } -static void gv11b_fb_reset(struct gk20a *g) +void gv11b_fb_reset(struct gk20a *g) { u32 val; @@ -251,7 +251,7 @@ static const char *const gpc_client_descs_gv11b[] = { "t1 36", "t1 37", "t1 38", "t1 39", }; -static noinline_for_stack void gv11b_init_uncompressed_kind_map(void) +noinline_for_stack void gv11b_init_uncompressed_kind_map(void) { int i; @@ -672,7 +672,7 @@ static noinline_for_stack bool gv11b_kind_zbc(u8 k) k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); } -static void gv11b_init_kind_attr(void) +void gv11b_init_kind_attr(void) { u16 k; @@ -1815,7 +1815,7 @@ static void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr) fb_mmu_fault_status_valid_clear_f()); } -static void gv11b_fb_hub_isr(struct gk20a *g) +void gv11b_fb_hub_isr(struct gk20a *g) { u32 status, niso_intr; @@ -1967,16 +1967,3 @@ static int gv11b_fb_fix_page_fault(struct gk20a *g, pte[1], pte[0]); return err; } - -void gv11b_init_fb(struct gpu_ops *gops) -{ - gp10b_init_fb(gops); - gops->fb.hub_isr = gv11b_fb_hub_isr; - gops->fb.reset = gv11b_fb_reset; - gops->fb.init_fs_state = gv11b_fb_init_fs_state; - gops->fb.init_cbc = gv11b_fb_init_cbc; - - gv11b_init_uncompressed_kind_map(); - gv11b_init_kind_attr(); - -} diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index 39cdfb77..3e2dd828 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -42,9 +42,13 @@ #define FAULT_TYPE_OTHER_AND_NONREPLAY 0 #define FAULT_TYPE_REPLAY 1 -struct gpu_ops; +struct gk20a; + +void gv11b_fb_init_fs_state(struct gk20a *g); +void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr); +void gv11b_fb_reset(struct gk20a *g); +void gv11b_fb_hub_isr(struct gk20a *g); -void gv11b_init_fb(struct gpu_ops *gops); u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g, unsigned int index); void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g, @@ -56,4 +60,7 @@ void gv11b_fb_disable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index); bool gv11b_fb_mmu_fault_pending(struct gk20a *g); + +noinline_for_stack void gv11b_init_uncompressed_kind_map(void); +void gv11b_init_kind_attr(void); #endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 282aa228..9f6c67c1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -29,9 +29,11 @@ #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" +#include "gk20a/fb_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" +#include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gp10b/ltc_gp10b.h" @@ -41,6 +43,7 @@ #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" +#include "gp10b/fb_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -175,6 +178,23 @@ static const struct gpu_ops gv11b_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, + .fb = { + .reset = gv11b_fb_reset, + .init_hw = gk20a_fb_init_hw, + .init_fs_state = gv11b_fb_init_fs_state, + .init_cbc = gv11b_fb_init_cbc, + .set_mmu_page_size = gm20b_fb_set_mmu_page_size, + .set_use_full_comp_tag_line = + gm20b_fb_set_use_full_comp_tag_line, + .compression_page_size = gp10b_fb_compression_page_size, + .compressible_page_size = gp10b_fb_compressible_page_size, + .vpr_info_fetch = gm20b_fb_vpr_info_fetch, + .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, + .set_debug_mode = gm20b_fb_set_debug_mode, + .tlb_invalidate = gk20a_fb_tlb_invalidate, + .hub_isr = gv11b_fb_hub_isr, + }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, @@ -405,6 +425,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; + gops->fb = gv11b_ops.fb; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; @@ -432,10 +453,12 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_fb(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); + gv11b_init_uncompressed_kind_map(); + gv11b_init_kind_attr(); + g->name = "gv11b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 96615351ad11a186f5869e56acb3c1948ab7b7cc Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 14:23:01 -0700 Subject: gpu: nvgpu: gv11b: Reorg mm HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic2c7d56e552645f2125d9c60a817967be1e8e765 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1533355 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 32 +++++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 32 ++++++++------------------------ drivers/gpu/nvgpu/gv11b/mm_gv11b.h | 17 +++++++++++++++-- 3 files changed, 54 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9f6c67c1..afc90aa7 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,6 +25,7 @@ #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -35,6 +36,7 @@ #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" +#include "gm20b/mm_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/therm_gp10b.h" @@ -44,6 +46,7 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/fb_gp10b.h" +#include "gp10b/mm_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -60,6 +63,8 @@ #include "regops_gv11b.h" #include "subctx_gv11b.h" +#include "common/linux/platform_gk20a_tegra.h" + #include #include @@ -333,6 +338,31 @@ static const struct gpu_ops gv11b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gv11b_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gv11b_gpu_phys_addr, + .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = gv11b_init_mm_setup_hw, + .is_bar1_supported = gv11b_mm_is_bar1_supported, + .init_inst_block = gv11b_init_inst_block, + .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gv11b_mm_remove_bar2_vm, + .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + }, .therm = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, @@ -429,6 +459,7 @@ int gv11b_init_hal(struct gk20a *g) gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; + gops->mm = gv11b_ops.mm; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; gops->regops = gv11b_ops.regops; @@ -453,7 +484,6 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 7ba8f74f..941a0bbe 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -34,12 +34,12 @@ #define NVGPU_L3_ALLOC_BIT BIT(36) -static bool gv11b_mm_is_bar1_supported(struct gk20a *g) +bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; } -static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, +void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, u32 big_page_size) { struct gk20a *g = gk20a_from_vm(vm); @@ -53,12 +53,12 @@ static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, g->ops.mm.set_big_page_size(g, inst_block, big_page_size); } -static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) +bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { return gv11b_fb_mmu_fault_pending(g); } -static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) +void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) { nvgpu_log_fn(g, " "); @@ -174,7 +174,7 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) } } -static void gv11b_mm_remove_bar2_vm(struct gk20a *g) +void gv11b_mm_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -221,7 +221,7 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) return err; } -static int gv11b_init_mm_setup_hw(struct gk20a *g) +int gv11b_init_mm_setup_hw(struct gk20a *g) { int err = 0; @@ -260,7 +260,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) * checking bit 36 of the phsyical address. So if a mapping should allocte lines * in the L3 this bit must be set. */ -static u64 gv11b_gpu_phys_addr(struct gk20a *g, +u64 gv11b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys) { if (attrs && attrs->t19x_attrs.l3_alloc) @@ -269,7 +269,7 @@ static u64 gv11b_gpu_phys_addr(struct gk20a *g, return phys; } -static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) +int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; @@ -318,19 +318,3 @@ static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); return -EBUSY; } - -void gv11b_init_mm(struct gpu_ops *gops) -{ - gp10b_init_mm(gops); - gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; - gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; - gops->mm.init_inst_block = gv11b_init_inst_block; - gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; - gops->mm.l2_flush = gv11b_mm_l2_flush; - gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; - gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; - gops->mm.fault_info_mem_destroy = - gv11b_mm_fault_info_mem_destroy; - gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; - gops->mm.init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup; -} diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h index a887c7f4..12f0fe63 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h @@ -18,7 +18,20 @@ #define HW_FAULT_BUF_STATUS_ALLOC_TRUE 1 #define HW_FAULT_BUF_STATUS_ALLOC_FALSE 0 -struct gpu_ops; +struct gk20a; +struct nvgpu_mem; +struct vm_gk20a; + +bool gv11b_mm_is_bar1_supported(struct gk20a *g); +void gv11b_init_inst_block(struct nvgpu_mem *inst_block, + struct vm_gk20a *vm, u32 big_page_size); +bool gv11b_mm_mmu_fault_pending(struct gk20a *g); +void gv11b_mm_remove_bar2_vm(struct gk20a *g); +int gv11b_init_mm_setup_hw(struct gk20a *g); +int gv11b_init_bar2_mm_hw_setup(struct gk20a *g); +void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate); +u64 gv11b_gpu_phys_addr(struct gk20a *g, + struct nvgpu_gmmu_attrs *attrs, u64 phys); +void gv11b_mm_fault_info_mem_destroy(struct gk20a *g); -void gv11b_init_mm(struct gpu_ops *gops); #endif -- cgit v1.2.2 From a4e095aa37ec5a6c09a8cc6477da9fa49a73cd77 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 11 Aug 2017 14:40:58 -0700 Subject: Revert "gpu: nvgpu: gv11b: Reorg mm HAL init" This reverts commit 96615351ad11a186f5869e56acb3c1948ab7b7cc, which conflicts with gv100 changes. Change-Id: I08797bb23dd9226f0228ce3235fce6feef8d82f3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537667 Reviewed-by: Shu Zhong Tested-by: Shu Zhong --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 32 +------------------------------- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 32 ++++++++++++++++++++++++-------- drivers/gpu/nvgpu/gv11b/mm_gv11b.h | 17 ++--------------- 3 files changed, 27 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index afc90aa7..9f6c67c1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,7 +25,6 @@ #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" -#include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -36,7 +35,6 @@ #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" -#include "gm20b/mm_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/therm_gp10b.h" @@ -46,7 +44,6 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/fb_gp10b.h" -#include "gp10b/mm_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -63,8 +60,6 @@ #include "regops_gv11b.h" #include "subctx_gv11b.h" -#include "common/linux/platform_gk20a_tegra.h" - #include #include @@ -338,31 +333,6 @@ static const struct gpu_ops gv11b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ - .mm = { - .support_sparse = gm20b_mm_support_sparse, - .gmmu_map = gk20a_locked_gmmu_map, - .gmmu_unmap = gk20a_locked_gmmu_unmap, - .vm_bind_channel = gk20a_vm_bind_channel, - .fb_flush = gk20a_mm_fb_flush, - .l2_invalidate = gk20a_mm_l2_invalidate, - .l2_flush = gv11b_mm_l2_flush, - .cbc_clean = gk20a_mm_cbc_clean, - .set_big_page_size = gm20b_mm_set_big_page_size, - .get_big_page_sizes = gm20b_mm_get_big_page_sizes, - .get_default_big_page_size = gp10b_mm_get_default_big_page_size, - .gpu_phys_addr = gv11b_gpu_phys_addr, - .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, - .get_mmu_levels = gp10b_mm_get_mmu_levels, - .init_pdb = gp10b_mm_init_pdb, - .init_mm_setup_hw = gv11b_init_mm_setup_hw, - .is_bar1_supported = gv11b_mm_is_bar1_supported, - .init_inst_block = gv11b_init_inst_block, - .mmu_fault_pending = gv11b_mm_mmu_fault_pending, - .init_bar2_vm = gb10b_init_bar2_vm, - .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, - .remove_bar2_vm = gv11b_mm_remove_bar2_vm, - .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, - }, .therm = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, @@ -459,7 +429,6 @@ int gv11b_init_hal(struct gk20a *g) gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; - gops->mm = gv11b_ops.mm; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; gops->regops = gv11b_ops.regops; @@ -484,6 +453,7 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); + gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 941a0bbe..7ba8f74f 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -34,12 +34,12 @@ #define NVGPU_L3_ALLOC_BIT BIT(36) -bool gv11b_mm_is_bar1_supported(struct gk20a *g) +static bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; } -void gv11b_init_inst_block(struct nvgpu_mem *inst_block, +static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, u32 big_page_size) { struct gk20a *g = gk20a_from_vm(vm); @@ -53,12 +53,12 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block, g->ops.mm.set_big_page_size(g, inst_block, big_page_size); } -bool gv11b_mm_mmu_fault_pending(struct gk20a *g) +static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { return gv11b_fb_mmu_fault_pending(g); } -void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) +static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) { nvgpu_log_fn(g, " "); @@ -174,7 +174,7 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) } } -void gv11b_mm_remove_bar2_vm(struct gk20a *g) +static void gv11b_mm_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -221,7 +221,7 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) return err; } -int gv11b_init_mm_setup_hw(struct gk20a *g) +static int gv11b_init_mm_setup_hw(struct gk20a *g) { int err = 0; @@ -260,7 +260,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) * checking bit 36 of the phsyical address. So if a mapping should allocte lines * in the L3 this bit must be set. */ -u64 gv11b_gpu_phys_addr(struct gk20a *g, +static u64 gv11b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys) { if (attrs && attrs->t19x_attrs.l3_alloc) @@ -269,7 +269,7 @@ u64 gv11b_gpu_phys_addr(struct gk20a *g, return phys; } -int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) +static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; @@ -318,3 +318,19 @@ int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); return -EBUSY; } + +void gv11b_init_mm(struct gpu_ops *gops) +{ + gp10b_init_mm(gops); + gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; + gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; + gops->mm.init_inst_block = gv11b_init_inst_block; + gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; + gops->mm.l2_flush = gv11b_mm_l2_flush; + gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; + gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; + gops->mm.fault_info_mem_destroy = + gv11b_mm_fault_info_mem_destroy; + gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; + gops->mm.init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup; +} diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h index 12f0fe63..a887c7f4 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h @@ -18,20 +18,7 @@ #define HW_FAULT_BUF_STATUS_ALLOC_TRUE 1 #define HW_FAULT_BUF_STATUS_ALLOC_FALSE 0 -struct gk20a; -struct nvgpu_mem; -struct vm_gk20a; - -bool gv11b_mm_is_bar1_supported(struct gk20a *g); -void gv11b_init_inst_block(struct nvgpu_mem *inst_block, - struct vm_gk20a *vm, u32 big_page_size); -bool gv11b_mm_mmu_fault_pending(struct gk20a *g); -void gv11b_mm_remove_bar2_vm(struct gk20a *g); -int gv11b_init_mm_setup_hw(struct gk20a *g); -int gv11b_init_bar2_mm_hw_setup(struct gk20a *g); -void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate); -u64 gv11b_gpu_phys_addr(struct gk20a *g, - struct nvgpu_gmmu_attrs *attrs, u64 phys); -void gv11b_mm_fault_info_mem_destroy(struct gk20a *g); +struct gpu_ops; +void gv11b_init_mm(struct gpu_ops *gops); #endif -- cgit v1.2.2 From 6486d4b8f1c9750f039374db00477e0af167cfbe Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 11 Aug 2017 14:41:50 -0700 Subject: Revert "gpu: nvgpu: gv11b: Reorg fb HAL initialization" Conflicts with gv100 changes This reverts commit da8e67f042760d54f3d6b5f84abbd9981d9fcd54. Change-Id: Ifd1a51debc0e92fc443e6ac0aad1b224821d6585 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537669 Reviewed-by: Shu Zhong Tested-by: Shu Zhong --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 25 +++++++++++++++++++------ drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 11 ++--------- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 25 +------------------------ 3 files changed, 22 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 384dfb20..35227576 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -75,7 +75,7 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) } -void gv11b_fb_init_fs_state(struct gk20a *g) +static void gv11b_fb_init_fs_state(struct gk20a *g) { nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb"); @@ -87,7 +87,7 @@ void gv11b_fb_init_fs_state(struct gk20a *g) gk20a_readl(g, fb_mmu_num_active_ltcs_r()))); } -void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) +static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) { u32 max_size = gr->max_comptag_mem; /* one tag line covers 64KB */ @@ -137,7 +137,7 @@ void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) } -void gv11b_fb_reset(struct gk20a *g) +static void gv11b_fb_reset(struct gk20a *g) { u32 val; @@ -251,7 +251,7 @@ static const char *const gpc_client_descs_gv11b[] = { "t1 36", "t1 37", "t1 38", "t1 39", }; -noinline_for_stack void gv11b_init_uncompressed_kind_map(void) +static noinline_for_stack void gv11b_init_uncompressed_kind_map(void) { int i; @@ -672,7 +672,7 @@ static noinline_for_stack bool gv11b_kind_zbc(u8 k) k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); } -void gv11b_init_kind_attr(void) +static void gv11b_init_kind_attr(void) { u16 k; @@ -1815,7 +1815,7 @@ static void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr) fb_mmu_fault_status_valid_clear_f()); } -void gv11b_fb_hub_isr(struct gk20a *g) +static void gv11b_fb_hub_isr(struct gk20a *g) { u32 status, niso_intr; @@ -1967,3 +1967,16 @@ static int gv11b_fb_fix_page_fault(struct gk20a *g, pte[1], pte[0]); return err; } + +void gv11b_init_fb(struct gpu_ops *gops) +{ + gp10b_init_fb(gops); + gops->fb.hub_isr = gv11b_fb_hub_isr; + gops->fb.reset = gv11b_fb_reset; + gops->fb.init_fs_state = gv11b_fb_init_fs_state; + gops->fb.init_cbc = gv11b_fb_init_cbc; + + gv11b_init_uncompressed_kind_map(); + gv11b_init_kind_attr(); + +} diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index 3e2dd828..39cdfb77 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -42,13 +42,9 @@ #define FAULT_TYPE_OTHER_AND_NONREPLAY 0 #define FAULT_TYPE_REPLAY 1 -struct gk20a; - -void gv11b_fb_init_fs_state(struct gk20a *g); -void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr); -void gv11b_fb_reset(struct gk20a *g); -void gv11b_fb_hub_isr(struct gk20a *g); +struct gpu_ops; +void gv11b_init_fb(struct gpu_ops *gops); u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g, unsigned int index); void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g, @@ -60,7 +56,4 @@ void gv11b_fb_disable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index); bool gv11b_fb_mmu_fault_pending(struct gk20a *g); - -noinline_for_stack void gv11b_init_uncompressed_kind_map(void); -void gv11b_init_kind_attr(void); #endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9f6c67c1..282aa228 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -29,11 +29,9 @@ #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" -#include "gk20a/fb_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" -#include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gp10b/ltc_gp10b.h" @@ -43,7 +41,6 @@ #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" -#include "gp10b/fb_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -178,23 +175,6 @@ static const struct gpu_ops gv11b_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, - .fb = { - .reset = gv11b_fb_reset, - .init_hw = gk20a_fb_init_hw, - .init_fs_state = gv11b_fb_init_fs_state, - .init_cbc = gv11b_fb_init_cbc, - .set_mmu_page_size = gm20b_fb_set_mmu_page_size, - .set_use_full_comp_tag_line = - gm20b_fb_set_use_full_comp_tag_line, - .compression_page_size = gp10b_fb_compression_page_size, - .compressible_page_size = gp10b_fb_compressible_page_size, - .vpr_info_fetch = gm20b_fb_vpr_info_fetch, - .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, - .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, - .set_debug_mode = gm20b_fb_set_debug_mode, - .tlb_invalidate = gk20a_fb_tlb_invalidate, - .hub_isr = gv11b_fb_hub_isr, - }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, @@ -425,7 +405,6 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; - gops->fb = gv11b_ops.fb; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; @@ -453,12 +432,10 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); + gv11b_init_fb(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); - gv11b_init_uncompressed_kind_map(); - gv11b_init_kind_attr(); - g->name = "gv11b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 545363e3422aa4711dccea291c994be31c5aff66 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 11 Aug 2017 14:43:50 -0700 Subject: Revert "gpu: nvgpu: gv11b: remove kind map inheritance" Conflicts with gv100 changes This reverts commit 2660d1d881d1536c1b723d9737ae9a04321d69f3. Change-Id: Id64e1353069aab2155fb0688b55cc7ce3b092516 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537672 Reviewed-by: Shu Zhong Tested-by: Shu Zhong --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 421 ++----------------------------------- 1 file changed, 16 insertions(+), 405 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 35227576..51ee55f8 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -30,11 +30,12 @@ #include "gv11b/fb_gv11b.h" #include "gv11b/ce_gv11b.h" +#include #include #include #include #include -#include + static int gv11b_fb_fix_page_fault(struct gk20a *g, struct mmu_fault_info *mmfault); @@ -251,440 +252,50 @@ static const char *const gpc_client_descs_gv11b[] = { "t1 36", "t1 37", "t1 38", "t1 39", }; -static noinline_for_stack void gv11b_init_uncompressed_kind_map(void) +static void gv11b_init_uncompressed_kind_map(void) { - int i; - - for (i = 0; i < 256; i++) - gk20a_uc_kind_map[i] = gmmu_pte_kind_invalid_v(); - - /* From gv11b */ gk20a_uc_kind_map[gmmu_pte_kind_c32_ms2_4cbra_v()] = gk20a_uc_kind_map[gmmu_pte_kind_c64_ms2_4cbra_v()] = gmmu_pte_kind_generic_16bx2_v(); - - /* From gp10b */ - gk20a_uc_kind_map[gmmu_pte_kind_z16_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms16_2cz_v()] = - gmmu_pte_kind_z16_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_4cbra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_4cbra_v()] = - gmmu_pte_kind_generic_16bx2_v(); - - /* From gm20b */ - gk20a_uc_kind_map[gmmu_pte_kind_s8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8_2s_v()] = - gmmu_pte_kind_s8_v(); - - /* From gk20a */ - gk20a_uc_kind_map[gmmu_pte_kind_z16_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_2z_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2z_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2z_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2z_v()] = - gmmu_pte_kind_z16_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms2_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms4_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms8_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms2_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms8_2cs_v()] = - gmmu_pte_kind_s8z24_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2zv_v()] = - gmmu_pte_kind_v8z24_ms4_vc4_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2zv_v()] = - gmmu_pte_kind_v8z24_ms8_vc8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2zv_v()] = - gmmu_pte_kind_v8z24_ms4_vc12_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2zv_v()] = - gmmu_pte_kind_v8z24_ms8_vc24_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms2_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms2_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms4_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms8_2cz_v()] = - gmmu_pte_kind_z24s8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms2_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms2_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms4_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms8_2cz_v()] = - gmmu_pte_kind_zf32_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v()] = - gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v()] = - gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v()] = - gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()] = - gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v()] = - gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v()] = - gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v()] = - gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()] = - gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_2cszv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms2_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms8_2cs_v()] = - gmmu_pte_kind_zf32_x24s8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_c32_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_2cba_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_2bra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms2_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cbr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cba_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2bra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms8_ms16_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms8_ms16_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_2cbr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_2cba_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_2bra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms2_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cbr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cba_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2bra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms8_ms16_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms8_ms16_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_2cr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms2_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms2_2cr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms4_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms4_2cr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms8_ms16_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms8_ms16_2cr_v()] = - gmmu_pte_kind_generic_16bx2_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2zv_v()] = - gmmu_pte_kind_z24v8_ms4_vc4_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2zv_v()] = - gmmu_pte_kind_z24v8_ms4_vc12_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2zv_v()] = - gmmu_pte_kind_z24v8_ms8_vc8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2zv_v()] = - gmmu_pte_kind_z24v8_ms8_vc24_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_x8c24_v()] = - gmmu_pte_kind_x8c24_v(); -} - -static noinline_for_stack bool gv11b_kind_supported(u8 k) -{ - return /* From gv11b */ - k == gmmu_pte_kind_c32_ms2_4cbra_v() - || k == gmmu_pte_kind_c64_ms2_4cbra_v() - /* From gp10b */ - || (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) - || k == gmmu_pte_kind_z16_ms16_2cz_v() - || k == gmmu_pte_kind_c32_ms4_4cbra_v() - || k == gmmu_pte_kind_c64_ms4_4cbra_v() - /* From gm20b */ - || (k == gmmu_pte_kind_smsked_message_v()) - || (k >= gmmu_pte_kind_s8_v() && - k <= gmmu_pte_kind_s8_2s_v()) - /* From gk20a */ - || gk20a_kind_work_creation(k) - || (k == gmmu_pte_kind_invalid_v()) - || (k == gmmu_pte_kind_pitch_v()) - || (k >= gmmu_pte_kind_z16_v() && - k <= gmmu_pte_kind_z16_ms8_2c_v()) - || (k >= gmmu_pte_kind_z16_2z_v() && - k <= gmmu_pte_kind_z16_ms8_2z_v()) - || (k == gmmu_pte_kind_s8z24_v()) - || (k >= gmmu_pte_kind_s8z24_2cz_v() && - k <= gmmu_pte_kind_s8z24_ms8_2cz_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_2zv_v()) - || (k == gmmu_pte_kind_z24s8_v()) - || (k >= gmmu_pte_kind_z24s8_2cz_v() && - k <= gmmu_pte_kind_z24s8_ms8_2cz_v()) - || (k == gmmu_pte_kind_zf32_v()) - || (k >= gmmu_pte_kind_zf32_2cz_v() && - k <= gmmu_pte_kind_zf32_ms8_2cz_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v() && - k <= gmmu_pte_kind_zf32_x24s8_v()) - || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && - k <= gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v()) - || (k == gmmu_pte_kind_generic_16bx2_v()) - || (k == gmmu_pte_kind_c32_2c_v()) - || (k == gmmu_pte_kind_c32_2cra_v()) - || (k == gmmu_pte_kind_c32_ms2_2c_v()) - || (k >= gmmu_pte_kind_c32_ms4_2c_v() && - k <= gmmu_pte_kind_c32_ms4_2cbr_v()) - || (k >= gmmu_pte_kind_c32_ms4_2cra_v() && - k <= gmmu_pte_kind_c64_2c_v()) - || (k == gmmu_pte_kind_c64_2cra_v()) - || (k == gmmu_pte_kind_c64_ms2_2c_v()) - || (k >= gmmu_pte_kind_c64_ms4_2c_v() && - k <= gmmu_pte_kind_c64_ms4_2cbr_v()) - || (k >= gmmu_pte_kind_c64_ms4_2cra_v() && - k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()) - || (k == gmmu_pte_kind_pitch_no_swizzle_v()); } -static noinline_for_stack bool gv11b_kind_z(u8 k) +static bool gv11b_kind_supported(u8 k) { - return /* From gv11b */ - (k == gmmu_pte_kind_c32_ms2_4cbra_v()) - || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) - /* From gp10b */ - || (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) - || (k == gmmu_pte_kind_z16_ms16_2cz_v()) - /* From gm20b */ - || (k >= gmmu_pte_kind_s8_v() && - k <= gmmu_pte_kind_s8_2s_v()) - /* From gk20a */ - || (k >= gmmu_pte_kind_z16_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()); + return (k == gmmu_pte_kind_c32_ms2_4cbra_v() + || k == gmmu_pte_kind_c64_ms2_4cbra_v()); } -static noinline_for_stack bool gv11b_kind_c(u8 k) +static bool gv11b_kind_z(u8 k) { - return gk20a_kind_work_creation(k) - || (k == gmmu_pte_kind_pitch_v()) - || (k == gmmu_pte_kind_generic_16bx2_v()) - || (k >= gmmu_pte_kind_c32_2c_v() && - k <= gmmu_pte_kind_c32_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c32_ms4_2c_v() && - k <= gmmu_pte_kind_c64_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c64_ms4_2c_v() && - k <= gmmu_pte_kind_pitch_no_swizzle_v()); + return (k == gmmu_pte_kind_c32_ms2_4cbra_v() + || k == gmmu_pte_kind_c64_ms2_4cbra_v()); } -static noinline_for_stack bool gv11b_kind_compressible(u8 k) +static bool gv11b_kind_compressible(u8 k) { - return /* From gv11b */ - (k == gmmu_pte_kind_c32_ms2_4cbra_v()) - || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) - /* From gp10b */ - || (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) - || (k == gmmu_pte_kind_z16_ms16_2cz_v()) - || (k == gmmu_pte_kind_c32_ms4_4cbra_v()) - || (k == gmmu_pte_kind_c64_ms4_4cbra_v()) - /* From gm20b */ - || (k >= gmmu_pte_kind_s8_v() && - k <= gmmu_pte_kind_s8_2s_v()) - /* From gk20a */ - || (k >= gmmu_pte_kind_s8z24_1z_v() && - k <= gmmu_pte_kind_s8z24_ms16_4cszv_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v()) - || (k >= gmmu_pte_kind_z24s8_1z_v() && - k <= gmmu_pte_kind_z24s8_ms16_4cszv_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v()) - || (k >= gmmu_pte_kind_zf32_1z_v() && - k <= gmmu_pte_kind_zf32_ms16_2cz_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()) - || (k >= gmmu_pte_kind_zf32_x24s8_1cs_v() && - k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()) - || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && - k <= gmmu_pte_kind_c32_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c32_ms4_2c_v() && - k <= gmmu_pte_kind_c64_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c64_ms4_2c_v() && - k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); + return (k == gmmu_pte_kind_c32_ms2_4cbra_v() + || k == gmmu_pte_kind_c64_ms2_4cbra_v()); } -static noinline_for_stack bool gv11b_kind_zbc(u8 k) +static bool gv11b_kind_zbc(u8 k) { - return /* From gv11b */ - (k == gmmu_pte_kind_c32_ms2_4cbra_v()) - || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) - /* From gp10b */ - || (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) - || (k == gmmu_pte_kind_z16_ms16_2cz_v()) - || (k == gmmu_pte_kind_c32_ms4_4cbra_v()) - || (k == gmmu_pte_kind_c64_ms4_4cbra_v()) - /* From gm20b */ - || (k >= gmmu_pte_kind_s8_v() && - k <= gmmu_pte_kind_s8_2s_v()) - /* From gk20a */ - || (k >= gmmu_pte_kind_z16_2c_v() && - k <= gmmu_pte_kind_z16_ms16_2c_v()) - || (k >= gmmu_pte_kind_s8z24_2cz_v() && - k <= gmmu_pte_kind_s8z24_ms16_4cszv_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2cs_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_2czv_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v()) - || (k >= gmmu_pte_kind_z24s8_2cs_v() && - k <= gmmu_pte_kind_z24s8_ms16_4cszv_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2cs_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_2czv_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v()) - || (k >= gmmu_pte_kind_zf32_2cs_v() && - k <= gmmu_pte_kind_zf32_ms16_2cz_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()) - || (k >= gmmu_pte_kind_zf32_x24s8_1cs_v() && - k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()) - || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && - k <= gmmu_pte_kind_c32_2cra_v()) - || (k >= gmmu_pte_kind_c32_ms2_2c_v() && - k <= gmmu_pte_kind_c32_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c32_ms4_2c_v() && - k <= gmmu_pte_kind_c32_ms4_2cra_v()) - || (k >= gmmu_pte_kind_c32_ms8_ms16_2c_v() && - k <= gmmu_pte_kind_c64_2cra_v()) - || (k >= gmmu_pte_kind_c64_ms2_2c_v() && - k <= gmmu_pte_kind_c64_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c64_ms4_2c_v() && - k <= gmmu_pte_kind_c64_ms4_2cra_v()) - || (k >= gmmu_pte_kind_c64_ms8_ms16_2c_v() && - k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); + return (k == gmmu_pte_kind_c32_ms2_4cbra_v() + || k == gmmu_pte_kind_c64_ms2_4cbra_v()); } static void gv11b_init_kind_attr(void) { u16 k; - for (k = 0; k < NV_KIND_ATTR_SIZE; k++) { + for (k = 0; k < 256; k++) { if (gv11b_kind_supported((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED; if (gv11b_kind_compressible((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE; if (gv11b_kind_z((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z; - if (gv11b_kind_c((u8)k)) - gk20a_kind_attr[k] |= GK20A_KIND_ATTR_C; if (gv11b_kind_zbc((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC; } -- cgit v1.2.2 From 78f1dac924221c9edbe51504b77e51caf2da7179 Mon Sep 17 00:00:00 2001 From: Sandarbh Jain Date: Wed, 9 Aug 2017 14:59:00 -0700 Subject: gpu: nvgpu: gv11b: PPC_IN_GPC_SHARED_BASE litter Adding missing GPU_LIT_PPC_IN_GPC_SHARED_BASE litter value Bug 1971835 Change-Id: If8851971ebea685fd6b3515b740aba8b64cae067 Signed-off-by: Sandarbh Jain Reviewed-on: https://git-master.nvidia.com/r/1536084 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 +++ drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 282aa228..7c38b611 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -108,6 +108,9 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_PPC_IN_GPC_BASE: ret = proj_ppc_in_gpc_base_v(); break; + case GPU_LIT_PPC_IN_GPC_SHARED_BASE: + ret = proj_ppc_in_gpc_shared_base_v(); + break; case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index a6515ba9..a17a7203 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -78,6 +78,10 @@ static inline u32 proj_ppc_in_gpc_base_v(void) { return 0x00003000; } +static inline u32 proj_ppc_in_gpc_shared_base_v(void) +{ + return 0x00003e00; +} static inline u32 proj_ppc_in_gpc_stride_v(void) { return 0x00000200; -- cgit v1.2.2 From de232ceb4b3bfa88650d1eed764357ba4a598076 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 31 Jul 2017 16:05:22 -0700 Subject: gpu: nvgpu: remove kind map inheritance Currently, the kind map initialization inherits from earlier chips' kind map definitions and simply adds on newly supported features. This is dangerous as changes in older architectures may affect newer architectures in unpredictable ways. This patch removes inheritance between subsequent architectures' kind map initializations. Jira NVGPU-74 Change-Id: Iab504d45b6ce2e625ed6788e62c1e7104e45c89a Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537747 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 421 +++++++++++++++++++++++++++++++++++-- 1 file changed, 405 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 51ee55f8..35227576 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -30,12 +30,11 @@ #include "gv11b/fb_gv11b.h" #include "gv11b/ce_gv11b.h" -#include #include #include #include #include - +#include static int gv11b_fb_fix_page_fault(struct gk20a *g, struct mmu_fault_info *mmfault); @@ -252,50 +251,440 @@ static const char *const gpc_client_descs_gv11b[] = { "t1 36", "t1 37", "t1 38", "t1 39", }; -static void gv11b_init_uncompressed_kind_map(void) +static noinline_for_stack void gv11b_init_uncompressed_kind_map(void) { + int i; + + for (i = 0; i < 256; i++) + gk20a_uc_kind_map[i] = gmmu_pte_kind_invalid_v(); + + /* From gv11b */ gk20a_uc_kind_map[gmmu_pte_kind_c32_ms2_4cbra_v()] = gk20a_uc_kind_map[gmmu_pte_kind_c64_ms2_4cbra_v()] = gmmu_pte_kind_generic_16bx2_v(); + + /* From gp10b */ + gk20a_uc_kind_map[gmmu_pte_kind_z16_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms16_2cz_v()] = + gmmu_pte_kind_z16_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_4cbra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_4cbra_v()] = + gmmu_pte_kind_generic_16bx2_v(); + + /* From gm20b */ + gk20a_uc_kind_map[gmmu_pte_kind_s8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8_2s_v()] = + gmmu_pte_kind_s8_v(); + + /* From gk20a */ + gk20a_uc_kind_map[gmmu_pte_kind_z16_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_2z_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2z_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2z_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2z_v()] = + gmmu_pte_kind_z16_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms2_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms4_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms8_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms2_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms8_2cs_v()] = + gmmu_pte_kind_s8z24_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2zv_v()] = + gmmu_pte_kind_v8z24_ms4_vc4_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2zv_v()] = + gmmu_pte_kind_v8z24_ms8_vc8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2zv_v()] = + gmmu_pte_kind_v8z24_ms4_vc12_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2zv_v()] = + gmmu_pte_kind_v8z24_ms8_vc24_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms2_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms2_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms4_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms8_2cz_v()] = + gmmu_pte_kind_z24s8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms2_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms2_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms4_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms8_2cz_v()] = + gmmu_pte_kind_zf32_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v()] = + gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v()] = + gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v()] = + gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()] = + gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v()] = + gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v()] = + gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v()] = + gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()] = + gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_2cszv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms2_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms8_2cs_v()] = + gmmu_pte_kind_zf32_x24s8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_c32_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_2cba_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_2bra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms2_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cbr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cba_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2bra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms8_ms16_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms8_ms16_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_2cbr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_2cba_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_2bra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms2_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cbr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cba_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2bra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms8_ms16_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms8_ms16_2cra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_2cr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms2_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms2_2cr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms4_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms4_2cr_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms8_ms16_2c_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c128_ms8_ms16_2cr_v()] = + gmmu_pte_kind_generic_16bx2_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2zv_v()] = + gmmu_pte_kind_z24v8_ms4_vc4_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2zv_v()] = + gmmu_pte_kind_z24v8_ms4_vc12_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2zv_v()] = + gmmu_pte_kind_z24v8_ms8_vc8_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2czv_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2zv_v()] = + gmmu_pte_kind_z24v8_ms8_vc24_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_x8c24_v()] = + gmmu_pte_kind_x8c24_v(); +} + +static noinline_for_stack bool gv11b_kind_supported(u8 k) +{ + return /* From gv11b */ + k == gmmu_pte_kind_c32_ms2_4cbra_v() + || k == gmmu_pte_kind_c64_ms2_4cbra_v() + /* From gp10b */ + || (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) + || k == gmmu_pte_kind_z16_ms16_2cz_v() + || k == gmmu_pte_kind_c32_ms4_4cbra_v() + || k == gmmu_pte_kind_c64_ms4_4cbra_v() + /* From gm20b */ + || (k == gmmu_pte_kind_smsked_message_v()) + || (k >= gmmu_pte_kind_s8_v() && + k <= gmmu_pte_kind_s8_2s_v()) + /* From gk20a */ + || gk20a_kind_work_creation(k) + || (k == gmmu_pte_kind_invalid_v()) + || (k == gmmu_pte_kind_pitch_v()) + || (k >= gmmu_pte_kind_z16_v() && + k <= gmmu_pte_kind_z16_ms8_2c_v()) + || (k >= gmmu_pte_kind_z16_2z_v() && + k <= gmmu_pte_kind_z16_ms8_2z_v()) + || (k == gmmu_pte_kind_s8z24_v()) + || (k >= gmmu_pte_kind_s8z24_2cz_v() && + k <= gmmu_pte_kind_s8z24_ms8_2cz_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_2zv_v()) + || (k == gmmu_pte_kind_z24s8_v()) + || (k >= gmmu_pte_kind_z24s8_2cz_v() && + k <= gmmu_pte_kind_z24s8_ms8_2cz_v()) + || (k == gmmu_pte_kind_zf32_v()) + || (k >= gmmu_pte_kind_zf32_2cz_v() && + k <= gmmu_pte_kind_zf32_ms8_2cz_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v() && + k <= gmmu_pte_kind_zf32_x24s8_v()) + || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && + k <= gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v()) + || (k == gmmu_pte_kind_generic_16bx2_v()) + || (k == gmmu_pte_kind_c32_2c_v()) + || (k == gmmu_pte_kind_c32_2cra_v()) + || (k == gmmu_pte_kind_c32_ms2_2c_v()) + || (k >= gmmu_pte_kind_c32_ms4_2c_v() && + k <= gmmu_pte_kind_c32_ms4_2cbr_v()) + || (k >= gmmu_pte_kind_c32_ms4_2cra_v() && + k <= gmmu_pte_kind_c64_2c_v()) + || (k == gmmu_pte_kind_c64_2cra_v()) + || (k == gmmu_pte_kind_c64_ms2_2c_v()) + || (k >= gmmu_pte_kind_c64_ms4_2c_v() && + k <= gmmu_pte_kind_c64_ms4_2cbr_v()) + || (k >= gmmu_pte_kind_c64_ms4_2cra_v() && + k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()) + || (k == gmmu_pte_kind_pitch_no_swizzle_v()); } -static bool gv11b_kind_supported(u8 k) +static noinline_for_stack bool gv11b_kind_z(u8 k) { - return (k == gmmu_pte_kind_c32_ms2_4cbra_v() - || k == gmmu_pte_kind_c64_ms2_4cbra_v()); + return /* From gv11b */ + (k == gmmu_pte_kind_c32_ms2_4cbra_v()) + || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) + /* From gp10b */ + || (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) + || (k == gmmu_pte_kind_z16_ms16_2cz_v()) + /* From gm20b */ + || (k >= gmmu_pte_kind_s8_v() && + k <= gmmu_pte_kind_s8_2s_v()) + /* From gk20a */ + || (k >= gmmu_pte_kind_z16_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()); } -static bool gv11b_kind_z(u8 k) +static noinline_for_stack bool gv11b_kind_c(u8 k) { - return (k == gmmu_pte_kind_c32_ms2_4cbra_v() - || k == gmmu_pte_kind_c64_ms2_4cbra_v()); + return gk20a_kind_work_creation(k) + || (k == gmmu_pte_kind_pitch_v()) + || (k == gmmu_pte_kind_generic_16bx2_v()) + || (k >= gmmu_pte_kind_c32_2c_v() && + k <= gmmu_pte_kind_c32_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c32_ms4_2c_v() && + k <= gmmu_pte_kind_c64_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c64_ms4_2c_v() && + k <= gmmu_pte_kind_pitch_no_swizzle_v()); } -static bool gv11b_kind_compressible(u8 k) +static noinline_for_stack bool gv11b_kind_compressible(u8 k) { - return (k == gmmu_pte_kind_c32_ms2_4cbra_v() - || k == gmmu_pte_kind_c64_ms2_4cbra_v()); + return /* From gv11b */ + (k == gmmu_pte_kind_c32_ms2_4cbra_v()) + || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) + /* From gp10b */ + || (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) + || (k == gmmu_pte_kind_z16_ms16_2cz_v()) + || (k == gmmu_pte_kind_c32_ms4_4cbra_v()) + || (k == gmmu_pte_kind_c64_ms4_4cbra_v()) + /* From gm20b */ + || (k >= gmmu_pte_kind_s8_v() && + k <= gmmu_pte_kind_s8_2s_v()) + /* From gk20a */ + || (k >= gmmu_pte_kind_s8z24_1z_v() && + k <= gmmu_pte_kind_s8z24_ms16_4cszv_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v()) + || (k >= gmmu_pte_kind_z24s8_1z_v() && + k <= gmmu_pte_kind_z24s8_ms16_4cszv_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v()) + || (k >= gmmu_pte_kind_zf32_1z_v() && + k <= gmmu_pte_kind_zf32_ms16_2cz_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()) + || (k >= gmmu_pte_kind_zf32_x24s8_1cs_v() && + k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()) + || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && + k <= gmmu_pte_kind_c32_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c32_ms4_2c_v() && + k <= gmmu_pte_kind_c64_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c64_ms4_2c_v() && + k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); } -static bool gv11b_kind_zbc(u8 k) +static noinline_for_stack bool gv11b_kind_zbc(u8 k) { - return (k == gmmu_pte_kind_c32_ms2_4cbra_v() - || k == gmmu_pte_kind_c64_ms2_4cbra_v()); + return /* From gv11b */ + (k == gmmu_pte_kind_c32_ms2_4cbra_v()) + || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) + /* From gp10b */ + || (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) + || (k == gmmu_pte_kind_z16_ms16_2cz_v()) + || (k == gmmu_pte_kind_c32_ms4_4cbra_v()) + || (k == gmmu_pte_kind_c64_ms4_4cbra_v()) + /* From gm20b */ + || (k >= gmmu_pte_kind_s8_v() && + k <= gmmu_pte_kind_s8_2s_v()) + /* From gk20a */ + || (k >= gmmu_pte_kind_z16_2c_v() && + k <= gmmu_pte_kind_z16_ms16_2c_v()) + || (k >= gmmu_pte_kind_s8z24_2cz_v() && + k <= gmmu_pte_kind_s8z24_ms16_4cszv_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2cs_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_2czv_v()) + || (k >= gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v() && + k <= gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v()) + || (k >= gmmu_pte_kind_z24s8_2cs_v() && + k <= gmmu_pte_kind_z24s8_ms16_4cszv_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2cs_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_2czv_v()) + || (k >= gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v() && + k <= gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v()) + || (k >= gmmu_pte_kind_zf32_2cs_v() && + k <= gmmu_pte_kind_zf32_ms16_2cz_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v() && + k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) + || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v() && + k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()) + || (k >= gmmu_pte_kind_zf32_x24s8_1cs_v() && + k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()) + || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && + k <= gmmu_pte_kind_c32_2cra_v()) + || (k >= gmmu_pte_kind_c32_ms2_2c_v() && + k <= gmmu_pte_kind_c32_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c32_ms4_2c_v() && + k <= gmmu_pte_kind_c32_ms4_2cra_v()) + || (k >= gmmu_pte_kind_c32_ms8_ms16_2c_v() && + k <= gmmu_pte_kind_c64_2cra_v()) + || (k >= gmmu_pte_kind_c64_ms2_2c_v() && + k <= gmmu_pte_kind_c64_ms2_2cbr_v()) + || (k >= gmmu_pte_kind_c64_ms4_2c_v() && + k <= gmmu_pte_kind_c64_ms4_2cra_v()) + || (k >= gmmu_pte_kind_c64_ms8_ms16_2c_v() && + k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); } static void gv11b_init_kind_attr(void) { u16 k; - for (k = 0; k < 256; k++) { + for (k = 0; k < NV_KIND_ATTR_SIZE; k++) { if (gv11b_kind_supported((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED; if (gv11b_kind_compressible((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE; if (gv11b_kind_z((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z; + if (gv11b_kind_c((u8)k)) + gk20a_kind_attr[k] |= GK20A_KIND_ATTR_C; if (gv11b_kind_zbc((u8)k)) gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC; } -- cgit v1.2.2 From 4bb0896912440d126ae47da350b448f37dabc63d Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 31 Jul 2017 14:40:46 -0700 Subject: gpu: nvgpu: Reorg fb HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3fdbf6059ef664caf8d33797a8a5f3f8eb6485bf Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537748 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 9 +-------- drivers/gpu/nvgpu/gv100/fb_gv100.h | 4 ++-- drivers/gpu/nvgpu/gv100/hal_gv100.c | 28 ++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 25 ++++++------------------- drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 11 +++++++++-- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 25 ++++++++++++++++++++++++- 6 files changed, 68 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c index a3785266..319ebad6 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -21,7 +21,6 @@ #include #include "gk20a/gk20a.h" -#include "gv11b/fb_gv11b.h" #include "gv100/fb_gv100.h" #include @@ -29,7 +28,7 @@ #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ -static void gv100_fb_reset(struct gk20a *g) +void gv100_fb_reset(struct gk20a *g) { u32 val; int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT; @@ -50,9 +49,3 @@ static void gv100_fb_reset(struct gk20a *g) val &= ~fb_mmu_priv_level_mask_write_violation_m(); gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); } - -void gv100_init_fb(struct gpu_ops *gops) -{ - gv11b_init_fb(gops); - gops->fb.reset = gv100_fb_reset; -} diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h index b234fa13..f3219177 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.h +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h @@ -16,7 +16,7 @@ #ifndef _NVGPU_GV100_FB #define _NVGPU_GV100_FB -struct gpu_ops; +struct gk20a; -void gv100_init_fb(struct gpu_ops *gops); +void gv100_fb_reset(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 337c607f..a2a131da 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -30,10 +30,14 @@ #include "gk20a/pramin_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" +#include "gk20a/fb_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" +#include "gm20b/fb_gm20b.h" + +#include "gp10b/fb_gp10b.h" #include "gp106/clk_gp106.h" #include "gp106/clk_arb_gp106.h" @@ -61,7 +65,7 @@ #include "gv100/gr_ctx_gv100.h" #include "gv100/mm_gv100.h" #include "gv11b/pmu_gv11b.h" -#include "gv100/fb_gv100.h" +#include "gv11b/fb_gv11b.h" #include "gv11b/fifo_gv11b.h" #include "gv11b/gv11b_gating_reglist.h" #include "gv11b/regops_gv11b.h" @@ -69,6 +73,7 @@ #include "gv100.h" #include "hal_gv100.h" +#include "gv100/fb_gv100.h" #include #include @@ -200,6 +205,23 @@ static const struct gpu_ops gv100_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, + .fb = { + .reset = gv100_fb_reset, + .init_hw = gk20a_fb_init_hw, + .init_fs_state = gv11b_fb_init_fs_state, + .init_cbc = gv11b_fb_init_cbc, + .set_mmu_page_size = gm20b_fb_set_mmu_page_size, + .set_use_full_comp_tag_line = + gm20b_fb_set_use_full_comp_tag_line, + .compression_page_size = gp10b_fb_compression_page_size, + .compressible_page_size = gp10b_fb_compressible_page_size, + .vpr_info_fetch = gm20b_fb_vpr_info_fetch, + .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, + .set_debug_mode = gm20b_fb_set_debug_mode, + .tlb_invalidate = gk20a_fb_tlb_invalidate, + .hub_isr = gv11b_fb_hub_isr, + }, .fifo = { .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, .bind_channel = channel_gm20b_bind, @@ -424,10 +446,12 @@ int gv100_init_hal(struct gk20a *g) g->bootstrap_owner = LSF_FALCON_ID_SEC2; gv11b_init_gr(g); - gv100_init_fb(gops); gv100_init_mm(gops); gp106_init_pmu_ops(g); + gv11b_init_uncompressed_kind_map(); + gv11b_init_kind_attr(); + g->name = "gv10x"; c->twod_class = FERMI_TWOD_A; diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 35227576..384dfb20 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -75,7 +75,7 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) } -static void gv11b_fb_init_fs_state(struct gk20a *g) +void gv11b_fb_init_fs_state(struct gk20a *g) { nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb"); @@ -87,7 +87,7 @@ static void gv11b_fb_init_fs_state(struct gk20a *g) gk20a_readl(g, fb_mmu_num_active_ltcs_r()))); } -static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) +void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) { u32 max_size = gr->max_comptag_mem; /* one tag line covers 64KB */ @@ -137,7 +137,7 @@ static void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) } -static void gv11b_fb_reset(struct gk20a *g) +void gv11b_fb_reset(struct gk20a *g) { u32 val; @@ -251,7 +251,7 @@ static const char *const gpc_client_descs_gv11b[] = { "t1 36", "t1 37", "t1 38", "t1 39", }; -static noinline_for_stack void gv11b_init_uncompressed_kind_map(void) +noinline_for_stack void gv11b_init_uncompressed_kind_map(void) { int i; @@ -672,7 +672,7 @@ static noinline_for_stack bool gv11b_kind_zbc(u8 k) k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); } -static void gv11b_init_kind_attr(void) +void gv11b_init_kind_attr(void) { u16 k; @@ -1815,7 +1815,7 @@ static void gv11b_fb_handle_mmu_fault(struct gk20a *g, u32 niso_intr) fb_mmu_fault_status_valid_clear_f()); } -static void gv11b_fb_hub_isr(struct gk20a *g) +void gv11b_fb_hub_isr(struct gk20a *g) { u32 status, niso_intr; @@ -1967,16 +1967,3 @@ static int gv11b_fb_fix_page_fault(struct gk20a *g, pte[1], pte[0]); return err; } - -void gv11b_init_fb(struct gpu_ops *gops) -{ - gp10b_init_fb(gops); - gops->fb.hub_isr = gv11b_fb_hub_isr; - gops->fb.reset = gv11b_fb_reset; - gops->fb.init_fs_state = gv11b_fb_init_fs_state; - gops->fb.init_cbc = gv11b_fb_init_cbc; - - gv11b_init_uncompressed_kind_map(); - gv11b_init_kind_attr(); - -} diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index 39cdfb77..3e2dd828 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -42,9 +42,13 @@ #define FAULT_TYPE_OTHER_AND_NONREPLAY 0 #define FAULT_TYPE_REPLAY 1 -struct gpu_ops; +struct gk20a; + +void gv11b_fb_init_fs_state(struct gk20a *g); +void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr); +void gv11b_fb_reset(struct gk20a *g); +void gv11b_fb_hub_isr(struct gk20a *g); -void gv11b_init_fb(struct gpu_ops *gops); u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g, unsigned int index); void gv11b_fb_fault_buf_set_state_hw(struct gk20a *g, @@ -56,4 +60,7 @@ void gv11b_fb_disable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index); bool gv11b_fb_mmu_fault_pending(struct gk20a *g); + +noinline_for_stack void gv11b_init_uncompressed_kind_map(void); +void gv11b_init_kind_attr(void); #endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 7c38b611..14b7a541 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -29,9 +29,11 @@ #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" +#include "gk20a/fb_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" +#include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gp10b/ltc_gp10b.h" @@ -41,6 +43,7 @@ #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" +#include "gp10b/fb_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -178,6 +181,23 @@ static const struct gpu_ops gv11b_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, + .fb = { + .reset = gv11b_fb_reset, + .init_hw = gk20a_fb_init_hw, + .init_fs_state = gv11b_fb_init_fs_state, + .init_cbc = gv11b_fb_init_cbc, + .set_mmu_page_size = gm20b_fb_set_mmu_page_size, + .set_use_full_comp_tag_line = + gm20b_fb_set_use_full_comp_tag_line, + .compression_page_size = gp10b_fb_compression_page_size, + .compressible_page_size = gp10b_fb_compressible_page_size, + .vpr_info_fetch = gm20b_fb_vpr_info_fetch, + .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, + .set_debug_mode = gm20b_fb_set_debug_mode, + .tlb_invalidate = gk20a_fb_tlb_invalidate, + .hub_isr = gv11b_fb_hub_isr, + }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, @@ -408,6 +428,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; + gops->fb = gv11b_ops.fb; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; @@ -435,10 +456,12 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_fb(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); + gv11b_init_uncompressed_kind_map(); + gv11b_init_kind_attr(); + g->name = "gv11b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 8ab6445df5b24c200ac4e346684119a85008e0e3 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 14:23:01 -0700 Subject: gpu: nvgpu: Reorg mm HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I5fd295c6473d5b4a6178c0c6be8fcf8f4c33f2e3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537754 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 33 +++++++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv100/mm_gv100.c | 10 +--------- drivers/gpu/nvgpu/gv100/mm_gv100.h | 4 ++-- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 30 +++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 32 ++++++++------------------------ drivers/gpu/nvgpu/gv11b/mm_gv11b.h | 17 +++++++++++++++-- 6 files changed, 86 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index a2a131da..74bc48fb 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -31,11 +31,13 @@ #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" #include "gk20a/fb_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/fb_gm20b.h" +#include "gm20b/mm_gm20b.h" #include "gp10b/fb_gp10b.h" @@ -55,6 +57,7 @@ #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" +#include "gp10b/mm_gp10b.h" #include "gv11b/hal_gv11b.h" #include "gv11b/gr_gv11b.h" @@ -63,7 +66,7 @@ #include "gv11b/gv11b.h" #include "gv11b/ce_gv11b.h" #include "gv100/gr_ctx_gv100.h" -#include "gv100/mm_gv100.h" +#include "gv11b/mm_gv11b.h" #include "gv11b/pmu_gv11b.h" #include "gv11b/fb_gv11b.h" #include "gv11b/fifo_gv11b.h" @@ -74,6 +77,7 @@ #include "gv100.h" #include "hal_gv100.h" #include "gv100/fb_gv100.h" +#include "gv100/mm_gv100.h" #include #include @@ -310,6 +314,32 @@ static const struct gpu_ops gv100_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gv11b_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gv11b_gpu_phys_addr, + .get_physical_addr_bits = NULL, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .get_vidmem_size = gv100_mm_get_vidmem_size, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = gv11b_init_mm_setup_hw, + .is_bar1_supported = gv11b_mm_is_bar1_supported, + .init_inst_block = gv11b_init_inst_block, + .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gv11b_mm_remove_bar2_vm, + .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + }, .pramin = { .enter = gk20a_pramin_enter, .exit = gk20a_pramin_exit, @@ -446,7 +476,6 @@ int gv100_init_hal(struct gk20a *g) g->bootstrap_owner = LSF_FALCON_ID_SEC2; gv11b_init_gr(g); - gv100_init_mm(gops); gp106_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c index fbc5df79..6952cb5e 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.c +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c @@ -14,12 +14,11 @@ */ #include "gk20a/gk20a.h" -#include "gv11b/mm_gv11b.h" #include "gv100/mm_gv100.h" #include -static size_t gv100_mm_get_vidmem_size(struct gk20a *g) +size_t gv100_mm_get_vidmem_size(struct gk20a *g) { u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r()); u32 mag = fb_mmu_local_memory_range_lower_mag_v(range); @@ -32,10 +31,3 @@ static size_t gv100_mm_get_vidmem_size(struct gk20a *g) return bytes; } - -void gv100_init_mm(struct gpu_ops *gops) -{ - gv11b_init_mm(gops); - gops->mm.get_vidmem_size = gv100_mm_get_vidmem_size; - gops->mm.get_physical_addr_bits = NULL; -} diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h index ff1bc3df..eeab7d56 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.h +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h @@ -16,8 +16,8 @@ #ifndef MM_GV100_H #define MM_GV100_H -struct gpu_ops; +struct gk20a; -void gv100_init_mm(struct gpu_ops *gops); +size_t gv100_mm_get_vidmem_size(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 14b7a541..f572084d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,6 +25,7 @@ #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -35,6 +36,7 @@ #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" +#include "gm20b/mm_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/therm_gp10b.h" @@ -44,6 +46,7 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/fb_gp10b.h" +#include "gp10b/mm_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -336,6 +339,31 @@ static const struct gpu_ops gv11b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gv11b_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gv11b_gpu_phys_addr, + .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = gv11b_init_mm_setup_hw, + .is_bar1_supported = gv11b_mm_is_bar1_supported, + .init_inst_block = gv11b_init_inst_block, + .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gv11b_mm_remove_bar2_vm, + .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + }, .therm = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, @@ -432,6 +460,7 @@ int gv11b_init_hal(struct gk20a *g) gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; + gops->mm = gv11b_ops.mm; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; gops->regops = gv11b_ops.regops; @@ -456,7 +485,6 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 7ba8f74f..941a0bbe 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -34,12 +34,12 @@ #define NVGPU_L3_ALLOC_BIT BIT(36) -static bool gv11b_mm_is_bar1_supported(struct gk20a *g) +bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; } -static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, +void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, u32 big_page_size) { struct gk20a *g = gk20a_from_vm(vm); @@ -53,12 +53,12 @@ static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, g->ops.mm.set_big_page_size(g, inst_block, big_page_size); } -static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) +bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { return gv11b_fb_mmu_fault_pending(g); } -static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) +void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) { nvgpu_log_fn(g, " "); @@ -174,7 +174,7 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) } } -static void gv11b_mm_remove_bar2_vm(struct gk20a *g) +void gv11b_mm_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -221,7 +221,7 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) return err; } -static int gv11b_init_mm_setup_hw(struct gk20a *g) +int gv11b_init_mm_setup_hw(struct gk20a *g) { int err = 0; @@ -260,7 +260,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) * checking bit 36 of the phsyical address. So if a mapping should allocte lines * in the L3 this bit must be set. */ -static u64 gv11b_gpu_phys_addr(struct gk20a *g, +u64 gv11b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys) { if (attrs && attrs->t19x_attrs.l3_alloc) @@ -269,7 +269,7 @@ static u64 gv11b_gpu_phys_addr(struct gk20a *g, return phys; } -static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) +int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; @@ -318,19 +318,3 @@ static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); return -EBUSY; } - -void gv11b_init_mm(struct gpu_ops *gops) -{ - gp10b_init_mm(gops); - gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; - gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; - gops->mm.init_inst_block = gv11b_init_inst_block; - gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; - gops->mm.l2_flush = gv11b_mm_l2_flush; - gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; - gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; - gops->mm.fault_info_mem_destroy = - gv11b_mm_fault_info_mem_destroy; - gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; - gops->mm.init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup; -} diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h index a887c7f4..12f0fe63 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h @@ -18,7 +18,20 @@ #define HW_FAULT_BUF_STATUS_ALLOC_TRUE 1 #define HW_FAULT_BUF_STATUS_ALLOC_FALSE 0 -struct gpu_ops; +struct gk20a; +struct nvgpu_mem; +struct vm_gk20a; + +bool gv11b_mm_is_bar1_supported(struct gk20a *g); +void gv11b_init_inst_block(struct nvgpu_mem *inst_block, + struct vm_gk20a *vm, u32 big_page_size); +bool gv11b_mm_mmu_fault_pending(struct gk20a *g); +void gv11b_mm_remove_bar2_vm(struct gk20a *g); +int gv11b_init_mm_setup_hw(struct gk20a *g); +int gv11b_init_bar2_mm_hw_setup(struct gk20a *g); +void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate); +u64 gv11b_gpu_phys_addr(struct gk20a *g, + struct nvgpu_gmmu_attrs *attrs, u64 phys); +void gv11b_mm_fault_info_mem_destroy(struct gk20a *g); -void gv11b_init_mm(struct gpu_ops *gops); #endif -- cgit v1.2.2 From bacbc7331223b0f80b36d7eff43009e5d7ac9aae Mon Sep 17 00:00:00 2001 From: Alexander Lewkowicz Date: Fri, 4 Aug 2017 15:51:42 -0700 Subject: gpu: nvgpu: gv11b: Fix computation of offset When reading NV_PGRAPH_PRI_GPC0_TPC1_SM1_DBGR_STATUS0, we are not reading the expected value. The offset of the sm is not added to the PRI. JIRA GPUT19X-75 bug: ? Change-Id: I2eeb24505e928044c3a3331fa5f493a3f118a3c8 Signed-off-by: Alexander Lewkowicz Reviewed-on: https://git-master.nvidia.com/r/1533953 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index b95152eb..2b0e8be7 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -3116,7 +3116,7 @@ static int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, u32 warp_esr, global_esr; struct nvgpu_timeout timeout; u32 offset = gk20a_gr_gpc_offset(g, gpc) + - gk20a_gr_tpc_offset(g, tpc); + gk20a_gr_tpc_offset(g, tpc) + gv11b_gr_sm_offset(g, sm); gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, -- cgit v1.2.2 From 6ff92bfb6e1ed68e29cef279f3275ac75ceaa4db Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Sun, 6 Aug 2017 14:44:11 +0530 Subject: gpu: nvgpu: Add wrapper over atomic_t and atomic64_t - added wrapper structs nvgpu_atomic_t and nvgpu_atomic64_t over atomic_t and atomic64_t - added nvgpu_atomic_* and nvgpu_atomic64_* APIs to access the above wrappers. JIRA NVGPU-121 Change-Id: I61667bb0a84c2fc475365abb79bffb42b8b4786a Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1533641 Reviewed-by: Terje Bergstrom Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity Tested-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index bd769f75..c2792414 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -315,11 +315,10 @@ void gv11b_dump_channel_status_ramfc(struct gk20a *g, inst_mem[ram_fc_sem_payload_lo_w()], inst_mem[ram_fc_sem_execute_w()]); if (hw_sema) - gk20a_debug_output(o, "SEMA STATE: value: 0x%08x " - "next_val: 0x%08x addr: 0x%010llx\n", - __nvgpu_semaphore_read(hw_sema), - atomic_read(&hw_sema->next_value), - nvgpu_hw_sema_addr(hw_sema)); + gk20a_debug_output(o, "SEMA STATE: value: 0x%08x next_val: 0x%08x addr: 0x%010llx\n", + __nvgpu_semaphore_read(hw_sema), + nvgpu_atomic_read(&hw_sema->next_value), + nvgpu_hw_sema_addr(hw_sema)); gk20a_debug_output(o, "\n"); } -- cgit v1.2.2 From cce0a55d2106865be14b3b39c083a0f55881f2a5 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 1 Aug 2017 17:12:03 -0700 Subject: gpu: nvgpu: gv11b: Reorg pmu HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3f8a763a7bebf201c2242eecde7ff998aad07d0a Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1530983 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 51 ++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 67 +++++++++++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 32 +++--------------- drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 5 ++- 4 files changed, 122 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 74bc48fb..bd13ec08 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -32,19 +32,23 @@ #include "gk20a/regops_gk20a.h" #include "gk20a/fb_gk20a.h" #include "gk20a/mm_gk20a.h" +#include "gk20a/pmu_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/mm_gm20b.h" +#include "gm20b/pmu_gm20b.h" +#include "gm20b/acr_gm20b.h" #include "gp10b/fb_gp10b.h" #include "gp106/clk_gp106.h" #include "gp106/clk_arb_gp106.h" #include "gp106/pmu_gp106.h" - +#include "gp106/acr_gp106.h" +#include "gp106/sec2_gp106.h" #include "gm206/bios_gm206.h" #include "gp106/therm_gp106.h" #include "gp106/xve_gp106.h" @@ -58,6 +62,7 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/pmu_gp10b.h" #include "gv11b/hal_gv11b.h" #include "gv11b/gr_gv11b.h" @@ -87,6 +92,7 @@ #include #include #include +#include static int gv100_get_litter_value(struct gk20a *g, int value) { @@ -345,6 +351,45 @@ static const struct gpu_ops gv100_ops = { .exit = gk20a_pramin_exit, .data032_r = pram_data032_r, }, + .pmu = { + .init_wpr_region = gm20b_pmu_init_acr, + .load_lsfalcon_ucode = gp106_load_falcon_ucode, + .is_lazy_bootstrap = gp106_is_lazy_bootstrap, + .is_priv_load = gp106_is_priv_load, + .prepare_ucode = gp106_prepare_ucode_blob, + .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn, + .get_wpr = gp106_wpr_info, + .alloc_blob_space = gp106_alloc_blob_space, + .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, + .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, + .falcon_wait_for_halt = sec2_wait_for_halt, + .falcon_clear_halt_interrupt_status = + sec2_clear_halt_interrupt_status, + .init_falcon_setup_hw = init_sec2_setup_hw1, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .is_pmu_supported = gp106_is_pmu_supported, + .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, + .pmu_elpg_statistics = gp106_pmu_elpg_statistics, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_is_lpwr_feature_supported = + gp106_pmu_is_lpwr_feature_supported, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_pg_param_post_init = nvgpu_lpwr_post_init, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_pg_init_param = gp106_pg_param_init, + .reset_engine = gp106_pmu_engine_reset, + .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg, + .write_dmatrfbase = gp10b_write_dmatrfbase, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .is_engine_in_reset = gp106_pmu_is_engine_in_reset, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, + }, .clk = { .init_clk_support = gp106_init_clk_support, .get_crystal_clk_hz = gp106_crystal_clk_hz, @@ -444,6 +489,7 @@ int gv100_init_hal(struct gk20a *g) gops->fecs_trace = gv100_ops.fecs_trace; gops->pramin = gv100_ops.pramin; gops->therm = gv100_ops.therm; + gops->pmu = gv100_ops.pmu; gops->mc = gv100_ops.mc; gops->debug = gv100_ops.debug; gops->dbg_session_ops = gv100_ops.dbg_session_ops; @@ -470,13 +516,14 @@ int gv100_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); /* for now */ __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); + g->pmu_lsf_pmu_wpr_init_done = 0; g->bootstrap_owner = LSF_FALCON_ID_SEC2; gv11b_init_gr(g); - gp106_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f572084d..521cafa3 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -31,12 +31,15 @@ #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" #include "gk20a/fb_gk20a.h" +#include "gk20a/pmu_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/mm_gm20b.h" +#include "gm20b/acr_gm20b.h" +#include "gm20b/pmu_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/therm_gp10b.h" @@ -47,6 +50,9 @@ #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/fb_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/pmu_gp10b.h" + +#include "gp106/pmu_gp106.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -70,6 +76,7 @@ #include #include #include +#include static int gv11b_get_litter_value(struct gk20a *g, int value) { @@ -368,6 +375,30 @@ static const struct gpu_ops gv11b_ops = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, }, + .pmu = { + .pmu_setup_elpg = gp10b_pmu_setup_elpg, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .write_dmatrfbase = gp10b_write_dmatrfbase, + .pmu_elpg_statistics = gp106_pmu_elpg_statistics, + .pmu_pg_init_param = gv11b_pg_gr_init, + .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, + .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, + .dump_secure_fuses = pmu_dump_security_fuses_gp10b, + .reset_engine = gp106_pmu_engine_reset, + .is_engine_in_reset = gp106_pmu_is_engine_in_reset, + .pmu_nsbootstrap = gv11b_pmu_bootstrap, + .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask, + .is_pmu_supported = gv11b_is_pmu_supported, + }, .regops = { .get_global_whitelist_ranges = gv11b_get_global_whitelist_ranges, @@ -463,6 +494,7 @@ int gv11b_init_hal(struct gk20a *g) gops->mm = gv11b_ops.mm; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; + gops->pmu = gv11b_ops.pmu; gops->regops = gv11b_ops.regops; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; @@ -479,13 +511,44 @@ int gv11b_init_hal(struct gk20a *g) gv11b_ops.chip_init_gpu_characteristics; gops->get_litter_value = gv11b_ops.get_litter_value; - /* boot in non-secure modes for time beeing */ + /* boot in non-secure modes for time being */ __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + /* priv security dependent ops */ + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + /* Add in ops from gm20b acr */ + gops->pmu.prepare_ucode = prepare_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn, + gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, + gops->pmu.is_priv_load = gm20b_is_priv_load, + gops->pmu.get_wpr = gm20b_wpr_info, + gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, + gops->pmu.pmu_populate_loader_cfg = + gm20b_pmu_populate_loader_cfg, + gops->pmu.flcn_populate_bl_dmem_desc = + gm20b_flcn_populate_bl_dmem_desc, + gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, + gops->pmu.falcon_clear_halt_interrupt_status = + clear_halt_interrupt_status, + gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, + + gops->pmu.init_wpr_region = gm20b_pmu_init_acr; + gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; + gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; + gops->pmu.is_priv_load = gp10b_is_priv_load; + } else { + /* Inherit from gk20a */ + gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, + + gops->pmu.load_lsfalcon_ucode = NULL; + gops->pmu.init_wpr_region = NULL; + gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; + } + gv11b_init_gr(g); - gv11b_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 35719dff..2b89fbcc 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -36,12 +36,12 @@ #define ALIGN_4KB 12 -static bool gv11b_is_pmu_supported(struct gk20a *g) +bool gv11b_is_pmu_supported(struct gk20a *g) { return true; } -static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) +int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); struct mm_gk20a *mm = &g->mm; @@ -178,7 +178,7 @@ static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg, msg->msg.pg.msg_type); } -static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) +int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) { struct nvgpu_pmu *pmu = &g->pmu; struct pmu_cmd cmd; @@ -206,7 +206,7 @@ static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) return 0; } -static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) +int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) { struct nvgpu_pmu *pmu = &g->pmu; struct pmu_cmd cmd; @@ -234,27 +234,3 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) return 0; } - -void gv11b_init_pmu_ops(struct gk20a *g) -{ - struct gpu_ops *gops = &g->ops; - - gp10b_init_pmu_ops(g); - gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; - gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; - gops->pmu.reset_engine = gp106_pmu_engine_reset; - gops->pmu.is_engine_in_reset = gp106_pmu_is_engine_in_reset; - gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; - gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; - gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; - gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; - gops->pmu.pmu_queue_head = gk20a_pmu_queue_head; - gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail; - gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; - gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; - gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; - gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; - gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; - gops->pmu.pmu_pg_init_param = gv11b_pg_gr_init; - gops->pmu.pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask; -} diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h index ce10c4cb..03fec2a3 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h @@ -18,6 +18,9 @@ struct gk20a; -void gv11b_init_pmu_ops(struct gk20a *g); +bool gv11b_is_pmu_supported(struct gk20a *g); +int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu); +int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); +int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id); #endif /*__PMU_GV11B_H_*/ -- cgit v1.2.2 From 2370fce04396b4bb66b679a54112731a0dbd7018 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 18 Aug 2017 10:35:34 -0700 Subject: gpu: nvpgu: gv100: Enable gv100 fb and mm ops Assign fb and mm ops for gv100. Change-Id: I031031935cdb1fa33fd9f06af2f2229480740bc5 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1541339 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index bd13ec08..e3c2d1cb 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -483,9 +483,11 @@ int gv100_init_hal(struct gk20a *g) gops->ltc = gv100_ops.ltc; gops->ce2 = gv100_ops.ce2; + gops->fb = gv100_ops.fb; gops->clock_gating = gv100_ops.clock_gating; gops->fifo = gv100_ops.fifo; gops->gr_ctx = gv100_ops.gr_ctx; + gops->mm = gv100_ops.mm; gops->fecs_trace = gv100_ops.fecs_trace; gops->pramin = gv100_ops.pramin; gops->therm = gv100_ops.therm; -- cgit v1.2.2 From ddeadd8cf250efa190ebc349776e90420a302038 Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Fri, 18 Aug 2017 16:29:55 +0530 Subject: gpu: nvgpu: Nvgpu abstraction for linux barriers. construct wrapper nvgpu_* methods to replace mb,rmb,wmb,smp_mb,smp_rmb,smp_wmb,read_barrier_depends and smp_read_barrier_depends. NVGPU-122 Change-Id: I97380c3b211733e682f198c35f35640af203359c Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1541197 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity Reviewed-by: Sourab Gupta GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 3 ++- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 384dfb20..a44589d5 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/kind_gk20a.h" @@ -721,7 +722,7 @@ static void gv11b_fb_fault_buffer_get_ptr_update(struct gk20a *g, /* make sure get ptr update is visible to everyone to avoid * reading already read entry */ - mb(); + nvgpu_mb(); } static u32 gv11b_fb_fault_buffer_get_index(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index c2792414..48d14e74 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -247,7 +248,7 @@ void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) nvgpu_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), c->gpfifo.put); /* commit everything to cpu */ - smp_mb(); + nvgpu_smp_mb(); gv11b_ring_channel_doorbell(c); } -- cgit v1.2.2 From 5df1d3ff7a23ec39ea5fc841b2dbfe98fa74b44a Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 18 Aug 2017 15:27:20 -0700 Subject: gpu: nvgpu: gv11b: release eng_method_buffers In case of any error while allocating eng_method_buffers release allocated buffers gracefully. Change-Id: Ic9d86b63d2405fd0113e63f2fc3f96166a4de9b5 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1541510 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 48d14e74..80bb64a0 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1543,7 +1543,8 @@ void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, { struct vm_gk20a *vm = g->mm.bar2.vm; int err = 0; - unsigned int i, runque, method_buffer_size; + int i; + unsigned int runque, method_buffer_size; unsigned int num_pbdma = g->fifo.num_pbdma; if (tsg->eng_method_buffers != NULL) @@ -1565,9 +1566,9 @@ void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, break; } if (err) { - for (i = runque; i < runque; i--) + for (i = (runque - 1); i >= 0; i--) nvgpu_dma_unmap_free(vm, - &tsg->eng_method_buffers[runque]); + &tsg->eng_method_buffers[i]); nvgpu_kfree(g, tsg->eng_method_buffers); tsg->eng_method_buffers = NULL; -- cgit v1.2.2 From bcf556b640a3680522b03042574081abe0e17fef Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Tue, 8 Aug 2017 15:48:23 -0700 Subject: gpu: nvgpu: correct NUM_FBPAS Although igpu does not have an FBPA unit, the hardware reports one, and the ucode leaves space for one in the HWPM context save buffer. So let NUM_FBPAS reflect this, so that registers that follow this section in the context buffer are offset properly JIRA EVLR-1716 Change-Id: I067d5ec3afd356bcb4270fc2b5d12daef2ce3944 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1535274 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 521cafa3..4b64d44d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -151,11 +151,14 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_SM_PRI_STRIDE: ret = proj_sm_stride_v(); break; - /* GV11B does not have a FBPA unit, despite what's listed in the - * hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS, - * so hardcode all values to 0. + /* Even though GV11B doesn't have an FBPA unit, the HW reports one, + * and the microcode as a result leaves space in the context buffer + * for one, so make sure SW accounts for this also. */ case GPU_LIT_NUM_FBPAS: + ret = proj_scal_litter_num_fbpas_v(); + break; + /* Hardcode FBPA values other than NUM_FBPAS to 0. */ case GPU_LIT_FBPA_STRIDE: case GPU_LIT_FBPA_BASE: case GPU_LIT_FBPA_SHARED_BASE: -- cgit v1.2.2 From 866165749a0b7b2e6b219bb26bffd69d790d97c5 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Thu, 17 Aug 2017 16:10:42 -0700 Subject: gpu: nvgpu: Reorg gr HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8feaa95a9830969221f7ac70a5ef61cdf25094c3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1542988 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 149 ++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 259 +++++++++++------------------------- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 140 ++++++++++++++++++- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 153 ++++++++++++++++++++- 4 files changed, 516 insertions(+), 185 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index e3c2d1cb..4f21e433 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -33,6 +33,7 @@ #include "gk20a/fb_gk20a.h" #include "gk20a/mm_gk20a.h" #include "gk20a/pmu_gk20a.h" +#include "gk20a/gr_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" @@ -43,6 +44,7 @@ #include "gm20b/acr_gm20b.h" #include "gp10b/fb_gp10b.h" +#include "gp10b/gr_gp10b.h" #include "gp106/clk_gp106.h" #include "gp106/clk_arb_gp106.h" @@ -215,6 +217,150 @@ static const struct gpu_ops gv100_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, + .gr = { + .init_gpc_mmu = gr_gv11b_init_gpc_mmu, + .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, + .cb_size_default = gr_gv11b_cb_size_default, + .calc_global_ctx_buffer_size = + gr_gv11b_calc_global_ctx_buffer_size, + .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, + .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, + .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, + .commit_global_pagepool = gr_gp10b_commit_global_pagepool, + .handle_sw_method = gr_gv11b_handle_sw_method, + .set_alpha_circular_buffer_size = + gr_gv11b_set_alpha_circular_buffer_size, + .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, + .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, + .is_valid_class = gr_gv11b_is_valid_class, + .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, + .is_valid_compute_class = gr_gv11b_is_valid_compute_class, + .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, + .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, + .init_fs_state = gr_gv11b_init_fs_state, + .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, + .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, + .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, + .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, + .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, + .free_channel_ctx = gk20a_free_channel_ctx, + .alloc_obj_ctx = gk20a_alloc_obj_ctx, + .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, + .get_zcull_info = gr_gk20a_get_zcull_info, + .is_tpc_addr = gr_gm20b_is_tpc_addr, + .get_tpc_num = gr_gm20b_get_tpc_num, + .detect_sm_arch = gr_gv11b_detect_sm_arch, + .add_zbc_color = gr_gp10b_add_zbc_color, + .add_zbc_depth = gr_gp10b_add_zbc_depth, + .zbc_set_table = gk20a_gr_zbc_set_table, + .zbc_query_table = gr_gk20a_query_zbc, + .pmu_save_zbc = gk20a_pmu_save_zbc, + .add_zbc = gr_gk20a_add_zbc, + .pagepool_default_size = gr_gv11b_pagepool_default_size, + .init_ctx_state = gr_gp10b_init_ctx_state, + .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, + .free_gr_ctx = gr_gp10b_free_gr_ctx, + .update_ctxsw_preemption_mode = + gr_gp10b_update_ctxsw_preemption_mode, + .dump_gr_regs = gr_gv11b_dump_gr_status_regs, + .update_pc_sampling = gr_gm20b_update_pc_sampling, + .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, + .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, + .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, + .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, + .get_max_fbps_count = gr_gm20b_get_max_fbps_count, + .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, + .wait_empty = gr_gv11b_wait_empty, + .init_cyclestats = gr_gv11b_init_cyclestats, + .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, + .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, + .bpt_reg_info = gv11b_gr_bpt_reg_info, + .get_access_map = gr_gv11b_get_access_map, + .handle_fecs_error = gr_gv11b_handle_fecs_error, + .handle_sm_exception = gr_gk20a_handle_sm_exception, + .handle_tex_exception = gr_gv11b_handle_tex_exception, + .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, + .enable_exceptions = gr_gv11b_enable_exceptions, + .get_lrf_tex_ltc_dram_override = get_ecc_override_val, + .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, + .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, + .record_sm_error_state = gv11b_gr_record_sm_error_state, + .update_sm_error_state = gv11b_gr_update_sm_error_state, + .clear_sm_error_state = gm20b_gr_clear_sm_error_state, + .suspend_contexts = gr_gp10b_suspend_contexts, + .resume_contexts = gr_gk20a_resume_contexts, + .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, + .fuse_override = gp10b_gr_fuse_override, + .init_sm_id_table = gr_gv11b_init_sm_id_table, + .load_smid_config = gr_gv11b_load_smid_config, + .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, + .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, + .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, + .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, + .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, + .setup_rop_mapping = gr_gv11b_setup_rop_mapping, + .program_zcull_mapping = gr_gv11b_program_zcull_mapping, + .commit_global_timeslice = gr_gv11b_commit_global_timeslice, + .commit_inst = gr_gv11b_commit_inst, + .write_zcull_ptr = gr_gv11b_write_zcull_ptr, + .write_pm_ptr = gr_gv11b_write_pm_ptr, + .init_elcg_mode = gr_gv11b_init_elcg_mode, + .load_tpc_mask = gr_gv11b_load_tpc_mask, + .inval_icache = gr_gk20a_inval_icache, + .trigger_suspend = gv11b_gr_sm_trigger_suspend, + .wait_for_pause = gr_gk20a_wait_for_pause, + .resume_from_pause = gv11b_gr_resume_from_pause, + .clear_sm_errors = gr_gk20a_clear_sm_errors, + .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, + .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, + .sm_debugger_attached = gv11b_gr_sm_debugger_attached, + .suspend_single_sm = gv11b_gr_suspend_single_sm, + .suspend_all_sms = gv11b_gr_suspend_all_sms, + .resume_single_sm = gv11b_gr_resume_single_sm, + .resume_all_sms = gv11b_gr_resume_all_sms, + .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, + .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, + .get_sm_no_lock_down_hww_global_esr_mask = + gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, + .lock_down_sm = gv11b_gr_lock_down_sm, + .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, + .clear_sm_hww = gv11b_gr_clear_sm_hww, + .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, + .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, + .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .set_boosted_ctx = gr_gp10b_set_boosted_ctx, + .set_preemption_mode = gr_gp10b_set_preemption_mode, + .set_czf_bypass = NULL, + .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, + .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, + .init_preemption_state = NULL, + .update_boosted_ctx = gr_gp10b_update_boosted_ctx, + .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, + .create_gr_sysfs = gr_gv11b_create_sysfs, + .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, + .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, + .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, + .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, + .zbc_s_query_table = gr_gv11b_zbc_s_query_table, + .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, + .restore_context_header = gv11b_restore_context_header, + .handle_gpc_gpcmmu_exception = + gr_gv11b_handle_gpc_gpcmmu_exception, + .add_zbc_type_s = gr_gv11b_add_zbc_type_s, + .get_egpc_base = gv11b_gr_get_egpc_base, + .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, + .handle_gpc_gpccs_exception = + gr_gv11b_handle_gpc_gpccs_exception, + .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, + .access_smpc_reg = gv11b_gr_access_smpc_reg, + .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, + .add_zbc_s = gr_gv11b_add_zbc_stencil, + .handle_gcc_exception = gr_gv11b_handle_gcc_exception, + .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, + .handle_tpc_sm_ecc_exception = + gr_gv11b_handle_tpc_sm_ecc_exception, + .decode_egpc_addr = gv11b_gr_decode_egpc_addr, + }, .fb = { .reset = gv100_fb_reset, .init_hw = gk20a_fb_init_hw, @@ -483,6 +629,7 @@ int gv100_init_hal(struct gk20a *g) gops->ltc = gv100_ops.ltc; gops->ce2 = gv100_ops.ce2; + gops->gr = gv100_ops.gr; gops->fb = gv100_ops.fb; gops->clock_gating = gv100_ops.clock_gating; gops->fifo = gv100_ops.fifo; @@ -525,8 +672,6 @@ int gv100_init_hal(struct gk20a *g) g->pmu_lsf_pmu_wpr_init_done = 0; g->bootstrap_owner = LSF_FALCON_ID_SEC2; - gv11b_init_gr(g); - gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 2b0e8be7..078272d1 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -51,7 +51,7 @@ #include #include -static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) +bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) { bool valid = false; @@ -80,7 +80,7 @@ static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) return valid; } -static bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) +bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) { bool valid = false; @@ -97,7 +97,7 @@ static bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num) return valid; } -static bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) +bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num) { bool valid = false; @@ -299,7 +299,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, } -static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) +void gr_gv11b_enable_hww_exceptions(struct gk20a *g) { /* enable exceptions */ gk20a_writel(g, gr_fe_hww_esr_r(), @@ -310,7 +310,7 @@ static void gr_gv11b_enable_hww_exceptions(struct gk20a *g) gr_memfmt_hww_esr_reset_active_f()); } -static void gr_gv11b_enable_exceptions(struct gk20a *g) +void gr_gv11b_enable_exceptions(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; u32 reg_val; @@ -581,7 +581,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, } -static int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, +int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event, struct channel_gk20a *fault_ch, u32 *hww_global_esr) @@ -606,7 +606,7 @@ static int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, return ret; } -static int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, +int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event, struct channel_gk20a *fault_ch, u32 *hww_global_esr) { @@ -852,7 +852,7 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, return ret; } -static int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, +int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, u32 gpc_exception) { if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpcmmu_m()) @@ -861,7 +861,7 @@ static int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, return 0; } -static int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, +int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, u32 gpc_exception) { if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpccs_m()) @@ -871,7 +871,7 @@ static int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, return 0; } -static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) +void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; u32 tpc_mask; @@ -889,13 +889,13 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(1))); } -static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, +int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event) { return 0; } -static int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, +int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, struct zbc_query_params *query_params) { u32 index = query_params->index_size; @@ -911,7 +911,7 @@ static int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, return 0; } -static bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, +bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *zbc_val, int *ret_val) { struct zbc_s_table *s_tbl; @@ -950,7 +950,7 @@ static bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, return added; } -static int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, +int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *stencil_val, u32 index) { u32 zbc_s; @@ -974,7 +974,7 @@ static int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, return 0; } -static int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, +int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, struct gr_gk20a *gr) { struct zbc_entry zbc_val; @@ -1005,7 +1005,7 @@ static int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, return 0; } -static int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr) +int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr) { int ret; u32 i; @@ -1025,12 +1025,12 @@ static int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr) return 0; } -static u32 gr_gv11b_pagepool_default_size(struct gk20a *g) +u32 gr_gv11b_pagepool_default_size(struct gk20a *g) { return gr_scc_pagepool_total_pages_hwmax_value_v(); } -static int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g) +int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; int size; @@ -1138,7 +1138,7 @@ static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) } } -static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, +int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data) { gk20a_dbg_fn(""); @@ -1192,7 +1192,7 @@ fail: return -EINVAL; } -static void gr_gv11b_bundle_cb_defaults(struct gk20a *g) +void gr_gv11b_bundle_cb_defaults(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; @@ -1204,7 +1204,7 @@ static void gr_gv11b_bundle_cb_defaults(struct gk20a *g) gr_pd_ab_dist_cfg2_token_limit_init_v(); } -static void gr_gv11b_cb_size_default(struct gk20a *g) +void gr_gv11b_cb_size_default(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; @@ -1215,7 +1215,7 @@ static void gr_gv11b_cb_size_default(struct gk20a *g) gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); } -static void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) +void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) { struct gr_gk20a *gr = &g->gr; u32 gpc_index, ppc_index, stride, val; @@ -1261,7 +1261,7 @@ static void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) } } -static void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data) +void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data) { struct gr_gk20a *gr = &g->gr; u32 gpc_index, ppc_index, stride, val; @@ -1442,7 +1442,7 @@ static int gr_gv11b_dump_gr_sm_regs(struct gk20a *g, return 0; } -static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, +int gr_gv11b_dump_gr_status_regs(struct gk20a *g, struct gk20a_debug_output *o) { struct gr_gk20a *gr = &g->gr; @@ -1595,7 +1595,7 @@ static bool gr_activity_empty_or_preempted(u32 val) return true; } -static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, +int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, u32 expect_delay) { u32 delay = expect_delay; @@ -1647,7 +1647,7 @@ static int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, return -EAGAIN; } -static void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, +void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, bool patch) { @@ -1676,7 +1676,7 @@ static void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, } -static void gr_gv11b_init_cyclestats(struct gk20a *g) +void gr_gv11b_init_cyclestats(struct gk20a *g) { #if defined(CONFIG_GK20A_CYCLE_STATS) g->gpu_characteristics.flags |= @@ -1688,7 +1688,7 @@ static void gr_gv11b_init_cyclestats(struct gk20a *g) #endif } -static void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) +void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) { #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); @@ -1706,7 +1706,7 @@ static void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); } -static void gr_gv11b_get_access_map(struct gk20a *g, +void gr_gv11b_get_access_map(struct gk20a *g, u32 **whitelist, int *num_entries) { static u32 wl_addr_gv11b[] = { @@ -1751,7 +1751,7 @@ static void gr_gv11b_get_access_map(struct gk20a *g, * * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing */ -static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, +int gr_gv11b_pre_process_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, bool sm_debugger_attached, struct channel_gk20a *fault_ch, bool *early_exit, bool *ignore_debugger) @@ -1940,7 +1940,7 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) } } -static int gr_gv11b_handle_fecs_error(struct gk20a *g, +int gr_gv11b_handle_fecs_error(struct gk20a *g, struct channel_gk20a *__ch, struct gr_gk20a_isr_data *isr_data) { @@ -1957,7 +1957,7 @@ static int gr_gv11b_handle_fecs_error(struct gk20a *g, return ret; } -static int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) +int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) { u32 map; u32 i, j, mapregs; @@ -2034,7 +2034,7 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) } } -static int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) +int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) { struct av_list_gk20a *sw_veid_bundle_init = &g->gr.ctx_vars.sw_veid_bundle_init; @@ -2099,7 +2099,7 @@ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, } } -static void gr_gv11b_detect_sm_arch(struct gk20a *g) +void gr_gv11b_detect_sm_arch(struct gk20a *g) { u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r()); @@ -2111,7 +2111,7 @@ static void gr_gv11b_detect_sm_arch(struct gk20a *g) gr_gpc0_tpc0_sm_arch_warp_count_v(v); } -static void gr_gv11b_init_sm_id_table(struct gk20a *g) +void gr_gv11b_init_sm_id_table(struct gk20a *g) { u32 gpc, tpc, sm; u32 sm_id = 0; @@ -2138,7 +2138,7 @@ static void gr_gv11b_init_sm_id_table(struct gk20a *g) nvgpu_log_info(g, " total number of sm = %d", g->gr.no_of_sm); } -static void gr_gv11b_program_sm_id_numbering(struct gk20a *g, +void gr_gv11b_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid) { u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); @@ -2156,7 +2156,7 @@ static void gr_gv11b_program_sm_id_numbering(struct gk20a *g, gr_gpc0_tpc0_pe_cfg_smid_value_f(global_tpc_index)); } -static int gr_gv11b_load_smid_config(struct gk20a *g) +int gr_gv11b_load_smid_config(struct gk20a *g) { u32 *tpc_sm_id; u32 i, j; @@ -2204,7 +2204,7 @@ static int gr_gv11b_load_smid_config(struct gk20a *g) return 0; } -static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) +int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) { u32 addr_lo; u32 addr_hi; @@ -2239,7 +2239,7 @@ static int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) -static int gr_gv11b_commit_global_timeslice(struct gk20a *g, +int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c, bool patch) { struct channel_ctx_gk20a *ch_ctx = NULL; @@ -2292,7 +2292,7 @@ static int gr_gv11b_commit_global_timeslice(struct gk20a *g, return 0; } -static void gv11b_restore_context_header(struct gk20a *g, +void gv11b_restore_context_header(struct gk20a *g, struct nvgpu_mem *ctxheader) { u32 va_lo, va_hi; @@ -2314,7 +2314,7 @@ static void gv11b_restore_context_header(struct gk20a *g, nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_num_save_ops_o(), 0); } -static void gr_gv11b_write_zcull_ptr(struct gk20a *g, +void gr_gv11b_write_zcull_ptr(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va) { u32 va_lo, va_hi; @@ -2329,7 +2329,7 @@ static void gr_gv11b_write_zcull_ptr(struct gk20a *g, } -static void gr_gv11b_write_pm_ptr(struct gk20a *g, +void gr_gv11b_write_pm_ptr(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va) { u32 va_lo, va_hi; @@ -2343,7 +2343,7 @@ static void gr_gv11b_write_pm_ptr(struct gk20a *g, ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi); } -static void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) +void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) { u32 gate_ctrl; @@ -2375,7 +2375,7 @@ static void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) gk20a_writel(g, therm_gate_ctrl_r(engine), gate_ctrl); } -static void gr_gv11b_load_tpc_mask(struct gk20a *g) +void gr_gv11b_load_tpc_mask(struct gk20a *g) { u32 pes_tpc_mask = 0, fuse_tpc_mask; u32 gpc, pes, val; @@ -2405,7 +2405,7 @@ static void gr_gv11b_load_tpc_mask(struct gk20a *g) } -static void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, +void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va) { u32 addr_lo, addr_hi; @@ -2426,7 +2426,7 @@ static void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, } -static int gr_gv11b_init_fs_state(struct gk20a *g) +int gr_gv11b_init_fs_state(struct gk20a *g) { u32 data; @@ -2451,7 +2451,7 @@ static int gr_gv11b_init_fs_state(struct gk20a *g) return gr_gm20b_init_fs_state(g); } -static void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, +void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, u32 *esr_sm_sel) { u32 reg_val; @@ -2469,7 +2469,7 @@ static void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); } -static int gv11b_gr_sm_trigger_suspend(struct gk20a *g) +int gv11b_gr_sm_trigger_suspend(struct gk20a *g) { u32 dbgr_control0; @@ -2491,7 +2491,7 @@ static int gv11b_gr_sm_trigger_suspend(struct gk20a *g) return 0; } -static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) +void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) { /* Check if we have at least one valid warp * get paused state on maxwell @@ -2559,7 +2559,7 @@ static void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) } } -static int gv11b_gr_update_sm_error_state(struct gk20a *g, +int gv11b_gr_update_sm_error_state(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id, struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state) { @@ -2638,7 +2638,7 @@ fail: return err; } -static int gv11b_gr_set_sm_debug_mode(struct gk20a *g, +int gv11b_gr_set_sm_debug_mode(struct gk20a *g, struct channel_gk20a *ch, u64 sms, bool enable) { struct nvgpu_dbg_gpu_reg_op *ops; @@ -2697,7 +2697,7 @@ static int gv11b_gr_set_sm_debug_mode(struct gk20a *g, return err; } -static int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) +int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) { int sm_id; struct gr_gk20a *gr = &g->gr; @@ -2737,7 +2737,7 @@ static int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) return 0; } -static void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g) +void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g) { /* clear hww */ @@ -2767,7 +2767,7 @@ static void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g) gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()); } -static bool gv11b_gr_sm_debugger_attached(struct gk20a *g) +bool gv11b_gr_sm_debugger_attached(struct gk20a *g) { u32 debugger_mode; u32 dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r()); @@ -2787,7 +2787,7 @@ static bool gv11b_gr_sm_debugger_attached(struct gk20a *g) return false; } -static void gv11b_gr_suspend_single_sm(struct gk20a *g, +void gv11b_gr_suspend_single_sm(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, bool check_errors) { @@ -2823,7 +2823,7 @@ static void gv11b_gr_suspend_single_sm(struct gk20a *g, } } -static void gv11b_gr_suspend_all_sms(struct gk20a *g, +void gv11b_gr_suspend_all_sms(struct gk20a *g, u32 global_esr_mask, bool check_errors) { struct gr_gk20a *gr = &g->gr; @@ -2868,7 +2868,7 @@ static void gv11b_gr_suspend_all_sms(struct gk20a *g, } } -static void gv11b_gr_resume_single_sm(struct gk20a *g, +void gv11b_gr_resume_single_sm(struct gk20a *g, u32 gpc, u32 tpc, u32 sm) { u32 dbgr_control0, dbgr_status0; @@ -2936,7 +2936,7 @@ static void gv11b_gr_resume_single_sm(struct gk20a *g, } -static void gv11b_gr_resume_all_sms(struct gk20a *g) +void gv11b_gr_resume_all_sms(struct gk20a *g) { u32 dbgr_control0, dbgr_status0; /* @@ -3001,7 +3001,7 @@ static void gv11b_gr_resume_all_sms(struct gk20a *g) dbgr_control0, dbgr_status0); } -static int gv11b_gr_resume_from_pause(struct gk20a *g) +int gv11b_gr_resume_from_pause(struct gk20a *g) { int err = 0; u32 reg_val; @@ -3020,7 +3020,7 @@ static int gv11b_gr_resume_from_pause(struct gk20a *g) return err; } -static u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, +u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm) { u32 offset = gk20a_gr_gpc_offset(g, gpc) + @@ -3032,7 +3032,7 @@ static u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, return hww_warp_esr; } -static u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, +u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm) { u32 offset = gk20a_gr_gpc_offset(g, gpc) + @@ -3045,7 +3045,7 @@ static u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, return hww_global_esr; } -static u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) +u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g) { /* * These three interrupts don't require locking down the SM. They can @@ -3104,7 +3104,7 @@ static void gv11b_gr_sm_dump_warp_bpt_pause_trap_mask_regs(struct gk20a *g, warps_paused, warps_trapped); } -static int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, +int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, bool check_errors) { @@ -3190,7 +3190,7 @@ static int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, return -ETIMEDOUT; } -static int gv11b_gr_lock_down_sm(struct gk20a *g, +int gv11b_gr_lock_down_sm(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, bool check_errors) { @@ -3212,7 +3212,7 @@ static int gv11b_gr_lock_down_sm(struct gk20a *g, check_errors); } -static void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, +void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr) { u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc) + @@ -3232,7 +3232,7 @@ static void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, offset)); } -static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, +int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event) { u32 esr; @@ -3263,7 +3263,7 @@ static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, static const u32 _num_ovr_perf_regs = 20; static u32 _ovr_perf_regs[20] = { 0, }; -static void gv11b_gr_init_ovr_sm_dsm_perf(void) +void gv11b_gr_init_ovr_sm_dsm_perf(void) { if (_ovr_perf_regs[0] != 0) return; @@ -3301,7 +3301,7 @@ static const u32 _num_sm_dsm_perf_ctrl_regs = 2; static u32 *_sm_dsm_perf_regs; static u32 _sm_dsm_perf_ctrl_regs[2]; -static void gv11b_gr_init_sm_dsm_reg_info(void) +void gv11b_gr_init_sm_dsm_reg_info(void) { if (_sm_dsm_perf_ctrl_regs[0] != 0) return; @@ -3312,7 +3312,7 @@ static void gv11b_gr_init_sm_dsm_reg_info(void) gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(); } -static void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, +void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, u32 *num_sm_dsm_perf_regs, u32 **sm_dsm_perf_regs, u32 *perf_register_stride) @@ -3323,7 +3323,7 @@ static void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); } -static void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, +void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, u32 *num_sm_dsm_perf_ctrl_regs, u32 **sm_dsm_perf_ctrl_regs, u32 *ctrl_register_stride) @@ -3334,14 +3334,14 @@ static void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); } -static void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, +void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, u32 **ovr_perf_regs) { *num_ovr_perf_regs = _num_ovr_perf_regs; *ovr_perf_regs = _ovr_perf_regs; } -static void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset) +void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset) { u32 reg_val; u32 quad_ctrl; @@ -3393,7 +3393,7 @@ static bool pri_is_egpc_addr_shared(struct gk20a *g, u32 addr) (addr < egpc_shared_base + gpc_stride); } -static bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr) +bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr) { u32 egpc_base = g->ops.gr.get_egpc_base(g); u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); @@ -3404,7 +3404,7 @@ static bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr) pri_is_egpc_addr_shared(g, addr); } -static bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr) +bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr) { u32 egpc_addr = 0; @@ -3454,7 +3454,7 @@ static u32 pri_etpc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 tpc) addr; } -static void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, +void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, u32 *egpc_num, u32 *etpc_num) { u32 egpc_addr = 0; @@ -3467,7 +3467,7 @@ static void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, "egpc_num = %d etpc_num = %d", *egpc_num, *etpc_num); } -static int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, +int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags) { u32 gpc_addr; @@ -3506,7 +3506,7 @@ static int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, return -EINVAL; } -static void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, +void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t) { u32 gpc_num, tpc_num; @@ -3569,12 +3569,12 @@ static void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, } } -static u32 gv11b_gr_get_egpc_base(struct gk20a *g) +u32 gv11b_gr_get_egpc_base(struct gk20a *g) { return EGPC_PRI_BASE; } -static void gr_gv11b_init_gpc_mmu(struct gk20a *g) +void gr_gv11b_init_gpc_mmu(struct gk20a *g) { u32 temp; @@ -3606,104 +3606,3 @@ static void gr_gv11b_init_gpc_mmu(struct gk20a *g) gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), gk20a_readl(g, fb_mmu_debug_rd_r())); } - -void gv11b_init_gr(struct gk20a *g) -{ - struct gpu_ops *gops = &g->ops; - - gp10b_init_gr(g); - gops->gr.init_preemption_state = NULL; - gops->gr.init_fs_state = gr_gv11b_init_fs_state; - gops->gr.detect_sm_arch = gr_gv11b_detect_sm_arch; - gops->gr.is_valid_class = gr_gv11b_is_valid_class; - gops->gr.is_valid_gfx_class = gr_gv11b_is_valid_gfx_class; - gops->gr.is_valid_compute_class = gr_gv11b_is_valid_compute_class; - gops->gr.set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va; - gops->gr.add_zbc_s = gr_gv11b_add_zbc_stencil; - gops->gr.load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl; - gops->gr.load_zbc_s_tbl = gr_gv11b_load_stencil_tbl; - gops->gr.zbc_s_query_table = gr_gv11b_zbc_s_query_table; - gops->gr.add_zbc_type_s = gr_gv11b_add_zbc_type_s; - gops->gr.pagepool_default_size = gr_gv11b_pagepool_default_size; - gops->gr.calc_global_ctx_buffer_size = - gr_gv11b_calc_global_ctx_buffer_size; - gops->gr.commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb; - gops->gr.handle_sw_method = gr_gv11b_handle_sw_method; - gops->gr.bundle_cb_defaults = gr_gv11b_bundle_cb_defaults; - gops->gr.cb_size_default = gr_gv11b_cb_size_default; - gops->gr.set_alpha_circular_buffer_size = - gr_gv11b_set_alpha_circular_buffer_size; - gops->gr.set_circular_buffer_size = - gr_gv11b_set_circular_buffer_size; - gops->gr.dump_gr_regs = gr_gv11b_dump_gr_status_regs; - gops->gr.wait_empty = gr_gv11b_wait_empty; - gops->gr.init_cyclestats = gr_gv11b_init_cyclestats; - gops->gr.set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask; - gops->gr.get_access_map = gr_gv11b_get_access_map; - gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; - gops->gr.handle_gcc_exception = gr_gv11b_handle_gcc_exception; - gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception; - gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions; - gops->gr.enable_exceptions = gr_gv11b_enable_exceptions; - gops->gr.enable_hww_exceptions = gr_gv11b_enable_hww_exceptions; - gops->gr.pre_process_sm_exception = - gr_gv11b_pre_process_sm_exception; - gops->gr.handle_fecs_error = gr_gv11b_handle_fecs_error; - gops->gr.create_gr_sysfs = gr_gv11b_create_sysfs; - gops->gr.setup_rop_mapping = gr_gv11b_setup_rop_mapping; - gops->gr.init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle; - gops->gr.program_zcull_mapping = gr_gv11b_program_zcull_mapping; - gops->gr.commit_global_timeslice = gr_gv11b_commit_global_timeslice; - gops->gr.init_sm_id_table = gr_gv11b_init_sm_id_table; - gops->gr.load_smid_config = gr_gv11b_load_smid_config; - gops->gr.program_sm_id_numbering = - gr_gv11b_program_sm_id_numbering; - gops->gr.commit_inst = gr_gv11b_commit_inst; - gops->gr.restore_context_header = gv11b_restore_context_header; - gops->gr.write_zcull_ptr = gr_gv11b_write_zcull_ptr; - gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; - gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode; - gops->gr.load_tpc_mask = gr_gv11b_load_tpc_mask; - gops->gr.handle_gpc_gpccs_exception = - gr_gv11b_handle_gpc_gpccs_exception; - gops->gr.set_czf_bypass = NULL; - gops->gr.handle_gpc_gpcmmu_exception = - gr_gv11b_handle_gpc_gpcmmu_exception; - gops->gr.get_esr_sm_sel = gv11b_gr_get_esr_sm_sel; - gops->gr.trigger_suspend = gv11b_gr_sm_trigger_suspend; - gops->gr.bpt_reg_info = gv11b_gr_bpt_reg_info; - gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; - gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode; - gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; - gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask; - gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached; - gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm; - gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms; - gops->gr.resume_single_sm = gv11b_gr_resume_single_sm; - gops->gr.resume_all_sms = gv11b_gr_resume_all_sms; - gops->gr.resume_from_pause = gv11b_gr_resume_from_pause; - gops->gr.get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr; - gops->gr.get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr; - gops->gr.get_sm_no_lock_down_hww_global_esr_mask = - gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask; - gops->gr.lock_down_sm = gv11b_gr_lock_down_sm; - gops->gr.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down; - gops->gr.clear_sm_hww = gv11b_gr_clear_sm_hww; - gops->gr.handle_tpc_sm_ecc_exception = - gr_gv11b_handle_tpc_sm_ecc_exception; - gops->gr.handle_tpc_mpc_exception = - gr_gv11b_handle_tpc_mpc_exception; - gops->gr.init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf; - gops->gr.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info; - gops->gr.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs; - gops->gr.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs; - gops->gr.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs; - gops->gr.access_smpc_reg = gv11b_gr_access_smpc_reg; - gops->gr.decode_egpc_addr = gv11b_gr_decode_egpc_addr; - gops->gr.egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table; - gops->gr.get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num; - gops->gr.get_egpc_base = gv11b_gr_get_egpc_base; - gops->gr.is_egpc_addr = gv11b_gr_pri_is_egpc_addr; - gops->gr.is_etpc_addr = gv11b_gr_pri_is_etpc_addr; - gops->gr.init_gpc_mmu = gr_gv11b_init_gpc_mmu; -} diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 69148554..9adace63 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -30,6 +30,9 @@ struct zbc_s_table { }; struct gk20a; +struct zbc_entry; +struct zbc_query_params; +struct channel_ctx_gk20a; enum { VOLTA_CHANNEL_GPFIFO_A = 0xC36F, @@ -59,11 +62,146 @@ enum { #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 -void gv11b_init_gr(struct gk20a *g); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct nvgpu_mem *mem); /*zcull*/ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, u32 *zcull_map_tiles); void gr_gv11b_create_sysfs(struct device *dev); + +bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num); +bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num); +bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num); +void gr_gv11b_enable_hww_exceptions(struct gk20a *g); +void gr_gv11b_enable_exceptions(struct gk20a *g); +int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, + u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr); +int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr); +int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, + u32 gpc_exception); +int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, + u32 gpc_exception); +void gr_gv11b_enable_gpc_exceptions(struct gk20a *g); +int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event); +int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_query_params *query_params); +bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *zbc_val, int *ret_val); +int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *stencil_val, u32 index); +int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, + struct gr_gk20a *gr); +int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr); +u32 gr_gv11b_pagepool_default_size(struct gk20a *g); +int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g); +int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data); +void gr_gv11b_bundle_cb_defaults(struct gk20a *g); +void gr_gv11b_cb_size_default(struct gk20a *g); +void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data); +void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data); +int gr_gv11b_dump_gr_status_regs(struct gk20a *g, + struct gk20a_debug_output *o); +int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, + u32 expect_delay); +void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, + struct channel_ctx_gk20a *ch_ctx, + u64 addr, bool patch); +void gr_gv11b_init_cyclestats(struct gk20a *g); +void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); +void gr_gv11b_get_access_map(struct gk20a *g, + u32 **whitelist, int *num_entries); +int gr_gv11b_pre_process_sm_exception(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, + bool sm_debugger_attached, struct channel_gk20a *fault_ch, + bool *early_exit, bool *ignore_debugger); +int gr_gv11b_handle_fecs_error(struct gk20a *g, + struct channel_gk20a *__ch, + struct gr_gk20a_isr_data *isr_data); +int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr); +int gr_gv11b_init_sw_veid_bundle(struct gk20a *g); +void gr_gv11b_detect_sm_arch(struct gk20a *g); +void gr_gv11b_init_sm_id_table(struct gk20a *g); +void gr_gv11b_program_sm_id_numbering(struct gk20a *g, + u32 gpc, u32 tpc, u32 smid); +int gr_gv11b_load_smid_config(struct gk20a *g); +int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); +int gr_gv11b_commit_global_timeslice(struct gk20a *g, + struct channel_gk20a *c, bool patch); +void gv11b_restore_context_header(struct gk20a *g, + struct nvgpu_mem *ctxheader); +void gr_gv11b_write_zcull_ptr(struct gk20a *g, + struct nvgpu_mem *mem, u64 gpu_va); +void gr_gv11b_write_pm_ptr(struct gk20a *g, + struct nvgpu_mem *mem, u64 gpu_va); +void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); +void gr_gv11b_load_tpc_mask(struct gk20a *g); +void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, + struct nvgpu_mem *mem, u64 gpu_va); +int gr_gv11b_init_fs_state(struct gk20a *g); +void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, + u32 *esr_sm_sel); +int gv11b_gr_sm_trigger_suspend(struct gk20a *g); +void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state); +int gv11b_gr_update_sm_error_state(struct gk20a *g, + struct channel_gk20a *ch, u32 sm_id, + struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state); +int gv11b_gr_set_sm_debug_mode(struct gk20a *g, + struct channel_gk20a *ch, u64 sms, bool enable); +int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc); +void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g); +bool gv11b_gr_sm_debugger_attached(struct gk20a *g); +void gv11b_gr_suspend_single_sm(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, + u32 global_esr_mask, bool check_errors); +void gv11b_gr_suspend_all_sms(struct gk20a *g, + u32 global_esr_mask, bool check_errors); +void gv11b_gr_resume_single_sm(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm); +void gv11b_gr_resume_all_sms(struct gk20a *g); +int gv11b_gr_resume_from_pause(struct gk20a *g); +u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm); +u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm); +u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); +int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, + u32 global_esr_mask, bool check_errors); +int gv11b_gr_lock_down_sm(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, + bool check_errors); +void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, + u32 global_esr); +int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, + u32 gpc, u32 tpc, bool *post_event); +void gv11b_gr_init_ovr_sm_dsm_perf(void); +void gv11b_gr_init_sm_dsm_reg_info(void); +void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, + u32 *num_sm_dsm_perf_regs, + u32 **sm_dsm_perf_regs, + u32 *perf_register_stride); +void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, + u32 *num_sm_dsm_perf_ctrl_regs, + u32 **sm_dsm_perf_ctrl_regs, + u32 *ctrl_register_stride); +void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, + u32 **ovr_perf_regs); +void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset); +bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr); +bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr); +void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, + u32 *egpc_num, u32 *etpc_num); +int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, + u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags); +void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, + u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t); +u32 gv11b_gr_get_egpc_base(struct gk20a *g); +void gr_gv11b_init_gpc_mmu(struct gk20a *g); + #endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4b64d44d..0c5776f0 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -32,6 +32,7 @@ #include "gk20a/regops_gk20a.h" #include "gk20a/fb_gk20a.h" #include "gk20a/pmu_gk20a.h" +#include "gk20a/gr_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" @@ -51,6 +52,7 @@ #include "gp10b/fb_gp10b.h" #include "gp10b/mm_gp10b.h" #include "gp10b/pmu_gp10b.h" +#include "gp10b/gr_gp10b.h" #include "gp106/pmu_gp106.h" @@ -194,6 +196,150 @@ static const struct gpu_ops gv11b_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, + .gr = { + .init_gpc_mmu = gr_gv11b_init_gpc_mmu, + .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, + .cb_size_default = gr_gv11b_cb_size_default, + .calc_global_ctx_buffer_size = + gr_gv11b_calc_global_ctx_buffer_size, + .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, + .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, + .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, + .commit_global_pagepool = gr_gp10b_commit_global_pagepool, + .handle_sw_method = gr_gv11b_handle_sw_method, + .set_alpha_circular_buffer_size = + gr_gv11b_set_alpha_circular_buffer_size, + .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, + .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, + .is_valid_class = gr_gv11b_is_valid_class, + .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, + .is_valid_compute_class = gr_gv11b_is_valid_compute_class, + .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, + .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, + .init_fs_state = gr_gv11b_init_fs_state, + .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, + .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, + .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, + .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, + .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, + .free_channel_ctx = gk20a_free_channel_ctx, + .alloc_obj_ctx = gk20a_alloc_obj_ctx, + .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, + .get_zcull_info = gr_gk20a_get_zcull_info, + .is_tpc_addr = gr_gm20b_is_tpc_addr, + .get_tpc_num = gr_gm20b_get_tpc_num, + .detect_sm_arch = gr_gv11b_detect_sm_arch, + .add_zbc_color = gr_gp10b_add_zbc_color, + .add_zbc_depth = gr_gp10b_add_zbc_depth, + .zbc_set_table = gk20a_gr_zbc_set_table, + .zbc_query_table = gr_gk20a_query_zbc, + .pmu_save_zbc = gk20a_pmu_save_zbc, + .add_zbc = gr_gk20a_add_zbc, + .pagepool_default_size = gr_gv11b_pagepool_default_size, + .init_ctx_state = gr_gp10b_init_ctx_state, + .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, + .free_gr_ctx = gr_gp10b_free_gr_ctx, + .update_ctxsw_preemption_mode = + gr_gp10b_update_ctxsw_preemption_mode, + .dump_gr_regs = gr_gv11b_dump_gr_status_regs, + .update_pc_sampling = gr_gm20b_update_pc_sampling, + .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, + .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, + .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, + .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, + .get_max_fbps_count = gr_gm20b_get_max_fbps_count, + .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, + .wait_empty = gr_gv11b_wait_empty, + .init_cyclestats = gr_gv11b_init_cyclestats, + .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, + .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, + .bpt_reg_info = gv11b_gr_bpt_reg_info, + .get_access_map = gr_gv11b_get_access_map, + .handle_fecs_error = gr_gv11b_handle_fecs_error, + .handle_sm_exception = gr_gk20a_handle_sm_exception, + .handle_tex_exception = gr_gv11b_handle_tex_exception, + .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, + .enable_exceptions = gr_gv11b_enable_exceptions, + .get_lrf_tex_ltc_dram_override = get_ecc_override_val, + .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, + .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, + .record_sm_error_state = gv11b_gr_record_sm_error_state, + .update_sm_error_state = gv11b_gr_update_sm_error_state, + .clear_sm_error_state = gm20b_gr_clear_sm_error_state, + .suspend_contexts = gr_gp10b_suspend_contexts, + .resume_contexts = gr_gk20a_resume_contexts, + .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, + .fuse_override = gp10b_gr_fuse_override, + .init_sm_id_table = gr_gv11b_init_sm_id_table, + .load_smid_config = gr_gv11b_load_smid_config, + .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, + .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, + .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, + .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, + .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, + .setup_rop_mapping = gr_gv11b_setup_rop_mapping, + .program_zcull_mapping = gr_gv11b_program_zcull_mapping, + .commit_global_timeslice = gr_gv11b_commit_global_timeslice, + .commit_inst = gr_gv11b_commit_inst, + .write_zcull_ptr = gr_gv11b_write_zcull_ptr, + .write_pm_ptr = gr_gv11b_write_pm_ptr, + .init_elcg_mode = gr_gv11b_init_elcg_mode, + .load_tpc_mask = gr_gv11b_load_tpc_mask, + .inval_icache = gr_gk20a_inval_icache, + .trigger_suspend = gv11b_gr_sm_trigger_suspend, + .wait_for_pause = gr_gk20a_wait_for_pause, + .resume_from_pause = gv11b_gr_resume_from_pause, + .clear_sm_errors = gr_gk20a_clear_sm_errors, + .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, + .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, + .sm_debugger_attached = gv11b_gr_sm_debugger_attached, + .suspend_single_sm = gv11b_gr_suspend_single_sm, + .suspend_all_sms = gv11b_gr_suspend_all_sms, + .resume_single_sm = gv11b_gr_resume_single_sm, + .resume_all_sms = gv11b_gr_resume_all_sms, + .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, + .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, + .get_sm_no_lock_down_hww_global_esr_mask = + gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, + .lock_down_sm = gv11b_gr_lock_down_sm, + .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, + .clear_sm_hww = gv11b_gr_clear_sm_hww, + .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, + .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, + .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .set_boosted_ctx = gr_gp10b_set_boosted_ctx, + .set_preemption_mode = gr_gp10b_set_preemption_mode, + .set_czf_bypass = NULL, + .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, + .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, + .init_preemption_state = NULL, + .update_boosted_ctx = gr_gp10b_update_boosted_ctx, + .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, + .create_gr_sysfs = gr_gv11b_create_sysfs, + .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, + .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, + .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, + .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, + .zbc_s_query_table = gr_gv11b_zbc_s_query_table, + .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, + .restore_context_header = gv11b_restore_context_header, + .handle_gpc_gpcmmu_exception = + gr_gv11b_handle_gpc_gpcmmu_exception, + .add_zbc_type_s = gr_gv11b_add_zbc_type_s, + .get_egpc_base = gv11b_gr_get_egpc_base, + .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, + .handle_gpc_gpccs_exception = + gr_gv11b_handle_gpc_gpccs_exception, + .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, + .access_smpc_reg = gv11b_gr_access_smpc_reg, + .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, + .add_zbc_s = gr_gv11b_add_zbc_stencil, + .handle_gcc_exception = gr_gv11b_handle_gcc_exception, + .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, + .handle_tpc_sm_ecc_exception = + gr_gv11b_handle_tpc_sm_ecc_exception, + .decode_egpc_addr = gv11b_gr_decode_egpc_addr, + }, .fb = { .reset = gv11b_fb_reset, .init_hw = gk20a_fb_init_hw, @@ -490,6 +636,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; + gops->gr = gv11b_ops.gr; gops->fb = gv11b_ops.fb; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; @@ -541,6 +688,8 @@ int gv11b_init_hal(struct gk20a *g) gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; gops->pmu.is_priv_load = gp10b_is_priv_load; + + gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; } else { /* Inherit from gk20a */ gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, @@ -549,9 +698,9 @@ int gv11b_init_hal(struct gk20a *g) gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; - } - gv11b_init_gr(g); + gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; + } gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); -- cgit v1.2.2 From 1ac8f6477df7bd1e1b1c5922b1916ae6450c07ad Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 21 Aug 2017 15:36:11 -0700 Subject: gpu: nvgpu: vgpu: add TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT Get max subctx count from RM server. Jira VFND-3797 Change-Id: I95de2271a77bedfa8703231fa45da05c7d2da3e6 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1543018 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 20 +++++++++++++++++++- include/linux/tegra_vgpu_t19x.h | 2 ++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c index b9df58ec..f8f021b7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -14,13 +14,31 @@ #include #include +#include "vgpu/vgpu.h" + #include "vgpu_fifo_gv11b.h" #include "vgpu_subctx_gv11b.h" +static int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) +{ + struct fifo_gk20a *f = &g->fifo; + int err; + + err = vgpu_get_attribute(vgpu_get_handle(g), + TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT, + &f->t19x.max_subctx_count); + if (err) { + nvgpu_err(g, "get max_subctx_count failed %d", err); + return err; + } + + return 0; +} + void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops) { vgpu_gp10b_init_fifo_ops(gops); - gops->fifo.init_fifo_setup_hw = NULL; + gops->fifo.init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw; gops->fifo.free_channel_ctx_header = vgpu_gv11b_free_subctx_header; } diff --git a/include/linux/tegra_vgpu_t19x.h b/include/linux/tegra_vgpu_t19x.h index f473275d..c2814f16 100644 --- a/include/linux/tegra_vgpu_t19x.h +++ b/include/linux/tegra_vgpu_t19x.h @@ -31,4 +31,6 @@ union tegra_vgpu_t19x_params { struct tegra_vgpu_free_ctx_header_params free_ctx_header; }; +#define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100 + #endif -- cgit v1.2.2 From c094ea161785a8c00bb2dc8c55e1a2bb8ffbcfc7 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Wed, 30 Aug 2017 15:03:25 +0530 Subject: gpu: nvgpu: gv11b: Secure boot support. This patch adds Secure boot support for T194. JIRA GPUT19X-5 Change-Id: If78e5e0ecfa58bcac132716c7f2c155f21899027 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1514558 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 285 +++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/acr_gv11b.h | 21 ++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 36 ++- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 37 +++ drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 2 + .../nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | 10 +- 7 files changed, 379 insertions(+), 13 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv11b/acr_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/acr_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index e91b4e69..d0a015bb 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -15,6 +15,7 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/ce_gv11b.o \ $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \ $(nvgpu-t19x)/gv11b/pmu_gv11b.o \ + $(nvgpu-t19x)/gv11b/acr_gv11b.o \ $(nvgpu-t19x)/gv11b/subctx_gv11b.o \ $(nvgpu-t19x)/gv11b/regops_gv11b.o \ $(nvgpu-t19x)/gv100/mm_gv100.o \ diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c new file mode 100644 index 00000000..26c5a891 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifdef CONFIG_DEBUG_FS +#include +#endif + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "acr_gv11b.h" +#include "pmu_gv11b.h" +#include "gk20a/pmu_gk20a.h" +#include "gm20b/mm_gm20b.h" +#include "gm20b/acr_gm20b.h" +#include "gp106/acr_gp106.h" + +#include + +/*Defines*/ +#define gv11b_dbg_pmu(fmt, arg...) \ + gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) + +static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value) +{ + dma_addr->lo |= u64_lo32(value); + dma_addr->hi |= u64_hi32(value); +} +/*Externs*/ + +/*Forwards*/ + +/*Loads ACR bin to FB mem and bootstraps PMU with bootloader code + * start and end are addresses of ucode blob in non-WPR region*/ +int gv11b_bootstrap_hs_flcn(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + struct vm_gk20a *vm = mm->pmu.vm; + int err = 0; + u64 *acr_dmem; + u32 img_size_in_bytes = 0; + u32 status, size, index; + u64 start; + struct acr_desc *acr = &g->acr; + struct nvgpu_firmware *acr_fw = acr->acr_fw; + struct flcn_bl_dmem_desc_v1 *bl_dmem_desc = &acr->bl_dmem_desc_v1; + u32 *acr_ucode_header_t210_load; + u32 *acr_ucode_data_t210_load; + + start = nvgpu_mem_get_addr(g, &acr->ucode_blob); + size = acr->ucode_blob.size; + + gv11b_dbg_pmu("acr ucode blob start %llx\n", start); + gv11b_dbg_pmu("acr ucode blob size %x\n", size); + + gv11b_dbg_pmu(""); + + if (!acr_fw) { + /*First time init case*/ + acr_fw = nvgpu_request_firmware(g, + GM20B_HSBIN_PMU_UCODE_IMAGE, 0); + if (!acr_fw) { + nvgpu_err(g, "pmu ucode get fail"); + return -ENOENT; + } + acr->acr_fw = acr_fw; + acr->hsbin_hdr = (struct bin_hdr *)acr_fw->data; + acr->fw_hdr = (struct acr_fw_header *)(acr_fw->data + + acr->hsbin_hdr->header_offset); + acr_ucode_data_t210_load = (u32 *)(acr_fw->data + + acr->hsbin_hdr->data_offset); + acr_ucode_header_t210_load = (u32 *)(acr_fw->data + + acr->fw_hdr->hdr_offset); + img_size_in_bytes = ALIGN((acr->hsbin_hdr->data_size), 256); + + gv11b_dbg_pmu("sig dbg offset %u\n", + acr->fw_hdr->sig_dbg_offset); + gv11b_dbg_pmu("sig dbg size %u\n", acr->fw_hdr->sig_dbg_size); + gv11b_dbg_pmu("sig prod offset %u\n", + acr->fw_hdr->sig_prod_offset); + gv11b_dbg_pmu("sig prod size %u\n", + acr->fw_hdr->sig_prod_size); + gv11b_dbg_pmu("patch loc %u\n", acr->fw_hdr->patch_loc); + gv11b_dbg_pmu("patch sig %u\n", acr->fw_hdr->patch_sig); + gv11b_dbg_pmu("header offset %u\n", acr->fw_hdr->hdr_offset); + gv11b_dbg_pmu("header size %u\n", acr->fw_hdr->hdr_size); + + /* Lets patch the signatures first.. */ + if (acr_ucode_patch_sig(g, acr_ucode_data_t210_load, + (u32 *)(acr_fw->data + + acr->fw_hdr->sig_prod_offset), + (u32 *)(acr_fw->data + + acr->fw_hdr->sig_dbg_offset), + (u32 *)(acr_fw->data + + acr->fw_hdr->patch_loc), + (u32 *)(acr_fw->data + + acr->fw_hdr->patch_sig)) < 0) { + nvgpu_err(g, "patch signatures fail"); + err = -1; + goto err_release_acr_fw; + } + err = nvgpu_dma_alloc_map_sys(vm, img_size_in_bytes, + &acr->acr_ucode); + if (err) { + err = -ENOMEM; + goto err_release_acr_fw; + } + + for (index = 0; index < 9; index++) + gv11b_dbg_pmu("acr_ucode_header_t210_load %u\n", + acr_ucode_header_t210_load[index]); + + acr_dmem = (u64 *) + &(((u8 *)acr_ucode_data_t210_load)[ + acr_ucode_header_t210_load[2]]); + acr->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *)((u8 *)( + acr->acr_ucode.cpu_va) + acr_ucode_header_t210_load[2]); + ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_start = + (start); + ((struct flcn_acr_desc_v1 *)acr_dmem)->nonwpr_ucode_blob_size = + size; + ((struct flcn_acr_desc_v1 *)acr_dmem)->regions.no_regions = 2; + ((struct flcn_acr_desc_v1 *)acr_dmem)->wpr_offset = 0; + + nvgpu_mem_wr_n(g, &acr->acr_ucode, 0, + acr_ucode_data_t210_load, img_size_in_bytes); + /* + * In order to execute this binary, we will be using + * a bootloader which will load this image into PMU IMEM/DMEM. + * Fill up the bootloader descriptor for PMU HAL to use.. + * TODO: Use standard descriptor which the generic bootloader is + * checked in. + */ + bl_dmem_desc->signature[0] = 0; + bl_dmem_desc->signature[1] = 0; + bl_dmem_desc->signature[2] = 0; + bl_dmem_desc->signature[3] = 0; + bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT; + flcn64_set_dma(&bl_dmem_desc->code_dma_base, + acr->acr_ucode.gpu_va); + bl_dmem_desc->non_sec_code_off = acr_ucode_header_t210_load[0]; + bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1]; + bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5]; + bl_dmem_desc->sec_code_size = acr_ucode_header_t210_load[6]; + bl_dmem_desc->code_entry_point = 0; /* Start at 0th offset */ + flcn64_set_dma(&bl_dmem_desc->data_dma_base, + acr->acr_ucode.gpu_va + + acr_ucode_header_t210_load[2]); + bl_dmem_desc->data_size = acr_ucode_header_t210_load[3]; + } else + acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0; + status = pmu_exec_gen_bl(g, bl_dmem_desc, 1); + if (status != 0) { + err = status; + goto err_free_ucode_map; + } + + return 0; +err_free_ucode_map: + nvgpu_dma_unmap_free(vm, &acr->acr_ucode); +err_release_acr_fw: + nvgpu_release_firmware(g, acr_fw); + acr->acr_fw = NULL; + + return err; +} + +static int bl_bootstrap(struct nvgpu_pmu *pmu, + struct flcn_bl_dmem_desc_v1 *pbl_desc, u32 bl_sz) +{ + struct gk20a *g = gk20a_from_pmu(pmu); + struct acr_desc *acr = &g->acr; + struct mm_gk20a *mm = &g->mm; + u32 virt_addr = 0; + struct hsflcn_bl_desc *pmu_bl_gm10x_desc = g->acr.pmu_hsbl_desc; + u32 dst; + + gk20a_dbg_fn(""); + + gk20a_writel(g, pwr_falcon_itfen_r(), + gk20a_readl(g, pwr_falcon_itfen_r()) | + pwr_falcon_itfen_ctxen_enable_f()); + gk20a_writel(g, pwr_pmu_new_instblk_r(), + pwr_pmu_new_instblk_ptr_f( + gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | + pwr_pmu_new_instblk_valid_f(1) | + pwr_pmu_new_instblk_target_sys_ncoh_f()); + + /*copy bootloader interface structure to dmem*/ + nvgpu_flcn_copy_to_dmem(pmu->flcn, 0, (u8 *)pbl_desc, + sizeof(struct flcn_bl_dmem_desc_v1), 0); + + /* copy bootloader to TOP of IMEM */ + dst = (pwr_falcon_hwcfg_imem_size_v( + gk20a_readl(g, pwr_falcon_hwcfg_r())) << 8) - bl_sz; + + nvgpu_flcn_copy_to_imem(pmu->flcn, dst, + (u8 *)(acr->hsbl_ucode.cpu_va), bl_sz, 0, 0, + pmu_bl_gm10x_desc->bl_start_tag); + + gv11b_dbg_pmu("Before starting falcon with BL\n"); + + virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8; + + nvgpu_flcn_bootstrap(pmu->flcn, virt_addr); + + return 0; +} + +int gv11b_init_pmu_setup_hw1(struct gk20a *g, + void *desc, u32 bl_sz) +{ + + struct nvgpu_pmu *pmu = &g->pmu; + int err; + + gk20a_dbg_fn(""); + + nvgpu_mutex_acquire(&pmu->isr_mutex); + nvgpu_flcn_reset(pmu->flcn); + pmu->isr_enabled = true; + nvgpu_mutex_release(&pmu->isr_mutex); + + /* setup apertures - virtual */ + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_noncoherent_sysmem_f()); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), + pwr_fbif_transcfg_mem_type_virtual_f()); + /* setup apertures - physical */ + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_noncoherent_sysmem_f()); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_coherent_sysmem_f()); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_noncoherent_sysmem_f()); + + /*Copying pmu cmdline args*/ + g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, + g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); + g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); + g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( + pmu, GK20A_PMU_TRACE_BUFSIZE); + g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); + g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( + pmu, GK20A_PMU_DMAIDX_VIRT); + nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, + (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), + g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); + /*disable irqs for hs falcon booting as we will poll for halt*/ + nvgpu_mutex_acquire(&pmu->isr_mutex); + pmu_enable_irq(pmu, false); + pmu->isr_enabled = false; + nvgpu_mutex_release(&pmu->isr_mutex); + /*Clearing mailbox register used to reflect capabilities*/ + gk20a_writel(g, pwr_falcon_mailbox1_r(), 0); + err = bl_bootstrap(pmu, desc, bl_sz); + if (err) + return err; + return 0; +} + diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.h b/drivers/gpu/nvgpu/gv11b/acr_gv11b.h new file mode 100644 index 00000000..60cf1b86 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ACR_GV11B_H_ +#define __ACR_GV11B_H_ + + +int gv11b_bootstrap_hs_flcn(struct gk20a *g); +int gv11b_init_pmu_setup_hw1(struct gk20a *g, + void *desc, u32 bl_sz); +#endif /*__PMU_GP106_H_*/ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0c5776f0..c6c8e18c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -55,6 +55,7 @@ #include "gp10b/gr_gp10b.h" #include "gp106/pmu_gp106.h" +#include "gp106/acr_gp106.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -65,6 +66,7 @@ #include "gr_ctx_gv11b.h" #include "mm_gv11b.h" #include "pmu_gv11b.h" +#include "acr_gv11b.h" #include "fb_gv11b.h" #include "fifo_gv11b.h" #include "gv11b_gating_reglist.h" @@ -79,6 +81,7 @@ #include #include #include +#include static int gv11b_get_litter_value(struct gk20a *g, int value) { @@ -633,6 +636,8 @@ int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + u32 val; + bool priv_security; gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; @@ -661,33 +666,38 @@ int gv11b_init_hal(struct gk20a *g) gv11b_ops.chip_init_gpu_characteristics; gops->get_litter_value = gv11b_ops.get_litter_value; - /* boot in non-secure modes for time being */ + val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); + if (val) { + priv_security = true; + pr_err("priv security is enabled\n"); + } else { + priv_security = false; + pr_err("priv security is disabled\n"); + } __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security); /* priv security dependent ops */ if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { /* Add in ops from gm20b acr */ - gops->pmu.prepare_ucode = prepare_ucode_blob, - gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn, - gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, - gops->pmu.is_priv_load = gm20b_is_priv_load, + gops->pmu.prepare_ucode = gp106_prepare_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn, gops->pmu.get_wpr = gm20b_wpr_info, gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, gops->pmu.pmu_populate_loader_cfg = - gm20b_pmu_populate_loader_cfg, + gp106_pmu_populate_loader_cfg, gops->pmu.flcn_populate_bl_dmem_desc = - gm20b_flcn_populate_bl_dmem_desc, + gp106_flcn_populate_bl_dmem_desc, gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, gops->pmu.falcon_clear_halt_interrupt_status = clear_halt_interrupt_status, - gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, + gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1, gops->pmu.init_wpr_region = gm20b_pmu_init_acr; gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; - gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; - gops->pmu.is_priv_load = gp10b_is_priv_load; + gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap, + gops->pmu.is_priv_load = gv11b_is_priv_load, gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; } else { @@ -702,8 +712,10 @@ int gv11b_init_hal(struct gk20a *g) gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; } + __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); + g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; g->name = "gv11b"; diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 2b89fbcc..41c6199e 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -28,6 +28,7 @@ #include "gp106/pmu_gp106.h" #include "pmu_gv11b.h" +#include "acr_gv11b.h" #include @@ -41,6 +42,42 @@ bool gv11b_is_pmu_supported(struct gk20a *g) return true; } +bool gv11b_is_lazy_bootstrap(u32 falcon_id) +{ + bool enable_status = false; + + switch (falcon_id) { + case LSF_FALCON_ID_FECS: + enable_status = true; + break; + case LSF_FALCON_ID_GPCCS: + enable_status = true; + break; + default: + break; + } + + return enable_status; +} + +bool gv11b_is_priv_load(u32 falcon_id) +{ + bool enable_status = false; + + switch (falcon_id) { + case LSF_FALCON_ID_FECS: + enable_status = true; + break; + case LSF_FALCON_ID_GPCCS: + enable_status = true; + break; + default: + break; + } + + return enable_status; +} + int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h index 03fec2a3..96ade0d2 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h @@ -22,5 +22,7 @@ bool gv11b_is_pmu_supported(struct gk20a *g); int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu); int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id); +bool gv11b_is_lazy_bootstrap(u32 falcon_id); +bool gv11b_is_priv_load(u32 falcon_id); #endif /*__PMU_GV11B_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h index 280a048a..b2801340 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -134,4 +134,12 @@ static inline u32 fuse_opt_feature_fuses_override_disable_r(void) { return 0x000213f0; } +static inline u32 fuse_opt_sec_debug_en_r(void) +{ + return 0x00021218; +} +static inline u32 fuse_opt_priv_sec_en_r(void) +{ + return 0x00021434; +} #endif -- cgit v1.2.2 From a42d6029a5afdf4fb2b9538a56808fbf3908a8ed Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 23 Aug 2017 10:04:58 -0700 Subject: gpu: nvgpu: gv11b: correct logic to get num of pce Correct the logic to get number of physical copy engines supported in gv11b. Change-Id: I02e0628364d056121d08dfcd0ddfb0c013207d4b Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1544207 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 8bf636b1..4f611799 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -36,7 +36,7 @@ u32 gv11b_ce_get_num_pce(struct gk20a *g) u32 num_pce; u32 ce_pce_map = gk20a_readl(g, ce_pce_map_r()); - num_pce = get_count_order(ce_pce_map) + 1; + num_pce = hweight32(ce_pce_map); nvgpu_log_info(g, "num PCE: %d", num_pce); return num_pce; } -- cgit v1.2.2 From 58018f0c1b6c1957598ba58168ba9303b5617f35 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Wed, 6 Sep 2017 13:27:17 +0300 Subject: gpu: nvgpu: gv11b: hold ch ref when getting ch from fd Add gk20a_channel_put() pair for gk20a_get_channel_from_file() that now returns the channel with a reference. Also fix resource leaks in gv11b_tsg_ioctl_bind_channel_ex's error paths. Change-Id: Ib348219defa67163657ca534826f504ebc59497e Signed-off-by: Konsta Holtta Reviewed-on: https://git-master.nvidia.com/r/1553276 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c index b0b1f9c4..87fbf010 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c @@ -33,21 +33,26 @@ static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g, nvgpu_mutex_acquire(&sched->control_lock); if (sched->control_locked) { err = -EPERM; - goto done; + goto mutex_release; } err = gk20a_busy(g); if (err) { nvgpu_err(g, "failed to power on gpu"); - goto done; + goto mutex_release; } ch = gk20a_get_channel_from_file(arg->channel_fd); - if (!ch) - return -EINVAL; - if (arg->subcontext_id < g->fifo.t19x.max_subctx_count) + if (!ch) { + err = -EINVAL; + goto idle; + } + if (arg->subcontext_id < g->fifo.t19x.max_subctx_count) { ch->t19x.subctx_id = arg->subcontext_id; - else - return -EINVAL; + } else { + err = -EINVAL; + goto ch_put; + } + nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d", ch->chid, ch->t19x.subctx_id); @@ -56,8 +61,11 @@ static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g, ch->t19x.runqueue_sel = 1; err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch); +ch_put: + gk20a_channel_put(ch); +idle: gk20a_idle(g); -done: +mutex_release: nvgpu_mutex_release(&sched->control_lock); return err; } -- cgit v1.2.2 From 91a85229996e80a4125a8661f24b1446f4020c83 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Fri, 8 Sep 2017 19:18:30 +0530 Subject: gpu: nvgpu: gv11b: add ops for getting timestamp. assign GPU bus ops for getting timestamps using PTIMER. BUG 1957272 Change-Id: I1ded165858849a6a93e6ae0617ec1423d48f75ed Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1555528 Reviewed-by: svc-mobile-coverity Reviewed-by: Seshendra Gadagottu Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index c6c8e18c..e9053081 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -73,6 +73,7 @@ #include "regops_gv11b.h" #include "subctx_gv11b.h" +#include #include #include @@ -610,6 +611,7 @@ static const struct gpu_ops gv11b_ops = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .read_ptimer = gk20a_read_ptimer, + .get_timestamps_zipper = nvgpu_get_timestamps_zipper, .bar1_bind = NULL, }, #if defined(CONFIG_GK20A_CYCLE_STATS) -- cgit v1.2.2 From f98e3c8348d20b6542c4d27921cb9f9822aaa17a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 6 Sep 2017 14:45:30 -0700 Subject: gpu: nvgpu: gv100: Don't assign XVE sw_init XVE sw_init HAL is removed due to moving XVE debugfs code to Linux module. Remove the assignment of the HAL. Change-Id: I90beada58f87c78dc752011ea3ec2a5473f0acc1 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1553913 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4f21e433..cd121455 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -597,7 +597,6 @@ static const struct gpu_ops gv100_ops = { }, #endif .xve = { - .sw_init = xve_sw_init_gp106, .get_speed = xve_get_speed_gp106, .set_speed = xve_set_speed_gp106, .available_speeds = xve_available_speeds_gp106, -- cgit v1.2.2 From 56d03664d00f77fa760757467e23d9dbc1a08cf8 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 31 Aug 2017 15:44:57 +0530 Subject: gpu: nvgpu: GV100 fecs/gpccs sign file path - Added paths of GV100 fecs/gpccs sign file. JIRA NVGPUGV100-7 Change-Id: I92d1fa51c1e66b3eb4009a0a51f6f3252cba41d9 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1549424 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/acr_t19x.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 drivers/gpu/nvgpu/acr_t19x.h diff --git a/drivers/gpu/nvgpu/acr_t19x.h b/drivers/gpu/nvgpu/acr_t19x.h new file mode 100644 index 00000000..fcf93bd0 --- /dev/null +++ b/drivers/gpu/nvgpu/acr_t19x.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_ACR_T19X_H_ +#define _NVGPU_ACR_T19X_H_ + +#define BIGGPU_FECS_UCODE_SIG "gv100/fecs_sig.bin" +#define BIGGPU_GPCCS_UCODE_SIG "gv100/gpccs_sig.bin" + +#endif -- cgit v1.2.2 From 52f50addc6cedf57fc3d8ff06314921499fb59e3 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 13 Sep 2017 17:35:03 +0530 Subject: gpu: nvgpu: add TSG enable/disable operations Add TSG enable/disable operations for gv11b/gv100 To disable a TSG we continue to use gk20a_disable_tsg() To enable a TSG add new API gv11b_fifo_enable_tsg() since TSG enable sequence is different for Volta than previous versions For Volta it is sufficient to loop over all the channels in TSG and enable them sequentially Bug 1739362 Change-Id: Id4b4684959204c6101ceda83487a41fbfcba8b5f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560642 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 15 +++++++++ drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 36 ++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 38 +++++++++++++++++++++- 6 files changed, 93 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cd121455..cc20fa43 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -397,6 +397,8 @@ static const struct gpu_ops gv100_ops = { .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, .preempt_channel = gv11b_fifo_preempt_channel, .preempt_tsg = gv11b_fifo_preempt_tsg, + .enable_tsg = gv11b_fifo_enable_tsg, + .disable_tsg = gk20a_disable_tsg, .update_runlist = gk20a_fifo_update_runlist, .trigger_mmu_fault = NULL, .get_mmu_fault_info = NULL, diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 80bb64a0..1d5e593c 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -785,6 +785,21 @@ static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) return ret; } +/* TSG enable sequence applicable for Volta and onwards */ +int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg) +{ + struct gk20a *g = tsg->g; + struct channel_gk20a *ch; + + down_read(&tsg->ch_list_lock); + nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) { + g->ops.fifo.enable_channel(ch); + } + up_read(&tsg->ch_list_lock); + + return 0; +} + int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) { struct fifo_gk20a *f = &g->fifo; diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 3fb2f6e9..e576714c 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -69,6 +69,7 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type); int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid); int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); +int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg); int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type); void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e9053081..947ac503 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -430,6 +430,8 @@ static const struct gpu_ops gv11b_ops = { .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, .preempt_channel = gv11b_fifo_preempt_channel, .preempt_tsg = gv11b_fifo_preempt_tsg, + .enable_tsg = gv11b_fifo_enable_tsg, + .disable_tsg = gk20a_disable_tsg, .update_runlist = gk20a_fifo_update_runlist, .trigger_mmu_fault = NULL, .get_mmu_fault_info = NULL, diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index f64f542c..664c0b80 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -110,6 +110,42 @@ static inline u32 ccsr_channel_status_v(u32 r) { return (r >> 24) & 0xf; } +static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) +{ + return 0x00000002; +} +static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) +{ + return 0x00000004; +} +static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) +{ + return 0x0000000a; +} +static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) +{ + return 0x0000000b; +} +static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) +{ + return 0x0000000c; +} +static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) +{ + return 0x0000000d; +} +static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) +{ + return 0x0000000e; +} +static inline u32 ccsr_channel_next_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 ccsr_channel_next_true_v(void) +{ + return 0x00000001; +} static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { return (v & 0x1) << 22; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index 618c4806..7e30c34b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -110,6 +110,42 @@ static inline u32 ccsr_channel_status_v(u32 r) { return (r >> 24) & 0xf; } +static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) +{ + return 0x00000002; +} +static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) +{ + return 0x00000004; +} +static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) +{ + return 0x0000000a; +} +static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) +{ + return 0x0000000b; +} +static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) +{ + return 0x0000000c; +} +static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) +{ + return 0x0000000d; +} +static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) +{ + return 0x0000000e; +} +static inline u32 ccsr_channel_next_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 ccsr_channel_next_true_v(void) +{ + return 0x00000001; +} static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { return (v & 0x1) << 22; -- cgit v1.2.2 From f720b309f1ea87a301bcb216983396f3d9c55abc Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 14 Sep 2017 05:48:07 -0700 Subject: gpu: nvgpu: add tsg_verify_status_faulted operation Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100 This API will check if channel has ENG_FAULTED status set, if yes it will clear CE method buffer in case saved out channel is same as faulted channel We need to write 0 to method count to invalidate CE method buffer Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100 Bug 200327095 Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560643 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 35 ++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 2 ++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ .../nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 12 ++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 12 ++++++++ 6 files changed, 65 insertions(+) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cc20fa43..9a2807a2 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -399,6 +399,8 @@ static const struct gpu_ops gv100_ops = { .preempt_tsg = gv11b_fifo_preempt_tsg, .enable_tsg = gv11b_fifo_enable_tsg, .disable_tsg = gk20a_disable_tsg, + .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, + .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, .update_runlist = gk20a_fifo_update_runlist, .trigger_mmu_fault = NULL, .get_mmu_fault_info = NULL, diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 1d5e593c..b4e4b875 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1811,3 +1811,38 @@ void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, else *pbdma_id = FIFO_INVAL_PBDMA_ID; } + +static bool gk20a_fifo_channel_status_is_eng_faulted(struct gk20a *g, u32 chid) +{ + u32 channel = gk20a_readl(g, ccsr_channel_r(chid)); + + return ccsr_channel_eng_faulted_v(channel) == + ccsr_channel_eng_faulted_true_v(); +} + +void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch) +{ + struct gk20a *g = ch->g; + struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; + + /* + * If channel has FAULTED set, clear the CE method buffer + * if saved out channel is same as faulted channel + */ + if (!gk20a_fifo_channel_status_is_eng_faulted(g, ch->chid)) + return; + + if (tsg->eng_method_buffers == NULL) + return; + + /* + * CE method buffer format : + * DWord0 = method count + * DWord1 = channel id + * + * It is sufficient to write 0 to method count to invalidate + */ + if ((u32)ch->chid == + nvgpu_mem_rd32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 1)) + nvgpu_mem_wr32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 0, 0); +} diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index e576714c..0cc1c7c2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -103,4 +103,6 @@ void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); int gv11b_init_fifo_setup_hw(struct gk20a *g); +void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch); + #endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 947ac503..fcc3b91a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -432,6 +432,8 @@ static const struct gpu_ops gv11b_ops = { .preempt_tsg = gv11b_fifo_preempt_tsg, .enable_tsg = gv11b_fifo_enable_tsg, .disable_tsg = gk20a_disable_tsg, + .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, + .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, .update_runlist = gk20a_fifo_update_runlist, .trigger_mmu_fault = NULL, .get_mmu_fault_info = NULL, diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index 664c0b80..dfebd60f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -146,6 +146,10 @@ static inline u32 ccsr_channel_next_true_v(void) { return 0x00000001; } +static inline u32 ccsr_channel_force_ctx_reload_true_f(void) +{ + return 0x100; +} static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { return (v & 0x1) << 22; @@ -158,10 +162,18 @@ static inline u32 ccsr_channel_eng_faulted_f(u32 v) { return (v & 0x1) << 23; } +static inline u32 ccsr_channel_eng_faulted_v(u32 r) +{ + return (r >> 23) & 0x1; +} static inline u32 ccsr_channel_eng_faulted_reset_f(void) { return 0x800000; } +static inline u32 ccsr_channel_eng_faulted_true_v(void) +{ + return 0x00000001; +} static inline u32 ccsr_channel_busy_v(u32 r) { return (r >> 28) & 0x1; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index 7e30c34b..bd1e31c7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -146,6 +146,10 @@ static inline u32 ccsr_channel_next_true_v(void) { return 0x00000001; } +static inline u32 ccsr_channel_force_ctx_reload_true_f(void) +{ + return 0x100; +} static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { return (v & 0x1) << 22; @@ -158,10 +162,18 @@ static inline u32 ccsr_channel_eng_faulted_f(u32 v) { return (v & 0x1) << 23; } +static inline u32 ccsr_channel_eng_faulted_v(u32 r) +{ + return (r >> 23) & 0x1; +} static inline u32 ccsr_channel_eng_faulted_reset_f(void) { return 0x800000; } +static inline u32 ccsr_channel_eng_faulted_true_v(void) +{ + return 0x00000001; +} static inline u32 ccsr_channel_busy_v(u32 r) { return (r >> 28) & 0x1; -- cgit v1.2.2 From 31a50f07e4458b43f46a9612e4b27893a50d53b3 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 31 Aug 2017 11:15:50 -0700 Subject: gpu: nvgpu: gv11b: Set pbdma, fb and ctxsw timeout for pre-si fb and ctxsw timeout detection should be disabled for simulation architectures. Also set timeouts to max for pbdma, fb and ctxsw timeouts. Bug 200289427 Change-Id: I8723d5ee9ea2535f401b1972c8c14ffab8f9504a Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1549522 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 43 +++++++++++++++++++--- .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 32 ++++++++++++++++ 2 files changed, 69 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b4e4b875..6f9e44fb 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1166,10 +1166,27 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) timeout = gk20a_readl(g, fifo_fb_timeout_r()); nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout); + if (!nvgpu_platform_is_silicon(g)) { + timeout = set_field(timeout, fifo_fb_timeout_period_m(), + fifo_fb_timeout_period_max_f()); + timeout = set_field(timeout, fifo_fb_timeout_detection_m(), + fifo_fb_timeout_detection_disabled_f()); + nvgpu_log_info(g, "new fifo_fb_timeout reg val = 0x%08x", + timeout); + gk20a_writel(g, fifo_fb_timeout_r(), timeout); + } + for (i = 0; i < host_num_pbdma; i++) { timeout = gk20a_readl(g, pbdma_timeout_r(i)); nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", timeout); + if (!nvgpu_platform_is_silicon(g)) { + timeout = set_field(timeout, pbdma_timeout_period_m(), + pbdma_timeout_period_max_f()); + nvgpu_log_info(g, "new pbdma_timeout reg val = 0x%08x", + timeout); + gk20a_writel(g, pbdma_timeout_r(i), timeout); + } } /* clear and enable pbdma interrupt */ @@ -1189,12 +1206,26 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) /* clear ctxsw timeout interrupts */ gk20a_writel(g, fifo_intr_ctxsw_timeout_r(), ~0); - /* enable ctxsw timeout */ - timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; - timeout = scale_ptimer(timeout, - ptimer_scalingfactor10x(g->ptimer_src_freq)); - timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); - gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); + if (nvgpu_platform_is_silicon(g)) { + /* enable ctxsw timeout */ + timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; + timeout = scale_ptimer(timeout, + ptimer_scalingfactor10x(g->ptimer_src_freq)); + timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); + gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); + } else { + timeout = gk20a_readl(g, fifo_eng_ctxsw_timeout_r()); + nvgpu_log_info(g, "fifo_eng_ctxsw_timeout reg val = 0x%08x", + timeout); + timeout = set_field(timeout, fifo_eng_ctxsw_timeout_period_m(), + fifo_eng_ctxsw_timeout_period_max_f()); + timeout = set_field(timeout, + fifo_eng_ctxsw_timeout_detection_m(), + fifo_eng_ctxsw_timeout_detection_disabled_f()); + nvgpu_log_info(g, "new fifo_eng_ctxsw_timeout reg val = 0x%08x", + timeout); + gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); + } /* clear runlist interrupts */ gk20a_writel(g, fifo_intr_runlist_r(), ~0); diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index e98c9f76..04d6f0f4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -382,6 +382,18 @@ static inline u32 fifo_fb_timeout_period_init_f(void) { return 0x3c00; } +static inline u32 fifo_fb_timeout_detection_m(void) +{ + return 0x1 << 31; +} +static inline u32 fifo_fb_timeout_detection_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 fifo_fb_timeout_detection_disabled_f(void) +{ + return 0x0; +} static inline u32 fifo_sched_disable_r(void) { return 0x00002630; @@ -538,18 +550,38 @@ static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) { return (v & 0x7fffffff) << 0; } +static inline u32 fifo_eng_ctxsw_timeout_period_m(void) +{ + return 0x7fffffff << 0; +} static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) { return (r >> 0) & 0x7fffffff; } +static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void) +{ + return 0x3fffff; +} +static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void) +{ + return 0x7fffffff; +} static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) { return (v & 0x1) << 31; } +static inline u32 fifo_eng_ctxsw_timeout_detection_m(void) +{ + return 0x1 << 31; +} static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) { return 0x80000000; } +static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void) +{ + return 0x0; +} static inline u32 fifo_pbdma_status_r(u32 i) { return 0x00003080 + i*4; -- cgit v1.2.2 From 622072d1c069581da80b14a7ea64e20d283877ab Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 11 Sep 2017 10:33:51 -0700 Subject: gpu: nvgpu: gv11b: poll tsgid for preempt done Use tsgid for polling preemption completion since id and next_id in pbdma and eng status point to tsgid Bug 200277163 Bug 1958308 Change-Id: I5636ce1f8b21ddac4c93d92ce0527fe0307f2cfc Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1557253 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 6f9e44fb..dce8ce9b 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -710,20 +710,24 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, u32 runlist_id; int func_ret; int ret = 0; + u32 tsgid; - gk20a_dbg_fn(""); - - if (id_type == ID_TYPE_TSG) + if (id_type == ID_TYPE_TSG) { runlist_id = f->tsg[id].runlist_id; - else + tsgid = id; + } else { runlist_id = f->channel[id].runlist_id; + tsgid = f->channel[id].tsgid; + } + + nvgpu_log_info(g, "Check preempt pending for tsgid = %u", tsgid); runlist_served_pbdmas = f->runlist_info[runlist_id].pbdma_bitmask; runlist_served_engines = f->runlist_info[runlist_id].eng_bitmask; for_each_set_bit(pbdma_id, &runlist_served_pbdmas, f->num_pbdma) { - func_ret = gv11b_fifo_poll_pbdma_chan_status(g, id, pbdma_id, + func_ret = gv11b_fifo_poll_pbdma_chan_status(g, tsgid, pbdma_id, timeout_rc_type); if (func_ret != 0) { gk20a_dbg_info("preempt timeout pbdma %d", pbdma_id); @@ -735,7 +739,7 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, for_each_set_bit(act_eng_id, &runlist_served_engines, f->num_engines) { - func_ret = gv11b_fifo_poll_eng_ctx_status(g, id, act_eng_id, + func_ret = gv11b_fifo_poll_eng_ctx_status(g, tsgid, act_eng_id, &f->runlist_info[runlist_id].reset_eng_bitmask, timeout_rc_type); -- cgit v1.2.2 From 1c850d0beef16216c21b3c833a5d3333ef229788 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 12 Sep 2017 13:29:59 -0700 Subject: gpu: nvgpu: gv11b: fecs_trace ops are set to NULL CTXSW_TRACE will be enabled only after it is verified. Set all function pointers for fecs_trace to NULL JIRA GPUT19X-42 Change-Id: I7a807f997f683c19541e55fa7e3d5d3ff6b645d2 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1558464 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index fcc3b91a..2abd6243 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -487,20 +487,20 @@ static const struct gpu_ops gv11b_ops = { }, #ifdef CONFIG_GK20A_CTXSW_TRACE .fecs_trace = { - .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, - .free_user_buffer = gk20a_ctxsw_dev_ring_free, - .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, - .init = gk20a_fecs_trace_init, - .deinit = gk20a_fecs_trace_deinit, - .enable = gk20a_fecs_trace_enable, - .disable = gk20a_fecs_trace_disable, - .is_enabled = gk20a_fecs_trace_is_enabled, - .reset = gk20a_fecs_trace_reset, - .flush = gp10b_fecs_trace_flush, - .poll = gk20a_fecs_trace_poll, - .bind_channel = gk20a_fecs_trace_bind_channel, - .unbind_channel = gk20a_fecs_trace_unbind_channel, - .max_entries = gk20a_gr_max_entries, + .alloc_user_buffer = NULL, + .free_user_buffer = NULL, + .mmap_user_buffer = NULL, + .init = NULL, + .deinit = NULL, + .enable = NULL, + .disable = NULL, + .is_enabled = NULL, + .reset = NULL, + .flush = NULL, + .poll = NULL, + .bind_channel = NULL, + .unbind_channel = NULL, + .max_entries = NULL, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { -- cgit v1.2.2 From e4e6a4a73469cc6f6fc38d4e643afe746976bcb2 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 31 Aug 2017 13:31:38 -0700 Subject: gpu: nvgpu: gv11b: remove double declaration gv11b_fb_fault_buf_configure_hw is declared twice. Fix the same by removing one of the declarations. Change-Id: I12a857b4225164067f0329530249ffc0dcdc1412 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1549661 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index 3e2dd828..eec90d23 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -58,7 +58,6 @@ void gv11b_fb_enable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); void gv11b_fb_disable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); -void gv11b_fb_fault_buf_configure_hw(struct gk20a *g, unsigned int index); bool gv11b_fb_mmu_fault_pending(struct gk20a *g); noinline_for_stack void gv11b_init_uncompressed_kind_map(void); -- cgit v1.2.2 From cedb24c7a09292ec8deee9ee17e1d7defeff0241 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 18 Sep 2017 10:46:06 -0700 Subject: gpu: nvgpu: gv11b: correct wl reg offset Corrected whitelist register address offset for gr_pri_gpcs_tpcs_sm_disp_ctrl. This offset value is changed for gv11b from gp10b. With wrong offset value, gl tests are generating "unhandled fecs error interrupt 0x00000002 for channel xxx". Bug 1958308 Change-Id: Iabfbb20ea1ee4ca8567d0cda940fa1e8cbff1bac Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1562615 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 078272d1..ee49a8f2 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1740,7 +1740,7 @@ void gr_gv11b_get_access_map(struct gk20a *g, 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ 0x419e84, /* gr_pri_gpcs_tpcs_sms_dbgr_control0 */ - 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ + 0x419ba4, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ }; *whitelist = wl_addr_gv11b; -- cgit v1.2.2 From 0420dd383e9aca0c764ad88979f88292603198d9 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 18 Sep 2017 11:17:15 -0700 Subject: gpu: nvgpu: gv11b: Initialize ctxsw hdr counters Initlize following context switch header counters for gv11b: ctxsw_prog_main_image_num_save_ops ctxsw_prog_main_image_num_restore_ops ctxsw_prog_main_image_num_wfi_save_ops ctxsw_prog_main_image_num_cta_save_ops ctxsw_prog_main_image_num_gfxp_save_ops ctxsw_prog_main_image_num_cilp_save_ops Reused gp10b gr hal function gr_gp10b_init_ctxsw_hdr_data() for this. Bug 1958308 Signed-off-by: seshendra Gadagottu Change-Id: I10d83e35ccd8cba517ebaba1f0e5bec5a0f68ba5 Reviewed-on: https://git-master.nvidia.com/r/1562655 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 4 ---- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index ee49a8f2..50b819ac 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2309,10 +2309,6 @@ void gv11b_restore_context_header(struct gk20a *g, ctxsw_prog_main_image_context_buffer_ptr_hi_o(), va_hi); nvgpu_mem_wr(g, ctxheader, ctxsw_prog_main_image_context_buffer_ptr_o(), va_lo); - nvgpu_mem_wr(g, ctxheader, - ctxsw_prog_main_image_num_restore_ops_o(), 0); - nvgpu_mem_wr(g, ctxheader, - ctxsw_prog_main_image_num_save_ops_o(), 0); } void gr_gv11b_write_zcull_ptr(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2abd6243..be3f2456 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -343,6 +343,7 @@ static const struct gpu_ops gv11b_ops = { .handle_tpc_sm_ecc_exception = gr_gv11b_handle_tpc_sm_ecc_exception, .decode_egpc_addr = gv11b_gr_decode_egpc_addr, + .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, }, .fb = { .reset = gv11b_fb_reset, -- cgit v1.2.2 From b454d30d89d3a3830fc44039ec543286444e9e13 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 14 Sep 2017 16:32:11 -0700 Subject: gpu: nvgpu: gv11b: enable per veid header for subctx Enable per veid header mode for subcontext header. Allocated only context header size for subcontext header. Bug 1958308 Change-Id: I6b45987eed968252326a366650fefd807975b70f Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1562681 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 4f64843c..ee89ecc2 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -53,7 +53,6 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) { struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; struct gk20a *g = c->g; - struct gr_gk20a *gr = &g->gr; int ret = 0; nvgpu_log(g, gpu_dbg_fn, "gv11b_alloc_subctx_header"); @@ -61,7 +60,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) if (ctx->mem.gpu_va == 0) { ret = nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_NO_KERNEL_MAPPING, - gr->ctx_vars.golden_image_size, + ctxsw_prog_fecs_header_v(), &ctx->mem); if (ret) { nvgpu_err(g, "failed to allocate sub ctx header"); @@ -124,6 +123,10 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi); nvgpu_mem_wr(g, gr_mem, ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo); + + nvgpu_mem_wr(g, gr_mem, + ctxsw_prog_main_image_ctl_o(), + ctxsw_prog_main_image_ctl_type_per_veid_header_v()); nvgpu_mem_end(g, gr_mem); return ret; } -- cgit v1.2.2 From 0a0da216db25e293c68b5c9c6fa88e559368dce2 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 19 Sep 2017 12:12:49 -0700 Subject: gpu: nvgpu: Use VBIOS HAL from gp106 instead of gm206 Use VBIOS HAL from gp106 instead of gm206. JIRA NVGPU-218 Change-Id: I835a1ce39818221f976ed5eca2bf3032317760b0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1563741 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9a2807a2..23ada798 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -51,7 +51,7 @@ #include "gp106/pmu_gp106.h" #include "gp106/acr_gp106.h" #include "gp106/sec2_gp106.h" -#include "gm206/bios_gm206.h" +#include "gp106/bios_gp106.h" #include "gp106/therm_gp106.h" #include "gp106/xve_gp106.h" #include "gp106/clk_gp106.h" @@ -622,7 +622,7 @@ static const struct gpu_ops gv100_ops = { }, .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, .get_litter_value = gv100_get_litter_value, - .bios_init = gm206_bios_init, + .bios_init = gp106_bios_init, }; int gv100_init_hal(struct gk20a *g) -- cgit v1.2.2 From 1586a9f0044987106371255b8133430040ed4f70 Mon Sep 17 00:00:00 2001 From: Alexander Lewkowicz Date: Tue, 19 Sep 2017 13:36:56 -0700 Subject: gpu: nvgpu: gv11b: Fix sm lock down Volta traphandler RM changes Sm lock-down is not being executed correctly. This results in a GPU being in an undefined state. A similar bug fix was already provided on the resman implementation. This fix is inspired by the CL change 21183102. That change refers to bug http://nvbugs/1800484 and bug http://nvbugs/200162542 This patch solves the issues mention in bug http://nvbugs/1992522 Change-Id: I601fef7c94e5ba419d7bf854877fa7a9f9b82cfa Signed-off-by: Alexander Lewkowicz Reviewed-on: https://git-master.nvidia.com/r/1563815 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 50b819ac..74ea0d2c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -3136,7 +3136,7 @@ int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, check_errors && (gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(warp_esr) == gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v()) && - ((global_esr & ~global_esr_mask) == 0); + ((global_esr & global_esr_mask) == 0); if (locked_down) { /* -- cgit v1.2.2 From ca2560af809a12d7aabd349b2b8e73932e70ffba Mon Sep 17 00:00:00 2001 From: Sreejith V Date: Mon, 18 Sep 2017 18:42:46 +0530 Subject: gpu: nvgpu: gv11b: remove misleading intendation warning Bug 200348860 Bug 200291879 Change-Id: Ia1e651d8365eae6e7aef69d79923d644c7067211 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1563869 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index dce8ce9b..189fe3f0 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -977,9 +977,9 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, client_type = mmfault->client_type; if (gk20a_is_channel_marked_as_tsg(refch)) tsg = &g->fifo.tsg[refch->tsgid]; - gv11b_fifo_reset_pbdma_and_eng_faulted(g, refch, - mmfault->faulted_pbdma, - mmfault->faulted_engine); + gv11b_fifo_reset_pbdma_and_eng_faulted(g, refch, + mmfault->faulted_pbdma, + mmfault->faulted_engine); } else { if (id_type == ID_TYPE_TSG) tsg = &g->fifo.tsg[id]; -- cgit v1.2.2 From a24382d09788ffc8f8688a473a38d37df589b131 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 20 Sep 2017 22:34:54 +0530 Subject: gpu: nvgpu: Add support for WPR info read from FB update .read_wpr_info HAL of gv11b & gv100 to point to gm20b_fb_read_wpr_info() JIRA NVGPU-128 Change-Id: I5ece4c72dbe0f9e7827888e2a15d8b7dda6fcb42 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1564684 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 23ada798..3dfe9e74 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -373,6 +373,7 @@ static const struct gpu_ops gv100_ops = { .compressible_page_size = gp10b_fb_compressible_page_size, .vpr_info_fetch = gm20b_fb_vpr_info_fetch, .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, .tlb_invalidate = gk20a_fb_tlb_invalidate, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index be3f2456..09825b98 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -357,6 +357,7 @@ static const struct gpu_ops gv11b_ops = { .compressible_page_size = gp10b_fb_compressible_page_size, .vpr_info_fetch = gm20b_fb_vpr_info_fetch, .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, .tlb_invalidate = gk20a_fb_tlb_invalidate, -- cgit v1.2.2 From 4d5216922b288a70f7434ac8f7c6c8274cc1462b Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 21 Sep 2017 09:09:24 -0700 Subject: gpu: nvgpu: fix coverity issues in GV100 HAL Fix value overwrite in switch statement on GV100 proj assignments bug 200291879 Change-Id: Id25f811f820a05b3d50cc9070369fe52f65a6bf3 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1565538 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 3dfe9e74..8cf8e245 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -138,6 +138,7 @@ static int gv100_get_litter_value(struct gk20a *g, int value) break; case GPU_LIT_PPC_IN_GPC_BASE: ret = proj_ppc_in_gpc_base_v(); + break; case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; -- cgit v1.2.2 From 39eb00dedac630f7945e22875d822a76d0caa578 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 20 Sep 2017 11:31:08 +0530 Subject: gpu: nvgpu: gv11b faclon hw header update - Update CPUCTL register to add soft/hard reset support - Added debug registers JIRA NVGPU-56 Change-Id: Id867dd3a6085131917c2ada88f9899e415348038 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1564156 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 60 +++++++++++++++++----- 1 file changed, 48 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index 6bdc5fd1..711c2b4b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -290,6 +290,14 @@ static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) { return (v & 0x1) << 1; } +static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) +{ + return (v & 0x1) << 3; +} static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) { return (v & 0x1) << 4; @@ -302,6 +310,10 @@ static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) { return (r >> 4) & 0x1; } +static inline u32 falcon_falcon_cpuctl_stopped_m(void) +{ + return 0x1 << 5; +} static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) { return (v & 0x1) << 6; @@ -390,18 +402,6 @@ static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) { return (r >> 9) & 0x1ff; } -static inline u32 falcon_falcon_hwcfg1_r(void) -{ - return 0x0000012c; -} -static inline u32 falcon_falcon_hwcfg1_core_rev_v(u32 r) -{ - return (r >> 0) & 0xf; -} -static inline u32 falcon_falcon_hwcfg1_security_model_v(u32 r) -{ - return (r >> 4) & 0x3; -} static inline u32 falcon_falcon_dmatrfbase_r(void) { return 0x00000110; @@ -438,6 +438,42 @@ static inline u32 falcon_falcon_dmatrffboffs_r(void) { return 0x0000011c; } +static inline u32 falcon_falcon_imctl_debug_r(void) +{ + return 0x0000015c; +} +static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 falcon_falcon_imstat_r(void) +{ + return 0x00000144; +} +static inline u32 falcon_falcon_traceidx_r(void) +{ + return 0x00000148; +} +static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 falcon_falcon_traceidx_idx_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 falcon_falcon_tracepc_r(void) +{ + return 0x0000014c; +} +static inline u32 falcon_falcon_tracepc_pc_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} static inline u32 falcon_falcon_exterraddr_r(void) { return 0x00000168; -- cgit v1.2.2 From c359afbfe20cf7851ce93f70a95d652420d504cd Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 21 Sep 2017 12:56:41 -0700 Subject: gpu: nvgpu: Change HW header licenses to MIT JIRA NVGPU-218 Change-Id: I7e506649a5e32c54bf6880b575dedb63097ebb1b Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1565708 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h | 24 ++++++++++------ .../include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h | 28 +++++++++++-------- .../nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h | 24 ++++++++++------ .../nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h | 24 ++++++++++------ .../nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h | 24 ++++++++++------ .../include/nvgpu/hw/gv100/hw_usermode_gv100.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h | 26 +++++++++++------- .../nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 26 +++++++++++------- .../include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h | 26 +++++++++++------- .../nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 24 ++++++++++------ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h | 26 +++++++++++------- .../nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h | 32 +++++++++++++--------- .../nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | 24 ++++++++++------ .../nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h | 24 ++++++++++------ .../nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 24 ++++++++++------ .../nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h | 26 +++++++++++------- .../nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h | 24 ++++++++++------ .../include/nvgpu/hw/gv11b/hw_usermode_gv11b.h | 24 ++++++++++------ 53 files changed, 806 insertions(+), 488 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h index c95d5af4..bc4f7f28 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index dfebd60f..ae0179f2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h index 26971f3f..6923d921 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h index f5593095..86075656 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h index ce726633..33c08bad 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h index 9466a695..1578a124 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h index c9b592bf..549c2f8f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h index b2b52ff2..0c2334da 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h index 15bdde6c..0aa2743d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h index af1915b2..750070ad 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h index f1d977d4..b5fc4b63 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h index 0cd59c3b..54bd1e35 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h index ab363e94..f0fc0773 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h index f8e7c2a4..d9c8a348 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h index 88c70f53..3250bf3e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h index 197fe550..ca9da11d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h index eb77b4c0..70cf0461 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h index 27feb5e9..741e5bc2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h index 44e804e7..ca851cd4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h index 7d83b4ae..b85c37aa 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h index 7fff981b..fa42ebbe 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h index d98002c0..2834acf8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h index c71e9a7d..d53deb15 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h index d993bddc..35b3ab33 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h index 86045e51..d49c9eed 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h index 4f15b39d..8680c11a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h index f082fdc7..534f66b3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h index 66571ae7..9fe7e591 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index bd1e31c7..3243e3e2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h index fbf10b82..8a0a9206 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h index a0f40de0..27ac297c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index 711c2b4b..fdeb4a37 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index fd5427ec..f902ae6c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index 04d6f0f4..0d85a486 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h index 380f8824..b2938b32 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h index b2801340..6bc0604b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index 383f7773..d84610f3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 153aef2f..1af014f6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index 1bcd1246..e1b0f47a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index 38040723..7228cd8b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index abdbc17d..025a7af3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h index 836c014b..5adee5f3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h index da2d4d2e..1568f310 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h index ce9e53ee..24509b08 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h index 89abfa3c..119e2075 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h index ae6ad795..85b86c98 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index a17a7203..7e7ad14a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 6c6dea4a..43c0c908 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index 69de33c6..c7f15f57 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index 7be6d074..64a7e292 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h index 7d5750c2..1181f177 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h @@ -1,17 +1,23 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h index dbfc99b9..694257ed 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h index 8bcf163f..e3749690 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_usermode_gv11b.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ /* * Function naming determines intended use: -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/acr_t19x.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/channel_t19x.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/common/mm/gmmu_t19x.c | 24 +++++++++++++-------- drivers/gpu/nvgpu/ecc_t19x.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/fifo_t19x.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gr_t19x.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv100/fb_gv100.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv100/fb_gv100.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv100/gv100.h | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv100/hal_gv100.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv100/hal_gv100.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv100/mm_gv100.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv100/mm_gv100.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/acr_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv11b/ce_gv11b.h | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv11b/ecc_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c | 25 +++++++++++++--------- drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/gv11b.c | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv11b/gv11b.h | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 25 +++++++++++++--------- drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/hal_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/ltc_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/mc_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/mm_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/gv11b/regops_gv11b.c | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv11b/regops_gv11b.h | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 24 +++++++++++++-------- drivers/gpu/nvgpu/gv11b/subctx_gv11b.h | 24 +++++++++++++-------- drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h | 24 +++++++++++++-------- drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h | 24 +++++++++++++-------- drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/tsg_t19x.h | 23 ++++++++++++++------ .../nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c | 23 ++++++++++++++------ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h | 23 ++++++++++++++------ drivers/gpu/nvgpu/vgpu/vgpu_t19x.h | 23 ++++++++++++++------ 60 files changed, 943 insertions(+), 456 deletions(-) diff --git a/drivers/gpu/nvgpu/acr_t19x.h b/drivers/gpu/nvgpu/acr_t19x.h index fcf93bd0..0693c6a1 100644 --- a/drivers/gpu/nvgpu/acr_t19x.h +++ b/drivers/gpu/nvgpu/acr_t19x.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_ACR_T19X_H_ diff --git a/drivers/gpu/nvgpu/channel_t19x.h b/drivers/gpu/nvgpu/channel_t19x.h index bb324426..d3cb71a1 100644 --- a/drivers/gpu/nvgpu/channel_t19x.h +++ b/drivers/gpu/nvgpu/channel_t19x.h @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_CHANNEL_T19X_H_ diff --git a/drivers/gpu/nvgpu/common/mm/gmmu_t19x.c b/drivers/gpu/nvgpu/common/mm/gmmu_t19x.c index 05abec1b..9f9c188d 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu_t19x.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu_t19x.c @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/ecc_t19x.h b/drivers/gpu/nvgpu/ecc_t19x.h index 27f00c6c..5b571ce1 100644 --- a/drivers/gpu/nvgpu/ecc_t19x.h +++ b/drivers/gpu/nvgpu/ecc_t19x.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_ECC_T19X_H_ #define _NVGPU_ECC_T19X_H_ diff --git a/drivers/gpu/nvgpu/fifo_t19x.h b/drivers/gpu/nvgpu/fifo_t19x.h index 25d5f41d..6d508304 100644 --- a/drivers/gpu/nvgpu/fifo_t19x.h +++ b/drivers/gpu/nvgpu/fifo_t19x.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _FIFO_T19X_H_ diff --git a/drivers/gpu/nvgpu/gr_t19x.h b/drivers/gpu/nvgpu/gr_t19x.h index a4506f1c..954472fa 100644 --- a/drivers/gpu/nvgpu/gr_t19x.h +++ b/drivers/gpu/nvgpu/gr_t19x.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_GR_T19X_H_ #define _NVGPU_GR_T19X_H_ diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c index 319ebad6..bcb6d740 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h index f3219177..d5a36661 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.h +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_GV100_FB diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c index 2e605cce..9f13abce 100644 --- a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h index 122e750f..2302d988 100644 --- a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __GR_CTX_GV100_H__ #define __GR_CTX_GV100_H__ diff --git a/drivers/gpu/nvgpu/gv100/gv100.h b/drivers/gpu/nvgpu/gv100/gv100.h index eeea64a4..7cc1f77b 100644 --- a/drivers/gpu/nvgpu/gv100/gv100.h +++ b/drivers/gpu/nvgpu/gv100/gv100.h @@ -3,17 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef GV100_H diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 8cf8e245..caa43a95 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h index a7c74db0..7dcf1d77 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.h +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_HAL_GV11B_H diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c index 6952cb5e..93688206 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.c +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h index eeab7d56..eba724f9 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.h +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef MM_GV100_H diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index 26c5a891..984d31da 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifdef CONFIG_DEBUG_FS diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.h b/drivers/gpu/nvgpu/gv11b/acr_gv11b.h index 60cf1b86..72b3ec35 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __ACR_GV11B_H_ diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 4f611799..86518ac7 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -3,17 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License along with - * this program. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "nvgpu/log.h" diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h index ce60ad3e..a0c7e0b1 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.h @@ -4,17 +4,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License along with - * this program. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __CE_GV11B_H__ #define __CE_GV11B_H__ diff --git a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h index 10750426..94b25c02 100644 --- a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_ECC_GV11B_H_ diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index a44589d5..f47a2fac 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index eec90d23..4ebee343 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_GV11B_FB diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 189fe3f0..8c9e58f7 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include #include diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 0cc1c7c2..f622aba8 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef FIFO_GV11B_H diff --git a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c index 920e4c16..514aadb1 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.c @@ -4,18 +4,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h index 8feb15fd..679403ef 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h @@ -3,17 +3,23 @@ * * Copyright (c) 2016 - 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __GR_CTX_GV11B_H__ #define __GR_CTX_GV11B_H__ diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 74ea0d2c..b96f2bc6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 9adace63..8880fbdd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_GR_GV11B_H_ diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index d0fb41c3..c8691ad5 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c @@ -3,17 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.h b/drivers/gpu/nvgpu/gv11b/gv11b.h index 142a66ba..3d5490e6 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gv11b.h @@ -3,17 +3,23 @@ * * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef GV11B_H diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c index 3b55eb41..b9953221 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c @@ -1,18 +1,23 @@ /* * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. * * This file is autogenerated. Do not edit. */ diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h index ba91a2a7..233189e0 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2016, NVIDIA Corporation. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 09825b98..f8bdc213 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.h b/drivers/gpu/nvgpu/gv11b/hal_gv11b.h index 7acbf03b..0fdda6f3 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_HAL_GV11B_H diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index b1d85c5a..a199e024 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h index e371afea..9b46e74c 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef LTC_GV11B_H diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index 59263e54..dab304e2 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/mc_gv11b.h index 53f25a39..de193a84 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef MC_GV11B_H diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 941a0bbe..6df29cb0 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h index 12f0fe63..d830b7cc 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h @@ -2,14 +2,23 @@ * GV11B MM * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef MM_GV11B_H diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 3f6b0153..c29d4a23 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 41c6199e..74ed9165 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include /* for udelay */ diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h index 96ade0d2..809970ff 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __PMU_GV11B_H_ diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c index 5e98f9f1..a29322b7 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c @@ -3,17 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h index dada9a7e..0ee2edfe 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.h @@ -4,17 +4,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __REGOPS_GV11B_H_ #define __REGOPS_GV11B_H_ diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index ee89ecc2..84d21a9a 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -3,17 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License along with - * this program. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h index d199711d..10dc0ba5 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h @@ -4,17 +4,23 @@ * * Copyright (c) 2016 - 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License along with - * this program. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __SUBCONTEXT_GV11B_H__ #define __SUBCONTEXT_GV11B_H__ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h index 8e1a4846..eea51fbb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __NVGPU_GMMU_T19X_H__ diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h index c456687b..fcf99778 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h @@ -1,17 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef __NVGPU_NVHOST_T19X_H__ diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h index 71841484..58f4fad1 100644 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h +++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_GPUID_T19X_H_ #define _NVGPU_GPUID_T19X_H_ diff --git a/drivers/gpu/nvgpu/tsg_t19x.h b/drivers/gpu/nvgpu/tsg_t19x.h index 2f359668..18c00821 100644 --- a/drivers/gpu/nvgpu/tsg_t19x.h +++ b/drivers/gpu/nvgpu/tsg_t19x.h @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_TSG_T19X_H_ diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 446eea26..887b654d 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c index f8f021b7..3df082fc 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h index a9c13b5f..b3c7f729 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _VGPU_FIFO_GV11B_H_ diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c index fcd31d20..a3d1cd90 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h index cc3171d4..933aa06b 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _VGPU_GR_GV11B_H_ diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index fff1a386..34f1198f 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c index 93341427..857e58c4 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h index bfcfe65c..0e09f4f6 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _VGPU_SUBCTX_GV11B_H_ diff --git a/drivers/gpu/nvgpu/vgpu/vgpu_t19x.h b/drivers/gpu/nvgpu/vgpu/vgpu_t19x.h index de3e0f80..8c020f80 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu_t19x.h +++ b/drivers/gpu/nvgpu/vgpu/vgpu_t19x.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _VGPU_T19X_H_ -- cgit v1.2.2 From 971987f363751076a9bddddf7deb5a5a17e8739a Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Wed, 20 Sep 2017 11:28:07 -0700 Subject: gpu: nvgpu: vgpu: unset gops->fifo.tsg_verify_status_faulted The native code of fault checking accesses channel registers which is impossible for vgpu. vgpu needs to implement its own later. Bug 200349281 Change-Id: Iea78ad5457bcc30d0545bbe2e1cd1dba76ed2680 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1564715 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c index 3df082fc..ff13b11f 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -50,4 +50,6 @@ void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops) gops->fifo.init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw; gops->fifo.free_channel_ctx_header = vgpu_gv11b_free_subctx_header; + /* TODO: implement it for CE fault */ + gops->fifo.tsg_verify_status_faulted = NULL; } -- cgit v1.2.2 From 9825a8ec69d54c725c38015006aed655d10ac567 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 15 Aug 2017 15:28:35 -0700 Subject: gpu: nvgpu: fix handling of EGPC_ETPC_SM addresses Implemented litter values for following defines: GPU_LIT_SMPC_PRI_BASE GPU_LIT_SMPC_PRI_SHARED_BASE GPU_LIT_SMPC_PRI_UNIQUE_BASE9 GPU_LIT_SMPC_PRI_STRIDE Added broadcast flags for smpc Handled all combinations of broadcast/unicast EGPC, ETPC, SM Bug 200337994 Change-Id: I7aa3c4d9ac4e819010061d44fb5a40056762f518 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1539075 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 106 +++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 12 +++ .../nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 16 ++++ 4 files changed, 127 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index b96f2bc6..f209012c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -3409,6 +3409,45 @@ bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr) pri_is_egpc_addr_shared(g, addr); } +static inline u32 pri_smpc_in_etpc_addr_mask(struct gk20a *g, u32 addr) +{ + u32 smpc_stride = nvgpu_get_litter_value(g, + GPU_LIT_SMPC_PRI_STRIDE); + + return (addr & (smpc_stride - 1)); +} + +static u32 pri_smpc_ext_addr(struct gk20a *g, u32 sm_offset, u32 gpc_num, + u32 tpc_num, u32 sm_num) +{ + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + u32 tpc_in_gpc_base = nvgpu_get_litter_value(g, + GPU_LIT_TPC_IN_GPC_BASE); + u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, + GPU_LIT_TPC_IN_GPC_STRIDE); + u32 egpc_base = g->ops.gr.get_egpc_base(g); + u32 smpc_unique_base = nvgpu_get_litter_value(g, + GPU_LIT_SMPC_PRI_UNIQUE_BASE); + u32 smpc_stride = nvgpu_get_litter_value(g, + GPU_LIT_SMPC_PRI_STRIDE); + + return (egpc_base + (gpc_num * gpc_stride) + tpc_in_gpc_base + + (tpc_num * tpc_in_gpc_stride) + + (sm_num * smpc_stride) + + (smpc_unique_base + sm_offset)); +} + +static bool pri_is_smpc_addr_in_etpc_shared(struct gk20a *g, u32 addr) +{ + u32 smpc_shared_base = nvgpu_get_litter_value(g, + GPU_LIT_SMPC_PRI_SHARED_BASE); + u32 smpc_stride = nvgpu_get_litter_value(g, + GPU_LIT_SMPC_PRI_STRIDE); + + return (addr >= smpc_shared_base) && + (addr < smpc_shared_base + smpc_stride); +} + bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr) { u32 egpc_addr = 0; @@ -3476,6 +3515,7 @@ int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags) { u32 gpc_addr; + u32 tpc_addr; if (g->ops.gr.is_egpc_addr(g, addr)) { nvgpu_log_info(g, "addr=0x%x is egpc", addr); @@ -3501,6 +3541,9 @@ int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, *tpc_num = g->ops.gr.get_tpc_num(g, gpc_addr); nvgpu_log_info(g, "tpc=0x%x", *tpc_num); } + tpc_addr = pri_tpccs_addr_mask(addr); + if (pri_is_smpc_addr_in_etpc_shared(g, tpc_addr)) + *broadcast_flags |= PRI_BROADCAST_FLAGS_SMPC; } nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, @@ -3511,6 +3554,25 @@ int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, return -EINVAL; } +static void gv11b_gr_update_priv_addr_table_smpc(struct gk20a *g, u32 gpc_num, + u32 tpc_num, u32 addr, + u32 *priv_addr_table, u32 *t) +{ + u32 sm_per_tpc, sm_num; + + nvgpu_log_info(g, "broadcast flags smpc"); + + sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); + for (sm_num = 0; sm_num < sm_per_tpc; sm_num++) { + priv_addr_table[*t] = pri_smpc_ext_addr(g, + pri_smpc_in_etpc_addr_mask(g, addr), + gpc_num, tpc_num, sm_num); + nvgpu_log_info(g, "priv_addr_table[%d]:%#08x", + *t, priv_addr_table[*t]); + (*t)++; + } +} + void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t) { @@ -3531,15 +3593,27 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, for (tpc_num = 0; tpc_num < g->gr.gpc_tpc_count[gpc_num]; tpc_num++) { - priv_addr_table[*t] = - pri_etpc_addr(g, - pri_tpccs_addr_mask(addr), - gpc_num, tpc_num); - nvgpu_log_info(g, - "priv_addr_table[%d]:%#08x", - *t, priv_addr_table[*t]); - (*t)++; + if (broadcast_flags & + PRI_BROADCAST_FLAGS_SMPC) { + gv11b_gr_update_priv_addr_table_smpc( + g, gpc_num, tpc_num, addr, + priv_addr_table, t); + } else { + priv_addr_table[*t] = + pri_etpc_addr(g, + pri_tpccs_addr_mask(addr), + gpc_num, tpc_num); + nvgpu_log_info(g, + "priv_addr_table[%d]:%#08x", + *t, priv_addr_table[*t]); + (*t)++; + } } + } else if (broadcast_flags & PRI_BROADCAST_FLAGS_SMPC) { + tpc_num = 0; + gv11b_gr_update_priv_addr_table_smpc( + g, gpc_num, tpc_num, addr, + priv_addr_table, t); } else { priv_addr_table[*t] = pri_egpc_addr(g, @@ -3553,10 +3627,17 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, } else if (!(broadcast_flags & PRI_BROADCAST_FLAGS_EGPC)) { if (broadcast_flags & PRI_BROADCAST_FLAGS_ETPC) { nvgpu_log_info(g, "broadcast flags etpc but not egpc"); + gpc_num = 0; for (tpc_num = 0; tpc_num < g->gr.gpc_tpc_count[gpc]; tpc_num++) { - priv_addr_table[*t] = + if (broadcast_flags & + PRI_BROADCAST_FLAGS_SMPC) + gv11b_gr_update_priv_addr_table_smpc( + g, gpc_num, tpc_num, addr, + priv_addr_table, t); + else { + priv_addr_table[*t] = pri_etpc_addr(g, pri_tpccs_addr_mask(addr), gpc, tpc_num); @@ -3564,7 +3645,14 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, "priv_addr_table[%d]:%#08x", *t, priv_addr_table[*t]); (*t)++; + } } + } else if (broadcast_flags & PRI_BROADCAST_FLAGS_SMPC) { + tpc_num = 0; + gpc_num = 0; + gv11b_gr_update_priv_addr_table_smpc( + g, gpc_num, tpc_num, addr, + priv_addr_table, t); } else { priv_addr_table[*t] = addr; nvgpu_log_info(g, "priv_addr_table[%d]:%#08x", diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 8880fbdd..3f06fe77 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -28,6 +28,8 @@ #define EGPC_PRI_BASE 0x580000 #define EGPC_PRI_SHARED_BASE 0x480000 +#define PRI_BROADCAST_FLAGS_SMPC BIT(17) + #define GV11B_ZBC_TYPE_STENCIL T19X_ZBC #define ZBC_STENCIL_CLEAR_FMT_INVAILD 0 #define ZBC_STENCIL_CLEAR_FMT_U8 1 diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f8bdc213..9baa3581 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -166,6 +166,18 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_SM_PRI_STRIDE: ret = proj_sm_stride_v(); break; + case GPU_LIT_SMPC_PRI_BASE: + ret = proj_smpc_base_v(); + break; + case GPU_LIT_SMPC_PRI_SHARED_BASE: + ret = proj_smpc_shared_base_v(); + break; + case GPU_LIT_SMPC_PRI_UNIQUE_BASE: + ret = proj_smpc_unique_base_v(); + break; + case GPU_LIT_SMPC_PRI_STRIDE: + ret = proj_smpc_stride_v(); + break; /* Even though GV11B doesn't have an FBPA unit, the HW reports one, * and the microcode as a result leaves space in the context buffer * for one, so make sure SW accounts for this also. diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 7e7ad14a..8406ea21 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -116,6 +116,22 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) { return 0x00001800; } +static inline u32 proj_smpc_base_v(void) +{ + return 0x00000200; +} +static inline u32 proj_smpc_shared_base_v(void) +{ + return 0x00000300; +} +static inline u32 proj_smpc_unique_base_v(void) +{ + return 0x00000600; +} +static inline u32 proj_smpc_stride_v(void) +{ + return 0x00000100; +} static inline u32 proj_host_num_engines_v(void) { return 0x00000004; -- cgit v1.2.2 From 1f6755b287cd5382a6e16baf0342bf6a7ab97f6c Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 26 Sep 2017 11:22:01 -0700 Subject: gpu: nvgpu: gv11b: set correct max subctx count Reading gr_pri_fe_chip_def_info_r() during gv11b_init_fifo_setup_hw on RTL platforms is giving "0xbadf1201" error because fecs part of priv ring is still in reset. This needs to be fixed after identifying relevant engine that needs to be brought out of reset. Until that time, use constant value from hw definition(whose value is 64): gr_pri_fe_chip_def_info_max_veid_count_init_v(). Bug 1983643 Change-Id: I66f2b6491c9d444c6f6919e76c72ec33a904bc90 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1568139 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Tested-by: Seema Khowala GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 8c9e58f7..26e444cc 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1779,8 +1779,7 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g) f->t19x.usermode_regs = g->regs + usermode_cfg0_r(); f->t19x.max_subctx_count = - gr_pri_fe_chip_def_info_max_veid_count_v( - gk20a_readl(g, gr_pri_fe_chip_def_info_r())); + gr_pri_fe_chip_def_info_max_veid_count_init_v(); return 0; } -- cgit v1.2.2 From 0d63e22a9920eb1e3d8653665cda650eca2311cd Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 27 Sep 2017 11:18:13 -0700 Subject: gpu: nvgpu: gv11b: check for memory aperture type Check for memory aperture type before setting relevant sysmem non-coherent or vidmem flags in ram entry. Modified following functions to correct memory aperture type: gv11b_get_ch_runlist_entry gv11b_subctx_commit_pdb Added following hw constants for chan_inst_target: ram_rl_entry_chan_inst_target_sys_mem_coh_v ram_rl_entry_chan_inst_target_vid_mem_v Change-Id: I85698044b9fe4c8baed71121845e4fb69dc33922 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1569521 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 8 ++++++-- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 5 ++++- drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | 8 ++++++++ drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 8 ++++++++ 4 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 26e444cc..5fe40663 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -107,9 +107,13 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) ram_rl_entry_chan_runqueue_selector_f( c->t19x.runqueue_sel) | ram_rl_entry_chan_userd_target_f( - ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | + nvgpu_aperture_mask(g, &g->fifo.userd, + ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), + ram_rl_entry_chan_userd_target_vid_mem_v())) | ram_rl_entry_chan_inst_target_f( - ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()); + nvgpu_aperture_mask(g, &c->inst_block, + ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(), + ram_rl_entry_chan_inst_target_vid_mem_v())); addr_lo = u64_lo32(c->userd_iova) >> ram_rl_entry_chan_userd_ptr_align_shift_v(); diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 84d21a9a..4951d3a4 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -158,12 +158,15 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, u32 format_word; u32 pdb_addr_lo, pdb_addr_hi; u64 pdb_addr; + u32 aperture = nvgpu_aperture_mask(g, vm->pdb.mem, + ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), + ram_in_sc_page_dir_base_target_vid_mem_v()); pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); pdb_addr_hi = u64_hi32(pdb_addr); format_word = ram_in_sc_page_dir_base_target_f( - ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | + aperture, 0) | ram_in_sc_page_dir_base_vol_f( ram_in_sc_page_dir_base_vol_true_v(), 0) | ram_in_sc_page_dir_base_fault_replay_tex_f(1, 0) | diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h index fa42ebbe..3a5bf6cb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h @@ -672,6 +672,14 @@ static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) { return 0x00000003; } +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) +{ + return 0x00000002U; +} +static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) +{ + return 0x00000000U; +} static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) { return (v & 0x3) << 6; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index c7f15f57..fe8bcd6b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -672,6 +672,14 @@ static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) { return 0x00000003; } +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) +{ + return 0x00000002U; +} +static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) +{ + return 0x00000000U; +} static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) { return (v & 0x3) << 6; -- cgit v1.2.2 From 058485d28538b033636180c11592a9088878c807 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 27 Sep 2017 14:15:02 -0700 Subject: gpu: nvgpu: gv100: disable ctxsw trace ctxsw_trace need modifications with subcontext. Disable it for time-being. Change-Id: I0f0e3d0653e159dca09c40c8d0b4c46643cd0496 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1569629 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Martinez Nieto Tested-by: David Martinez Nieto Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index caa43a95..c9b9a1ca 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -465,20 +465,20 @@ static const struct gpu_ops gv100_ops = { }, #ifdef CONFIG_GK20A_CTXSW_TRACE .fecs_trace = { - .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, - .free_user_buffer = gk20a_ctxsw_dev_ring_free, - .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, - .init = gk20a_fecs_trace_init, - .deinit = gk20a_fecs_trace_deinit, - .enable = gk20a_fecs_trace_enable, - .disable = gk20a_fecs_trace_disable, - .is_enabled = gk20a_fecs_trace_is_enabled, - .reset = gk20a_fecs_trace_reset, - .flush = gp10b_fecs_trace_flush, - .poll = gk20a_fecs_trace_poll, - .bind_channel = gk20a_fecs_trace_bind_channel, - .unbind_channel = gk20a_fecs_trace_unbind_channel, - .max_entries = gk20a_gr_max_entries, + .alloc_user_buffer = NULL, + .free_user_buffer = NULL, + .mmap_user_buffer = NULL, + .init = NULL, + .deinit = NULL, + .enable = NULL, + .disable = NULL, + .is_enabled = NULL, + .reset = NULL, + .flush = NULL, + .poll = NULL, + .bind_channel = NULL, + .unbind_channel = NULL, + .max_entries = NULL, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { -- cgit v1.2.2 From f63f96866dd3cd696e37cf7e83d419cca4f965fa Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 28 Sep 2017 16:57:16 -0700 Subject: gpu: nvgpu: gv11b: init therm regs for pwr/clk init *eng_delay*, *eng_idle_filt*, *fecs_idle_filter* and *hubmmu_idle_filter* in therm regs. Change-Id: I4ab5374084e993cd96ef28ace87b6013b996178d Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1570556 Reviewed-by: Terje Bergstrom Reviewed-by: Seshendra Gadagottu Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 +- drivers/gpu/nvgpu/gv11b/therm_gv11b.c | 75 ++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/therm_gv11b.h | 28 ++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 24 +++++++ 5 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/gv11b/therm_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/therm_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index d0a015bb..bbc1118d 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -18,6 +18,7 @@ nvgpu-y += \ $(nvgpu-t19x)/gv11b/acr_gv11b.o \ $(nvgpu-t19x)/gv11b/subctx_gv11b.o \ $(nvgpu-t19x)/gv11b/regops_gv11b.o \ + $(nvgpu-t19x)/gv11b/therm_gv11b.o \ $(nvgpu-t19x)/gv100/mm_gv100.o \ $(nvgpu-t19x)/gv100/gr_ctx_gv100.o \ $(nvgpu-t19x)/gv100/fb_gv100.o \ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9baa3581..f2fb9972 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -81,6 +81,7 @@ #include "gv11b_gating_reglist.h" #include "regops_gv11b.h" #include "subctx_gv11b.h" +#include "therm_gv11b.h" #include #include @@ -553,7 +554,7 @@ static const struct gpu_ops gv11b_ops = { }, .therm = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, - .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, + .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, }, .pmu = { .pmu_setup_elpg = gp10b_pmu_setup_elpg, diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.c b/drivers/gpu/nvgpu/gv11b/therm_gv11b.c new file mode 100644 index 00000000..18987119 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/therm_gv11b.c @@ -0,0 +1,75 @@ +/* + * GV11B Therm + * + * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gk20a/gk20a.h" + +#include + +#include + +int gv11b_elcg_init_idle_filters(struct gk20a *g) +{ + u32 gate_ctrl, idle_filter; + u32 engine_id; + u32 active_engine_id = 0; + struct fifo_gk20a *f = &g->fifo; + + if (nvgpu_platform_is_simulation(g)) + return 0; + + gk20a_dbg_info("init clock/power gate reg"); + + for (engine_id = 0; engine_id < f->num_engines; engine_id++) { + active_engine_id = f->active_engines_list[engine_id]; + + gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_idle_filt_exp_m(), + therm_gate_ctrl_eng_idle_filt_exp__prod_f()); + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_idle_filt_mant_m(), + therm_gate_ctrl_eng_idle_filt_mant__prod_f()); + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_delay_before_m(), + therm_gate_ctrl_eng_delay_before__prod_f()); + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_delay_after_m(), + therm_gate_ctrl_eng_delay_after__prod_f()); + gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); + } + + idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r()); + idle_filter = set_field(idle_filter, + therm_fecs_idle_filter_value_m(), + therm_fecs_idle_filter_value__prod_f()); + gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter); + + idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r()); + idle_filter = set_field(idle_filter, + therm_hubmmu_idle_filter_value_m(), + therm_hubmmu_idle_filter_value__prod_f()); + gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter); + + return 0; +} diff --git a/drivers/gpu/nvgpu/gv11b/therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/therm_gv11b.h new file mode 100644 index 00000000..1d89597b --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/therm_gv11b.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef THERM_GV11B_H +#define THERM_GV11B_H + +struct gk20a; +int gv11b_elcg_init_idle_filters(struct gk20a *g); + +#endif /* THERM_GV11B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index 64a7e292..b47e37f4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -240,6 +240,10 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) { return 0x1f << 8; } +static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) +{ + return 0x200; +} static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) { return (v & 0x7) << 13; @@ -248,6 +252,10 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) { return 0x7 << 13; } +static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) +{ + return 0x2000; +} static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) { return (v & 0xf) << 16; @@ -256,6 +264,10 @@ static inline u32 therm_gate_ctrl_eng_delay_before_m(void) { return 0xf << 16; } +static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) +{ + return 0x40000; +} static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) { return (v & 0xf) << 20; @@ -264,6 +276,10 @@ static inline u32 therm_gate_ctrl_eng_delay_after_m(void) { return 0xf << 20; } +static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) +{ + return 0x0; +} static inline u32 therm_fecs_idle_filter_r(void) { return 0x00020288; @@ -272,6 +288,10 @@ static inline u32 therm_fecs_idle_filter_value_m(void) { return 0xffffffff << 0; } +static inline u32 therm_fecs_idle_filter_value__prod_f(void) +{ + return 0x0; +} static inline u32 therm_hubmmu_idle_filter_r(void) { return 0x0002028c; @@ -280,6 +300,10 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void) { return 0xffffffff << 0; } +static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) +{ + return 0x0; +} static inline u32 therm_clk_slowdown_r(u32 i) { return 0x00020160 + i*4; -- cgit v1.2.2 From 192afccf7c9982ea47b46fd4b7ace4114ff7b45e Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Fri, 22 Sep 2017 15:36:36 +0530 Subject: gpu: nvgpu: gv11b: skip clk gating prog for pre-si For pre-silicon platforms, clock gating should be skipped as it is not supported. Added new flags "can_"x"lcg" to check platform capability before programming SLCG,BLCG and ELCG. Bug 200314250 Change-Id: Iec7564b00b988cdd50a02f3130662727839c5047 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1566251 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 3 ++ drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 49 +++++++++++----------- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 7 ++++ .../nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 3 ++ 4 files changed, 38 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index f209012c..da632aac 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2352,6 +2352,9 @@ void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine) { u32 gate_ctrl; + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_ELCG)) + return; + gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(engine)); switch (mode) { diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c index b9953221..ff4880c4 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c @@ -27,6 +27,7 @@ #include #include "gv11b_gating_reglist.h" +#include struct gating_desc { u32 addr; @@ -282,7 +283,7 @@ void gv11b_slcg_bus_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_bus) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -301,7 +302,7 @@ void gv11b_slcg_ce2_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_ce2) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -320,7 +321,7 @@ void gv11b_slcg_chiplet_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_chiplet) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -344,7 +345,7 @@ void gv11b_slcg_fb_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_fb) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -363,7 +364,7 @@ void gv11b_slcg_fifo_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_fifo) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -382,7 +383,7 @@ void gr_gv11b_slcg_gr_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_gr) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -401,7 +402,7 @@ void ltc_gv11b_slcg_ltc_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_ltc) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -420,7 +421,7 @@ void gv11b_slcg_perf_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_perf) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -439,7 +440,7 @@ void gv11b_slcg_priring_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_priring) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -458,7 +459,7 @@ void gv11b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_pwr_csb) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -477,7 +478,7 @@ void gv11b_slcg_pmu_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_pmu) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -496,7 +497,7 @@ void gv11b_slcg_therm_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_therm) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -515,7 +516,7 @@ void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_slcg_xbar) / sizeof(struct gating_desc); - if (!g->slcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) return; for (i = 0; i < size; i++) { @@ -534,7 +535,7 @@ void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_blcg_bus) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { @@ -553,7 +554,7 @@ void gv11b_blcg_ce_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_blcg_ce) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { @@ -572,7 +573,7 @@ void gv11b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_blcg_ctxsw_prog) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { @@ -591,7 +592,7 @@ void gv11b_blcg_fb_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_blcg_fb) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { @@ -610,7 +611,7 @@ void gv11b_blcg_fifo_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_blcg_fifo) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { @@ -629,7 +630,7 @@ void gv11b_blcg_gr_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_blcg_gr) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { @@ -648,7 +649,7 @@ void gv11b_blcg_ltc_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_blcg_ltc) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { @@ -667,7 +668,7 @@ void gv11b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_blcg_pwr_csb) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { @@ -686,7 +687,7 @@ void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_blcg_pmu) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { @@ -705,7 +706,7 @@ void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_blcg_xbar) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { @@ -724,7 +725,7 @@ void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, u32 i; u32 size = sizeof(gv11b_pg_gr) / sizeof(struct gating_desc); - if (!g->blcg_enabled) + if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) return; for (i = 0; i < size; i++) { diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index c29d4a23..d2c690f4 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -133,6 +133,13 @@ struct gk20a_platform t19x_gpu_tegra_platform = { .probe = gv11b_tegra_probe, .remove = gv11b_tegra_remove, + .enable_slcg = false, + .enable_blcg = false, + .enable_elcg = false, + .can_slcg = false, + .can_blcg = false, + .can_elcg = false, + /* power management callbacks */ .suspend = gv11b_tegra_suspend, .railgate = gv11b_tegra_railgate, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 887b654d..396359c3 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -72,6 +72,9 @@ struct gk20a_platform gv11b_vgpu_tegra_platform = { .enable_elcg = false, .enable_elpg = false, .enable_aelpg = false, + .can_slcg = false, + .can_blcg = false, + .can_elcg = false, .ch_wdt_timeout_ms = 5000, -- cgit v1.2.2 From dc5edb1417390b583b5ff2406e554ce0770e02ae Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 16 Aug 2017 16:13:18 -0700 Subject: gpu: nvgpu: rename ops.mm.get_physical_addr_bits T19x/gv100 version of same patch in kernel/nvgpu. Change-Id: I7174864cf1e072af61609c0843da16fcafe54c02 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1566750 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index c9b9a1ca..72864c5f 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -494,7 +494,6 @@ static const struct gpu_ops gv100_ops = { .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, .gpu_phys_addr = gv11b_gpu_phys_addr, - .get_physical_addr_bits = NULL, .get_mmu_levels = gp10b_mm_get_mmu_levels, .get_vidmem_size = gv100_mm_get_vidmem_size, .init_pdb = gp10b_mm_init_pdb, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f2fb9972..0c509ee2 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -540,7 +540,7 @@ static const struct gpu_ops gv11b_ops = { .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, .gpu_phys_addr = gv11b_gpu_phys_addr, - .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, + .get_iommu_bit = gp10b_mm_get_iommu_bit, .get_mmu_levels = gp10b_mm_get_mmu_levels, .init_pdb = gp10b_mm_init_pdb, .init_mm_setup_hw = gv11b_init_mm_setup_hw, -- cgit v1.2.2 From 3663e9cccc73589b1b2aa2148c8cb220bad99077 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Fri, 29 Sep 2017 20:09:55 +0530 Subject: gpu: nvgpu: gv100 hw header for Falcon controller - Constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions Change-Id: I039e269b18ea8aea48b30d3af84b347ae5509413 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1570998 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h | 599 +++++++++++++++++++++ 1 file changed, 599 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h new file mode 100644 index 00000000..122956bb --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_falcon_gv100.h @@ -0,0 +1,599 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_falcon_gv100_h_ +#define _hw_falcon_gv100_h_ + +static inline u32 falcon_falcon_irqsset_r(void) +{ + return 0x00000000U; +} +static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40U; +} +static inline u32 falcon_falcon_irqsclr_r(void) +{ + return 0x00000004U; +} +static inline u32 falcon_falcon_irqstat_r(void) +{ + return 0x00000008U; +} +static inline u32 falcon_falcon_irqstat_halt_true_f(void) +{ + return 0x10U; +} +static inline u32 falcon_falcon_irqstat_exterr_true_f(void) +{ + return 0x20U; +} +static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40U; +} +static inline u32 falcon_falcon_irqmode_r(void) +{ + return 0x0000000cU; +} +static inline u32 falcon_falcon_irqmset_r(void) +{ + return 0x00000010U; +} +static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 falcon_falcon_irqmclr_r(void) +{ + return 0x00000014U; +} +static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_irqmask_r(void) +{ + return 0x00000018U; +} +static inline u32 falcon_falcon_irqdest_r(void) +{ + return 0x0000001cU; +} +static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1U) << 16U; +} +static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1U) << 17U; +} +static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1U) << 18U; +} +static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1U) << 19U; +} +static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1U) << 20U; +} +static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1U) << 21U; +} +static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1U) << 22U; +} +static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1U) << 23U; +} +static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xffU) << 24U; +} +static inline u32 falcon_falcon_curctx_r(void) +{ + return 0x00000050U; +} +static inline u32 falcon_falcon_nxtctx_r(void) +{ + return 0x00000054U; +} +static inline u32 falcon_falcon_mailbox0_r(void) +{ + return 0x00000040U; +} +static inline u32 falcon_falcon_mailbox1_r(void) +{ + return 0x00000044U; +} +static inline u32 falcon_falcon_itfen_r(void) +{ + return 0x00000048U; +} +static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1U; +} +static inline u32 falcon_falcon_idlestate_r(void) +{ + return 0x0000004cU; +} +static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0U) & 0x1U; +} +static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1U) & 0x7fffU; +} +static inline u32 falcon_falcon_os_r(void) +{ + return 0x00000080U; +} +static inline u32 falcon_falcon_engctl_r(void) +{ + return 0x000000a4U; +} +static inline u32 falcon_falcon_cpuctl_r(void) +{ + return 0x00000100U; +} +static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1U << 4U; +} +static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4U) & 0x1U; +} +static inline u32 falcon_falcon_cpuctl_stopped_m(void) +{ + return 0x1U << 5U; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1U << 6U; +} +static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6U) & 0x1U; +} +static inline u32 falcon_falcon_cpuctl_alias_r(void) +{ + return 0x00000130U; +} +static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 falcon_falcon_imemc_r(u32 i) +{ + return 0x00000180U + i*16U; +} +static inline u32 falcon_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3fU) << 2U; +} +static inline u32 falcon_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1U) << 24U; +} +static inline u32 falcon_falcon_imemd_r(u32 i) +{ + return 0x00000184U + i*16U; +} +static inline u32 falcon_falcon_imemt_r(u32 i) +{ + return 0x00000188U + i*16U; +} +static inline u32 falcon_falcon_sctl_r(void) +{ + return 0x00000240U; +} +static inline u32 falcon_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4U; +} +static inline u32 falcon_falcon_bootvec_r(void) +{ + return 0x00000104U; +} +static inline u32 falcon_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffffU) << 0U; +} +static inline u32 falcon_falcon_dmactl_r(void) +{ + return 0x0000010cU; +} +static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1U << 1U; +} +static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1U << 2U; +} +static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 falcon_falcon_hwcfg_r(void) +{ + return 0x00000108U; +} +static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0U) & 0x1ffU; +} +static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9U) & 0x1ffU; +} +static inline u32 falcon_falcon_dmatrfbase_r(void) +{ + return 0x00000110U; +} +static inline u32 falcon_falcon_dmatrfbase1_r(void) +{ + return 0x00000128U; +} +static inline u32 falcon_falcon_dmatrfmoffs_r(void) +{ + return 0x00000114U; +} +static inline u32 falcon_falcon_dmatrfcmd_r(void) +{ + return 0x00000118U; +} +static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7U) << 8U; +} +static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7U) << 12U; +} +static inline u32 falcon_falcon_dmatrffboffs_r(void) +{ + return 0x0000011cU; +} +static inline u32 falcon_falcon_imctl_debug_r(void) +{ + return 0x0000015cU; +} +static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) +{ + return (v & 0xffffffU) << 0U; +} +static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) +{ + return (v & 0x7U) << 24U; +} +static inline u32 falcon_falcon_imstat_r(void) +{ + return 0x00000144U; +} +static inline u32 falcon_falcon_traceidx_r(void) +{ + return 0x00000148U; +} +static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) +{ + return (r >> 16U) & 0xffU; +} +static inline u32 falcon_falcon_traceidx_idx_f(u32 v) +{ + return (v & 0xffU) << 0U; +} +static inline u32 falcon_falcon_tracepc_r(void) +{ + return 0x0000014cU; +} +static inline u32 falcon_falcon_tracepc_pc_v(u32 r) +{ + return (r >> 0U) & 0xffffffU; +} +static inline u32 falcon_falcon_exterraddr_r(void) +{ + return 0x00000168U; +} +static inline u32 falcon_falcon_exterrstat_r(void) +{ + return 0x0000016cU; +} +static inline u32 falcon_falcon_exterrstat_valid_m(void) +{ + return 0x1U << 31U; +} +static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31U) & 0x1U; +} +static inline u32 falcon_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001U; +} +static inline u32 falcon_falcon_icd_cmd_r(void) +{ + return 0x00000200U; +} +static inline u32 falcon_falcon_icd_cmd_opc_s(void) +{ + return 4U; +} +static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xfU) << 0U; +} +static inline u32 falcon_falcon_icd_cmd_opc_m(void) +{ + return 0xfU << 0U; +} +static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0U) & 0xfU; +} +static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8U; +} +static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xeU; +} +static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1fU) << 8U; +} +static inline u32 falcon_falcon_icd_rdata_r(void) +{ + return 0x0000020cU; +} +static inline u32 falcon_falcon_dmemc_r(u32 i) +{ + return 0x000001c0U + i*8U; +} +static inline u32 falcon_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3fU) << 2U; +} +static inline u32 falcon_falcon_dmemc_offs_m(void) +{ + return 0x3fU << 2U; +} +static inline u32 falcon_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xffU) << 8U; +} +static inline u32 falcon_falcon_dmemc_blk_m(void) +{ + return 0xffU << 8U; +} +static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1U) << 24U; +} +static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1U) << 25U; +} +static inline u32 falcon_falcon_dmemd_r(u32 i) +{ + return 0x000001c4U + i*8U; +} +static inline u32 falcon_falcon_debug1_r(void) +{ + return 0x00000090U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) +{ + return 1U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) +{ + return (v & 0x1U) << 16U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) +{ + return 0x1U << 16U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) +{ + return (r >> 16U) & 0x1U; +} +static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) +{ + return 0x0U; +} +static inline u32 falcon_falcon_debuginfo_r(void) +{ + return 0x00000094U; +} +#endif -- cgit v1.2.2 From a61661172728fd0c173c1ebd73cc45233a1c23a4 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Sat, 30 Sep 2017 12:51:51 +0530 Subject: gpu: nvgpu: falcon: Qualify unsigned HW constants - Falcon HW header re-generate for gv11b. - Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions Change-Id: I313945edac1112a32c965d9565b30dc95a002752 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1571352 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h | 270 ++++++++++----------- 1 file changed, 135 insertions(+), 135 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h index fdeb4a37..4bb8f2de 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h @@ -58,542 +58,542 @@ static inline u32 falcon_falcon_irqsset_r(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 falcon_falcon_irqsset_swgen0_set_f(void) { - return 0x40; + return 0x40U; } static inline u32 falcon_falcon_irqsclr_r(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 falcon_falcon_irqstat_r(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 falcon_falcon_irqstat_halt_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 falcon_falcon_irqstat_exterr_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 falcon_falcon_irqstat_swgen0_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 falcon_falcon_irqmode_r(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 falcon_falcon_irqmset_r(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 falcon_falcon_irqmset_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 falcon_falcon_irqmset_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 falcon_falcon_irqmset_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 falcon_falcon_irqmclr_r(void) { - return 0x00000014; + return 0x00000014U; } static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 falcon_falcon_irqmclr_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 falcon_falcon_irqmclr_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 falcon_falcon_irqmask_r(void) { - return 0x00000018; + return 0x00000018U; } static inline u32 falcon_falcon_irqdest_r(void) { - return 0x0000001c; + return 0x0000001cU; } static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v) { - return (v & 0x1) << 21; + return (v & 0x1U) << 21U; } static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v) { - return (v & 0x1) << 23; + return (v & 0x1U) << 23U; } static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 falcon_falcon_curctx_r(void) { - return 0x00000050; + return 0x00000050U; } static inline u32 falcon_falcon_nxtctx_r(void) { - return 0x00000054; + return 0x00000054U; } static inline u32 falcon_falcon_mailbox0_r(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 falcon_falcon_mailbox1_r(void) { - return 0x00000044; + return 0x00000044U; } static inline u32 falcon_falcon_itfen_r(void) { - return 0x00000048; + return 0x00000048U; } static inline u32 falcon_falcon_itfen_ctxen_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 falcon_falcon_idlestate_r(void) { - return 0x0000004c; + return 0x0000004cU; } static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r) { - return (r >> 1) & 0x7fff; + return (r >> 1U) & 0x7fffU; } static inline u32 falcon_falcon_os_r(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 falcon_falcon_engctl_r(void) { - return 0x000000a4; + return 0x000000a4U; } static inline u32 falcon_falcon_cpuctl_r(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 falcon_falcon_cpuctl_halt_intr_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 falcon_falcon_cpuctl_stopped_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 6U) & 0x1U; } static inline u32 falcon_falcon_cpuctl_alias_r(void) { - return 0x00000130; + return 0x00000130U; } static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 falcon_falcon_imemc_r(u32 i) { - return 0x00000180 + i*16; + return 0x00000180U + i*16U; } static inline u32 falcon_falcon_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 falcon_falcon_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 falcon_falcon_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 falcon_falcon_imemd_r(u32 i) { - return 0x00000184 + i*16; + return 0x00000184U + i*16U; } static inline u32 falcon_falcon_imemt_r(u32 i) { - return 0x00000188 + i*16; + return 0x00000188U + i*16U; } static inline u32 falcon_falcon_sctl_r(void) { - return 0x00000240; + return 0x00000240U; } static inline u32 falcon_falcon_mmu_phys_sec_r(void) { - return 0x00100ce4; + return 0x00100ce4U; } static inline u32 falcon_falcon_bootvec_r(void) { - return 0x00000104; + return 0x00000104U; } static inline u32 falcon_falcon_bootvec_vec_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 falcon_falcon_dmactl_r(void) { - return 0x0000010c; + return 0x0000010cU; } static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 falcon_falcon_hwcfg_r(void) { - return 0x00000108; + return 0x00000108U; } static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r) { - return (r >> 9) & 0x1ff; + return (r >> 9U) & 0x1ffU; } static inline u32 falcon_falcon_dmatrfbase_r(void) { - return 0x00000110; + return 0x00000110U; } static inline u32 falcon_falcon_dmatrfbase1_r(void) { - return 0x00000128; + return 0x00000128U; } static inline u32 falcon_falcon_dmatrfmoffs_r(void) { - return 0x00000114; + return 0x00000114U; } static inline u32 falcon_falcon_dmatrfcmd_r(void) { - return 0x00000118; + return 0x00000118U; } static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 falcon_falcon_dmatrffboffs_r(void) { - return 0x0000011c; + return 0x0000011cU; } static inline u32 falcon_falcon_imctl_debug_r(void) { - return 0x0000015c; + return 0x0000015cU; } static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v) { - return (v & 0x7) << 24; + return (v & 0x7U) << 24U; } static inline u32 falcon_falcon_imstat_r(void) { - return 0x00000144; + return 0x00000144U; } static inline u32 falcon_falcon_traceidx_r(void) { - return 0x00000148; + return 0x00000148U; } static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 falcon_falcon_traceidx_idx_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 falcon_falcon_tracepc_r(void) { - return 0x0000014c; + return 0x0000014cU; } static inline u32 falcon_falcon_tracepc_pc_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 falcon_falcon_exterraddr_r(void) { - return 0x00000168; + return 0x00000168U; } static inline u32 falcon_falcon_exterrstat_r(void) { - return 0x0000016c; + return 0x0000016cU; } static inline u32 falcon_falcon_exterrstat_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 falcon_falcon_exterrstat_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 falcon_falcon_exterrstat_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 falcon_falcon_icd_cmd_r(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 falcon_falcon_icd_cmd_opc_s(void) { - return 4; + return 4U; } static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 falcon_falcon_icd_cmd_opc_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void) { - return 0x8; + return 0x8U; } static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void) { - return 0xe; + return 0xeU; } static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 falcon_falcon_icd_rdata_r(void) { - return 0x0000020c; + return 0x0000020cU; } static inline u32 falcon_falcon_dmemc_r(u32 i) { - return 0x000001c0 + i*8; + return 0x000001c0U + i*8U; } static inline u32 falcon_falcon_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 falcon_falcon_dmemc_offs_m(void) { - return 0x3f << 2; + return 0x3fU << 2U; } static inline u32 falcon_falcon_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 falcon_falcon_dmemc_blk_m(void) { - return 0xff << 8; + return 0xffU << 8U; } static inline u32 falcon_falcon_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 falcon_falcon_dmemc_aincr_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 falcon_falcon_dmemd_r(u32 i) { - return 0x000001c4 + i*8; + return 0x000001c4U + i*8U; } static inline u32 falcon_falcon_debug1_r(void) { - return 0x00000090; + return 0x00000090U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void) { - return 1; + return 1U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 falcon_falcon_debuginfo_r(void) { - return 0x00000094; + return 0x00000094U; } #endif -- cgit v1.2.2 From 19d602da31f81d9dc89a42b2bc84ce14a300773b Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 3 Oct 2017 14:01:51 +0530 Subject: gpu: nvgpu: verify channel status while closing per-platform We right now call gk20a_fifo_tsg_unbind_channel_verify_status() to verify channel status while unbinding a channel from TSG while closing Add support to do this verification per-platform and keep this disabled for vgpu platforms Bug 200327095 Change-Id: I6e2a6a09c784d24ac49477d5450b7d4b671878e3 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1572369 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 72864c5f..028c9d84 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -410,6 +410,7 @@ static const struct gpu_ops gv100_ops = { .preempt_tsg = gv11b_fifo_preempt_tsg, .enable_tsg = gv11b_fifo_enable_tsg, .disable_tsg = gk20a_disable_tsg, + .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status, .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, .update_runlist = gk20a_fifo_update_runlist, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0c509ee2..f366a90e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -456,6 +456,7 @@ static const struct gpu_ops gv11b_ops = { .preempt_tsg = gv11b_fifo_preempt_tsg, .enable_tsg = gv11b_fifo_enable_tsg, .disable_tsg = gk20a_disable_tsg, + .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status, .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, .update_runlist = gk20a_fifo_update_runlist, -- cgit v1.2.2 From 6fe9bdeb9af81d42d6f5d8edcc98487d3fb155ea Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 25 Sep 2017 15:39:09 -0700 Subject: gpu: nvgpu: gv11b: track init veid bundle Add debug prints to track veid bundle init and also return err for subctx init failure. Bug 1983643 Change-Id: I9e6a32e76b1c7deba3a47157ba253976d88b2324 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1568070 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index da632aac..da683af6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2023,7 +2023,7 @@ int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) return 0; } -static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) +static int gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) { struct av_list_gk20a *sw_veid_bundle_init = &g->gr.ctx_vars.sw_veid_bundle_init; @@ -2033,7 +2033,7 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) num_subctx = g->fifo.t19x.max_subctx_count; for (j = 0; j < num_subctx; j++) { - + nvgpu_log_fn(g, "write bundle_address_r for subctx: %d", j); gk20a_writel(g, gr_pipe_bundle_address_r(), sw_veid_bundle_init->l[index].addr | gr_pipe_bundle_address_veid_f(j)); @@ -2041,6 +2041,7 @@ static void gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) err = gr_gk20a_wait_fe_idle(g, gk20a_get_gr_idle_timeout(g), GR_IDLE_CHECK_DEFAULT); } + return err; } int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) @@ -2051,30 +2052,34 @@ int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) u32 last_bundle_data = 0; u32 err = 0; - gk20a_dbg_fn(""); for (i = 0; i < sw_veid_bundle_init->count; i++) { + nvgpu_log_fn(g, "veid bundle count: %d", i); if (i == 0 || last_bundle_data != sw_veid_bundle_init->l[i].value) { gk20a_writel(g, gr_pipe_bundle_data_r(), sw_veid_bundle_init->l[i].value); last_bundle_data = sw_veid_bundle_init->l[i].value; + nvgpu_log_fn(g, "last_bundle_data : 0x%08x", + last_bundle_data); } if (gr_pipe_bundle_address_value_v( sw_veid_bundle_init->l[i].addr) == GR_GO_IDLE_BUNDLE) { + nvgpu_log_fn(g, "go idle bundle"); gk20a_writel(g, gr_pipe_bundle_address_r(), sw_veid_bundle_init->l[i].addr); err |= gr_gk20a_wait_idle(g, gk20a_get_gr_idle_timeout(g), GR_IDLE_CHECK_DEFAULT); } else - gv11b_write_bundle_veid_state(g, i); + err = gv11b_write_bundle_veid_state(g, i); - if (err) + if (err) { + nvgpu_err(g, "failed to init sw veid bundle"); break; + } } - gk20a_dbg_fn("done"); return err; } -- cgit v1.2.2 From 6647e5c9569258fbf3db096275a79f86f86ed3a6 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 5 Oct 2017 10:25:51 -0700 Subject: gpu: nvgpu: gv11b: disable cycle stat Feature will be enabled after it is verified. To disable cycle stat, do not set NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS and NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT Bug 200352825 Change-Id: I3f0d58a8095f3a0996964056029c12cff45f0a5b Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1573760 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index da683af6..c3f19fa2 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1688,12 +1688,7 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, void gr_gv11b_init_cyclestats(struct gk20a *g) { #if defined(CONFIG_GK20A_CYCLE_STATS) - g->gpu_characteristics.flags |= - NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS; - g->gpu_characteristics.flags |= - NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT; -#else - (void)g; + /* TODO: waiting for cycle stats to be implemented for gv11b */ #endif } -- cgit v1.2.2 From bb1c38e2f5f133a4281f73f8076a206ec728bd22 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 6 Oct 2017 10:36:49 -0700 Subject: gpu: nvgpu: gv11b: perfbuffer enable and disable dbg ops set to NULL Will be enabled after feature is verified on volta Bug 200352825 Change-Id: Idbe318ea82051e53f15caecf2afb15d72b99acea Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1574482 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f366a90e..4a289d8f 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -633,8 +633,8 @@ static const struct gpu_ops gv11b_ops = { nvgpu_check_and_set_context_reservation, .release_profiler_reservation = nvgpu_release_profiler_reservation, - .perfbuffer_enable = gk20a_perfbuf_enable_locked, - .perfbuffer_disable = gk20a_perfbuf_disable_locked, + .perfbuffer_enable = NULL, + .perfbuffer_disable = NULL, }, .bus = { .init_hw = gk20a_bus_init_hw, -- cgit v1.2.2 From f518304e0d8102216c7c0022cd4b66fcd844264c Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 3 Aug 2017 21:43:50 -0700 Subject: gpu: nvgpu: fix GV100 hal definitions These changes allow GV100 to init the basic HALs to pass nvgpu_submit_twod (1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency issues (2) Properly enable FB (3) Fan control requires the execution of the pre-os FW, without it the SKU201 is extremely noisy JIRA: NVGPUGV100-9 Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1539926 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 2 + drivers/gpu/nvgpu/gv100/bios_gv100.c | 108 +++++++++++++++++++++ drivers/gpu/nvgpu/gv100/bios_gv100.h | 31 ++++++ drivers/gpu/nvgpu/gv100/fifo_gv100.c | 32 ++++++ drivers/gpu/nvgpu/gv100/fifo_gv100.h | 32 ++++++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 22 +++-- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 4 +- .../nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | 4 + 8 files changed, 227 insertions(+), 8 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv100/bios_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/bios_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/fifo_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/fifo_gv100.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index bbc1118d..1ca21fb5 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -22,6 +22,8 @@ nvgpu-y += \ $(nvgpu-t19x)/gv100/mm_gv100.o \ $(nvgpu-t19x)/gv100/gr_ctx_gv100.o \ $(nvgpu-t19x)/gv100/fb_gv100.o \ + $(nvgpu-t19x)/gv100/bios_gv100.o \ + $(nvgpu-t19x)/gv100/fifo_gv100.o \ $(nvgpu-t19x)/gv100/hal_gv100.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.c b/drivers/gpu/nvgpu/gv100/bios_gv100.c new file mode 100644 index 00000000..9ca05a11 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/bios_gv100.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gp106/bios_gp106.h" +#include "bios_gv100.h" + +#include +#include + +#define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */ +#define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */ + +#define SCRATCH_PREOS_PROGRESS 6 +#define PREOS_PROGRESS_MASK(r) ((r >> 12) & 0xf) +#define PREOS_PROGRESS_NOT_STARTED 0 +#define PREOS_PROGRESS_STARTED 1 +#define PREOS_PROGRESS_EXIT 2 +#define PREOS_PROGRESS_EXIT_SECUREMODE 3 +#define PREOS_PROGRESS_ABORTED 6 + +#define SCRATCH_PMU_EXIT_AND_HALT 1 +#define PMU_EXIT_AND_HALT_SET(r, v) ((r & ~0x200UL) | v) +#define PMU_EXIT_AND_HALT_YES (0x1UL << 9) + +#define SCRATCH_PRE_OS_RELOAD 1 +#define PRE_OS_RELOAD_SET(r, v) ((r & ~0x100UL) | v) +#define PRE_OS_RELOAD_YES (0x1UL << 8) + + +void gv100_bios_preos_reload_check(struct gk20a *g) +{ + u32 progress = gk20a_readl(g, + bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); + + if (PREOS_PROGRESS_MASK(progress) != PREOS_PROGRESS_NOT_STARTED) { + u32 reload = gk20a_readl(g, + bus_sw_scratch_r(SCRATCH_PRE_OS_RELOAD)); + + gk20a_writel(g, bus_sw_scratch_r(SCRATCH_PRE_OS_RELOAD), + PRE_OS_RELOAD_SET(reload, PRE_OS_RELOAD_YES)); + } +} + +int gv100_bios_preos_wait_for_halt(struct gk20a *g) +{ + int err = -EINVAL; + u32 progress; + u32 tmp; + int preos_completed; + struct nvgpu_timeout timeout; + + nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT); + + /* Check the progress */ + progress = gk20a_readl(g, bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); + + if (PREOS_PROGRESS_MASK(progress) == PREOS_PROGRESS_STARTED) { + err = 0; + + /* Complete the handshake */ + tmp = gk20a_readl(g, + bus_sw_scratch_r(SCRATCH_PMU_EXIT_AND_HALT)); + + gk20a_writel(g, bus_sw_scratch_r(SCRATCH_PMU_EXIT_AND_HALT), + PMU_EXIT_AND_HALT_SET(tmp, PMU_EXIT_AND_HALT_YES)); + + nvgpu_timeout_init(g, &timeout, + PMU_BOOT_TIMEOUT_MAX / + PMU_BOOT_TIMEOUT_DEFAULT, + NVGPU_TIMER_RETRY_TIMER); + + do { + progress = gk20a_readl(g, + bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); + preos_completed = pwr_falcon_cpuctl_halt_intr_v( + gk20a_readl(g, pwr_falcon_cpuctl_r())) && + (PREOS_PROGRESS_MASK(progress) == + PREOS_PROGRESS_EXIT); + nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT); + } while (!preos_completed && !nvgpu_timeout_expired(&timeout)); + } + + return err; +} diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.h b/drivers/gpu/nvgpu/gv100/bios_gv100.h new file mode 100644 index 00000000..c6433f57 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/bios_gv100.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_BIOS_GV100_H +#define NVGPU_BIOS_GV100_H + +struct gk20a; + +void gv100_bios_preos_reload_check(struct gk20a *g); +int gv100_bios_preos_wait_for_halt(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c new file mode 100644 index 00000000..e19301e6 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c @@ -0,0 +1,32 @@ +/* + * GV100 fifo + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "fifo_gv100.h" + +#include + +u32 gv100_fifo_get_num_fifos(struct gk20a *g) +{ + return ccsr_channel__size_1_v(); +} diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.h b/drivers/gpu/nvgpu/gv100/fifo_gv100.h new file mode 100644 index 00000000..3ffb417c --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.h @@ -0,0 +1,32 @@ +/* + * GV100 Fifo + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef FIFO_GV100_H +#define FIFO_GV100_H + +#include +struct gk20a; + +u32 gv100_fifo_get_num_fifos(struct gk20a *g); +#endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 028c9d84..7f7ab785 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -61,6 +61,7 @@ #include "gp106/acr_gp106.h" #include "gp106/sec2_gp106.h" #include "gp106/bios_gp106.h" +#include "gv100/bios_gv100.h" #include "gp106/therm_gp106.h" #include "gp106/xve_gp106.h" #include "gp106/clk_gp106.h" @@ -85,6 +86,10 @@ #include "gv11b/mm_gv11b.h" #include "gv11b/pmu_gv11b.h" #include "gv11b/fb_gv11b.h" +#include "gv100/mm_gv100.h" +#include "gv11b/pmu_gv11b.h" +#include "gv100/fb_gv100.h" +#include "gv100/fifo_gv100.h" #include "gv11b/fifo_gv11b.h" #include "gv11b/gv11b_gating_reglist.h" #include "gv11b/regops_gv11b.h" @@ -208,6 +213,11 @@ int gv100_init_gpu_characteristics(struct gk20a *g) static const struct gpu_ops gv100_ops = { + .bios = { + .init = gp106_bios_init, + .preos_wait_for_halt = gv100_bios_preos_wait_for_halt, + .preos_reload_check = gv100_bios_preos_reload_check, + }, .ltc = { .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, @@ -218,7 +228,7 @@ static const struct gpu_ops gv100_ops = { .init_comptags = gp10b_ltc_init_comptags, .cbc_ctrl = gm20b_ltc_cbc_ctrl, .isr = gv11b_ltc_isr, - .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .cbc_fix_config = NULL, .flush = gm20b_flush_ltc, .set_enabled = gp10b_ltc_set_enabled, }, @@ -374,8 +384,7 @@ static const struct gpu_ops gv100_ops = { .fb = { .reset = gv100_fb_reset, .init_hw = gk20a_fb_init_hw, - .init_fs_state = gv11b_fb_init_fs_state, - .init_cbc = gv11b_fb_init_cbc, + .init_fs_state = NULL, .set_mmu_page_size = gm20b_fb_set_mmu_page_size, .set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line, @@ -417,7 +426,7 @@ static const struct gpu_ops gv100_ops = { .trigger_mmu_fault = NULL, .get_mmu_fault_info = NULL, .wait_engine_idle = gk20a_fifo_wait_engine_idle, - .get_num_fifos = gv11b_fifo_get_num_fifos, + .get_num_fifos = gv100_fifo_get_num_fifos, .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, @@ -633,7 +642,6 @@ static const struct gpu_ops gv100_ops = { }, .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, .get_litter_value = gv100_get_litter_value, - .bios_init = gp106_bios_init, }; int gv100_init_hal(struct gk20a *g) @@ -641,6 +649,7 @@ int gv100_init_hal(struct gk20a *g) struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + gops->bios = gv100_ops.bios; gops->ltc = gv100_ops.ltc; gops->ce2 = gv100_ops.ce2; gops->gr = gv100_ops.gr; @@ -674,7 +683,6 @@ int gv100_init_hal(struct gk20a *g) gops->chip_init_gpu_characteristics = gv100_ops.chip_init_gpu_characteristics; gops->get_litter_value = gv100_ops.get_litter_value; - gops->bios_init = gv100_ops.bios_init; __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); @@ -689,6 +697,8 @@ int gv100_init_hal(struct gk20a *g) gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); + g->bootstrap_owner = LSF_FALCON_ID_SEC2; + g->name = "gv10x"; c->twod_class = FERMI_TWOD_A; diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 6df29cb0..e452462e 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -118,7 +118,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, fb_size = (g->ops.fifo.get_num_fifos(g) + 1) * gmmu_fault_buf_size_v(); - err = nvgpu_dma_alloc_map_sys(vm, fb_size, + err = nvgpu_dma_alloc_map(vm, fb_size, &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); if (err) { nvgpu_err(g, @@ -131,7 +131,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, HW_FAULT_BUF_STATUS_ALLOC_TRUE; *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY; - err = nvgpu_dma_alloc_map_sys(vm, fb_size, + err = nvgpu_dma_alloc_map(vm, fb_size, &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); if (err) { nvgpu_err(g, diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h index bc4f7f28..2c89ccd6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h @@ -56,6 +56,10 @@ #ifndef _hw_bus_gv100_h_ #define _hw_bus_gv100_h_ +static inline u32 bus_sw_scratch_r(u32 i) +{ + return 0x00001580 + i*4; +} static inline u32 bus_bar0_window_r(void) { return 0x00001700; -- cgit v1.2.2 From 514c80d8d2d80cf9fa16447f7cd99d723ba5ce70 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 29 Sep 2017 12:39:57 -0700 Subject: gpu: nvgpu: gv11b: Qualify unsigned HW constants Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions. Change-Id: Ic93ef7f7a6beae57be7759c7eb3df9148afed824 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1571162 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- .../nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h | 82 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 64 +- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h | 24 +- .../include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h | 198 +- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h | 884 +++---- .../nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 314 +-- .../nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h | 64 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | 46 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 716 +++--- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 2428 ++++++++++---------- .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 372 +-- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 96 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 296 +-- .../nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h | 76 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h | 2 +- .../nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h | 54 +- .../nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h | 10 +- .../nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h | 16 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h | 64 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h | 446 ++-- .../nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h | 354 +-- .../nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 176 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h | 28 +- .../nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h | 88 +- 24 files changed, 3449 insertions(+), 3449 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h index 9fe7e591..d1d9b34a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h @@ -58,166 +58,166 @@ static inline u32 bus_bar0_window_r(void) { - return 0x00001700; + return 0x00001700U; } static inline u32 bus_bar0_window_base_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 bus_bar0_window_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 bus_bar1_block_r(void) { - return 0x00001704; + return 0x00001704U; } static inline u32 bus_bar1_block_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 bus_bar1_block_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 bus_bar1_block_mode_virtual_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 bus_bar2_block_r(void) { - return 0x00001714; + return 0x00001714U; } static inline u32 bus_bar2_block_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 bus_bar2_block_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 bus_bar2_block_mode_virtual_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 bus_bar1_block_ptr_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 bus_bar2_block_ptr_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 bus_bind_status_r(void) { - return 0x00001710; + return 0x00001710U; } static inline u32 bus_bind_status_bar1_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 bus_bind_status_bar1_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar1_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 bus_bind_status_bar1_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar1_outstanding_true_f(void) { - return 0x2; + return 0x2U; } static inline u32 bus_bind_status_bar2_pending_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 bus_bind_status_bar2_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar2_pending_busy_f(void) { - return 0x4; + return 0x4U; } static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 bus_bind_status_bar2_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar2_outstanding_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 bus_intr_0_r(void) { - return 0x00001100; + return 0x00001100U; } static inline u32 bus_intr_0_pri_squash_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 bus_intr_0_pri_fecserr_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 bus_intr_0_pri_timeout_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 bus_intr_en_0_r(void) { - return 0x00001140; + return 0x00001140U; } static inline u32 bus_intr_en_0_pri_squash_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 bus_intr_en_0_pri_fecserr_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 bus_intr_en_0_pri_timeout_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index 3243e3e2..e21a4738 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h @@ -58,130 +58,130 @@ static inline u32 ccsr_channel_inst_r(u32 i) { - return 0x00800000 + i*8; + return 0x00800000U + i*8U; } static inline u32 ccsr_channel_inst__size_1_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ccsr_channel_inst_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 ccsr_channel_inst_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 ccsr_channel_inst_bind_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 ccsr_channel_inst_bind_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 ccsr_channel_r(u32 i) { - return 0x00800004 + i*8; + return 0x00800004U + i*8U; } static inline u32 ccsr_channel__size_1_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ccsr_channel_enable_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ccsr_channel_enable_set_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 ccsr_channel_enable_set_true_f(void) { - return 0x400; + return 0x400U; } static inline u32 ccsr_channel_enable_clr_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 ccsr_channel_status_v(u32 r) { - return (r >> 24) & 0xf; + return (r >> 24U) & 0xfU; } static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) { - return 0x0000000a; + return 0x0000000aU; } static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) { - return 0x0000000d; + return 0x0000000dU; } static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 ccsr_channel_next_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 ccsr_channel_next_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ccsr_channel_force_ctx_reload_true_f(void) { - return 0x100; + return 0x100U; } static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 ccsr_channel_eng_faulted_f(u32 v) { - return (v & 0x1) << 23; + return (v & 0x1U) << 23U; } static inline u32 ccsr_channel_eng_faulted_v(u32 r) { - return (r >> 23) & 0x1; + return (r >> 23U) & 0x1U; } static inline u32 ccsr_channel_eng_faulted_reset_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 ccsr_channel_eng_faulted_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ccsr_channel_busy_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h index 8a0a9206..efc14d00 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h @@ -58,50 +58,50 @@ static inline u32 ce_intr_status_r(u32 i) { - return 0x00104410 + i*128; + return 0x00104410U + i*128U; } static inline u32 ce_intr_status_blockpipe_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ce_intr_status_blockpipe_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 ce_intr_status_nonblockpipe_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 ce_intr_status_nonblockpipe_reset_f(void) { - return 0x2; + return 0x2U; } static inline u32 ce_intr_status_launcherr_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 ce_intr_status_launcherr_reset_f(void) { - return 0x4; + return 0x4U; } static inline u32 ce_intr_status_invalid_config_pending_f(void) { - return 0x8; + return 0x8U; } static inline u32 ce_intr_status_invalid_config_reset_f(void) { - return 0x8; + return 0x8U; } static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) { - return 0x10; + return 0x10U; } static inline u32 ce_pce_map_r(void) { - return 0x00104028; + return 0x00104028U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h index 27ac297c..623a8c15 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h @@ -58,398 +58,398 @@ static inline u32 ctxsw_prog_fecs_header_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ctxsw_prog_main_image_ctl_o(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) { - return 0x00000011; + return 0x00000011U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) { - return 0x00000012; + return 0x00000012U; } static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) { - return 0x00000021; + return 0x00000021U; } static inline u32 ctxsw_prog_main_image_patch_count_o(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ctxsw_prog_main_image_context_id_o(void) { - return 0x000000f0; + return 0x000000f0U; } static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) { - return 0x00000014; + return 0x00000014U; } static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) { - return 0x00000018; + return 0x00000018U; } static inline u32 ctxsw_prog_main_image_zcull_o(void) { - return 0x0000001c; + return 0x0000001cU; } static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 ctxsw_prog_main_image_pm_o(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 ctxsw_prog_main_image_pm_mode_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) { - return 0x7 << 3; + return 0x7U << 3U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) { - return 0x8; + return 0x8U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) { - return 0x0000002c; + return 0x0000002cU; } static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) { - return 0x000000d0; + return 0x000000d0U; } static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) { - return 0x000000d4; + return 0x000000d4U; } static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) { - return 0x000000d8; + return 0x000000d8U; } static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) { - return 0x000000dc; + return 0x000000dcU; } static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) { - return 0x00000060; + return 0x00000060U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) { - return 0x00000094; + return 0x00000094U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) { - return 0x00000068; + return 0x00000068U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) { - return 0x00000070; + return 0x00000070U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) { - return 0x00000074; + return 0x00000074U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) { - return 0x00000078; + return 0x00000078U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) { - return 0x0000007c; + return 0x0000007cU; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_magic_value_o(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) { - return 0x600dc0de; + return 0x600dc0deU; } static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) { - return 0x000000b8; + return 0x000000b8U; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) { - return 0x000000bc; + return 0x000000bcU; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) { - return 0x000000c4; + return 0x000000c4U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) { - return 0x000000c8; + return 0x000000c8U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) { - return 0x000000cc; + return 0x000000ccU; } static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) { - return 0x000000e0; + return 0x000000e0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) { - return 0x000000e4; + return 0x000000e4U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_local_image_ppc_info_o(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 ctxsw_prog_local_magic_value_o(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) { - return 0xad0becab; + return 0xad0becabU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) { - return 0x000000ec; + return 0x000000ecU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) { - return 0x000000a0; + return 0x000000a0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) { - return 2; + return 2U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) { - return 0x2; + return 0x2U; } static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) { - return 0x000000a4; + return 0x000000a4U; } static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) { - return 0x000000a8; + return 0x000000a8U; } static inline u32 ctxsw_prog_main_image_misc_options_o(void) { - return 0x0000003c; + return 0x0000003cU; } static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) { - return 0x1; + return 0x1U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) { - return 0x00000084; + return 0x00000084U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) { - return 0x1; + return 0x1U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) { - return 0x2; + return 0x2U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h index f902ae6c..ea3c7939 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h @@ -58,1770 +58,1770 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void) { - return 0x00100800; + return 0x00100800U; } static inline u32 fb_mmu_ctrl_r(void) { - return 0x00100c80; + return 0x00100c80U; } static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) { - return (r >> 11) & 0x1; + return (r >> 11U) & 0x1U; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_priv_mmu_phy_secure_r(void) { - return 0x00100ce4; + return 0x00100ce4U; } static inline u32 fb_mmu_invalidate_pdb_r(void) { - return 0x00100cb8; + return 0x00100cb8U; } static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_invalidate_r(void) { - return 0x00100cbc; + return 0x00100cbcU; } static inline u32 fb_mmu_invalidate_all_va_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_invalidate_replay_s(void) { - return 3; + return 3U; } static inline u32 fb_mmu_invalidate_replay_f(u32 v) { - return (v & 0x7) << 3; + return (v & 0x7U) << 3U; } static inline u32 fb_mmu_invalidate_replay_m(void) { - return 0x7 << 3; + return 0x7U << 3U; } static inline u32 fb_mmu_invalidate_replay_v(u32 r) { - return (r >> 3) & 0x7; + return (r >> 3U) & 0x7U; } static inline u32 fb_mmu_invalidate_replay_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_replay_start_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_invalidate_sys_membar_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 fb_mmu_invalidate_sys_membar_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 6U) & 0x1U; } static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_invalidate_ack_s(void) { - return 2; + return 2U; } static inline u32 fb_mmu_invalidate_ack_f(u32 v) { - return (v & 0x3) << 7; + return (v & 0x3U) << 7U; } static inline u32 fb_mmu_invalidate_ack_m(void) { - return 0x3 << 7; + return 0x3U << 7U; } static inline u32 fb_mmu_invalidate_ack_v(u32 r) { - return (r >> 7) & 0x3; + return (r >> 7U) & 0x3U; } static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) { - return 0x100; + return 0x100U; } static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) { - return 6; + return 6U; } static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) { - return (v & 0x3f) << 9; + return (v & 0x3fU) << 9U; } static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) { - return 0x3f << 9; + return 0x3fU << 9U; } static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) { - return (r >> 9) & 0x3f; + return (r >> 9U) & 0x3fU; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) { - return 5; + return 5U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) { - return (v & 0x1f) << 15; + return (v & 0x1fU) << 15U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) { - return 0x1f << 15; + return 0x1fU << 15U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) { - return (r >> 15) & 0x1f; + return (r >> 15U) & 0x1fU; } static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) { - return 3; + return 3U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) { - return (v & 0x7) << 24; + return (v & 0x7U) << 24U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) { - return 0x7 << 24; + return 0x7U << 24U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) { - return (r >> 24) & 0x7; + return (r >> 24U) & 0x7U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) { - return 0x5000000; + return 0x5000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) { - return 0x6000000; + return 0x6000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) { - return 0x7000000; + return 0x7000000U; } static inline u32 fb_mmu_invalidate_trigger_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_trigger_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_invalidate_trigger_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_invalidate_trigger_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_invalidate_trigger_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_debug_wr_r(void) { - return 0x00100cc8; + return 0x00100cc8U; } static inline u32 fb_mmu_debug_wr_aperture_s(void) { - return 2; + return 2U; } static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 fb_mmu_debug_wr_aperture_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_debug_wr_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_wr_vol_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_debug_wr_vol_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_debug_wr_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fb_mmu_debug_rd_r(void) { - return 0x00100ccc; + return 0x00100cccU; } static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_debug_rd_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_rd_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fb_mmu_debug_ctrl_r(void) { - return 0x00100cc4; + return 0x00100cc4U; } static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 fb_mmu_debug_ctrl_debug_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_vpr_info_r(void) { - return 0x00100cd0; + return 0x00100cd0U; } static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 fb_mmu_vpr_info_fetch_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_vpr_info_fetch_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_l2tlb_ecc_status_r(void) { - return 0x00100e70; + return 0x00100e70U; } static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 18; + return 0x1U << 18U; } static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void) { - return 0x00100e74; + return 0x00100e74U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void) { - return 0x00100e78; + return 0x00100e78U; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_l2tlb_ecc_address_r(void) { - return 0x00100e7c; + return 0x00100e7cU; } static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void) { - return 32; + return 32U; } static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_hubtlb_ecc_status_r(void) { - return 0x00100e84; + return 0x00100e84U; } static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 18; + return 0x1U << 18U; } static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void) { - return 0x00100e88; + return 0x00100e88U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void) { - return 0x00100e8c; + return 0x00100e8cU; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_hubtlb_ecc_address_r(void) { - return 0x00100e90; + return 0x00100e90U; } static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void) { - return 32; + return 32U; } static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fillunit_ecc_status_r(void) { - return 0x00100e98; + return 0x00100e98U; } static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 18; + return 0x1U << 18U; } static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void) { - return 0x00100e9c; + return 0x00100e9cU; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void) { - return 0x00100ea0; + return 0x00100ea0U; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fb_mmu_fillunit_ecc_address_r(void) { - return 0x00100ea4; + return 0x00100ea4U; } static inline u32 fb_mmu_fillunit_ecc_address_index_s(void) { - return 32; + return 32U; } static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_niso_flush_sysmem_addr_r(void) { - return 0x00100c10; + return 0x00100c10U; } static inline u32 fb_niso_intr_r(void) { - return 0x00100a20; + return 0x00100a20U; } static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_m(void) { - return 0x1 << 26; + return 0x1U << 26U; } static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_niso_intr_en_r(u32 i) { - return 0x00100a24 + i*4; + return 0x00100a24U + i*4U; } static inline u32 fb_niso_intr_en__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) { - return (v & 0x1) << 27; + return (v & 0x1U) << 27U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(u32 v) { - return (v & 0x1) << 26; + return (v & 0x1U) << 26U; } static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_niso_intr_en_set_r(u32 i) { - return 0x00100a2c + i*4; + return 0x00100a2cU + i*4U; } static inline u32 fb_niso_intr_en_set__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(void) { - return 0x1 << 26; + return 0x1U << 26U; } static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_niso_intr_en_clr_r(u32 i) { - return 0x00100a34 + i*4; + return 0x00100a34U + i*4U; } static inline u32 fb_niso_intr_en_clr__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(void) { - return 0x1 << 26; + return 0x1U << 26U; } static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) { - return 0x00100e24 + i*20; + return 0x00100e24U + i*20U; } static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) { - return (v & 0x3) << 1; + return (v & 0x3U) << 1U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) { - return (r >> 1) & 0x3; + return (r >> 1U) & 0x3U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) { - return 0x00100e28 + i*20; + return 0x00100e28U + i*20U; } static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_buffer_get_r(u32 i) { - return 0x00100e2c + i*20; + return 0x00100e2cU + i*20U; } static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) { - return 0xfffff << 0; + return 0xfffffU << 0U; } static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_buffer_put_r(u32 i) { - return 0x00100e30 + i*20; + return 0x00100e30U + i*20U; } static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_buffer_size_r(u32 i) { - return 0x00100e34 + i*20; + return 0x00100e34U + i*20U; } static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_size_enable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_addr_lo_r(void) { - return 0x00100e4c; + return 0x00100e4cU; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_addr_hi_r(void) { - return 0x00100e50; + return 0x00100e50U; } static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_inst_lo_r(void) { - return 0x00100e54; + return 0x00100e54U; } static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) { - return (r >> 10) & 0x3; + return (r >> 10U) & 0x3U; } static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_inst_hi_r(void) { - return 0x00100e58; + return 0x00100e58U; } static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_info_r(void) { - return 0x00100e5c; + return 0x00100e5cU; } static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) { - return (r >> 7) & 0x1; + return (r >> 7U) & 0x1U; } static inline u32 fb_mmu_fault_info_client_v(u32 r) { - return (r >> 8) & 0x7f; + return (r >> 8U) & 0x7fU; } static inline u32 fb_mmu_fault_info_access_type_v(u32 r) { - return (r >> 16) & 0xf; + return (r >> 16U) & 0xfU; } static inline u32 fb_mmu_fault_info_client_type_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) { - return (r >> 24) & 0x1f; + return (r >> 24U) & 0x1fU; } static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_info_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_status_r(void) { - return 0x00100e60; + return 0x00100e60U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_fault_status_replayable_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 fb_mmu_fault_status_replayable_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_set_f(void) { - return 0x100; + return 0x100U; } static inline u32 fb_mmu_fault_status_replayable_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) { - return 0x200; + return 0x200U; } static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_error_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) { - return 0x400; + return 0x400U; } static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) { - return 0x800; + return 0x800U; } static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) { - return 0x1 << 13; + return 0x1U << 13U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) { - return 0x1 << 14; + return 0x1U << 14U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 fb_mmu_fault_status_busy_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_mmu_fault_status_busy_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_busy_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_status_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_status_valid_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_valid_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_status_valid_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_valid_clear_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_num_active_ltcs_r(void) { - return 0x00100ec0; + return 0x00100ec0U; } static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 fb_mmu_cbc_base_r(void) { - return 0x00100ec4; + return 0x00100ec4U; } static inline u32 fb_mmu_cbc_base_address_f(u32 v) { - return (v & 0x3ffffff) << 0; + return (v & 0x3ffffffU) << 0U; } static inline u32 fb_mmu_cbc_base_address_v(u32 r) { - return (r >> 0) & 0x3ffffff; + return (r >> 0U) & 0x3ffffffU; } static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 fb_mmu_cbc_top_r(void) { - return 0x00100ec8; + return 0x00100ec8U; } static inline u32 fb_mmu_cbc_top_size_f(u32 v) { - return (v & 0x7fff) << 0; + return (v & 0x7fffU) << 0U; } static inline u32 fb_mmu_cbc_top_size_v(u32 r) { - return (r >> 0) & 0x7fff; + return (r >> 0U) & 0x7fffU; } static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 fb_mmu_cbc_max_r(void) { - return 0x00100ecc; + return 0x00100eccU; } static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 fb_mmu_cbc_max_safe_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_cbc_max_safe_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_cbc_max_safe_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void) { - return 0x00000001; + return 0x00000001U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index 0d85a486..59cc7a1d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h @@ -58,630 +58,630 @@ static inline u32 fifo_bar1_base_r(void) { - return 0x00002254; + return 0x00002254U; } static inline u32 fifo_bar1_base_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 fifo_bar1_base_ptr_align_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fifo_bar1_base_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_bar1_base_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fifo_userd_writeback_r(void) { - return 0x0000225c; + return 0x0000225cU; } static inline u32 fifo_userd_writeback_timer_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fifo_userd_writeback_timer_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_userd_writeback_timer_shorter_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_userd_writeback_timer_100us_v(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 fifo_userd_writeback_timescale_f(u32 v) { - return (v & 0xf) << 12; + return (v & 0xfU) << 12U; } static inline u32 fifo_userd_writeback_timescale_0_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_runlist_base_r(void) { - return 0x00002270; + return 0x00002270U; } static inline u32 fifo_runlist_base_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 fifo_runlist_base_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 fifo_runlist_r(void) { - return 0x00002274; + return 0x00002274U; } static inline u32 fifo_runlist_engine_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 fifo_eng_runlist_base_r(u32 i) { - return 0x00002280 + i*8; + return 0x00002280U + i*8U; } static inline u32 fifo_eng_runlist_base__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fifo_eng_runlist_r(u32 i) { - return 0x00002284 + i*8; + return 0x00002284U + i*8U; } static inline u32 fifo_eng_runlist__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fifo_eng_runlist_length_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fifo_eng_runlist_length_max_v(void) { - return 0x0000ffff; + return 0x0000ffffU; } static inline u32 fifo_eng_runlist_pending_true_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fifo_pb_timeslice_r(u32 i) { - return 0x00002350 + i*4; + return 0x00002350U + i*4U; } static inline u32 fifo_pb_timeslice_timeout_16_f(void) { - return 0x10; + return 0x10U; } static inline u32 fifo_pb_timeslice_timescale_0_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_pb_timeslice_enable_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fifo_pbdma_map_r(u32 i) { - return 0x00002390 + i*4; + return 0x00002390U + i*4U; } static inline u32 fifo_intr_0_r(void) { - return 0x00002100; + return 0x00002100U; } static inline u32 fifo_intr_0_bind_error_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_intr_0_bind_error_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_intr_0_sched_error_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 fifo_intr_0_sched_error_reset_f(void) { - return 0x100; + return 0x100U; } static inline u32 fifo_intr_0_chsw_error_pending_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 fifo_intr_0_chsw_error_reset_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 fifo_intr_0_lb_error_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_intr_0_lb_error_reset_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fifo_intr_0_runlist_event_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fifo_intr_0_channel_intr_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 fifo_intr_en_0_r(void) { - return 0x00002140; + return 0x00002140U; } static inline u32 fifo_intr_en_0_sched_error_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 fifo_intr_en_0_sched_error_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 fifo_intr_en_1_r(void) { - return 0x00002528; + return 0x00002528U; } static inline u32 fifo_intr_bind_error_r(void) { - return 0x0000252c; + return 0x0000252cU; } static inline u32 fifo_intr_sched_error_r(void) { - return 0x0000254c; + return 0x0000254cU; } static inline u32 fifo_intr_sched_error_code_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fifo_intr_chsw_error_r(void) { - return 0x0000256c; + return 0x0000256cU; } static inline u32 fifo_intr_ctxsw_timeout_r(void) { - return 0x00002a30; + return 0x00002a30U; } static inline u32 fifo_intr_ctxsw_timeout_engine_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_intr_ctxsw_timeout_engine_v(u32 r, u32 i) { - return (r >> (0 + i*1)) & 0x1; + return (r >> (0U + i*1U)) & 0x1U; } static inline u32 fifo_intr_ctxsw_timeout_engine__size_1_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 fifo_intr_ctxsw_timeout_engine_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_intr_ctxsw_timeout_engine_pending_f(u32 i) { - return 0x1 << (0 + i*1); + return 0x1U << (0U + i*1U); } static inline u32 fifo_intr_ctxsw_timeout_info_r(u32 i) { - return 0x00003200 + i*4; + return 0x00003200U + i*4U; } static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) { - return (r >> 14) & 0x3; + return (r >> 14U) & 0x3U; } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) { - return (r >> 0) & 0x3fff; + return (r >> 0U) & 0x3fffU; } static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) { - return (r >> 16) & 0x3fff; + return (r >> 16U) & 0x3fffU; } static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) { - return (r >> 30) & 0x3; + return (r >> 30U) & 0x3U; } static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_intr_ctxsw_timeout_info_status_ack_received_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_intr_pbdma_id_r(void) { - return 0x000025a0; + return 0x000025a0U; } static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) { - return (r >> (0 + i*1)) & 0x1; + return (r >> (0U + i*1U)) & 0x1U; } static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_intr_runlist_r(void) { - return 0x00002a00; + return 0x00002a00U; } static inline u32 fifo_fb_timeout_r(void) { - return 0x00002a04; + return 0x00002a04U; } static inline u32 fifo_fb_timeout_period_m(void) { - return 0x3fffffff << 0; + return 0x3fffffffU << 0U; } static inline u32 fifo_fb_timeout_period_max_f(void) { - return 0x3fffffff; + return 0x3fffffffU; } static inline u32 fifo_fb_timeout_period_init_f(void) { - return 0x3c00; + return 0x3c00U; } static inline u32 fifo_fb_timeout_detection_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fifo_fb_timeout_detection_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fifo_fb_timeout_detection_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_sched_disable_r(void) { - return 0x00002630; + return 0x00002630U; } static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_sched_disable_runlist_m(u32 i) { - return 0x1 << (0 + i*1); + return 0x1U << (0U + i*1U); } static inline u32 fifo_sched_disable_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_runlist_preempt_r(void) { - return 0x00002638; + return 0x00002638U; } static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_runlist_preempt_runlist_m(u32 i) { - return 0x1 << (0 + i*1); + return 0x1U << (0U + i*1U); } static inline u32 fifo_runlist_preempt_runlist_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_preempt_r(void) { - return 0x00002634; + return 0x00002634U; } static inline u32 fifo_preempt_pending_true_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fifo_preempt_type_channel_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_preempt_type_tsg_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_preempt_chid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 fifo_preempt_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 fifo_engine_status_r(u32 i) { - return 0x00002640 + i*8; + return 0x00002640U + i*8U; } static inline u32 fifo_engine_status__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 fifo_engine_status_id_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 fifo_engine_status_id_type_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 fifo_engine_status_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_id_type_tsgid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctx_status_v(u32 r) { - return (r >> 13) & 0x7; + return (r >> 13U) & 0x7U; } static inline u32 fifo_engine_status_ctx_status_valid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 fifo_engine_status_next_id_v(u32 r) { - return (r >> 16) & 0xfff; + return (r >> 16U) & 0xfffU; } static inline u32 fifo_engine_status_next_id_type_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 fifo_engine_status_next_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_eng_reload_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fifo_engine_status_faulted_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fifo_engine_status_faulted_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_engine_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fifo_engine_status_engine_idle_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_engine_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctxsw_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 fifo_eng_ctxsw_timeout_r(void) { - return 0x00002a0c; + return 0x00002a0cU; } static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) { - return (v & 0x7fffffff) << 0; + return (v & 0x7fffffffU) << 0U; } static inline u32 fifo_eng_ctxsw_timeout_period_m(void) { - return 0x7fffffff << 0; + return 0x7fffffffU << 0U; } static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) { - return (r >> 0) & 0x7fffffff; + return (r >> 0U) & 0x7fffffffU; } static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void) { - return 0x3fffff; + return 0x3fffffU; } static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void) { - return 0x7fffffff; + return 0x7fffffffU; } static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fifo_eng_ctxsw_timeout_detection_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_pbdma_status_r(u32 i) { - return 0x00003080 + i*4; + return 0x00003080U + i*4U; } static inline u32 fifo_pbdma_status__size_1_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_pbdma_status_id_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 fifo_pbdma_status_id_type_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 fifo_pbdma_status_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_pbdma_status_chan_status_v(u32 r) { - return (r >> 13) & 0x7; + return (r >> 13U) & 0x7U; } static inline u32 fifo_pbdma_status_chan_status_valid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 fifo_pbdma_status_next_id_v(u32 r) { - return (r >> 16) & 0xfff; + return (r >> 16U) & 0xfffU; } static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_pbdma_status_chsw_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_cfg0_r(void) { - return 0x00002004; + return 0x00002004U; } static inline u32 fifo_cfg0_num_pbdma_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 fifo_fb_iface_r(void) { - return 0x000026f0; + return 0x000026f0U; } static inline u32 fifo_fb_iface_control_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fifo_fb_iface_control_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_fb_iface_status_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 fifo_fb_iface_status_enabled_f(void) { - return 0x10; + return 0x10U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h index b2938b32..45c01de0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h @@ -58,130 +58,130 @@ static inline u32 flush_l2_system_invalidate_r(void) { - return 0x00070004; + return 0x00070004U; } static inline u32 flush_l2_system_invalidate_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_system_invalidate_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_system_invalidate_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_flush_dirty_r(void) { - return 0x00070010; + return 0x00070010U; } static inline u32 flush_l2_flush_dirty_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_flush_dirty_pending_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_flush_dirty_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_flush_dirty_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_flush_dirty_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_clean_comptags_r(void) { - return 0x0007000c; + return 0x0007000cU; } static inline u32 flush_l2_clean_comptags_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_clean_comptags_pending_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_clean_comptags_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_clean_comptags_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_clean_comptags_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_fb_flush_r(void) { - return 0x00070000; + return 0x00070000U; } static inline u32 flush_fb_flush_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_fb_flush_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_fb_flush_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_fb_flush_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_fb_flush_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h index 6bc0604b..f8d9b196 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h @@ -58,94 +58,94 @@ static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) { - return 0x00021c38 + i*4; + return 0x00021c38U + i*4U; } static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) { - return 0x00021838 + i*4; + return 0x00021838U + i*4U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) { - return 0x00021944; + return 0x00021944U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) { - return 0x00021948; + return 0x00021948U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) { - return 0x1; + return 0x1U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) { - return 0x0; + return 0x0U; } static inline u32 fuse_status_opt_fbio_r(void) { - return 0x00021c14; + return 0x00021c14U; } static inline u32 fuse_status_opt_fbio_data_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fuse_status_opt_fbio_data_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fuse_status_opt_fbio_data_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) { - return 0x00021d70 + i*4; + return 0x00021d70U + i*4U; } static inline u32 fuse_status_opt_fbp_r(void) { - return 0x00021d38; + return 0x00021d38U; } static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) { - return (r >> (0 + i*1)) & 0x1; + return (r >> (0U + i*1U)) & 0x1U; } static inline u32 fuse_opt_ecc_en_r(void) { - return 0x00021228; + return 0x00021228U; } static inline u32 fuse_opt_feature_fuses_override_disable_r(void) { - return 0x000213f0; + return 0x000213f0U; } static inline u32 fuse_opt_sec_debug_en_r(void) { - return 0x00021218; + return 0x00021218U; } static inline u32 fuse_opt_priv_sec_en_r(void) { - return 0x00021434; + return 0x00021434U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index d84610f3..c39cc2d8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -58,1434 +58,1434 @@ static inline u32 gmmu_new_pde_is_pte_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_is_pte_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_aperture_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_aperture_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_aperture_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_pde_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pde_address_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_vol_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_vol_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_pde_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_new_pde__size_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_dual_pde_is_pte_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_big_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_aperture_small_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_dual_pde_vol_small_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_vol_big_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_dual_pde__size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gmmu_new_pte__size_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_pte_valid_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_valid_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 gmmu_new_pte_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_privilege_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_privilege_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 gmmu_new_pte_privilege_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pte_address_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_address_vid_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pte_address_vid_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_vol_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_vol_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_pte_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_aperture_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_aperture_video_memory_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_pte_read_only_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_read_only_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 gmmu_new_pte_comptagline_f(u32 v) { - return (v & 0x3ffff) << 4; + return (v & 0x3ffffU) << 4U; } static inline u32 gmmu_new_pte_comptagline_w(void) { - return 1; + return 1U; } static inline u32 gmmu_new_pte_kind_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gmmu_new_pte_kind_w(void) { - return 1; + return 1U; } static inline u32 gmmu_new_pte_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_pte_kind_f(u32 v) { - return (v & 0xff) << 4; + return (v & 0xffU) << 4U; } static inline u32 gmmu_pte_kind_w(void) { - return 1; + return 1U; } static inline u32 gmmu_pte_kind_invalid_v(void) { - return 0x000000ff; + return 0x000000ffU; } static inline u32 gmmu_pte_kind_pitch_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gmmu_pte_kind_z16_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_pte_kind_z16_2c_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 gmmu_pte_kind_z16_2z_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) { - return 0x0000000a; + return 0x0000000aU; } static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 gmmu_pte_kind_z16_2cz_v(void) { - return 0x00000036; + return 0x00000036U; } static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) { - return 0x00000037; + return 0x00000037U; } static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) { - return 0x00000038; + return 0x00000038U; } static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) { - return 0x00000039; + return 0x00000039U; } static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) { - return 0x0000005f; + return 0x0000005fU; } static inline u32 gmmu_pte_kind_s8z24_v(void) { - return 0x00000011; + return 0x00000011U; } static inline u32 gmmu_pte_kind_s8z24_1z_v(void) { - return 0x00000012; + return 0x00000012U; } static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) { - return 0x00000013; + return 0x00000013U; } static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) { - return 0x00000014; + return 0x00000014U; } static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) { - return 0x00000015; + return 0x00000015U; } static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) { - return 0x00000016; + return 0x00000016U; } static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) { - return 0x00000017; + return 0x00000017U; } static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) { - return 0x00000018; + return 0x00000018U; } static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) { - return 0x00000019; + return 0x00000019U; } static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) { - return 0x0000001a; + return 0x0000001aU; } static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) { - return 0x0000001b; + return 0x0000001bU; } static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) { - return 0x0000001c; + return 0x0000001cU; } static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) { - return 0x0000001d; + return 0x0000001dU; } static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) { - return 0x0000001e; + return 0x0000001eU; } static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) { - return 0x0000001f; + return 0x0000001fU; } static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) { - return 0x00000021; + return 0x00000021U; } static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) { - return 0x00000022; + return 0x00000022U; } static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) { - return 0x00000023; + return 0x00000023U; } static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) { - return 0x00000024; + return 0x00000024U; } static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) { - return 0x00000025; + return 0x00000025U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) { - return 0x00000026; + return 0x00000026U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) { - return 0x00000027; + return 0x00000027U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) { - return 0x00000029; + return 0x00000029U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) { - return 0x0000002e; + return 0x0000002eU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) { - return 0x0000002f; + return 0x0000002fU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) { - return 0x00000031; + return 0x00000031U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) { - return 0x00000032; + return 0x00000032U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) { - return 0x00000033; + return 0x00000033U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) { - return 0x00000034; + return 0x00000034U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) { - return 0x00000035; + return 0x00000035U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) { - return 0x0000003a; + return 0x0000003aU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) { - return 0x0000003b; + return 0x0000003bU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) { - return 0x0000003c; + return 0x0000003cU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) { - return 0x0000003d; + return 0x0000003dU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) { - return 0x0000003e; + return 0x0000003eU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) { - return 0x0000003f; + return 0x0000003fU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) { - return 0x00000041; + return 0x00000041U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) { - return 0x00000042; + return 0x00000042U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) { - return 0x00000043; + return 0x00000043U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) { - return 0x00000044; + return 0x00000044U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) { - return 0x00000045; + return 0x00000045U; } static inline u32 gmmu_pte_kind_z24s8_v(void) { - return 0x00000046; + return 0x00000046U; } static inline u32 gmmu_pte_kind_z24s8_1z_v(void) { - return 0x00000047; + return 0x00000047U; } static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) { - return 0x00000048; + return 0x00000048U; } static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) { - return 0x00000049; + return 0x00000049U; } static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) { - return 0x0000004a; + return 0x0000004aU; } static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) { - return 0x0000004b; + return 0x0000004bU; } static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) { - return 0x0000004c; + return 0x0000004cU; } static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) { - return 0x0000004d; + return 0x0000004dU; } static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) { - return 0x0000004e; + return 0x0000004eU; } static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) { - return 0x0000004f; + return 0x0000004fU; } static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) { - return 0x00000050; + return 0x00000050U; } static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) { - return 0x00000051; + return 0x00000051U; } static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) { - return 0x00000052; + return 0x00000052U; } static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) { - return 0x00000053; + return 0x00000053U; } static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) { - return 0x00000054; + return 0x00000054U; } static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) { - return 0x00000055; + return 0x00000055U; } static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) { - return 0x00000056; + return 0x00000056U; } static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) { - return 0x00000057; + return 0x00000057U; } static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) { - return 0x00000058; + return 0x00000058U; } static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) { - return 0x00000059; + return 0x00000059U; } static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) { - return 0x0000005a; + return 0x0000005aU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) { - return 0x0000005b; + return 0x0000005bU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) { - return 0x0000005c; + return 0x0000005cU; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) { - return 0x0000005d; + return 0x0000005dU; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) { - return 0x0000005e; + return 0x0000005eU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) { - return 0x00000063; + return 0x00000063U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) { - return 0x00000065; + return 0x00000065U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) { - return 0x00000066; + return 0x00000066U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) { - return 0x00000067; + return 0x00000067U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) { - return 0x00000068; + return 0x00000068U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) { - return 0x00000069; + return 0x00000069U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) { - return 0x0000006a; + return 0x0000006aU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) { - return 0x0000006f; + return 0x0000006fU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) { - return 0x00000070; + return 0x00000070U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) { - return 0x00000071; + return 0x00000071U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) { - return 0x00000072; + return 0x00000072U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) { - return 0x00000073; + return 0x00000073U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) { - return 0x00000074; + return 0x00000074U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) { - return 0x00000075; + return 0x00000075U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) { - return 0x00000076; + return 0x00000076U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) { - return 0x00000077; + return 0x00000077U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) { - return 0x00000078; + return 0x00000078U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) { - return 0x00000079; + return 0x00000079U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) { - return 0x0000007a; + return 0x0000007aU; } static inline u32 gmmu_pte_kind_zf32_v(void) { - return 0x0000007b; + return 0x0000007bU; } static inline u32 gmmu_pte_kind_zf32_1z_v(void) { - return 0x0000007c; + return 0x0000007cU; } static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) { - return 0x0000007d; + return 0x0000007dU; } static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) { - return 0x0000007e; + return 0x0000007eU; } static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) { - return 0x0000007f; + return 0x0000007fU; } static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 gmmu_pte_kind_zf32_2cs_v(void) { - return 0x00000081; + return 0x00000081U; } static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) { - return 0x00000082; + return 0x00000082U; } static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) { - return 0x00000083; + return 0x00000083U; } static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) { - return 0x00000084; + return 0x00000084U; } static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) { - return 0x00000085; + return 0x00000085U; } static inline u32 gmmu_pte_kind_zf32_2cz_v(void) { - return 0x00000086; + return 0x00000086U; } static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) { - return 0x00000087; + return 0x00000087U; } static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) { - return 0x00000088; + return 0x00000088U; } static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) { - return 0x00000089; + return 0x00000089U; } static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) { - return 0x0000008a; + return 0x0000008aU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) { - return 0x0000008b; + return 0x0000008bU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) { - return 0x0000008c; + return 0x0000008cU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) { - return 0x0000008d; + return 0x0000008dU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) { - return 0x0000008e; + return 0x0000008eU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) { - return 0x0000008f; + return 0x0000008fU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) { - return 0x00000090; + return 0x00000090U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) { - return 0x00000091; + return 0x00000091U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) { - return 0x00000092; + return 0x00000092U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) { - return 0x00000097; + return 0x00000097U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) { - return 0x00000098; + return 0x00000098U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) { - return 0x00000099; + return 0x00000099U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) { - return 0x0000009a; + return 0x0000009aU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) { - return 0x0000009b; + return 0x0000009bU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) { - return 0x0000009c; + return 0x0000009cU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) { - return 0x0000009d; + return 0x0000009dU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) { - return 0x0000009e; + return 0x0000009eU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) { - return 0x0000009f; + return 0x0000009fU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) { - return 0x000000a0; + return 0x000000a0U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) { - return 0x000000a1; + return 0x000000a1U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) { - return 0x000000a2; + return 0x000000a2U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) { - return 0x000000a3; + return 0x000000a3U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) { - return 0x000000a4; + return 0x000000a4U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) { - return 0x000000a5; + return 0x000000a5U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) { - return 0x000000a6; + return 0x000000a6U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) { - return 0x000000a7; + return 0x000000a7U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) { - return 0x000000a8; + return 0x000000a8U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) { - return 0x000000a9; + return 0x000000a9U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) { - return 0x000000aa; + return 0x000000aaU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) { - return 0x000000ab; + return 0x000000abU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) { - return 0x000000ac; + return 0x000000acU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) { - return 0x000000ad; + return 0x000000adU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) { - return 0x000000ae; + return 0x000000aeU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) { - return 0x000000b3; + return 0x000000b3U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) { - return 0x000000b4; + return 0x000000b4U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) { - return 0x000000b5; + return 0x000000b5U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) { - return 0x000000b6; + return 0x000000b6U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) { - return 0x000000b7; + return 0x000000b7U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) { - return 0x000000b8; + return 0x000000b8U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) { - return 0x000000b9; + return 0x000000b9U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) { - return 0x000000ba; + return 0x000000baU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) { - return 0x000000bb; + return 0x000000bbU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) { - return 0x000000bc; + return 0x000000bcU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) { - return 0x000000bd; + return 0x000000bdU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) { - return 0x000000be; + return 0x000000beU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) { - return 0x000000bf; + return 0x000000bfU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) { - return 0x000000c1; + return 0x000000c1U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) { - return 0x000000c2; + return 0x000000c2U; } static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) { - return 0x000000c3; + return 0x000000c3U; } static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) { - return 0x000000c4; + return 0x000000c4U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) { - return 0x000000c5; + return 0x000000c5U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) { - return 0x000000c6; + return 0x000000c6U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) { - return 0x000000c7; + return 0x000000c7U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) { - return 0x000000c8; + return 0x000000c8U; } static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) { - return 0x000000ce; + return 0x000000ceU; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) { - return 0x000000cf; + return 0x000000cfU; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) { - return 0x000000d0; + return 0x000000d0U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) { - return 0x000000d1; + return 0x000000d1U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) { - return 0x000000d2; + return 0x000000d2U; } static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) { - return 0x000000d3; + return 0x000000d3U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) { - return 0x000000d4; + return 0x000000d4U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) { - return 0x000000d5; + return 0x000000d5U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) { - return 0x000000d6; + return 0x000000d6U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) { - return 0x000000d7; + return 0x000000d7U; } static inline u32 gmmu_pte_kind_generic_16bx2_v(void) { - return 0x000000fe; + return 0x000000feU; } static inline u32 gmmu_pte_kind_c32_2c_v(void) { - return 0x000000d8; + return 0x000000d8U; } static inline u32 gmmu_pte_kind_c32_2cbr_v(void) { - return 0x000000d9; + return 0x000000d9U; } static inline u32 gmmu_pte_kind_c32_2cba_v(void) { - return 0x000000da; + return 0x000000daU; } static inline u32 gmmu_pte_kind_c32_2cra_v(void) { - return 0x000000db; + return 0x000000dbU; } static inline u32 gmmu_pte_kind_c32_2bra_v(void) { - return 0x000000dc; + return 0x000000dcU; } static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) { - return 0x000000dd; + return 0x000000ddU; } static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) { - return 0x000000de; + return 0x000000deU; } static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) { - return 0x000000cc; + return 0x000000ccU; } static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) { - return 0x000000df; + return 0x000000dfU; } static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) { - return 0x000000e0; + return 0x000000e0U; } static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) { - return 0x000000e1; + return 0x000000e1U; } static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) { - return 0x000000e2; + return 0x000000e2U; } static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) { - return 0x000000e3; + return 0x000000e3U; } static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) { - return 0x0000002c; + return 0x0000002cU; } static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) { - return 0x000000e4; + return 0x000000e4U; } static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) { - return 0x000000e5; + return 0x000000e5U; } static inline u32 gmmu_pte_kind_c64_2c_v(void) { - return 0x000000e6; + return 0x000000e6U; } static inline u32 gmmu_pte_kind_c64_2cbr_v(void) { - return 0x000000e7; + return 0x000000e7U; } static inline u32 gmmu_pte_kind_c64_2cba_v(void) { - return 0x000000e8; + return 0x000000e8U; } static inline u32 gmmu_pte_kind_c64_2cra_v(void) { - return 0x000000e9; + return 0x000000e9U; } static inline u32 gmmu_pte_kind_c64_2bra_v(void) { - return 0x000000ea; + return 0x000000eaU; } static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) { - return 0x000000eb; + return 0x000000ebU; } static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) { - return 0x000000ec; + return 0x000000ecU; } static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) { - return 0x000000cd; + return 0x000000cdU; } static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) { - return 0x000000ed; + return 0x000000edU; } static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) { - return 0x000000ee; + return 0x000000eeU; } static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) { - return 0x000000ef; + return 0x000000efU; } static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) { - return 0x000000f0; + return 0x000000f0U; } static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) { - return 0x000000f1; + return 0x000000f1U; } static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) { - return 0x0000002d; + return 0x0000002dU; } static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) { - return 0x000000f2; + return 0x000000f2U; } static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) { - return 0x000000f3; + return 0x000000f3U; } static inline u32 gmmu_pte_kind_c128_2c_v(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 gmmu_pte_kind_c128_2cr_v(void) { - return 0x000000f5; + return 0x000000f5U; } static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) { - return 0x000000f6; + return 0x000000f6U; } static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) { - return 0x000000f7; + return 0x000000f7U; } static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) { - return 0x000000f9; + return 0x000000f9U; } static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) { - return 0x000000fa; + return 0x000000faU; } static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) { - return 0x000000fb; + return 0x000000fbU; } static inline u32 gmmu_pte_kind_x8c24_v(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) { - return 0x000000fd; + return 0x000000fdU; } static inline u32 gmmu_pte_kind_smsked_message_v(void) { - return 0x000000ca; + return 0x000000caU; } static inline u32 gmmu_pte_kind_smhost_message_v(void) { - return 0x000000cb; + return 0x000000cbU; } static inline u32 gmmu_pte_kind_s8_v(void) { - return 0x0000002a; + return 0x0000002aU; } static inline u32 gmmu_pte_kind_s8_2s_v(void) { - return 0x0000002b; + return 0x0000002bU; } static inline u32 gmmu_fault_client_type_gpc_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gmmu_fault_client_type_hub_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_type_unbound_inst_block_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) { - return 0x0000001f; + return 0x0000001fU; } static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) { - return 0x0000000f; + return 0x0000000fU; } static inline u32 gmmu_fault_buf_size_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r) { - return (r >> 8) & 0x3; + return (r >> 8U) & 0x3U; } static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void) { - return 0; + return 0U; } static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) { - return 0; + return 0U; } static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gmmu_fault_buf_entry_inst_hi_w(void) { - return 1; + return 1U; } static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void) { - return 2; + return 2U; } static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) { - return 2; + return 2U; } static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gmmu_fault_buf_entry_addr_hi_w(void) { - return 3; + return 3U; } static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void) { - return 4; + return 4U; } static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void) { - return 5; + return 5U; } static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 gmmu_fault_buf_entry_engine_id_w(void) { - return 6; + return 6U; } static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gmmu_fault_buf_entry_fault_type_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r) { - return (r >> 7) & 0x1; + return (r >> 7U) & 0x1U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void) { - return 0x80; + return 0x80U; } static inline u32 gmmu_fault_buf_entry_client_v(u32 r) { - return (r >> 8) & 0x7f; + return (r >> 8U) & 0x7fU; } static inline u32 gmmu_fault_buf_entry_client_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r) { - return (r >> 16) & 0xf; + return (r >> 16U) & 0xfU; } static inline u32 gmmu_fault_buf_entry_access_type_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r) { - return (r >> 24) & 0x1f; + return (r >> 24U) & 0x1fU; } static inline u32 gmmu_fault_buf_entry_gpc_id_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 gmmu_fault_buf_entry_protected_mode_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gmmu_fault_buf_entry_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gmmu_fault_buf_entry_valid_w(void) { - return 7; + return 7U; } static inline u32 gmmu_fault_buf_entry_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_buf_entry_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 1af014f6..3bdf2de2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -58,4858 +58,4858 @@ static inline u32 gr_intr_r(void) { - return 0x00400100; + return 0x00400100U; } static inline u32 gr_intr_notify_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_intr_notify_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_intr_semaphore_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_semaphore_reset_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_illegal_method_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_intr_illegal_method_reset_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_intr_illegal_notify_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_intr_illegal_notify_reset_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_intr_firmware_method_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 gr_intr_firmware_method_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_intr_firmware_method_reset_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_intr_illegal_class_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_intr_illegal_class_reset_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_intr_fecs_error_pending_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_intr_fecs_error_reset_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_intr_class_error_pending_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_intr_class_error_reset_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_intr_exception_pending_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_intr_exception_reset_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_fecs_intr_r(void) { - return 0x00400144; + return 0x00400144U; } static inline u32 gr_class_error_r(void) { - return 0x00400110; + return 0x00400110U; } static inline u32 gr_class_error_code_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_intr_nonstall_r(void) { - return 0x00400120; + return 0x00400120U; } static inline u32 gr_intr_nonstall_trap_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_en_r(void) { - return 0x0040013c; + return 0x0040013cU; } static inline u32 gr_exception_r(void) { - return 0x00400108; + return 0x00400108U; } static inline u32 gr_exception_fe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_exception_gpc_m(void) { - return 0x1 << 24; + return 0x1U << 24U; } static inline u32 gr_exception_memfmt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_exception_ds_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_exception_sked_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_exception1_r(void) { - return 0x00400118; + return 0x00400118U; } static inline u32 gr_exception1_gpc_0_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_exception2_r(void) { - return 0x0040011c; + return 0x0040011cU; } static inline u32 gr_exception_en_r(void) { - return 0x00400138; + return 0x00400138U; } static inline u32 gr_exception_en_fe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_exception_en_fe_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_exception_en_gpc_m(void) { - return 0x1 << 24; + return 0x1U << 24U; } static inline u32 gr_exception_en_gpc_enabled_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 gr_exception_en_memfmt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_exception_en_memfmt_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_exception_en_ds_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_exception_en_ds_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_exception1_en_r(void) { - return 0x00400130; + return 0x00400130U; } static inline u32 gr_exception2_en_r(void) { - return 0x00400134; + return 0x00400134U; } static inline u32 gr_gpfifo_ctl_r(void) { - return 0x00400500; + return 0x00400500U; } static inline u32 gr_gpfifo_ctl_access_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpfifo_ctl_access_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpfifo_ctl_access_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_gpfifo_status_r(void) { - return 0x00400504; + return 0x00400504U; } static inline u32 gr_trapped_addr_r(void) { - return 0x00400704; + return 0x00400704U; } static inline u32 gr_trapped_addr_mthd_v(u32 r) { - return (r >> 2) & 0xfff; + return (r >> 2U) & 0xfffU; } static inline u32 gr_trapped_addr_subch_v(u32 r) { - return (r >> 16) & 0x7; + return (r >> 16U) & 0x7U; } static inline u32 gr_trapped_data_lo_r(void) { - return 0x00400708; + return 0x00400708U; } static inline u32 gr_trapped_data_hi_r(void) { - return 0x0040070c; + return 0x0040070cU; } static inline u32 gr_status_r(void) { - return 0x00400700; + return 0x00400700U; } static inline u32 gr_status_fe_method_upper_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_status_fe_method_lower_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 gr_status_fe_method_lower_idle_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_status_fe_gi_v(u32 r) { - return (r >> 21) & 0x1; + return (r >> 21U) & 0x1U; } static inline u32 gr_status_mask_r(void) { - return 0x00400610; + return 0x00400610U; } static inline u32 gr_status_1_r(void) { - return 0x00400604; + return 0x00400604U; } static inline u32 gr_status_2_r(void) { - return 0x00400608; + return 0x00400608U; } static inline u32 gr_engine_status_r(void) { - return 0x0040060c; + return 0x0040060cU; } static inline u32 gr_engine_status_value_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_pri_be0_becs_be_exception_r(void) { - return 0x00410204; + return 0x00410204U; } static inline u32 gr_pri_be0_becs_be_exception_en_r(void) { - return 0x00410208; + return 0x00410208U; } static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) { - return 0x00502c90; + return 0x00502c90U; } static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) { - return 0x00502c94; + return 0x00502c94U; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) { - return 0x00504508; + return 0x00504508U; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { - return 0x0050450c; + return 0x0050450cU; } static inline u32 gr_activity_0_r(void) { - return 0x00400380; + return 0x00400380U; } static inline u32 gr_activity_1_r(void) { - return 0x00400384; + return 0x00400384U; } static inline u32 gr_activity_2_r(void) { - return 0x00400388; + return 0x00400388U; } static inline u32 gr_activity_4_r(void) { - return 0x00400390; + return 0x00400390U; } static inline u32 gr_activity_4_gpc0_s(void) { - return 3; + return 3U; } static inline u32 gr_activity_4_gpc0_f(u32 v) { - return (v & 0x7) << 0; + return (v & 0x7U) << 0U; } static inline u32 gr_activity_4_gpc0_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 gr_activity_4_gpc0_v(u32 r) { - return (r >> 0) & 0x7; + return (r >> 0U) & 0x7U; } static inline u32 gr_activity_4_gpc0_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_activity_4_gpc0_preempted_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_pri_gpc0_gcc_dbg_r(void) { - return 0x00501000; + return 0x00501000U; } static inline u32 gr_pri_gpcs_gcc_dbg_r(void) { - return 0x00419000; + return 0x00419000U; } static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) { - return 0x0050433c; + return 0x0050433cU; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) { - return 0x00419b3c; + return 0x00419b3cU; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_sked_activity_r(void) { - return 0x00407054; + return 0x00407054U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) { - return 0x00502c80; + return 0x00502c80U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) { - return 0x00502c84; + return 0x00502c84U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) { - return 0x00502c88; + return 0x00502c88U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) { - return 0x00502c8c; + return 0x00502c8cU; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) { - return 0x00504500; + return 0x00504500U; } static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) { - return 0x00504d00; + return 0x00504d00U; } static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) { - return 0x00501d00; + return 0x00501d00U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) { - return 0x0041ac80; + return 0x0041ac80U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) { - return 0x0041ac84; + return 0x0041ac84U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) { - return 0x0041ac88; + return 0x0041ac88U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) { - return 0x0041ac8c; + return 0x0041ac8cU; } static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) { - return 0x0041c500; + return 0x0041c500U; } static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) { - return 0x0041cd00; + return 0x0041cd00U; } static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) { - return 0x00419d00; + return 0x00419d00U; } static inline u32 gr_pri_be0_becs_be_activity0_r(void) { - return 0x00410200; + return 0x00410200U; } static inline u32 gr_pri_be1_becs_be_activity0_r(void) { - return 0x00410600; + return 0x00410600U; } static inline u32 gr_pri_bes_becs_be_activity0_r(void) { - return 0x00408a00; + return 0x00408a00U; } static inline u32 gr_pri_ds_mpipe_status_r(void) { - return 0x00405858; + return 0x00405858U; } static inline u32 gr_pri_fe_go_idle_info_r(void) { - return 0x00404194; + return 0x00404194U; } static inline u32 gr_pri_fe_chip_def_info_r(void) { - return 0x00404030; + return 0x00404030U; } static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) { - return 0x00504238; + return 0x00504238U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { - return 0x00504358; + return 0x00504358U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) { - return 0x1 << 13; + return 0x1U << 13U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) { - return 0x1 << 14; + return 0x1U << 14U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 24) & 0x1; + return (r >> 24U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 26) & 0x1; + return (r >> 26U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) { - return 0x0050435c; + return 0x0050435cU; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) { - return 0x00504360; + return 0x00504360U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) { - return 0x0050436c; + return 0x0050436cU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) { - return 0x00504370; + return 0x00504370U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) { - return 0x00504374; + return 0x00504374U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void) { - return 0x0050464c; + return 0x0050464cU; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 18) & 0x1; + return (r >> 18U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void) { - return 0x00504650; + return 0x00504650U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void) { - return 0x00504654; + return 0x00504654U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) { - return 0x00504624; + return 0x00504624U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r(void) { - return 0x00504628; + return 0x00504628U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r(void) { - return 0x0050462c; + return 0x0050462cU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) { - return 0x00504638; + return 0x00504638U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 18) & 0x1; + return (r >> 18U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) { - return 0x0050463c; + return 0x0050463cU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) { - return 0x00504640; + return 0x00504640U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) { - return 0x005042c4; + return 0x005042c4U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) { - return 0x00504430; + return 0x00504430U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) { - return 0x00504434; + return 0x00504434U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_pri_be0_crop_status1_r(void) { - return 0x00410134; + return 0x00410134U; } static inline u32 gr_pri_bes_crop_status1_r(void) { - return 0x00408934; + return 0x00408934U; } static inline u32 gr_pri_be0_zrop_status_r(void) { - return 0x00410048; + return 0x00410048U; } static inline u32 gr_pri_be0_zrop_status2_r(void) { - return 0x0041004c; + return 0x0041004cU; } static inline u32 gr_pri_bes_zrop_status_r(void) { - return 0x00408848; + return 0x00408848U; } static inline u32 gr_pri_bes_zrop_status2_r(void) { - return 0x0040884c; + return 0x0040884cU; } static inline u32 gr_pipe_bundle_address_r(void) { - return 0x00400200; + return 0x00400200U; } static inline u32 gr_pipe_bundle_address_value_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pipe_bundle_address_veid_f(u32 v) { - return (v & 0x3f) << 20; + return (v & 0x3fU) << 20U; } static inline u32 gr_pipe_bundle_address_veid_w(void) { - return 0; + return 0U; } static inline u32 gr_pipe_bundle_data_r(void) { - return 0x00400204; + return 0x00400204U; } static inline u32 gr_pipe_bundle_config_r(void) { - return 0x00400208; + return 0x00400208U; } static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_fe_hww_esr_r(void) { - return 0x00404000; + return 0x00404000U; } static inline u32 gr_fe_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_fe_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) { - return 0x00419eac; + return 0x00419eacU; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) { - return 0x0050472c; + return 0x0050472cU; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) { - return 0x00419eb4; + return 0x00419eb4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) { - return 0x00504734; + return 0x00504734U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_fe_go_idle_timeout_r(void) { - return 0x00404154; + return 0x00404154U; } static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) { - return 0x1800; + return 0x1800U; } static inline u32 gr_fe_object_table_r(u32 i) { - return 0x00404200 + i*4; + return 0x00404200U + i*4U; } static inline u32 gr_fe_object_table_nvclass_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_fe_tpc_fs_r(u32 i) { - return 0x0040a200 + i*4; + return 0x0040a200U + i*4U; } static inline u32 gr_pri_mme_shadow_raw_index_r(void) { - return 0x00404488; + return 0x00404488U; } static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pri_mme_shadow_raw_data_r(void) { - return 0x0040448c; + return 0x0040448cU; } static inline u32 gr_mme_hww_esr_r(void) { - return 0x00404490; + return 0x00404490U; } static inline u32 gr_mme_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_mme_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_memfmt_hww_esr_r(void) { - return 0x00404600; + return 0x00404600U; } static inline u32 gr_memfmt_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_memfmt_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_fecs_cpuctl_r(void) { - return 0x00409100; + return 0x00409100U; } static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_cpuctl_alias_r(void) { - return 0x00409130; + return 0x00409130U; } static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_dmactl_r(void) { - return 0x0040910c; + return 0x0040910cU; } static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_fecs_os_r(void) { - return 0x00409080; + return 0x00409080U; } static inline u32 gr_fecs_idlestate_r(void) { - return 0x0040904c; + return 0x0040904cU; } static inline u32 gr_fecs_mailbox0_r(void) { - return 0x00409040; + return 0x00409040U; } static inline u32 gr_fecs_mailbox1_r(void) { - return 0x00409044; + return 0x00409044U; } static inline u32 gr_fecs_irqstat_r(void) { - return 0x00409008; + return 0x00409008U; } static inline u32 gr_fecs_irqmode_r(void) { - return 0x0040900c; + return 0x0040900cU; } static inline u32 gr_fecs_irqmask_r(void) { - return 0x00409018; + return 0x00409018U; } static inline u32 gr_fecs_irqdest_r(void) { - return 0x0040901c; + return 0x0040901cU; } static inline u32 gr_fecs_curctx_r(void) { - return 0x00409050; + return 0x00409050U; } static inline u32 gr_fecs_nxtctx_r(void) { - return 0x00409054; + return 0x00409054U; } static inline u32 gr_fecs_engctl_r(void) { - return 0x004090a4; + return 0x004090a4U; } static inline u32 gr_fecs_debug1_r(void) { - return 0x00409090; + return 0x00409090U; } static inline u32 gr_fecs_debuginfo_r(void) { - return 0x00409094; + return 0x00409094U; } static inline u32 gr_fecs_icd_cmd_r(void) { - return 0x00409200; + return 0x00409200U; } static inline u32 gr_fecs_icd_cmd_opc_s(void) { - return 4; + return 4U; } static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_fecs_icd_cmd_opc_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) { - return 0xe; + return 0xeU; } static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 gr_fecs_icd_rdata_r(void) { - return 0x0040920c; + return 0x0040920cU; } static inline u32 gr_fecs_imemc_r(u32 i) { - return 0x00409180 + i*16; + return 0x00409180U + i*16U; } static inline u32 gr_fecs_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_fecs_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_fecs_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_fecs_imemd_r(u32 i) { - return 0x00409184 + i*16; + return 0x00409184U + i*16U; } static inline u32 gr_fecs_imemt_r(u32 i) { - return 0x00409188 + i*16; + return 0x00409188U + i*16U; } static inline u32 gr_fecs_imemt_tag_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_dmemc_r(u32 i) { - return 0x004091c0 + i*8; + return 0x004091c0U + i*8U; } static inline u32 gr_fecs_dmemc_offs_s(void) { - return 6; + return 6U; } static inline u32 gr_fecs_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_fecs_dmemc_offs_m(void) { - return 0x3f << 2; + return 0x3fU << 2U; } static inline u32 gr_fecs_dmemc_offs_v(u32 r) { - return (r >> 2) & 0x3f; + return (r >> 2U) & 0x3fU; } static inline u32 gr_fecs_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_fecs_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_fecs_dmemd_r(u32 i) { - return 0x004091c4 + i*8; + return 0x004091c4U + i*8U; } static inline u32 gr_fecs_dmatrfbase_r(void) { - return 0x00409110; + return 0x00409110U; } static inline u32 gr_fecs_dmatrfmoffs_r(void) { - return 0x00409114; + return 0x00409114U; } static inline u32 gr_fecs_dmatrffboffs_r(void) { - return 0x0040911c; + return 0x0040911cU; } static inline u32 gr_fecs_dmatrfcmd_r(void) { - return 0x00409118; + return 0x00409118U; } static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 gr_fecs_bootvec_r(void) { - return 0x00409104; + return 0x00409104U; } static inline u32 gr_fecs_bootvec_vec_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_falcon_hwcfg_r(void) { - return 0x00409108; + return 0x00409108U; } static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) { - return 0x0041a108; + return 0x0041a108U; } static inline u32 gr_fecs_falcon_rm_r(void) { - return 0x00409084; + return 0x00409084U; } static inline u32 gr_fecs_current_ctx_r(void) { - return 0x00409b00; + return 0x00409b00U; } static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_current_ctx_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_current_ctx_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_current_ctx_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_current_ctx_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 gr_fecs_current_ctx_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_current_ctx_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_fecs_current_ctx_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_fecs_current_ctx_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_fecs_current_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_method_data_r(void) { - return 0x00409500; + return 0x00409500U; } static inline u32 gr_fecs_method_push_r(void) { - return 0x00409504; + return 0x00409504U; } static inline u32 gr_fecs_method_push_adr_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) { - return 0x3; + return 0x3U; } static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) { - return 0x00000015; + return 0x00000015U; } static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) { - return 0x00000016; + return 0x00000016U; } static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) { - return 0x00000025; + return 0x00000025U; } static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) { - return 0x00000031; + return 0x00000031U; } static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) { - return 0x00000032; + return 0x00000032U; } static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) { - return 0x00000038; + return 0x00000038U; } static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) { - return 0x00000039; + return 0x00000039U; } static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) { - return 0x21; + return 0x21U; } static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) { - return 0x0000001a; + return 0x0000001aU; } static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) { - return 0x0000003a; + return 0x0000003aU; } static inline u32 gr_fecs_host_int_status_r(void) { - return 0x00409c18; + return 0x00409c18U; } static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) { - return (v & 0x1) << 21; + return (v & 0x1U) << 21U; } static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) { - return 0x1 << 21; + return 0x1U << 21U; } static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) { - return 0x1 << 22; + return 0x1U << 22U; } static inline u32 gr_fecs_host_int_clear_r(void) { - return 0x00409c20; + return 0x00409c20U; } static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fecs_host_int_enable_r(void) { - return 0x00409c24; + return 0x00409c24U; } static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) { - return 0x00409614; + return 0x00409614U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) { - return 0x0040960c; + return 0x0040960cU; } static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) { - return 0x00409800 + i*4; + return 0x00409800U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) { - return 0x004098c0 + i*4; + return 0x004098c0U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) { - return 0x00409840 + i*4; + return 0x00409840U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_fs_r(void) { - return 0x00409604; + return 0x00409604U; } static inline u32 gr_fecs_fs_num_available_gpcs_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_fecs_fs_num_available_gpcs_m(void) { - return 0x1f << 0; + return 0x1fU << 0U; } static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_fecs_fs_num_available_fbps_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 gr_fecs_fs_num_available_fbps_m(void) { - return 0x1f << 16; + return 0x1fU << 16U; } static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } static inline u32 gr_fecs_cfg_r(void) { - return 0x00409620; + return 0x00409620U; } static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_fecs_rc_lanes_r(void) { - return 0x00409880; + return 0x00409880U; } static inline u32 gr_fecs_rc_lanes_num_chains_s(void) { - return 6; + return 6U; } static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_fecs_rc_lanes_num_chains_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_fecs_ctxsw_status_1_r(void) { - return 0x00409400; + return 0x00409400U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 gr_fecs_arb_ctx_adr_r(void) { - return 0x00409a24; + return 0x00409a24U; } static inline u32 gr_fecs_new_ctx_r(void) { - return 0x00409b04; + return 0x00409b04U; } static inline u32 gr_fecs_new_ctx_ptr_s(void) { - return 28; + return 28U; } static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_new_ctx_ptr_m(void) { - return 0xfffffff << 0; + return 0xfffffffU << 0U; } static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_new_ctx_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_new_ctx_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_new_ctx_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_new_ctx_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_new_ctx_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_new_ctx_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_fecs_new_ctx_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_fecs_new_ctx_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_fecs_arb_ctx_ptr_r(void) { - return 0x00409a0c; + return 0x00409a0cU; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) { - return 28; + return 28U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) { - return 0xfffffff << 0; + return 0xfffffffU << 0U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_arb_ctx_cmd_r(void) { - return 0x00409a10; + return 0x00409a10U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) { - return 0x1f << 0; + return 0x1fU << 0U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) { - return 0x00409c00; + return 0x00409c00U; } static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) { - return 0x00502c04; + return 0x00502c04U; } static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) { - return 0x00502400; + return 0x00502400U; } static inline u32 gr_fecs_ctxsw_idlestate_r(void) { - return 0x00409420; + return 0x00409420U; } static inline u32 gr_fecs_feature_override_ecc_r(void) { - return 0x00409658; + return 0x00409658U; } static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) { - return 0x00502420; + return 0x00502420U; } static inline u32 gr_rstr2d_gpc_map_r(u32 i) { - return 0x0040780c + i*4; + return 0x0040780cU + i*4U; } static inline u32 gr_rstr2d_map_table_cfg_r(void) { - return 0x004078bc; + return 0x004078bcU; } static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_pd_hww_esr_r(void) { - return 0x00406018; + return 0x00406018U; } static inline u32 gr_pd_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pd_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) { - return 0x00406028 + i*4; + return 0x00406028U + i*4U; } static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) { - return (v & 0xf) << 4; + return (v & 0xfU) << 4U; } static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) { - return (v & 0xf) << 12; + return (v & 0xfU) << 12U; } static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) { - return (v & 0xf) << 24; + return (v & 0xfU) << 24U; } static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) { - return (v & 0xf) << 28; + return (v & 0xfU) << 28U; } static inline u32 gr_pd_ab_dist_cfg0_r(void) { - return 0x004064c0; + return 0x004064c0U; } static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pd_ab_dist_cfg1_r(void) { - return 0x004064c4; + return 0x004064c4U; } static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) { - return 0xffff; + return 0xffffU; } static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 gr_pd_ab_dist_cfg2_r(void) { - return 0x004064c8; + return 0x004064c8U; } static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) { - return (v & 0x1fff) << 0; + return (v & 0x1fffU) << 0U; } static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) { - return 0x00000380; + return 0x00000380U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) { - return (v & 0x1fff) << 16; + return (v & 0x1fffU) << 16U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) { - return 0x00000302; + return 0x00000302U; } static inline u32 gr_pd_dist_skip_table_r(u32 i) { - return 0x004064d0 + i*4; + return 0x004064d0U + i*4U; } static inline u32 gr_pd_dist_skip_table__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gr_ds_debug_r(void) { - return 0x00405800; + return 0x00405800U; } static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 gr_ds_zbc_color_r_r(void) { - return 0x00405804; + return 0x00405804U; } static inline u32 gr_ds_zbc_color_r_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_g_r(void) { - return 0x00405808; + return 0x00405808U; } static inline u32 gr_ds_zbc_color_g_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_b_r(void) { - return 0x0040580c; + return 0x0040580cU; } static inline u32 gr_ds_zbc_color_b_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_a_r(void) { - return 0x00405810; + return 0x00405810U; } static inline u32 gr_ds_zbc_color_a_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_fmt_r(void) { - return 0x00405814; + return 0x00405814U; } static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) { - return (v & 0x7f) << 0; + return (v & 0x7fU) << 0U; } static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 gr_ds_zbc_z_r(void) { - return 0x00405818; + return 0x00405818U; } static inline u32 gr_ds_zbc_z_val_s(void) { - return 32; + return 32U; } static inline u32 gr_ds_zbc_z_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_z_val_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 gr_ds_zbc_z_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gr_ds_zbc_z_val__init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_ds_zbc_z_val__init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_z_fmt_r(void) { - return 0x0040581c; + return 0x0040581cU; } static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_zbc_tbl_index_r(void) { - return 0x00405820; + return 0x00405820U; } static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_ds_zbc_tbl_ld_r(void) { - return 0x00405824; + return 0x00405824U; } static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ds_tga_constraintlogic_beta_r(void) { - return 0x00405830; + return 0x00405830U; } static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) { - return 0x0040585c; + return 0x0040585cU; } static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_ds_hww_esr_r(void) { - return 0x00405840; + return 0x00405840U; } static inline u32 gr_ds_hww_esr_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_ds_hww_esr_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 gr_ds_hww_esr_reset_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_ds_hww_esr_reset_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 gr_ds_hww_esr_reset_task_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_hww_esr_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_ds_hww_esr_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_ds_hww_esr_2_r(void) { - return 0x00405848; + return 0x00405848U; } static inline u32 gr_ds_hww_esr_2_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 gr_ds_hww_esr_2_reset_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 gr_ds_hww_esr_2_reset_task_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_hww_esr_2_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_ds_hww_report_mask_r(void) { - return 0x00405844; + return 0x00405844U; } static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) { - return 0x80; + return 0x80U; } static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 gr_ds_hww_report_mask_2_r(void) { - return 0x0040584c; + return 0x0040584cU; } static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) { - return 0x00405870 + i*4; + return 0x00405870U + i*4U; } static inline u32 gr_scc_bundle_cb_base_r(void) { - return 0x00408004; + return 0x00408004U; } static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_scc_bundle_cb_size_r(void) { - return 0x00408008; + return 0x00408008U; } static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) { - return (v & 0x7ff) << 0; + return (v & 0x7ffU) << 0U; } static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_scc_pagepool_base_r(void) { - return 0x0040800c; + return 0x0040800cU; } static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_scc_pagepool_r(void) { - return 0x00408010; + return 0x00408010U; } static inline u32 gr_scc_pagepool_total_pages_f(u32 v) { - return (v & 0x3ff) << 0; + return (v & 0x3ffU) << 0U; } static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_scc_pagepool_max_valid_pages_s(void) { - return 10; + return 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) { - return (v & 0x3ff) << 10; + return (v & 0x3ffU) << 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_m(void) { - return 0x3ff << 10; + return 0x3ffU << 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) { - return (r >> 10) & 0x3ff; + return (r >> 10U) & 0x3ffU; } static inline u32 gr_scc_pagepool_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_scc_init_r(void) { - return 0x0040802c; + return 0x0040802cU; } static inline u32 gr_scc_init_ram_trigger_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_scc_hww_esr_r(void) { - return 0x00408030; + return 0x00408030U; } static inline u32 gr_scc_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_scc_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_sked_hww_esr_r(void) { - return 0x00407020; + return 0x00407020U; } static inline u32 gr_sked_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_sked_hww_esr_en_r(void) { - return 0x00407024; + return 0x00407024U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) { - return 0x1 << 25; + return 0x1U << 25U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 gr_cwd_fs_r(void) { - return 0x00405b00; + return 0x00405b00U; } static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) { - return 0x00405b60 + i*4; + return 0x00405b60U + i*4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) { - return 4; + return 4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) { - return 4; + return 4U; } static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) { - return (v & 0xf) << 4; + return (v & 0xfU) << 4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_cwd_sm_id_r(u32 i) { - return 0x00405ba0 + i*4; + return 0x00405ba0U + i*4U; } static inline u32 gr_cwd_sm_id__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpc0_fs_gpc_r(void) { - return 0x00502608; + return 0x00502608U; } static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } static inline u32 gr_gpc0_cfg_r(void) { - return 0x00502620; + return 0x00502620U; } static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpccs_rc_lanes_r(void) { - return 0x00502880; + return 0x00502880U; } static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_gpccs_rc_lane_size_r(void) { - return 0x00502910; + return 0x00502910U; } static inline u32 gr_gpccs_rc_lane_size_v_s(void) { - return 24; + return 24U; } static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_gpccs_rc_lane_size_v_m(void) { - return 0xffffff << 0; + return 0xffffffU << 0U; } static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_zcull_fs_r(void) { - return 0x00500910; + return 0x00500910U; } static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x1ffU) << 0U; } static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 gr_gpc0_zcull_ram_addr_r(void) { - return 0x00500914; + return 0x00500914U; } static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) { - return 0x00500918; + return 0x00500918U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) { - return 0x00800000; + return 0x00800000U; } static inline u32 gr_gpc0_zcull_total_ram_size_r(void) { - return 0x00500920; + return 0x00500920U; } static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) { - return 0x00500a04 + i*32; + return 0x00500a04U + i*32U; } static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) { - return 0x00500c10 + i*4; + return 0x00500c10U + i*4U; } static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) { - return 0x00500c30 + i*4; + return 0x00500c30U + i*4U; } static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) { - return 0x00504088; + return 0x00504088U; } static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) { - return 0x00504608; + return 0x00504608U; } static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_tpc0_sm_arch_r(void) { - return 0x00504330; + return 0x00504330U; } static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) { - return (r >> 8) & 0xfff; + return (r >> 8U) & 0xfffU; } static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) { - return (r >> 20) & 0xfff; + return (r >> 20U) & 0xfffU; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) { - return 0x00503018; + return 0x00503018U; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) { - return 0x005030c0; + return 0x005030c0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) { - return 0x3fffff << 0; + return 0x3fffffU << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) { - return 0x00001100; + return 0x00001100U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) { - return 0x005030f4; + return 0x005030f4U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) { - return 0x005030e4; + return 0x005030e4U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) { - return 0x005030f8; + return 0x005030f8U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) { - return 0x005030f0; + return 0x005030f0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) { - return 0x00419e00; + return 0x00419e00U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) { - return 0x00419e04; + return 0x00419e04U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) { - return 21; + return 21U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) { - return (v & 0x1fffff) << 0; + return (v & 0x1fffffU) << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) { - return 0x1fffff << 0; + return 0x1fffffU << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) { - return (r >> 0) & 0x1fffff; + return (r >> 0U) & 0x1fffffU; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) { - return 0x80; + return 0x80U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpccs_falcon_addr_r(void) { - return 0x0041a0ac; + return 0x0041a0acU; } static inline u32 gr_gpccs_falcon_addr_lsb_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_gpccs_falcon_addr_lsb_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpccs_falcon_addr_msb_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) { - return (v & 0x3f) << 6; + return (v & 0x3fU) << 6U; } static inline u32 gr_gpccs_falcon_addr_msb_m(void) { - return 0x3f << 6; + return 0x3fU << 6U; } static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) { - return (r >> 6) & 0x3f; + return (r >> 6U) & 0x3fU; } static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpccs_falcon_addr_ext_s(void) { - return 12; + return 12U; } static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpccs_falcon_addr_ext_m(void) { - return 0xfff << 0; + return 0xfffU << 0U; } static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 gr_gpccs_cpuctl_r(void) { - return 0x0041a100; + return 0x0041a100U; } static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpccs_dmactl_r(void) { - return 0x0041a10c; + return 0x0041a10cU; } static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpccs_imemc_r(u32 i) { - return 0x0041a180 + i*16; + return 0x0041a180U + i*16U; } static inline u32 gr_gpccs_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_gpccs_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpccs_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_gpccs_imemd_r(u32 i) { - return 0x0041a184 + i*16; + return 0x0041a184U + i*16U; } static inline u32 gr_gpccs_imemt_r(u32 i) { - return 0x0041a188 + i*16; + return 0x0041a188U + i*16U; } static inline u32 gr_gpccs_imemt__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_gpccs_imemt_tag_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpccs_dmemc_r(u32 i) { - return 0x0041a1c0 + i*8; + return 0x0041a1c0U + i*8U; } static inline u32 gr_gpccs_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_gpccs_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_gpccs_dmemd_r(u32 i) { - return 0x0041a1c4 + i*8; + return 0x0041a1c4U + i*8U; } static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) { - return 0x0041a800 + i*4; + return 0x0041a800U + i*4U; } static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) { - return 0x00418e24; + return 0x00418e24U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) { - return 32; + return 32U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) { - return 0x00418e28; + return 0x00418e28U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) { - return 11; + return 11U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) { - return (v & 0x7ff) << 0; + return (v & 0x7ffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) { - return 0x7ff << 0; + return 0x7ffU << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) { - return (r >> 0) & 0x7ff; + return (r >> 0U) & 0x7ffU; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) { - return 0x30; + return 0x30U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) { - return 0x005001dc; + return 0x005001dcU; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) { - return 0x00000170; + return 0x00000170U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) { - return 0x005001d8; + return 0x005001d8U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) { - return 0x004181e4; + return 0x004181e4U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) { - return 0x0041befc; + return 0x0041befcU; } static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) { - return 0x00418ea0 + i*4; + return 0x00418ea0U + i*4U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) { - return 0x3fffff << 0; + return 0x3fffffU << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) { - return 0x00418010 + i*4; + return 0x00418010U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) { - return 0x0041804c + i*4; + return 0x0041804cU + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) { - return 0x00418088 + i*4; + return 0x00418088U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) { - return 0x004180c4 + i*4; + return 0x004180c4U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) { - return 0x00418100; + return 0x00418100U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) { - return 0x00418110 + i*4; + return 0x00418110U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) { - return 0x0041814c; + return 0x0041814cU; } static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) { - return 0x0041815c + i*4; + return 0x0041815cU + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) { - return 0x00418198; + return 0x00418198U; } static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) { - return 0x00418810; + return 0x00418810U; } static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_crstr_gpc_map_r(u32 i) { - return 0x00418b08 + i*4; + return 0x00418b08U + i*4U; } static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) { - return (v & 0x1f) << 5; + return (v & 0x1fU) << 5U; } static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) { - return (v & 0x1f) << 10; + return (v & 0x1fU) << 10U; } static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) { - return (v & 0x1f) << 15; + return (v & 0x1fU) << 15U; } static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) { - return (v & 0x1f) << 20; + return (v & 0x1fU) << 20U; } static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) { - return (v & 0x1f) << 25; + return (v & 0x1fU) << 25U; } static inline u32 gr_crstr_map_table_cfg_r(void) { - return 0x00418bb8; + return 0x00418bb8U; } static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) { - return 0x00418980 + i*4; + return 0x00418980U + i*4U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) { - return (v & 0x7) << 0; + return (v & 0x7U) << 0U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) { - return (v & 0x7) << 4; + return (v & 0x7U) << 4U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) { - return (v & 0x7) << 16; + return (v & 0x7U) << 16U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) { - return (v & 0x7) << 20; + return (v & 0x7U) << 20U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) { - return (v & 0x7) << 24; + return (v & 0x7U) << 24U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) { - return (v & 0x7) << 28; + return (v & 0x7U) << 28U; } static inline u32 gr_gpcs_gpm_pd_cfg_r(void) { - return 0x00418c6c; + return 0x00418c6cU; } static inline u32 gr_gpcs_gcc_pagepool_base_r(void) { - return 0x00419004; + return 0x00419004U; } static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_gcc_pagepool_r(void) { - return 0x00419008; + return 0x00419008U; } static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) { - return (v & 0x3ff) << 0; + return (v & 0x3ffU) << 0U; } static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) { - return 0x0041980c; + return 0x0041980cU; } static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) { - return 0x00419848; + return 0x00419848U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) { - return 0x00419c00; + return 0x00419c00U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) { - return 0x00419c2c; + return 0x00419c2cU; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) { - return 0x00419ea8; + return 0x00419ea8U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) { - return 0x00504728; + return 0x00504728U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) { - return 0x00419d0c; + return 0x00419d0cU; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { - return 0x0050450c; + return 0x0050450cU; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) { - return 0x0041ac94; + return 0x0041ac94U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v) { - return (v & 0x1) << 15; + return (v & 0x1U) << 15U; } static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { - return 0x00502c90; + return 0x00502c90U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) { - return 0x1 << 14; + return 0x1U << 14U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_f(u32 v) { - return (v & 0x1) << 15; + return (v & 0x1U) << 15U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) { - return 0x00501048; + return 0x00501048U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r(void) { - return 0x0050104c; + return 0x0050104cU; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r(void) { - return 0x00501054; + return 0x00501054U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { - return 0x00504508; + return 0x00504508U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) { - return 0x00504704; + return 0x00504704U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) { - return 0x00504708; + return 0x00504708U; } static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) { - return 0x0050470c; + return 0x0050470cU; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) { - return 0x00504710; + return 0x00504710U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) { - return 0x00504714; + return 0x00504714U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) { - return 0x00504718; + return 0x00504718U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) { - return 0x0050471c; + return 0x0050471cU; } static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) { - return 0x00419e90; + return 0x00419e90U; } static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) { - return 0x00419e94; + return 0x00419e94U; } static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) { - return 0x00419e80; + return 0x00419e80U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) { - return 0x00504700; + return 0x00504700U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) { - return 0x00504730; + return 0x00504730U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) { - return 0xff << 16; + return 0xffU << 16U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) { - return 0xf << 24; + return 0xfU << 24U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) { - return 0x0050460c; + return 0x0050460cU; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) { - return 0x00504738; + return 0x00504738U; } static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) { - return 0x005043a0; + return 0x005043a0U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) { - return 0x00419ba0; + return 0x00419ba0U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) { - return 0x005043b0; + return 0x005043b0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) { - return 0x00419bb0; + return 0x00419bb0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) { - return 0x0041be08; + return 0x0041be08U; } static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) { - return 0x0041bf00 + i*4; + return 0x0041bf00U + i*4U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) { - return 0x0041bfd0; + return 0x0041bfd0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) { - return (v & 0x7) << 21; + return (v & 0x7U) << 21U; } static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) { - return 0x0041bfd4; + return 0x0041bfd4U; } static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) { - return 0x0041bfb0 + i*4; + return 0x0041bfb0U + i*4U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gr_bes_zrop_settings_r(void) { - return 0x00408850; + return 0x00408850U; } static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_be0_crop_debug3_r(void) { - return 0x00410108; + return 0x00410108U; } static inline u32 gr_bes_crop_debug3_r(void) { - return 0x00408908; + return 0x00408908U; } static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_bes_crop_settings_r(void) { - return 0x00408958; + return 0x00408958U; } static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 gr_zcull_subregion_qty_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) { - return 0x00419a00; + return 0x00419a00U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) { - return 0x1 << 19; + return 0x1U << 19U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) { - return 0x00419bf0; + return 0x00419bf0U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) { - return 0x00584200; + return 0x00584200U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void) { - return 0x00584204; + return 0x00584204U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void) { - return 0x00584208; + return 0x00584208U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void) { - return 0x00584210; + return 0x00584210U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void) { - return 0x00584214; + return 0x00584214U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void) { - return 0x00584218; + return 0x00584218U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void) { - return 0x0058421c; + return 0x0058421cU; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void) { - return 0x0058420c; + return 0x0058420cU; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void) { - return 0x00584220; + return 0x00584220U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void) { - return 0x00584224; + return 0x00584224U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void) { - return 0x00584228; + return 0x00584228U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void) { - return 0x0058422c; + return 0x0058422cU; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void) { - return 0x00584230; + return 0x00584230U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void) { - return 0x00584234; + return 0x00584234U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void) { - return 0x00584238; + return 0x00584238U; } static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void) { - return 0x0058423c; + return 0x0058423cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void) { - return 0x00584600; + return 0x00584600U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void) { - return 0x00584604; + return 0x00584604U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void) { - return 0x00584624; + return 0x00584624U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void) { - return 0x00584628; + return 0x00584628U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void) { - return 0x0058462c; + return 0x0058462cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void) { - return 0x00584630; + return 0x00584630U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void) { - return 0x00584634; + return 0x00584634U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void) { - return 0x00584638; + return 0x00584638U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void) { - return 0x0058463c; + return 0x0058463cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void) { - return 0x00584640; + return 0x00584640U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void) { - return 0x00584644; + return 0x00584644U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void) { - return 0x00584648; + return 0x00584648U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void) { - return 0x0058464c; + return 0x0058464cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void) { - return 0x00584650; + return 0x00584650U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void) { - return 0x00584654; + return 0x00584654U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void) { - return 0x00584658; + return 0x00584658U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void) { - return 0x0058465c; + return 0x0058465cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void) { - return 0x00584660; + return 0x00584660U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void) { - return 0x00584614; + return 0x00584614U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void) { - return 0x00584618; + return 0x00584618U; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void) { - return 0x0058461c; + return 0x0058461cU; } static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void) { - return 0x00584620; + return 0x00584620U; } static inline u32 gr_fe_pwr_mode_r(void) { - return 0x00404170; + return 0x00404170U; } static inline u32 gr_fe_pwr_mode_mode_auto_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fe_pwr_mode_req_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 gr_fe_pwr_mode_req_send_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_fe_pwr_mode_req_done_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) { - return 0x00418880; + return 0x00418880U; } static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) { - return 0x3 << 3; + return 0x3U << 3U; } static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) { - return 0x3 << 5; + return 0x3U << 5U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) { - return 0x00418890; + return 0x00418890U; } static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) { - return 0x00418894; + return 0x00418894U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) { - return 0x004188b0; + return 0x004188b0U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) { - return 0x004188b4; + return 0x004188b4U; } static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) { - return 0x004188b8; + return 0x004188b8U; } static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) { - return 0x004188ac; + return 0x004188acU; } static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) { - return 0x00419e84; + return 0x00419e84U; } static inline u32 gr_fe_gfxp_wfi_timeout_r(void) { - return 0x004041c0; + return 0x004041c0U; } static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) { - return 0x00419bd8; + return 0x00419bd8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) { - return 0x7 << 8; + return 0x7U << 8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) { - return 0x00419ba4; + return 0x00419ba4U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) { - return 0x3 << 11; + return 0x3U << 11U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 gr_gpcs_tc_debug0_r(void) { - return 0x00418708; + return 0x00418708U; } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x1ffU) << 0U; } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { - return 0x1ff << 0; + return 0x1ffU << 0U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_r(void) { - return 0x00500324; + return 0x00500324U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_r(void) { - return 0x00500314; + return 0x00500314U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 18; + return 0x1U << 18U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1 << 19; + return 0x1U << 19U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1 << 17; + return 0x1U << 17U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_r(void) { - return 0x00500320; + return 0x00500320U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_index_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r(void) { - return 0x00500318; + return 0x00500318U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r(void) { - return 0x0050031c; + return 0x0050031cU; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 gr_gpc0_gpccs_hww_esr_r(void) { - return 0x00502c98; + return 0x00502c98U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void) { - return 0x00502678; + return 0x00502678U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void) { - return 0x00502684; + return 0x00502684U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v) { - return (v & 0x7fffff) << 0; + return (v & 0x7fffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void) { - return 20; + return 20U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) { - return 0xfffff << 0; + return 0xfffffU << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void) { - return 0x0050267c; + return 0x0050267cU; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void) { - return 0x00502680; + return 0x00502680U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 gr_fecs_falcon_ecc_status_r(void) { - return 0x00409678; + return 0x00409678U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_fecs_falcon_ecc_address_r(void) { - return 0x00409684; + return 0x00409684U; } static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v) { - return (v & 0x7fffff) << 0; + return (v & 0x7fffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void) { - return 20; + return 20U; } static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) { - return 0xfffff << 0; + return 0xfffffU << 0U; } static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void) { - return 0x0040967c; + return 0x0040967cU; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void) { - return 0x00409680; + return 0x00409680U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index e1b0f47a..769bcf0c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -58,746 +58,746 @@ static inline u32 ltc_pltcg_base_v(void) { - return 0x00140000; + return 0x00140000U; } static inline u32 ltc_pltcg_extent_v(void) { - return 0x0017ffff; + return 0x0017ffffU; } static inline u32 ltc_ltc0_ltss_v(void) { - return 0x00140200; + return 0x00140200U; } static inline u32 ltc_ltc0_lts0_v(void) { - return 0x00140400; + return 0x00140400U; } static inline u32 ltc_ltcs_ltss_v(void) { - return 0x0017e200; + return 0x0017e200U; } static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) { - return 0x0014046c; + return 0x0014046cU; } static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) { - return 0x00140518; + return 0x00140518U; } static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) { - return 0x0017e318; + return 0x0017e318U; } static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) { - return 0x00140494; + return 0x00140494U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) { - return (r >> 16) & 0x3; + return (r >> 16U) & 0x3U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) { - return 0x0017e26c; + return 0x0017e26cU; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) { - return 0x2; + return 0x2U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) { - return 0x4; + return 0x4U; } static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) { - return 0x0014046c; + return 0x0014046cU; } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) { - return 0x0017e270; + return 0x0017e270U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x3ffffU) << 0U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) { - return 0x0017e274; + return 0x0017e274U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x3ffffU) << 0U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) { - return 0x0003ffff; + return 0x0003ffffU; } static inline u32 ltc_ltcs_ltss_cbc_base_r(void) { - return 0x0017e278; + return 0x0017e278U; } static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) { - return (r >> 0) & 0x3ffffff; + return (r >> 0U) & 0x3ffffffU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) { - return 0x0017e27c; + return 0x0017e27cU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) { - return (r >> 24) & 0x1; + return (r >> 24U) & 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) { - return (r >> 25) & 0x1; + return (r >> 25U) & 0x1U; } static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) { - return 0x0017e000; + return 0x0017e000U; } static inline u32 ltc_ltcs_ltss_cbc_param_r(void) { - return 0x0017e280; + return 0x0017e280U; } static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) { - return (r >> 24) & 0xf; + return (r >> 24U) & 0xfU; } static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) { - return (r >> 28) & 0xf; + return (r >> 28U) & 0xfU; } static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) { - return 0x0017e3f4; + return 0x0017e3f4U; } static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) { - return 0x0017e2ac; + return 0x0017e2acU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) { - return 0x0017e338; + return 0x0017e338U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) { - return 0x0017e33c + i*4; + return 0x0017e33cU + i*4U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) { - return 0x0017e34c; + return 0x0017e34cU; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) { - return 32; + return 32U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) { - return 0x0017e204; + return 0x0017e204U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) { - return 8; + return 8U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) { - return 0x0017e2b0; + return 0x0017e2b0U; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_g_elpg_r(void) { - return 0x0017e214; + return 0x0017e214U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_ltss_g_elpg_r(void) { - return 0x00140214; + return 0x00140214U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_g_elpg_r(void) { - return 0x00142214; + return 0x00142214U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_intr_r(void) { - return 0x0017e20c; + return 0x0017e20cU; } static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 ltc_ltc0_lts0_intr_r(void) { - return 0x0014040c; + return 0x0014040cU; } static inline u32 ltc_ltcs_ltss_intr3_r(void) { - return 0x0017e388; + return 0x0017e388U; } static inline u32 ltc_ltcs_ltss_intr3_ecc_corrected_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 ltc_ltcs_ltss_intr3_ecc_uncorrected_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 ltc_ltc0_lts0_intr3_r(void) { - return 0x00140588; + return 0x00140588U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_r(void) { - return 0x001404f0; + return 0x001404f0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(void) { - return 0x1 << 18; + return 0x1U << 18U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m(void) { - return 0x1 << 19; + return 0x1U << 19U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m(void) { - return 0x1 << 17; + return 0x1U << 17U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_address_r(void) { - return 0x001404fc; + return 0x001404fcU; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(void) { - return 0x001404f4; + return 0x001404f4U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(void) { - return 0x001404f8; + return 0x001404f8U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_s(void) { - return 16; + return 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m(void) { - return 0xffff << 16; + return 0xffffU << 16U; } static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) { - return 0x0014051c; + return 0x0014051cU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) { - return 0xff << 16; + return 0xffU << 16U; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) { - return 0x0017e2a0; + return 0x0017e2a0U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) { - return (r >> 8) & 0xf; + return (r >> 8U) & 0xfU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) { - return 0x300; + return 0x300U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) { - return 0x0017e2a4; + return 0x0017e2a4U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) { - return (r >> 8) & 0xf; + return (r >> 8U) & 0xfU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) { - return 0x300; + return 0x300U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) { - return 0x001402a0; + return 0x001402a0U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) { - return 0x001402a4; + return 0x001402a4U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) { - return 0x001422a0; + return 0x001422a0U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) { - return 0x001422a4; + return 0x001422a4U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) { - return 0x0014058c; + return 0x0014058cU; } static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index 7228cd8b..bff73076 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h @@ -58,194 +58,194 @@ static inline u32 mc_boot_0_r(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 mc_boot_0_architecture_v(u32 r) { - return (r >> 24) & 0x1f; + return (r >> 24U) & 0x1fU; } static inline u32 mc_boot_0_implementation_v(u32 r) { - return (r >> 20) & 0xf; + return (r >> 20U) & 0xfU; } static inline u32 mc_boot_0_major_revision_v(u32 r) { - return (r >> 4) & 0xf; + return (r >> 4U) & 0xfU; } static inline u32 mc_boot_0_minor_revision_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 mc_intr_r(u32 i) { - return 0x00000100 + i*4; + return 0x00000100U + i*4U; } static inline u32 mc_intr_pfifo_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 mc_intr_hub_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 mc_intr_pgraph_pending_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 mc_intr_pmu_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 mc_intr_ltc_pending_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 mc_intr_priv_ring_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 mc_intr_pbus_pending_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 mc_intr_en_r(u32 i) { - return 0x00000140 + i*4; + return 0x00000140U + i*4U; } static inline u32 mc_intr_en_set_r(u32 i) { - return 0x00000160 + i*4; + return 0x00000160U + i*4U; } static inline u32 mc_intr_en_clear_r(u32 i) { - return 0x00000180 + i*4; + return 0x00000180U + i*4U; } static inline u32 mc_enable_r(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 mc_enable_xbar_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 mc_enable_l2_enabled_f(void) { - return 0x8; + return 0x8U; } static inline u32 mc_enable_pmedia_s(void) { - return 1; + return 1U; } static inline u32 mc_enable_pmedia_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 mc_enable_pmedia_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 mc_enable_pmedia_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 mc_enable_ce0_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 mc_enable_pfifo_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 mc_enable_pgraph_enabled_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 mc_enable_pwr_v(u32 r) { - return (r >> 13) & 0x1; + return (r >> 13U) & 0x1U; } static inline u32 mc_enable_pwr_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 mc_enable_pwr_enabled_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 mc_enable_pfb_enabled_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 mc_enable_ce2_m(void) { - return 0x1 << 21; + return 0x1U << 21U; } static inline u32 mc_enable_ce2_enabled_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 mc_enable_blg_enabled_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 mc_enable_perfmon_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 mc_enable_hub_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 mc_intr_ltc_r(void) { - return 0x000001c0; + return 0x000001c0U; } static inline u32 mc_enable_pb_r(void) { - return 0x00000204; + return 0x00000204U; } static inline u32 mc_enable_pb_0_s(void) { - return 1; + return 1U; } static inline u32 mc_enable_pb_0_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 mc_enable_pb_0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 mc_enable_pb_0_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 mc_enable_pb_0_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 mc_elpg_enable_r(void) { - return 0x0000020c; + return 0x0000020cU; } static inline u32 mc_elpg_enable_xbar_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 mc_elpg_enable_pfb_enabled_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 mc_elpg_enable_hub_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 mc_elpg_enable_l2_enabled_f(void) { - return 0x8; + return 0x8U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 025a7af3..74ff4002 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -58,594 +58,594 @@ static inline u32 pbdma_gp_entry1_r(void) { - return 0x10000004; + return 0x10000004U; } static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pbdma_gp_entry1_length_f(u32 v) { - return (v & 0x1fffff) << 10; + return (v & 0x1fffffU) << 10U; } static inline u32 pbdma_gp_entry1_length_v(u32 r) { - return (r >> 10) & 0x1fffff; + return (r >> 10U) & 0x1fffffU; } static inline u32 pbdma_gp_base_r(u32 i) { - return 0x00040048 + i*8192; + return 0x00040048U + i*8192U; } static inline u32 pbdma_gp_base__size_1_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 pbdma_gp_base_offset_f(u32 v) { - return (v & 0x1fffffff) << 3; + return (v & 0x1fffffffU) << 3U; } static inline u32 pbdma_gp_base_rsvd_s(void) { - return 3; + return 3U; } static inline u32 pbdma_gp_base_hi_r(u32 i) { - return 0x0004004c + i*8192; + return 0x0004004cU + i*8192U; } static inline u32 pbdma_gp_base_hi_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 pbdma_gp_fetch_r(u32 i) { - return 0x00040050 + i*8192; + return 0x00040050U + i*8192U; } static inline u32 pbdma_gp_get_r(u32 i) { - return 0x00040014 + i*8192; + return 0x00040014U + i*8192U; } static inline u32 pbdma_gp_put_r(u32 i) { - return 0x00040000 + i*8192; + return 0x00040000U + i*8192U; } static inline u32 pbdma_pb_fetch_r(u32 i) { - return 0x00040054 + i*8192; + return 0x00040054U + i*8192U; } static inline u32 pbdma_pb_fetch_hi_r(u32 i) { - return 0x00040058 + i*8192; + return 0x00040058U + i*8192U; } static inline u32 pbdma_get_r(u32 i) { - return 0x00040018 + i*8192; + return 0x00040018U + i*8192U; } static inline u32 pbdma_get_hi_r(u32 i) { - return 0x0004001c + i*8192; + return 0x0004001cU + i*8192U; } static inline u32 pbdma_put_r(u32 i) { - return 0x0004005c + i*8192; + return 0x0004005cU + i*8192U; } static inline u32 pbdma_put_hi_r(u32 i) { - return 0x00040060 + i*8192; + return 0x00040060U + i*8192U; } static inline u32 pbdma_pb_header_r(u32 i) { - return 0x00040084 + i*8192; + return 0x00040084U + i*8192U; } static inline u32 pbdma_pb_header_priv_user_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_method_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_subchannel_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_level_main_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_first_true_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_pb_header_type_inc_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_pb_header_type_non_inc_f(void) { - return 0x60000000; + return 0x60000000U; } static inline u32 pbdma_hdr_shadow_r(u32 i) { - return 0x00040118 + i*8192; + return 0x00040118U + i*8192U; } static inline u32 pbdma_subdevice_r(u32 i) { - return 0x00040094 + i*8192; + return 0x00040094U + i*8192U; } static inline u32 pbdma_subdevice_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 pbdma_subdevice_status_active_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 pbdma_subdevice_channel_dma_enable_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_method0_r(u32 i) { - return 0x000400c0 + i*8192; + return 0x000400c0U + i*8192U; } static inline u32 pbdma_method0_fifo_size_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 pbdma_method0_addr_f(u32 v) { - return (v & 0xfff) << 2; + return (v & 0xfffU) << 2U; } static inline u32 pbdma_method0_addr_v(u32 r) { - return (r >> 2) & 0xfff; + return (r >> 2U) & 0xfffU; } static inline u32 pbdma_method0_subch_v(u32 r) { - return (r >> 16) & 0x7; + return (r >> 16U) & 0x7U; } static inline u32 pbdma_method0_first_true_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_method0_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_method1_r(u32 i) { - return 0x000400c8 + i*8192; + return 0x000400c8U + i*8192U; } static inline u32 pbdma_method2_r(u32 i) { - return 0x000400d0 + i*8192; + return 0x000400d0U + i*8192U; } static inline u32 pbdma_method3_r(u32 i) { - return 0x000400d8 + i*8192; + return 0x000400d8U + i*8192U; } static inline u32 pbdma_data0_r(u32 i) { - return 0x000400c4 + i*8192; + return 0x000400c4U + i*8192U; } static inline u32 pbdma_acquire_r(u32 i) { - return 0x00040030 + i*8192; + return 0x00040030U + i*8192U; } static inline u32 pbdma_acquire_retry_man_2_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_acquire_retry_exp_2_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_acquire_timeout_exp_f(u32 v) { - return (v & 0xf) << 11; + return (v & 0xfU) << 11U; } static inline u32 pbdma_acquire_timeout_exp_max_v(void) { - return 0x0000000f; + return 0x0000000fU; } static inline u32 pbdma_acquire_timeout_exp_max_f(void) { - return 0x7800; + return 0x7800U; } static inline u32 pbdma_acquire_timeout_man_f(u32 v) { - return (v & 0xffff) << 15; + return (v & 0xffffU) << 15U; } static inline u32 pbdma_acquire_timeout_man_max_v(void) { - return 0x0000ffff; + return 0x0000ffffU; } static inline u32 pbdma_acquire_timeout_man_max_f(void) { - return 0x7fff8000; + return 0x7fff8000U; } static inline u32 pbdma_acquire_timeout_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_acquire_timeout_en_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_status_r(u32 i) { - return 0x00040100 + i*8192; + return 0x00040100U + i*8192U; } static inline u32 pbdma_channel_r(u32 i) { - return 0x00040120 + i*8192; + return 0x00040120U + i*8192U; } static inline u32 pbdma_signature_r(u32 i) { - return 0x00040010 + i*8192; + return 0x00040010U + i*8192U; } static inline u32 pbdma_signature_hw_valid_f(void) { - return 0xface; + return 0xfaceU; } static inline u32 pbdma_signature_sw_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_userd_r(u32 i) { - return 0x00040008 + i*8192; + return 0x00040008U + i*8192U; } static inline u32 pbdma_userd_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_userd_target_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 pbdma_userd_addr_f(u32 v) { - return (v & 0x7fffff) << 9; + return (v & 0x7fffffU) << 9U; } static inline u32 pbdma_config_r(u32 i) { - return 0x000400f4 + i*8192; + return 0x000400f4U + i*8192U; } static inline u32 pbdma_config_l2_evict_first_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_l2_evict_normal_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_config_l2_evict_last_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_config_ce_split_enable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_ce_split_disable_f(void) { - return 0x10; + return 0x10U; } static inline u32 pbdma_config_auth_level_non_privileged_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_auth_level_privileged_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_config_userd_writeback_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_userd_writeback_enable_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 pbdma_userd_hi_r(u32 i) { - return 0x0004000c + i*8192; + return 0x0004000cU + i*8192U; } static inline u32 pbdma_userd_hi_addr_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pbdma_hce_ctrl_r(u32 i) { - return 0x000400e4 + i*8192; + return 0x000400e4U + i*8192U; } static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) { - return 0x20; + return 0x20U; } static inline u32 pbdma_intr_0_r(u32 i) { - return 0x00040108 + i*8192; + return 0x00040108U + i*8192U; } static inline u32 pbdma_intr_0_memreq_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pbdma_intr_0_memreq_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_intr_0_memack_extra_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) { - return 0x8; + return 0x8U; } static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 pbdma_intr_0_memflush_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 pbdma_intr_0_memop_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 pbdma_intr_0_lbconnect_pending_f(void) { - return 0x80; + return 0x80U; } static inline u32 pbdma_intr_0_lbreq_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 pbdma_intr_0_lback_extra_pending_f(void) { - return 0x400; + return 0x400U; } static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) { - return 0x800; + return 0x800U; } static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 pbdma_intr_0_gpfifo_pending_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 pbdma_intr_0_gpptr_pending_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 pbdma_intr_0_gpentry_pending_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 pbdma_intr_0_gpcrc_pending_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 pbdma_intr_0_pbptr_pending_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 pbdma_intr_0_pbentry_pending_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 pbdma_intr_0_pbcrc_pending_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 pbdma_intr_0_method_pending_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 pbdma_intr_0_methodcrc_pending_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_intr_0_device_pending_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 pbdma_intr_0_eng_reset_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 pbdma_intr_0_semaphore_pending_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 pbdma_intr_0_acquire_pending_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 pbdma_intr_0_pri_pending_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_intr_0_pbseg_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 pbdma_intr_0_signature_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_intr_1_r(u32 i) { - return 0x00040148 + i*8192; + return 0x00040148U + i*8192U; } static inline u32 pbdma_intr_1_ctxnotvalid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_intr_en_0_r(u32 i) { - return 0x0004010c + i*8192; + return 0x0004010cU + i*8192U; } static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_en_1_r(u32 i) { - return 0x0004014c + i*8192; + return 0x0004014cU + i*8192U; } static inline u32 pbdma_intr_stall_r(u32 i) { - return 0x0004013c + i*8192; + return 0x0004013cU + i*8192U; } static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_stall_1_r(u32 i) { - return 0x00040140 + i*8192; + return 0x00040140U + i*8192U; } static inline u32 pbdma_udma_nop_r(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pbdma_runlist_timeslice_r(u32 i) { - return 0x000400f8 + i*8192; + return 0x000400f8U + i*8192U; } static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) { - return 0x80; + return 0x80U; } static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) { - return 0x3000; + return 0x3000U; } static inline u32 pbdma_runlist_timeslice_enable_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 pbdma_target_r(u32 i) { - return 0x000400ac + i*8192; + return 0x000400acU + i*8192U; } static inline u32 pbdma_target_engine_sw_f(void) { - return 0x1f; + return 0x1fU; } static inline u32 pbdma_target_eng_ctx_valid_true_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 pbdma_target_eng_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_ce_ctx_valid_true_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 pbdma_target_ce_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 pbdma_target_should_send_tsg_event_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_target_should_send_tsg_event_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_set_channel_info_r(u32 i) { - return 0x000400fc + i*8192; + return 0x000400fcU + i*8192U; } static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_set_channel_info_veid_f(u32 v) { - return (v & 0x3f) << 8; + return (v & 0x3fU) << 8U; } static inline u32 pbdma_timeout_r(u32 i) { - return 0x0004012c + i*8192; + return 0x0004012cU + i*8192U; } static inline u32 pbdma_timeout_period_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 pbdma_timeout_period_max_f(void) { - return 0xffffffff; + return 0xffffffffU; } static inline u32 pbdma_timeout_period_init_f(void) { - return 0x10000; + return 0x10000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h index 5adee5f3..788a6ab6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h @@ -58,154 +58,154 @@ static inline u32 perf_pmasys_control_r(void) { - return 0x0024a000; + return 0x0024a000U; } static inline u32 perf_pmasys_control_membuf_status_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) { - return 0x10; + return 0x10U; } static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) { - return (r >> 5) & 0x1; + return (r >> 5U) & 0x1U; } static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) { - return 0x20; + return 0x20U; } static inline u32 perf_pmasys_mem_block_r(void) { - return 0x0024a070; + return 0x0024a070U; } static inline u32 perf_pmasys_mem_block_base_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 perf_pmasys_mem_block_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 perf_pmasys_mem_block_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 perf_pmasys_mem_block_target_lfb_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 perf_pmasys_mem_block_target_lfb_f(void) { - return 0x0; + return 0x0U; } static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 perf_pmasys_mem_block_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 perf_pmasys_mem_block_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 perf_pmasys_mem_block_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_mem_block_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 perf_pmasys_mem_block_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 perf_pmasys_mem_block_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 perf_pmasys_outbase_r(void) { - return 0x0024a074; + return 0x0024a074U; } static inline u32 perf_pmasys_outbase_ptr_f(u32 v) { - return (v & 0x7ffffff) << 5; + return (v & 0x7ffffffU) << 5U; } static inline u32 perf_pmasys_outbaseupper_r(void) { - return 0x0024a078; + return 0x0024a078U; } static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 perf_pmasys_outsize_r(void) { - return 0x0024a07c; + return 0x0024a07cU; } static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) { - return (v & 0x7ffffff) << 5; + return (v & 0x7ffffffU) << 5U; } static inline u32 perf_pmasys_mem_bytes_r(void) { - return 0x0024a084; + return 0x0024a084U; } static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 perf_pmasys_mem_bump_r(void) { - return 0x0024a088; + return 0x0024a088U; } static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 perf_pmasys_enginestatus_r(void) { - return 0x0024a0a4; + return 0x0024a0a4U; } static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) { - return 0x10; + return 0x10U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h index 1568f310..456d6316 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h @@ -58,6 +58,6 @@ static inline u32 pram_data032_r(u32 i) { - return 0x00700000 + i*4; + return 0x00700000U + i*4U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h index 24509b08..a653681d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h @@ -58,110 +58,110 @@ static inline u32 pri_ringmaster_command_r(void) { - return 0x0012004c; + return 0x0012004cU; } static inline u32 pri_ringmaster_command_cmd_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 pri_ringmaster_command_cmd_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) { - return 0x2; + return 0x2U; } static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) { - return 0x3; + return 0x3U; } static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 pri_ringmaster_command_data_r(void) { - return 0x00120048; + return 0x00120048U; } static inline u32 pri_ringmaster_start_results_r(void) { - return 0x00120050; + return 0x00120050U; } static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 pri_ringmaster_intr_status0_r(void) { - return 0x00120058; + return 0x00120058U; } static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 pri_ringmaster_intr_status1_r(void) { - return 0x0012005c; + return 0x0012005cU; } static inline u32 pri_ringmaster_global_ctl_r(void) { - return 0x00120060; + return 0x00120060U; } static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) { - return 0x0; + return 0x0U; } static inline u32 pri_ringmaster_enum_fbp_r(void) { - return 0x00120074; + return 0x00120074U; } static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 pri_ringmaster_enum_gpc_r(void) { - return 0x00120078; + return 0x00120078U; } static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 pri_ringmaster_enum_ltc_r(void) { - return 0x0012006c; + return 0x0012006cU; } static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h index 119e2075..47da22c0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h @@ -58,22 +58,22 @@ static inline u32 pri_ringstation_gpc_master_config_r(u32 i) { - return 0x00128300 + i*4; + return 0x00128300U + i*4U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) { - return 0x00128120; + return 0x00128120U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) { - return 0x00128124; + return 0x00128124U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) { - return 0x00128128; + return 0x00128128U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) { - return 0x0012812c; + return 0x0012812cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h index 85b86c98..622b6d7b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h @@ -58,34 +58,34 @@ static inline u32 pri_ringstation_sys_master_config_r(u32 i) { - return 0x00122300 + i*4; + return 0x00122300U + i*4U; } static inline u32 pri_ringstation_sys_decode_config_r(void) { - return 0x00122204; + return 0x00122204U; } static inline u32 pri_ringstation_sys_decode_config_ring_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringstation_sys_priv_error_adr_r(void) { - return 0x00122120; + return 0x00122120U; } static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) { - return 0x00122124; + return 0x00122124U; } static inline u32 pri_ringstation_sys_priv_error_info_r(void) { - return 0x00122128; + return 0x00122128U; } static inline u32 pri_ringstation_sys_priv_error_code_r(void) { - return 0x0012212c; + return 0x0012212cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h index 8406ea21..808fe316 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h @@ -58,130 +58,130 @@ static inline u32 proj_gpc_base_v(void) { - return 0x00500000; + return 0x00500000U; } static inline u32 proj_gpc_shared_base_v(void) { - return 0x00418000; + return 0x00418000U; } static inline u32 proj_gpc_stride_v(void) { - return 0x00008000; + return 0x00008000U; } static inline u32 proj_ltc_stride_v(void) { - return 0x00002000; + return 0x00002000U; } static inline u32 proj_lts_stride_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 proj_fbpa_stride_v(void) { - return 0x00004000; + return 0x00004000U; } static inline u32 proj_ppc_in_gpc_base_v(void) { - return 0x00003000; + return 0x00003000U; } static inline u32 proj_ppc_in_gpc_shared_base_v(void) { - return 0x00003e00; + return 0x00003e00U; } static inline u32 proj_ppc_in_gpc_stride_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 proj_rop_base_v(void) { - return 0x00410000; + return 0x00410000U; } static inline u32 proj_rop_shared_base_v(void) { - return 0x00408800; + return 0x00408800U; } static inline u32 proj_rop_stride_v(void) { - return 0x00000400; + return 0x00000400U; } static inline u32 proj_tpc_in_gpc_base_v(void) { - return 0x00004000; + return 0x00004000U; } static inline u32 proj_tpc_in_gpc_stride_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 proj_tpc_in_gpc_shared_base_v(void) { - return 0x00001800; + return 0x00001800U; } static inline u32 proj_smpc_base_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 proj_smpc_shared_base_v(void) { - return 0x00000300; + return 0x00000300U; } static inline u32 proj_smpc_unique_base_v(void) { - return 0x00000600; + return 0x00000600U; } static inline u32 proj_smpc_stride_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 proj_host_num_engines_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 proj_host_num_pbdma_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 proj_scal_litter_num_fbps_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 proj_scal_litter_num_fbpas_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 proj_scal_litter_num_gpcs_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 proj_scal_litter_num_zcull_banks_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 proj_scal_max_gpcs_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 proj_scal_max_tpc_per_gpc_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 proj_sm_stride_v(void) { - return 0x00000080; + return 0x00000080U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h index 43c0c908..eba6d806 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h @@ -58,894 +58,894 @@ static inline u32 pwr_falcon_irqsset_r(void) { - return 0x0010a000; + return 0x0010a000U; } static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) { - return 0x40; + return 0x40U; } static inline u32 pwr_falcon_irqsclr_r(void) { - return 0x0010a004; + return 0x0010a004U; } static inline u32 pwr_falcon_irqstat_r(void) { - return 0x0010a008; + return 0x0010a008U; } static inline u32 pwr_falcon_irqstat_halt_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 pwr_falcon_irqstat_exterr_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 pwr_falcon_irqmode_r(void) { - return 0x0010a00c; + return 0x0010a00cU; } static inline u32 pwr_falcon_irqmset_r(void) { - return 0x0010a010; + return 0x0010a010U; } static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqmset_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqmset_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v) { - return (v & 0x1) << 15; + return (v & 0x1U) << 15U; } static inline u32 pwr_falcon_irqmclr_r(void) { - return 0x0010a014; + return 0x0010a014U; } static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v) { - return (v & 0x1) << 15; + return (v & 0x1U) << 15U; } static inline u32 pwr_falcon_irqmask_r(void) { - return 0x0010a018; + return 0x0010a018U; } static inline u32 pwr_falcon_irqdest_r(void) { - return 0x0010a01c; + return 0x0010a01cU; } static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v) { - return (v & 0x1) << 15; + return (v & 0x1U) << 15U; } static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) { - return (v & 0x1) << 21; + return (v & 0x1U) << 21U; } static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) { - return (v & 0x1) << 23; + return (v & 0x1U) << 23U; } static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) { - return (v & 0x1) << 27; + return (v & 0x1U) << 27U; } static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 pwr_falcon_curctx_r(void) { - return 0x0010a050; + return 0x0010a050U; } static inline u32 pwr_falcon_nxtctx_r(void) { - return 0x0010a054; + return 0x0010a054U; } static inline u32 pwr_falcon_mailbox0_r(void) { - return 0x0010a040; + return 0x0010a040U; } static inline u32 pwr_falcon_mailbox1_r(void) { - return 0x0010a044; + return 0x0010a044U; } static inline u32 pwr_falcon_itfen_r(void) { - return 0x0010a048; + return 0x0010a048U; } static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_falcon_idlestate_r(void) { - return 0x0010a04c; + return 0x0010a04cU; } static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) { - return (r >> 1) & 0x7fff; + return (r >> 1U) & 0x7fffU; } static inline u32 pwr_falcon_os_r(void) { - return 0x0010a080; + return 0x0010a080U; } static inline u32 pwr_falcon_engctl_r(void) { - return 0x0010a0a4; + return 0x0010a0a4U; } static inline u32 pwr_falcon_cpuctl_r(void) { - return 0x0010a100; + return 0x0010a100U; } static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 6U) & 0x1U; } static inline u32 pwr_falcon_cpuctl_alias_r(void) { - return 0x0010a130; + return 0x0010a130U; } static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_pmu_scpctl_stat_r(void) { - return 0x0010ac08; + return 0x0010ac08U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 pwr_falcon_imemc_r(u32 i) { - return 0x0010a180 + i*16; + return 0x0010a180U + i*16U; } static inline u32 pwr_falcon_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 pwr_falcon_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_imemd_r(u32 i) { - return 0x0010a184 + i*16; + return 0x0010a184U + i*16U; } static inline u32 pwr_falcon_imemt_r(u32 i) { - return 0x0010a188 + i*16; + return 0x0010a188U + i*16U; } static inline u32 pwr_falcon_sctl_r(void) { - return 0x0010a240; + return 0x0010a240U; } static inline u32 pwr_falcon_mmu_phys_sec_r(void) { - return 0x00100ce4; + return 0x00100ce4U; } static inline u32 pwr_falcon_bootvec_r(void) { - return 0x0010a104; + return 0x0010a104U; } static inline u32 pwr_falcon_bootvec_vec_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_falcon_dmactl_r(void) { - return 0x0010a10c; + return 0x0010a10cU; } static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_falcon_hwcfg_r(void) { - return 0x0010a108; + return 0x0010a108U; } static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) { - return (r >> 9) & 0x1ff; + return (r >> 9U) & 0x1ffU; } static inline u32 pwr_falcon_dmatrfbase_r(void) { - return 0x0010a110; + return 0x0010a110U; } static inline u32 pwr_falcon_dmatrfbase1_r(void) { - return 0x0010a128; + return 0x0010a128U; } static inline u32 pwr_falcon_dmatrfmoffs_r(void) { - return 0x0010a114; + return 0x0010a114U; } static inline u32 pwr_falcon_dmatrfcmd_r(void) { - return 0x0010a118; + return 0x0010a118U; } static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 pwr_falcon_dmatrffboffs_r(void) { - return 0x0010a11c; + return 0x0010a11cU; } static inline u32 pwr_falcon_exterraddr_r(void) { - return 0x0010a168; + return 0x0010a168U; } static inline u32 pwr_falcon_exterrstat_r(void) { - return 0x0010a16c; + return 0x0010a16cU; } static inline u32 pwr_falcon_exterrstat_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 pwr_falcon_exterrstat_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 pwr_pmu_falcon_icd_cmd_r(void) { - return 0x0010a200; + return 0x0010a200U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) { - return 4; + return 4U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) { - return 0x8; + return 0x8U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) { - return 0xe; + return 0xeU; } static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 pwr_pmu_falcon_icd_rdata_r(void) { - return 0x0010a20c; + return 0x0010a20cU; } static inline u32 pwr_falcon_dmemc_r(u32 i) { - return 0x0010a1c0 + i*8; + return 0x0010a1c0U + i*8U; } static inline u32 pwr_falcon_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 pwr_falcon_dmemc_offs_m(void) { - return 0x3f << 2; + return 0x3fU << 2U; } static inline u32 pwr_falcon_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_dmemc_blk_m(void) { - return 0xff << 8; + return 0xffU << 8U; } static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 pwr_falcon_dmemd_r(u32 i) { - return 0x0010a1c4 + i*8; + return 0x0010a1c4U + i*8U; } static inline u32 pwr_pmu_new_instblk_r(void) { - return 0x0010a480; + return 0x0010a480U; } static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 pwr_pmu_new_instblk_target_fb_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 pwr_pmu_mutex_id_r(void) { - return 0x0010a488; + return 0x0010a488U; } static inline u32 pwr_pmu_mutex_id_value_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pwr_pmu_mutex_id_value_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) { - return 0x000000ff; + return 0x000000ffU; } static inline u32 pwr_pmu_mutex_id_release_r(void) { - return 0x0010a48c; + return 0x0010a48cU; } static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pwr_pmu_mutex_id_release_value_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_mutex_r(u32 i) { - return 0x0010a580 + i*4; + return 0x0010a580U + i*4U; } static inline u32 pwr_pmu_mutex__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 pwr_pmu_mutex_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pwr_pmu_mutex_value_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_queue_head_r(u32 i) { - return 0x0010a800 + i*4; + return 0x0010a800U + i*4U; } static inline u32 pwr_pmu_queue_head__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pwr_pmu_queue_head_address_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_queue_head_address_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_queue_tail_r(u32 i) { - return 0x0010a820 + i*4; + return 0x0010a820U + i*4U; } static inline u32 pwr_pmu_queue_tail__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pwr_pmu_queue_tail_address_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_queue_tail_address_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_msgq_head_r(void) { - return 0x0010a4c8; + return 0x0010a4c8U; } static inline u32 pwr_pmu_msgq_head_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_msgq_head_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_msgq_tail_r(void) { - return 0x0010a4cc; + return 0x0010a4ccU; } static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_idle_mask_r(u32 i) { - return 0x0010a504 + i*16; + return 0x0010a504U + i*16U; } static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 pwr_pmu_idle_count_r(u32 i) { - return 0x0010a508 + i*16; + return 0x0010a508U + i*16U; } static inline u32 pwr_pmu_idle_count_value_f(u32 v) { - return (v & 0x7fffffff) << 0; + return (v & 0x7fffffffU) << 0U; } static inline u32 pwr_pmu_idle_count_value_v(u32 r) { - return (r >> 0) & 0x7fffffff; + return (r >> 0U) & 0x7fffffffU; } static inline u32 pwr_pmu_idle_count_reset_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 pwr_pmu_idle_ctrl_r(u32 i) { - return 0x0010a50c + i*16; + return 0x0010a50cU + i*16U; } static inline u32 pwr_pmu_idle_ctrl_value_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) { - return 0x2; + return 0x2U; } static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) { - return 0x3; + return 0x3U; } static inline u32 pwr_pmu_idle_ctrl_filter_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) { - return 0x0010a9f0 + i*8; + return 0x0010a9f0U + i*8U; } static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) { - return 0x0010a9f4 + i*8; + return 0x0010a9f4U + i*8U; } static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) { - return 0x0010aa30 + i*8; + return 0x0010aa30U + i*8U; } static inline u32 pwr_pmu_debug_r(u32 i) { - return 0x0010a5c0 + i*4; + return 0x0010a5c0U + i*4U; } static inline u32 pwr_pmu_debug__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 pwr_pmu_mailbox_r(u32 i) { - return 0x0010a450 + i*4; + return 0x0010a450U + i*4U; } static inline u32 pwr_pmu_mailbox__size_1_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 pwr_pmu_bar0_addr_r(void) { - return 0x0010a7a0; + return 0x0010a7a0U; } static inline u32 pwr_pmu_bar0_data_r(void) { - return 0x0010a7a4; + return 0x0010a7a4U; } static inline u32 pwr_pmu_bar0_ctl_r(void) { - return 0x0010a7ac; + return 0x0010a7acU; } static inline u32 pwr_pmu_bar0_timeout_r(void) { - return 0x0010a7a8; + return 0x0010a7a8U; } static inline u32 pwr_pmu_bar0_fecs_error_r(void) { - return 0x0010a988; + return 0x0010a988U; } static inline u32 pwr_pmu_bar0_error_status_r(void) { - return 0x0010a7b0; + return 0x0010a7b0U; } static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) { - return 0x0010a6c0 + i*4; + return 0x0010a6c0U + i*4U; } static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) { - return 0x0010a6e8 + i*4; + return 0x0010a6e8U + i*4U; } static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) { - return 0x0010a710 + i*4; + return 0x0010a710U + i*4U; } static inline u32 pwr_pmu_pg_intren_r(u32 i) { - return 0x0010a760 + i*4; + return 0x0010a760U + i*4U; } static inline u32 pwr_fbif_transcfg_r(u32 i) { - return 0x0010ae00 + i*4; + return 0x0010ae00U + i*4U; } static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) { - return 0x2; + return 0x2U; } static inline u32 pwr_fbif_transcfg_mem_type_s(void) { - return 1; + return 1U; } static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_fbif_transcfg_mem_type_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) { - return 0x4; + return 0x4U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h index fe8bcd6b..1191e580 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h @@ -58,619 +58,619 @@ static inline u32 ram_in_ramfc_s(void) { - return 4096; + return 4096U; } static inline u32 ram_in_ramfc_w(void) { - return 0; + return 0U; } static inline u32 ram_in_page_dir_base_target_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_page_dir_base_target_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 ram_in_page_dir_base_vol_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_vol_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 ram_in_page_dir_base_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 ram_in_big_page_size_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 ram_in_big_page_size_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 ram_in_big_page_size_w(void) { - return 128; + return 128U; } static inline u32 ram_in_big_page_size_128kb_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_big_page_size_64kb_f(void) { - return 0x800; + return 0x800U; } static inline u32 ram_in_page_dir_base_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_page_dir_base_lo_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_page_dir_base_hi_w(void) { - return 129; + return 129U; } static inline u32 ram_in_engine_cs_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_cs_wfi_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_cs_wfi_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_engine_cs_fg_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_engine_cs_fg_f(void) { - return 0x8; + return 0x8U; } static inline u32 ram_in_engine_wfi_mode_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 ram_in_engine_wfi_mode_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_mode_physical_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_wfi_mode_virtual_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_engine_wfi_target_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_engine_wfi_target_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_in_engine_wfi_target_local_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_engine_wfi_ptr_lo_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ram_in_engine_wfi_ptr_hi_w(void) { - return 133; + return 133U; } static inline u32 ram_in_engine_wfi_veid_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 ram_in_engine_wfi_veid_w(void) { - return 134; + return 134U; } static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) { - return 136; + return 136U; } static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) { - return 137; + return 137U; } static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) { - return (v & 0x3) << (0 + i*0); + return (v & 0x3U) << (0U + i*0U); } static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) { - return (v & 0x1) << (2 + i*0); + return (v & 0x1U) << (2U + i*0U); } static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) { - return (v & 0x1) << (4 + i*0); + return (v & 0x1U) << (4U + i*0U); } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) { - return (v & 0x1) << (5 + i*0); + return (v & 0x1U) << (5U + i*0U); } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) { - return (v & 0x1) << (10 + i*0); + return (v & 0x1U) << (10U + i*0U); } static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) { - return (v & 0x1) << (11 + i*0); + return (v & 0x1U) << (11U + i*0U); } static inline u32 ram_in_sc_big_page_size__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_big_page_size_64kb_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) { - return (v & 0xfffff) << (12 + i*0); + return (v & 0xfffffU) << (12U + i*0U); } static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) { - return (v & 0xffffffff) << (0 + i*0); + return (v & 0xffffffffU) << (0U + i*0U); } static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_sc_page_dir_base_target_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_big_page_size_0_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 ram_in_sc_big_page_size_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) { - return 169; + return 169U; } static inline u32 ram_in_base_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ram_in_alloc_size_v(void) { - return 0x00001000; + return 0x00001000U; } static inline u32 ram_fc_size_val_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ram_fc_gp_put_w(void) { - return 0; + return 0U; } static inline u32 ram_fc_userd_w(void) { - return 2; + return 2U; } static inline u32 ram_fc_userd_hi_w(void) { - return 3; + return 3U; } static inline u32 ram_fc_signature_w(void) { - return 4; + return 4U; } static inline u32 ram_fc_gp_get_w(void) { - return 5; + return 5U; } static inline u32 ram_fc_pb_get_w(void) { - return 6; + return 6U; } static inline u32 ram_fc_pb_get_hi_w(void) { - return 7; + return 7U; } static inline u32 ram_fc_pb_top_level_get_w(void) { - return 8; + return 8U; } static inline u32 ram_fc_pb_top_level_get_hi_w(void) { - return 9; + return 9U; } static inline u32 ram_fc_acquire_w(void) { - return 12; + return 12U; } static inline u32 ram_fc_sem_addr_hi_w(void) { - return 14; + return 14U; } static inline u32 ram_fc_sem_addr_lo_w(void) { - return 15; + return 15U; } static inline u32 ram_fc_sem_payload_lo_w(void) { - return 16; + return 16U; } static inline u32 ram_fc_sem_payload_hi_w(void) { - return 39; + return 39U; } static inline u32 ram_fc_sem_execute_w(void) { - return 17; + return 17U; } static inline u32 ram_fc_gp_base_w(void) { - return 18; + return 18U; } static inline u32 ram_fc_gp_base_hi_w(void) { - return 19; + return 19U; } static inline u32 ram_fc_gp_fetch_w(void) { - return 20; + return 20U; } static inline u32 ram_fc_pb_fetch_w(void) { - return 21; + return 21U; } static inline u32 ram_fc_pb_fetch_hi_w(void) { - return 22; + return 22U; } static inline u32 ram_fc_pb_put_w(void) { - return 23; + return 23U; } static inline u32 ram_fc_pb_put_hi_w(void) { - return 24; + return 24U; } static inline u32 ram_fc_pb_header_w(void) { - return 33; + return 33U; } static inline u32 ram_fc_pb_count_w(void) { - return 34; + return 34U; } static inline u32 ram_fc_subdevice_w(void) { - return 37; + return 37U; } static inline u32 ram_fc_target_w(void) { - return 43; + return 43U; } static inline u32 ram_fc_hce_ctrl_w(void) { - return 57; + return 57U; } static inline u32 ram_fc_chid_w(void) { - return 58; + return 58U; } static inline u32 ram_fc_chid_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_fc_chid_id_w(void) { - return 0; + return 0U; } static inline u32 ram_fc_config_w(void) { - return 61; + return 61U; } static inline u32 ram_fc_runlist_timeslice_w(void) { - return 62; + return 62U; } static inline u32 ram_fc_set_channel_info_w(void) { - return 63; + return 63U; } static inline u32 ram_userd_base_shift_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 ram_userd_chan_size_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ram_userd_put_w(void) { - return 16; + return 16U; } static inline u32 ram_userd_get_w(void) { - return 17; + return 17U; } static inline u32 ram_userd_ref_w(void) { - return 18; + return 18U; } static inline u32 ram_userd_put_hi_w(void) { - return 19; + return 19U; } static inline u32 ram_userd_ref_threshold_w(void) { - return 20; + return 20U; } static inline u32 ram_userd_top_level_get_w(void) { - return 22; + return 22U; } static inline u32 ram_userd_top_level_get_hi_w(void) { - return 23; + return 23U; } static inline u32 ram_userd_get_hi_w(void) { - return 24; + return 24U; } static inline u32 ram_userd_gp_get_w(void) { - return 34; + return 34U; } static inline u32 ram_userd_gp_put_w(void) { - return 35; + return 35U; } static inline u32 ram_userd_gp_top_level_get_w(void) { - return 22; + return 22U; } static inline u32 ram_userd_gp_top_level_get_hi_w(void) { - return 23; + return 23U; } static inline u32 ram_rl_entry_size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ram_rl_entry_type_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 ram_rl_entry_type_channel_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_type_tsg_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) { - return (v & 0x3) << 4; + return (v & 0x3U) << 4U; } static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) { @@ -682,94 +682,94 @@ static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) } static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) { - return (v & 0x3) << 6; + return (v & 0x3U) << 6U; } static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_rl_entry_chid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_tsg_length_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ram_rl_entry_tsg_length_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_tsg_length_min_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_tsg_length_max_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index b47e37f4..ce265901 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -58,187 +58,187 @@ static inline u32 therm_use_a_r(void) { - return 0x00020798; + return 0x00020798U; } static inline u32 therm_use_a_ext_therm_0_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_use_a_ext_therm_1_enable_f(void) { - return 0x2; + return 0x2U; } static inline u32 therm_use_a_ext_therm_2_enable_f(void) { - return 0x4; + return 0x4U; } static inline u32 therm_evt_ext_therm_0_r(void) { - return 0x00020700; + return 0x00020700U; } static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) { - return (v & 0x3f) << 24; + return (v & 0x3fU) << 24U; } static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) { - return (v & 0x3) << 30; + return (v & 0x3U) << 30U; } static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 therm_evt_ext_therm_1_r(void) { - return 0x00020704; + return 0x00020704U; } static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) { - return (v & 0x3f) << 24; + return (v & 0x3fU) << 24U; } static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) { - return (v & 0x3) << 30; + return (v & 0x3U) << 30U; } static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 therm_evt_ext_therm_2_r(void) { - return 0x00020708; + return 0x00020708U; } static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) { - return (v & 0x3f) << 24; + return (v & 0x3fU) << 24U; } static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) { - return (v & 0x3) << 30; + return (v & 0x3U) << 30U; } static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 therm_weight_1_r(void) { - return 0x00020024; + return 0x00020024U; } static inline u32 therm_config1_r(void) { - return 0x00020050; + return 0x00020050U; } static inline u32 therm_config2_r(void) { - return 0x00020130; + return 0x00020130U; } static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 therm_config2_grad_enable_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 therm_gate_ctrl_r(u32 i) { - return 0x00020200 + i*4; + return 0x00020200U + i*4U; } static inline u32 therm_gate_ctrl_eng_clk_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 therm_gate_ctrl_eng_clk_run_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) { - return 0x2; + return 0x2U; } static inline u32 therm_gate_ctrl_blk_clk_m(void) { - return 0x3 << 2; + return 0x3U << 2U; } static inline u32 therm_gate_ctrl_blk_clk_run_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) { - return 0x4; + return 0x4U; } static inline u32 therm_gate_ctrl_idle_holdoff_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) { - return 0x10; + return 0x10U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) { - return 0x1f << 8; + return 0x1fU << 8U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) { @@ -246,11 +246,11 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) { - return (v & 0x7) << 13; + return (v & 0x7U) << 13U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) { - return 0x7 << 13; + return 0x7U << 13U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) { @@ -258,11 +258,11 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) } static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 therm_gate_ctrl_eng_delay_before_m(void) { - return 0xf << 16; + return 0xfU << 16U; } static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) { @@ -270,11 +270,11 @@ static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) } static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 therm_gate_ctrl_eng_delay_after_m(void) { - return 0xf << 20; + return 0xfU << 20U; } static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) { @@ -282,11 +282,11 @@ static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) } static inline u32 therm_fecs_idle_filter_r(void) { - return 0x00020288; + return 0x00020288U; } static inline u32 therm_fecs_idle_filter_value_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 therm_fecs_idle_filter_value__prod_f(void) { @@ -294,11 +294,11 @@ static inline u32 therm_fecs_idle_filter_value__prod_f(void) } static inline u32 therm_hubmmu_idle_filter_r(void) { - return 0x0002028c; + return 0x0002028cU; } static inline u32 therm_hubmmu_idle_filter_value_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) { @@ -306,130 +306,130 @@ static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) } static inline u32 therm_clk_slowdown_r(u32 i) { - return 0x00020160 + i*4; + return 0x00020160U + i*4U; } static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) { - return (v & 0x3f) << 16; + return (v & 0x3fU) << 16U; } static inline u32 therm_clk_slowdown_idle_factor_m(void) { - return 0x3f << 16; + return 0x3fU << 16U; } static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) { - return (r >> 16) & 0x3f; + return (r >> 16U) & 0x3fU; } static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_grad_stepping_table_r(u32 i) { - return 0x000202c8 + i*4; + return 0x000202c8U + i*4U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) { - return 0x2; + return 0x2U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) { - return 0x6; + return 0x6U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) { - return 0xe; + return 0xeU; } static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) { - return (v & 0x3f) << 6; + return (v & 0x3fU) << 6U; } static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) { - return 0x3f << 6; + return 0x3fU << 6U; } static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) { - return (v & 0x3f) << 12; + return (v & 0x3fU) << 12U; } static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) { - return 0x3f << 12; + return 0x3fU << 12U; } static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) { - return (v & 0x3f) << 18; + return (v & 0x3fU) << 18U; } static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) { - return 0x3f << 18; + return 0x3fU << 18U; } static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) { - return (v & 0x3f) << 24; + return (v & 0x3fU) << 24U; } static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) { - return 0x3f << 24; + return 0x3fU << 24U; } static inline u32 therm_grad_stepping0_r(void) { - return 0x000202c0; + return 0x000202c0U; } static inline u32 therm_grad_stepping0_feature_s(void) { - return 1; + return 1U; } static inline u32 therm_grad_stepping0_feature_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 therm_grad_stepping0_feature_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 therm_grad_stepping0_feature_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 therm_grad_stepping0_feature_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_grad_stepping1_r(void) { - return 0x000202c4; + return 0x000202c4U; } static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 therm_clk_timing_r(u32 i) { - return 0x000203c0 + i*4; + return 0x000203c0U + i*4U; } static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 therm_clk_timing_grad_slowdown_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) { - return 0x10000; + return 0x10000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h index 1181f177..61440213 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h @@ -58,58 +58,58 @@ static inline u32 timer_pri_timeout_r(void) { - return 0x00009080; + return 0x00009080U; } static inline u32 timer_pri_timeout_period_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 timer_pri_timeout_period_m(void) { - return 0xffffff << 0; + return 0xffffffU << 0U; } static inline u32 timer_pri_timeout_period_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 timer_pri_timeout_en_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 timer_pri_timeout_en_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 timer_pri_timeout_en_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 timer_pri_timeout_en_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 timer_pri_timeout_en_en_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 timer_pri_timeout_save_0_r(void) { - return 0x00009084; + return 0x00009084U; } static inline u32 timer_pri_timeout_save_1_r(void) { - return 0x00009088; + return 0x00009088U; } static inline u32 timer_pri_timeout_fecs_errcode_r(void) { - return 0x0000908c; + return 0x0000908cU; } static inline u32 timer_time_0_r(void) { - return 0x00009400; + return 0x00009400U; } static inline u32 timer_time_1_r(void) { - return 0x00009410; + return 0x00009410U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h index 694257ed..89e4aebb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h @@ -58,178 +58,178 @@ static inline u32 top_num_gpcs_r(void) { - return 0x00022430; + return 0x00022430U; } static inline u32 top_num_gpcs_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_tpc_per_gpc_r(void) { - return 0x00022434; + return 0x00022434U; } static inline u32 top_tpc_per_gpc_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_num_fbps_r(void) { - return 0x00022438; + return 0x00022438U; } static inline u32 top_num_fbps_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_ltc_per_fbp_r(void) { - return 0x00022450; + return 0x00022450U; } static inline u32 top_ltc_per_fbp_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_slices_per_ltc_r(void) { - return 0x0002245c; + return 0x0002245cU; } static inline u32 top_slices_per_ltc_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_num_ltcs_r(void) { - return 0x00022454; + return 0x00022454U; } static inline u32 top_num_ces_r(void) { - return 0x00022444; + return 0x00022444U; } static inline u32 top_num_ces_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_device_info_r(u32 i) { - return 0x00022700 + i*4; + return 0x00022700U + i*4U; } static inline u32 top_device_info__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 top_device_info_chain_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 top_device_info_chain_enable_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 top_device_info_engine_enum_v(u32 r) { - return (r >> 26) & 0xf; + return (r >> 26U) & 0xfU; } static inline u32 top_device_info_runlist_enum_v(u32 r) { - return (r >> 21) & 0xf; + return (r >> 21U) & 0xfU; } static inline u32 top_device_info_intr_enum_v(u32 r) { - return (r >> 15) & 0x1f; + return (r >> 15U) & 0x1fU; } static inline u32 top_device_info_reset_enum_v(u32 r) { - return (r >> 9) & 0x1f; + return (r >> 9U) & 0x1fU; } static inline u32 top_device_info_type_enum_v(u32 r) { - return (r >> 2) & 0x1fffffff; + return (r >> 2U) & 0x1fffffffU; } static inline u32 top_device_info_type_enum_graphics_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_type_enum_graphics_f(void) { - return 0x0; + return 0x0U; } static inline u32 top_device_info_type_enum_copy2_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 top_device_info_type_enum_copy2_f(void) { - return 0xc; + return 0xcU; } static inline u32 top_device_info_type_enum_lce_v(void) { - return 0x00000013; + return 0x00000013U; } static inline u32 top_device_info_type_enum_lce_f(void) { - return 0x4c; + return 0x4cU; } static inline u32 top_device_info_engine_v(u32 r) { - return (r >> 5) & 0x1; + return (r >> 5U) & 0x1U; } static inline u32 top_device_info_runlist_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 top_device_info_intr_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 top_device_info_reset_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 top_device_info_entry_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 top_device_info_entry_not_valid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_entry_enum_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 top_device_info_entry_data_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 top_device_info_data_type_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 top_device_info_data_type_enum2_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_data_inst_id_v(u32 r) { - return (r >> 26) & 0xf; + return (r >> 26U) & 0xfU; } static inline u32 top_device_info_data_pri_base_v(u32 r) { - return (r >> 12) & 0xfff; + return (r >> 12U) & 0xfffU; } static inline u32 top_device_info_data_pri_base_align_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 top_device_info_data_fault_id_enum_v(u32 r) { - return (r >> 3) & 0x7f; + return (r >> 3U) & 0x7fU; } static inline u32 top_device_info_data_fault_id_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 top_device_info_data_fault_id_valid_v(void) { - return 0x00000001; + return 0x00000001U; } #endif -- cgit v1.2.2 From ade9f5e03f1d0fd4987fc3f9fafb12e4118ac570 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 10 Oct 2017 13:18:02 -0700 Subject: gpu: nvgpu: Remove phys_addr_t from common code Remove phys_addr_t change for corresponding change in the nvgpu main repo. JIRA NVGPU-30 JIRA NVGPU-226 Change-Id: I05a19bc51e949279edef6e9ad7161226cbca51a7 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1576466 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/common/linux/nvhost_t19x.c | 5 ++--- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 3 ++- drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h | 5 +++-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c b/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c index 0b2ae08c..21cf62ec 100644 --- a/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c @@ -23,11 +23,10 @@ int nvgpu_nvhost_syncpt_unit_interface_get_aperture( struct nvgpu_nvhost_dev *nvhost_dev, - phys_addr_t *base, - size_t *size) + u64 *base, size_t *size) { return nvhost_syncpt_unit_interface_get_aperture( - nvhost_dev->host1x_pdev, base, size); + nvhost_dev->host1x_pdev, (phys_addr_t *)base, size); } u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index f47a2fac..9301ebc6 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -108,7 +108,8 @@ void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) u64 compbit_base_post_divide64; if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) - compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); + compbit_store_iova = nvgpu_mem_get_phys_addr(g, + &gr->compbit_store.mem); else compbit_store_iova = nvgpu_mem_get_addr(g, &gr->compbit_store.mem); diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h index fcf99778..4b499882 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h @@ -24,12 +24,13 @@ #define __NVGPU_NVHOST_T19X_H__ #ifdef CONFIG_TEGRA_GK20A_NVHOST +#include + struct nvgpu_nvhost_dev; int nvgpu_nvhost_syncpt_unit_interface_get_aperture( struct nvgpu_nvhost_dev *nvhost_dev, - phys_addr_t *base, - size_t *size); + u64 *base, size_t *size); u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id); #endif -- cgit v1.2.2 From 82f235b5299c65446398d63fd3c982853fc1de23 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 29 Sep 2017 12:41:48 -0700 Subject: gpu: nvgpu: gv100: Qualify unsigned HW constants Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions. Change-Id: If3c1e25dcb07ce6857a4798f2c5308e2948fe5e0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1571163 Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit --- .../nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | 84 +- .../nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 64 +- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h | 24 +- .../include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h | 198 +- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | 708 +++---- .../nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h | 246 +-- .../nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h | 64 +- .../nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h | 42 +- .../nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h | 614 +++---- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 1926 ++++++++++---------- .../nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h | 280 +-- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | 96 +- .../nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | 296 +-- .../nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h | 76 +- .../nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h | 2 +- .../nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h | 54 +- .../nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h | 10 +- .../nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h | 16 +- .../nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | 54 +- .../nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h | 438 ++--- .../nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h | 354 ++-- .../nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h | 120 +- .../nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h | 28 +- .../nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h | 88 +- .../include/nvgpu/hw/gv100/hw_usermode_gv100.h | 18 +- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h | 42 +- .../nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h | 74 +- 27 files changed, 3008 insertions(+), 3008 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h index 2c89ccd6..7771f1ea 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h @@ -58,170 +58,170 @@ static inline u32 bus_sw_scratch_r(u32 i) { - return 0x00001580 + i*4; + return 0x00001580U + i*4U; } static inline u32 bus_bar0_window_r(void) { - return 0x00001700; + return 0x00001700U; } static inline u32 bus_bar0_window_base_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 bus_bar0_window_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 bus_bar1_block_r(void) { - return 0x00001704; + return 0x00001704U; } static inline u32 bus_bar1_block_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 bus_bar1_block_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 bus_bar1_block_mode_virtual_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 bus_bar2_block_r(void) { - return 0x00001714; + return 0x00001714U; } static inline u32 bus_bar2_block_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 bus_bar2_block_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 bus_bar2_block_mode_virtual_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 bus_bar1_block_ptr_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 bus_bar2_block_ptr_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 bus_bind_status_r(void) { - return 0x00001710; + return 0x00001710U; } static inline u32 bus_bind_status_bar1_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 bus_bind_status_bar1_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar1_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 bus_bind_status_bar1_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar1_outstanding_true_f(void) { - return 0x2; + return 0x2U; } static inline u32 bus_bind_status_bar2_pending_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 bus_bind_status_bar2_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar2_pending_busy_f(void) { - return 0x4; + return 0x4U; } static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 bus_bind_status_bar2_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 bus_bind_status_bar2_outstanding_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 bus_intr_0_r(void) { - return 0x00001100; + return 0x00001100U; } static inline u32 bus_intr_0_pri_squash_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 bus_intr_0_pri_fecserr_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 bus_intr_0_pri_timeout_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 bus_intr_en_0_r(void) { - return 0x00001140; + return 0x00001140U; } static inline u32 bus_intr_en_0_pri_squash_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 bus_intr_en_0_pri_fecserr_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 bus_intr_en_0_pri_timeout_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index ae0179f2..b1478037 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h @@ -58,130 +58,130 @@ static inline u32 ccsr_channel_inst_r(u32 i) { - return 0x00800000 + i*8; + return 0x00800000U + i*8U; } static inline u32 ccsr_channel_inst__size_1_v(void) { - return 0x00001000; + return 0x00001000U; } static inline u32 ccsr_channel_inst_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 ccsr_channel_inst_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 ccsr_channel_inst_bind_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 ccsr_channel_inst_bind_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 ccsr_channel_r(u32 i) { - return 0x00800004 + i*8; + return 0x00800004U + i*8U; } static inline u32 ccsr_channel__size_1_v(void) { - return 0x00001000; + return 0x00001000U; } static inline u32 ccsr_channel_enable_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ccsr_channel_enable_set_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 ccsr_channel_enable_set_true_f(void) { - return 0x400; + return 0x400U; } static inline u32 ccsr_channel_enable_clr_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 ccsr_channel_status_v(u32 r) { - return (r >> 24) & 0xf; + return (r >> 24U) & 0xfU; } static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) { - return 0x0000000a; + return 0x0000000aU; } static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) { - return 0x0000000d; + return 0x0000000dU; } static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 ccsr_channel_next_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 ccsr_channel_next_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ccsr_channel_force_ctx_reload_true_f(void) { - return 0x100; + return 0x100U; } static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 ccsr_channel_eng_faulted_f(u32 v) { - return (v & 0x1) << 23; + return (v & 0x1U) << 23U; } static inline u32 ccsr_channel_eng_faulted_v(u32 r) { - return (r >> 23) & 0x1; + return (r >> 23U) & 0x1U; } static inline u32 ccsr_channel_eng_faulted_reset_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 ccsr_channel_eng_faulted_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ccsr_channel_busy_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h index 6923d921..18b5fc66 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ce_gv100.h @@ -58,50 +58,50 @@ static inline u32 ce_intr_status_r(u32 i) { - return 0x00104410 + i*128; + return 0x00104410U + i*128U; } static inline u32 ce_intr_status_blockpipe_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ce_intr_status_blockpipe_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 ce_intr_status_nonblockpipe_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 ce_intr_status_nonblockpipe_reset_f(void) { - return 0x2; + return 0x2U; } static inline u32 ce_intr_status_launcherr_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 ce_intr_status_launcherr_reset_f(void) { - return 0x4; + return 0x4U; } static inline u32 ce_intr_status_invalid_config_pending_f(void) { - return 0x8; + return 0x8U; } static inline u32 ce_intr_status_invalid_config_reset_f(void) { - return 0x8; + return 0x8U; } static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) { - return 0x10; + return 0x10U; } static inline u32 ce_pce_map_r(void) { - return 0x00104028; + return 0x00104028U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h index 86075656..cd792835 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h @@ -58,398 +58,398 @@ static inline u32 ctxsw_prog_fecs_header_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ctxsw_prog_main_image_ctl_o(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) { - return 0x00000011; + return 0x00000011U; } static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) { - return 0x00000012; + return 0x00000012U; } static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) { - return 0x00000021; + return 0x00000021U; } static inline u32 ctxsw_prog_main_image_patch_count_o(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ctxsw_prog_main_image_context_id_o(void) { - return 0x000000f0; + return 0x000000f0U; } static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) { - return 0x00000014; + return 0x00000014U; } static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) { - return 0x00000018; + return 0x00000018U; } static inline u32 ctxsw_prog_main_image_zcull_o(void) { - return 0x0000001c; + return 0x0000001cU; } static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 ctxsw_prog_main_image_pm_o(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 ctxsw_prog_main_image_pm_mode_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) { - return 0x7 << 3; + return 0x7U << 3U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) { - return 0x8; + return 0x8U; } static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) { - return 0x0000002c; + return 0x0000002cU; } static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) { - return 0x000000d0; + return 0x000000d0U; } static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) { - return 0x000000d4; + return 0x000000d4U; } static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) { - return 0x000000d8; + return 0x000000d8U; } static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) { - return 0x000000dc; + return 0x000000dcU; } static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) { - return 0x00000060; + return 0x00000060U; } static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) { - return 0x00000094; + return 0x00000094U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) { - return 0x00000068; + return 0x00000068U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) { - return 0x00000070; + return 0x00000070U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) { - return 0x00000074; + return 0x00000074U; } static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) { - return 0x00000078; + return 0x00000078U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) { - return 0x0000007c; + return 0x0000007cU; } static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_magic_value_o(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) { - return 0x600dc0de; + return 0x600dc0deU; } static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) { - return 0x000000b8; + return 0x000000b8U; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) { - return 0x000000bc; + return 0x000000bcU; } static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) { - return 0x000000c4; + return 0x000000c4U; } static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) { - return 0x000000c8; + return 0x000000c8U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) { - return 0x000000cc; + return 0x000000ccU; } static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) { - return 0x000000e0; + return 0x000000e0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) { - return 0x000000e4; + return 0x000000e4U; } static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ctxsw_prog_local_image_ppc_info_o(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) { - return (r >> 16) & 0xffff; + return (r >> 16U) & 0xffffU; } static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 ctxsw_prog_local_magic_value_o(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) { - return 0xad0becab; + return 0xad0becabU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) { - return 0x000000ec; + return 0x000000ecU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) { - return 0x000000a0; + return 0x000000a0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) { - return 2; + return 2U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) { - return 0x2; + return 0x2U; } static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) { - return 0x000000a4; + return 0x000000a4U; } static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) { - return 0x000000a8; + return 0x000000a8U; } static inline u32 ctxsw_prog_main_image_misc_options_o(void) { - return 0x0000003c; + return 0x0000003cU; } static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) { - return 0x1; + return 0x1U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) { - return 0x00000084; + return 0x00000084U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) { - return 0x1; + return 0x1U; } static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) { - return 0x2; + return 0x2U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h index 33c08bad..3bba3fb8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -58,1418 +58,1418 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void) { - return 0x00100800; + return 0x00100800U; } static inline u32 fb_mmu_ctrl_r(void) { - return 0x00100c80; + return 0x00100c80U; } static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) { - return (r >> 11) & 0x1; + return (r >> 11U) & 0x1U; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_priv_mmu_phy_secure_r(void) { - return 0x00100ce4; + return 0x00100ce4U; } static inline u32 fb_mmu_invalidate_pdb_r(void) { - return 0x00100cb8; + return 0x00100cb8U; } static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_invalidate_r(void) { - return 0x00100cbc; + return 0x00100cbcU; } static inline u32 fb_mmu_invalidate_all_va_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_invalidate_replay_s(void) { - return 3; + return 3U; } static inline u32 fb_mmu_invalidate_replay_f(u32 v) { - return (v & 0x7) << 3; + return (v & 0x7U) << 3U; } static inline u32 fb_mmu_invalidate_replay_m(void) { - return 0x7 << 3; + return 0x7U << 3U; } static inline u32 fb_mmu_invalidate_replay_v(u32 r) { - return (r >> 3) & 0x7; + return (r >> 3U) & 0x7U; } static inline u32 fb_mmu_invalidate_replay_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_replay_start_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_invalidate_sys_membar_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 fb_mmu_invalidate_sys_membar_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 6U) & 0x1U; } static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_invalidate_ack_s(void) { - return 2; + return 2U; } static inline u32 fb_mmu_invalidate_ack_f(u32 v) { - return (v & 0x3) << 7; + return (v & 0x3U) << 7U; } static inline u32 fb_mmu_invalidate_ack_m(void) { - return 0x3 << 7; + return 0x3U << 7U; } static inline u32 fb_mmu_invalidate_ack_v(u32 r) { - return (r >> 7) & 0x3; + return (r >> 7U) & 0x3U; } static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) { - return 0x100; + return 0x100U; } static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) { - return 6; + return 6U; } static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) { - return (v & 0x3f) << 9; + return (v & 0x3fU) << 9U; } static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) { - return 0x3f << 9; + return 0x3fU << 9U; } static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) { - return (r >> 9) & 0x3f; + return (r >> 9U) & 0x3fU; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) { - return 5; + return 5U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) { - return (v & 0x1f) << 15; + return (v & 0x1fU) << 15U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) { - return 0x1f << 15; + return 0x1fU << 15U; } static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) { - return (r >> 15) & 0x1f; + return (r >> 15U) & 0x1fU; } static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) { - return 3; + return 3U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) { - return (v & 0x7) << 24; + return (v & 0x7U) << 24U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) { - return 0x7 << 24; + return 0x7U << 24U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) { - return (r >> 24) & 0x7; + return (r >> 24U) & 0x7U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) { - return 0x5000000; + return 0x5000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) { - return 0x6000000; + return 0x6000000U; } static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) { - return 0x7000000; + return 0x7000000U; } static inline u32 fb_mmu_invalidate_trigger_s(void) { - return 1; + return 1U; } static inline u32 fb_mmu_invalidate_trigger_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_invalidate_trigger_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_invalidate_trigger_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_invalidate_trigger_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_debug_wr_r(void) { - return 0x00100cc8; + return 0x00100cc8U; } static inline u32 fb_mmu_debug_wr_aperture_s(void) { - return 2; + return 2U; } static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 fb_mmu_debug_wr_aperture_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_debug_wr_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_wr_vol_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_debug_wr_vol_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_debug_wr_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fb_mmu_debug_rd_r(void) { - return 0x00100ccc; + return 0x00100cccU; } static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_debug_rd_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_debug_rd_addr_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fb_mmu_debug_ctrl_r(void) { - return 0x00100cc4; + return 0x00100cc4U; } static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 fb_mmu_debug_ctrl_debug_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_vpr_info_r(void) { - return 0x00100cd0; + return 0x00100cd0U; } static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 fb_mmu_vpr_info_fetch_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_vpr_info_fetch_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_niso_flush_sysmem_addr_r(void) { - return 0x00100c10; + return 0x00100c10U; } static inline u32 fb_niso_intr_r(void) { - return 0x00100a20; + return 0x00100a20U; } static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_r(u32 i) { - return 0x00100a24 + i*4; + return 0x00100a24U + i*4U; } static inline u32 fb_niso_intr_en__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) { - return (v & 0x1) << 27; + return (v & 0x1U) << 27U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_set_r(u32 i) { - return 0x00100a2c + i*4; + return 0x00100a2cU + i*4U; } static inline u32 fb_niso_intr_en_set__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_clr_r(u32 i) { - return 0x00100a34 + i*4; + return 0x00100a34U + i*4U; } static inline u32 fb_niso_intr_en_clr__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) { - return 0x1 << 27; + return 0x1U << 27U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) { - return 0x1 << 28; + return 0x1U << 28U; } static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) { - return 0x1 << 29; + return 0x1U << 29U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) { - return 0x00100e24 + i*20; + return 0x00100e24U + i*20U; } static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) { - return (v & 0x3) << 1; + return (v & 0x3U) << 1U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) { - return (r >> 1) & 0x3; + return (r >> 1U) & 0x3U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) { - return 0x00100e28 + i*20; + return 0x00100e28U + i*20U; } static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_buffer_get_r(u32 i) { - return 0x00100e2c + i*20; + return 0x00100e2cU + i*20U; } static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) { - return 0xfffff << 0; + return 0xfffffU << 0U; } static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_buffer_put_r(u32 i) { - return 0x00100e30 + i*20; + return 0x00100e30U + i*20U; } static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_buffer_size_r(u32 i) { - return 0x00100e34 + i*20; + return 0x00100e34U + i*20U; } static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) { - return (v & 0xfffff) << 0; + return (v & 0xfffffU) << 0U; } static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0U) & 0xfffffU; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 fb_mmu_fault_buffer_size_enable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_addr_lo_r(void) { - return 0x00100e4c; + return 0x00100e4cU; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_addr_hi_r(void) { - return 0x00100e50; + return 0x00100e50U; } static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_inst_lo_r(void) { - return 0x00100e54; + return 0x00100e54U; } static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) { - return (r >> 10) & 0x3; + return (r >> 10U) & 0x3U; } static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) { - return (r >> 12) & 0xfffff; + return (r >> 12U) & 0xfffffU; } static inline u32 fb_mmu_fault_inst_hi_r(void) { - return 0x00100e58; + return 0x00100e58U; } static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 fb_mmu_fault_info_r(void) { - return 0x00100e5c; + return 0x00100e5cU; } static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) { - return (r >> 7) & 0x1; + return (r >> 7U) & 0x1U; } static inline u32 fb_mmu_fault_info_client_v(u32 r) { - return (r >> 8) & 0x7f; + return (r >> 8U) & 0x7fU; } static inline u32 fb_mmu_fault_info_access_type_v(u32 r) { - return (r >> 16) & 0xf; + return (r >> 16U) & 0xfU; } static inline u32 fb_mmu_fault_info_client_type_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) { - return (r >> 24) & 0x1f; + return (r >> 24U) & 0x1fU; } static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_mmu_fault_info_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fb_mmu_fault_status_r(void) { - return 0x00100e60; + return 0x00100e60U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) { - return 0x1; + return 0x1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) { - return 0x2; + return 0x2U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) { - return 0x4; + return 0x4U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) { - return 0x8; + return 0x8U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) { - return 0x10; + return 0x10U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) { - return 0x20; + return 0x20U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) { - return 0x40; + return 0x40U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) { - return 0x80; + return 0x80U; } static inline u32 fb_mmu_fault_status_replayable_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 fb_mmu_fault_status_replayable_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_set_f(void) { - return 0x100; + return 0x100U; } static inline u32 fb_mmu_fault_status_replayable_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) { - return 0x200; + return 0x200U; } static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_error_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) { - return 0x400; + return 0x400U; } static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) { - return 0x800; + return 0x800U; } static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) { - return 0x1 << 13; + return 0x1U << 13U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) { - return 0x0; + return 0x0U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) { - return 0x1 << 14; + return 0x1U << 14U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 fb_mmu_fault_status_busy_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 fb_mmu_fault_status_busy_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_busy_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fb_mmu_fault_status_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 fb_mmu_fault_status_valid_set_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_valid_set_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_fault_status_valid_clear_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fb_mmu_fault_status_valid_clear_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fb_mmu_local_memory_range_r(void) { - return 0x00100ce0; + return 0x00100ce0U; } static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r) { - return (r >> 4) & 0x3f; + return (r >> 4U) & 0x3fU; } static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fb_niso_scrub_status_r(void) { - return 0x00100b20; + return 0x00100b20U; } static inline u32 fb_niso_scrub_status_flag_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fb_mmu_priv_level_mask_r(void) { - return 0x00100cdc; + return 0x00100cdcU; } static inline u32 fb_mmu_priv_level_mask_write_violation_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h index 1578a124..743afb1e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fifo_gv100.h @@ -58,494 +58,494 @@ static inline u32 fifo_bar1_base_r(void) { - return 0x00002254; + return 0x00002254U; } static inline u32 fifo_bar1_base_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 fifo_bar1_base_ptr_align_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 fifo_bar1_base_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_bar1_base_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fifo_userd_writeback_r(void) { - return 0x0000225c; + return 0x0000225cU; } static inline u32 fifo_userd_writeback_timer_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fifo_userd_writeback_timer_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_userd_writeback_timer_shorter_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 fifo_userd_writeback_timer_100us_v(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 fifo_userd_writeback_timescale_f(u32 v) { - return (v & 0xf) << 12; + return (v & 0xfU) << 12U; } static inline u32 fifo_userd_writeback_timescale_0_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_runlist_base_r(void) { - return 0x00002270; + return 0x00002270U; } static inline u32 fifo_runlist_base_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 fifo_runlist_base_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 fifo_runlist_r(void) { - return 0x00002274; + return 0x00002274U; } static inline u32 fifo_runlist_engine_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 fifo_eng_runlist_base_r(u32 i) { - return 0x00002280 + i*8; + return 0x00002280U + i*8U; } static inline u32 fifo_eng_runlist_base__size_1_v(void) { - return 0x0000000d; + return 0x0000000dU; } static inline u32 fifo_eng_runlist_r(u32 i) { - return 0x00002284 + i*8; + return 0x00002284U + i*8U; } static inline u32 fifo_eng_runlist__size_1_v(void) { - return 0x0000000d; + return 0x0000000dU; } static inline u32 fifo_eng_runlist_length_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fifo_eng_runlist_length_max_v(void) { - return 0x0000ffff; + return 0x0000ffffU; } static inline u32 fifo_eng_runlist_pending_true_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fifo_pb_timeslice_r(u32 i) { - return 0x00002350 + i*4; + return 0x00002350U + i*4U; } static inline u32 fifo_pb_timeslice_timeout_16_f(void) { - return 0x10; + return 0x10U; } static inline u32 fifo_pb_timeslice_timescale_0_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_pb_timeslice_enable_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 fifo_pbdma_map_r(u32 i) { - return 0x00002390 + i*4; + return 0x00002390U + i*4U; } static inline u32 fifo_intr_0_r(void) { - return 0x00002100; + return 0x00002100U; } static inline u32 fifo_intr_0_bind_error_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_intr_0_bind_error_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_intr_0_sched_error_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 fifo_intr_0_sched_error_reset_f(void) { - return 0x100; + return 0x100U; } static inline u32 fifo_intr_0_chsw_error_pending_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 fifo_intr_0_chsw_error_reset_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 fifo_intr_0_lb_error_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_intr_0_lb_error_reset_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 fifo_intr_0_runlist_event_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 fifo_intr_0_channel_intr_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 fifo_intr_en_0_r(void) { - return 0x00002140; + return 0x00002140U; } static inline u32 fifo_intr_en_0_sched_error_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 fifo_intr_en_0_sched_error_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 fifo_intr_en_1_r(void) { - return 0x00002528; + return 0x00002528U; } static inline u32 fifo_intr_bind_error_r(void) { - return 0x0000252c; + return 0x0000252cU; } static inline u32 fifo_intr_sched_error_r(void) { - return 0x0000254c; + return 0x0000254cU; } static inline u32 fifo_intr_sched_error_code_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fifo_intr_chsw_error_r(void) { - return 0x0000256c; + return 0x0000256cU; } static inline u32 fifo_intr_pbdma_id_r(void) { - return 0x000025a0; + return 0x000025a0U; } static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) { - return (r >> (0 + i*1)) & 0x1; + return (r >> (0U + i*1U)) & 0x1U; } static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 fifo_intr_runlist_r(void) { - return 0x00002a00; + return 0x00002a00U; } static inline u32 fifo_fb_timeout_r(void) { - return 0x00002a04; + return 0x00002a04U; } static inline u32 fifo_fb_timeout_period_m(void) { - return 0x3fffffff << 0; + return 0x3fffffffU << 0U; } static inline u32 fifo_fb_timeout_period_max_f(void) { - return 0x3fffffff; + return 0x3fffffffU; } static inline u32 fifo_fb_timeout_period_init_f(void) { - return 0x3c00; + return 0x3c00U; } static inline u32 fifo_sched_disable_r(void) { - return 0x00002630; + return 0x00002630U; } static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_sched_disable_runlist_m(u32 i) { - return 0x1 << (0 + i*1); + return 0x1U << (0U + i*1U); } static inline u32 fifo_sched_disable_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_runlist_preempt_r(void) { - return 0x00002638; + return 0x00002638U; } static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 fifo_runlist_preempt_runlist_m(u32 i) { - return 0x1 << (0 + i*1); + return 0x1U << (0U + i*1U); } static inline u32 fifo_runlist_preempt_runlist_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_preempt_r(void) { - return 0x00002634; + return 0x00002634U; } static inline u32 fifo_preempt_pending_true_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 fifo_preempt_type_channel_f(void) { - return 0x0; + return 0x0U; } static inline u32 fifo_preempt_type_tsg_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 fifo_preempt_chid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 fifo_preempt_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 fifo_engine_status_r(u32 i) { - return 0x00002640 + i*8; + return 0x00002640U + i*8U; } static inline u32 fifo_engine_status__size_1_v(void) { - return 0x0000000f; + return 0x0000000fU; } static inline u32 fifo_engine_status_id_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 fifo_engine_status_id_type_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 fifo_engine_status_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_id_type_tsgid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctx_status_v(u32 r) { - return (r >> 13) & 0x7; + return (r >> 13U) & 0x7U; } static inline u32 fifo_engine_status_ctx_status_valid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 fifo_engine_status_next_id_v(u32 r) { - return (r >> 16) & 0xfff; + return (r >> 16U) & 0xfffU; } static inline u32 fifo_engine_status_next_id_type_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 fifo_engine_status_next_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_eng_reload_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 fifo_engine_status_faulted_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 fifo_engine_status_faulted_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_engine_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 fifo_engine_status_engine_idle_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_engine_status_engine_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctxsw_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 fifo_pbdma_status_r(u32 i) { - return 0x00003080 + i*4; + return 0x00003080U + i*4U; } static inline u32 fifo_pbdma_status__size_1_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 fifo_pbdma_status_id_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 fifo_pbdma_status_id_type_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 fifo_pbdma_status_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_pbdma_status_chan_status_v(u32 r) { - return (r >> 13) & 0x7; + return (r >> 13U) & 0x7U; } static inline u32 fifo_pbdma_status_chan_status_valid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 fifo_pbdma_status_next_id_v(u32 r) { - return (r >> 16) & 0xfff; + return (r >> 16U) & 0xfffU; } static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 fifo_pbdma_status_chsw_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 fifo_cfg0_r(void) { - return 0x00002004; + return 0x00002004U; } static inline u32 fifo_cfg0_num_pbdma_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 fifo_fb_iface_r(void) { - return 0x000026f0; + return 0x000026f0U; } static inline u32 fifo_fb_iface_control_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fifo_fb_iface_control_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 fifo_fb_iface_status_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 fifo_fb_iface_status_enabled_f(void) { - return 0x10; + return 0x10U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h index 549c2f8f..b6045626 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_flush_gv100.h @@ -58,130 +58,130 @@ static inline u32 flush_l2_system_invalidate_r(void) { - return 0x00070004; + return 0x00070004U; } static inline u32 flush_l2_system_invalidate_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_system_invalidate_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_system_invalidate_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_flush_dirty_r(void) { - return 0x00070010; + return 0x00070010U; } static inline u32 flush_l2_flush_dirty_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_flush_dirty_pending_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_flush_dirty_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_flush_dirty_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_flush_dirty_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_clean_comptags_r(void) { - return 0x0007000c; + return 0x0007000cU; } static inline u32 flush_l2_clean_comptags_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_l2_clean_comptags_pending_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_clean_comptags_pending_empty_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_clean_comptags_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_l2_clean_comptags_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_fb_flush_r(void) { - return 0x00070000; + return 0x00070000U; } static inline u32 flush_fb_flush_pending_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 flush_fb_flush_pending_busy_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 flush_fb_flush_pending_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 flush_fb_flush_outstanding_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 flush_fb_flush_outstanding_true_v(void) { - return 0x00000001; + return 0x00000001U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h index 0c2334da..f7eacd29 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h @@ -58,86 +58,86 @@ static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) { - return 0x00021c38 + i*4; + return 0x00021c38U + i*4U; } static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) { - return 0x00021838 + i*4; + return 0x00021838U + i*4U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) { - return 0x00021944; + return 0x00021944U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) { - return 0x00021948; + return 0x00021948U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) { - return 0x1; + return 0x1U; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) { - return 0x0; + return 0x0U; } static inline u32 fuse_status_opt_fbio_r(void) { - return 0x00021c14; + return 0x00021c14U; } static inline u32 fuse_status_opt_fbio_data_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 fuse_status_opt_fbio_data_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 fuse_status_opt_fbio_data_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) { - return 0x00021d70 + i*4; + return 0x00021d70U + i*4U; } static inline u32 fuse_status_opt_fbp_r(void) { - return 0x00021d38; + return 0x00021d38U; } static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) { - return (r >> (0 + i*1)) & 0x1; + return (r >> (0U + i*1U)) & 0x1U; } static inline u32 fuse_opt_ecc_en_r(void) { - return 0x00021228; + return 0x00021228U; } static inline u32 fuse_opt_feature_fuses_override_disable_r(void) { - return 0x000213f0; + return 0x000213f0U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h index 0aa2743d..cf89f5f8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gmmu_gv100.h @@ -58,1230 +58,1230 @@ static inline u32 gmmu_new_pde_is_pte_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_is_pte_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_aperture_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_aperture_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_aperture_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_pde_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pde_address_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_vol_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pde_vol_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_pde_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pde_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_new_pde__size_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_dual_pde_is_pte_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_big_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_aperture_small_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) { - return 0x2; + return 0x2U; } static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_dual_pde_vol_small_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_vol_big_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { - return 2; + return 2U; } static inline u32 gmmu_new_dual_pde_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_dual_pde__size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gmmu_new_pte__size_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_new_pte_valid_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_valid_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 gmmu_new_pte_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_privilege_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_privilege_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 gmmu_new_pte_privilege_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pte_address_sys_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_address_vid_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 gmmu_new_pte_address_vid_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_vol_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_vol_true_f(void) { - return 0x8; + return 0x8U; } static inline u32 gmmu_new_pte_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_aperture_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_aperture_video_memory_f(void) { - return 0x0; + return 0x0U; } static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) { - return 0x4; + return 0x4U; } static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) { - return 0x6; + return 0x6U; } static inline u32 gmmu_new_pte_read_only_w(void) { - return 0; + return 0U; } static inline u32 gmmu_new_pte_read_only_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 gmmu_new_pte_comptagline_f(u32 v) { - return (v & 0x3ffff) << 4; + return (v & 0x3ffffU) << 4U; } static inline u32 gmmu_new_pte_comptagline_w(void) { - return 1; + return 1U; } static inline u32 gmmu_new_pte_kind_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gmmu_new_pte_kind_w(void) { - return 1; + return 1U; } static inline u32 gmmu_new_pte_address_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gmmu_pte_kind_f(u32 v) { - return (v & 0xff) << 4; + return (v & 0xffU) << 4U; } static inline u32 gmmu_pte_kind_w(void) { - return 1; + return 1U; } static inline u32 gmmu_pte_kind_invalid_v(void) { - return 0x000000ff; + return 0x000000ffU; } static inline u32 gmmu_pte_kind_pitch_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gmmu_pte_kind_z16_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_pte_kind_z16_2c_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 gmmu_pte_kind_z16_2z_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) { - return 0x0000000a; + return 0x0000000aU; } static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 gmmu_pte_kind_z16_2cz_v(void) { - return 0x00000036; + return 0x00000036U; } static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) { - return 0x00000037; + return 0x00000037U; } static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) { - return 0x00000038; + return 0x00000038U; } static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) { - return 0x00000039; + return 0x00000039U; } static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) { - return 0x0000005f; + return 0x0000005fU; } static inline u32 gmmu_pte_kind_s8z24_v(void) { - return 0x00000011; + return 0x00000011U; } static inline u32 gmmu_pte_kind_s8z24_1z_v(void) { - return 0x00000012; + return 0x00000012U; } static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) { - return 0x00000013; + return 0x00000013U; } static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) { - return 0x00000014; + return 0x00000014U; } static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) { - return 0x00000015; + return 0x00000015U; } static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) { - return 0x00000016; + return 0x00000016U; } static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) { - return 0x00000017; + return 0x00000017U; } static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) { - return 0x00000018; + return 0x00000018U; } static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) { - return 0x00000019; + return 0x00000019U; } static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) { - return 0x0000001a; + return 0x0000001aU; } static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) { - return 0x0000001b; + return 0x0000001bU; } static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) { - return 0x0000001c; + return 0x0000001cU; } static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) { - return 0x0000001d; + return 0x0000001dU; } static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) { - return 0x0000001e; + return 0x0000001eU; } static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) { - return 0x0000001f; + return 0x0000001fU; } static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) { - return 0x00000021; + return 0x00000021U; } static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) { - return 0x00000022; + return 0x00000022U; } static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) { - return 0x00000023; + return 0x00000023U; } static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) { - return 0x00000024; + return 0x00000024U; } static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) { - return 0x00000025; + return 0x00000025U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) { - return 0x00000026; + return 0x00000026U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) { - return 0x00000027; + return 0x00000027U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) { - return 0x00000029; + return 0x00000029U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) { - return 0x0000002e; + return 0x0000002eU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) { - return 0x0000002f; + return 0x0000002fU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) { - return 0x00000031; + return 0x00000031U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) { - return 0x00000032; + return 0x00000032U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) { - return 0x00000033; + return 0x00000033U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) { - return 0x00000034; + return 0x00000034U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) { - return 0x00000035; + return 0x00000035U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) { - return 0x0000003a; + return 0x0000003aU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) { - return 0x0000003b; + return 0x0000003bU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) { - return 0x0000003c; + return 0x0000003cU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) { - return 0x0000003d; + return 0x0000003dU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) { - return 0x0000003e; + return 0x0000003eU; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) { - return 0x0000003f; + return 0x0000003fU; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) { - return 0x00000041; + return 0x00000041U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) { - return 0x00000042; + return 0x00000042U; } static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) { - return 0x00000043; + return 0x00000043U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) { - return 0x00000044; + return 0x00000044U; } static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) { - return 0x00000045; + return 0x00000045U; } static inline u32 gmmu_pte_kind_z24s8_v(void) { - return 0x00000046; + return 0x00000046U; } static inline u32 gmmu_pte_kind_z24s8_1z_v(void) { - return 0x00000047; + return 0x00000047U; } static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) { - return 0x00000048; + return 0x00000048U; } static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) { - return 0x00000049; + return 0x00000049U; } static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) { - return 0x0000004a; + return 0x0000004aU; } static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) { - return 0x0000004b; + return 0x0000004bU; } static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) { - return 0x0000004c; + return 0x0000004cU; } static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) { - return 0x0000004d; + return 0x0000004dU; } static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) { - return 0x0000004e; + return 0x0000004eU; } static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) { - return 0x0000004f; + return 0x0000004fU; } static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) { - return 0x00000050; + return 0x00000050U; } static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) { - return 0x00000051; + return 0x00000051U; } static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) { - return 0x00000052; + return 0x00000052U; } static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) { - return 0x00000053; + return 0x00000053U; } static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) { - return 0x00000054; + return 0x00000054U; } static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) { - return 0x00000055; + return 0x00000055U; } static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) { - return 0x00000056; + return 0x00000056U; } static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) { - return 0x00000057; + return 0x00000057U; } static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) { - return 0x00000058; + return 0x00000058U; } static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) { - return 0x00000059; + return 0x00000059U; } static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) { - return 0x0000005a; + return 0x0000005aU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) { - return 0x0000005b; + return 0x0000005bU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) { - return 0x0000005c; + return 0x0000005cU; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) { - return 0x0000005d; + return 0x0000005dU; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) { - return 0x0000005e; + return 0x0000005eU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) { - return 0x00000063; + return 0x00000063U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) { - return 0x00000064; + return 0x00000064U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) { - return 0x00000065; + return 0x00000065U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) { - return 0x00000066; + return 0x00000066U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) { - return 0x00000067; + return 0x00000067U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) { - return 0x00000068; + return 0x00000068U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) { - return 0x00000069; + return 0x00000069U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) { - return 0x0000006a; + return 0x0000006aU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) { - return 0x0000006f; + return 0x0000006fU; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) { - return 0x00000070; + return 0x00000070U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) { - return 0x00000071; + return 0x00000071U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) { - return 0x00000072; + return 0x00000072U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) { - return 0x00000073; + return 0x00000073U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) { - return 0x00000074; + return 0x00000074U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) { - return 0x00000075; + return 0x00000075U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) { - return 0x00000076; + return 0x00000076U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) { - return 0x00000077; + return 0x00000077U; } static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) { - return 0x00000078; + return 0x00000078U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) { - return 0x00000079; + return 0x00000079U; } static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) { - return 0x0000007a; + return 0x0000007aU; } static inline u32 gmmu_pte_kind_zf32_v(void) { - return 0x0000007b; + return 0x0000007bU; } static inline u32 gmmu_pte_kind_zf32_1z_v(void) { - return 0x0000007c; + return 0x0000007cU; } static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) { - return 0x0000007d; + return 0x0000007dU; } static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) { - return 0x0000007e; + return 0x0000007eU; } static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) { - return 0x0000007f; + return 0x0000007fU; } static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 gmmu_pte_kind_zf32_2cs_v(void) { - return 0x00000081; + return 0x00000081U; } static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) { - return 0x00000082; + return 0x00000082U; } static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) { - return 0x00000083; + return 0x00000083U; } static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) { - return 0x00000084; + return 0x00000084U; } static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) { - return 0x00000085; + return 0x00000085U; } static inline u32 gmmu_pte_kind_zf32_2cz_v(void) { - return 0x00000086; + return 0x00000086U; } static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) { - return 0x00000087; + return 0x00000087U; } static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) { - return 0x00000088; + return 0x00000088U; } static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) { - return 0x00000089; + return 0x00000089U; } static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) { - return 0x0000008a; + return 0x0000008aU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) { - return 0x0000008b; + return 0x0000008bU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) { - return 0x0000008c; + return 0x0000008cU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) { - return 0x0000008d; + return 0x0000008dU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) { - return 0x0000008e; + return 0x0000008eU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) { - return 0x0000008f; + return 0x0000008fU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) { - return 0x00000090; + return 0x00000090U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) { - return 0x00000091; + return 0x00000091U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) { - return 0x00000092; + return 0x00000092U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) { - return 0x00000097; + return 0x00000097U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) { - return 0x00000098; + return 0x00000098U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) { - return 0x00000099; + return 0x00000099U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) { - return 0x0000009a; + return 0x0000009aU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) { - return 0x0000009b; + return 0x0000009bU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) { - return 0x0000009c; + return 0x0000009cU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) { - return 0x0000009d; + return 0x0000009dU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) { - return 0x0000009e; + return 0x0000009eU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) { - return 0x0000009f; + return 0x0000009fU; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) { - return 0x000000a0; + return 0x000000a0U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) { - return 0x000000a1; + return 0x000000a1U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) { - return 0x000000a2; + return 0x000000a2U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) { - return 0x000000a3; + return 0x000000a3U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) { - return 0x000000a4; + return 0x000000a4U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) { - return 0x000000a5; + return 0x000000a5U; } static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) { - return 0x000000a6; + return 0x000000a6U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) { - return 0x000000a7; + return 0x000000a7U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) { - return 0x000000a8; + return 0x000000a8U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) { - return 0x000000a9; + return 0x000000a9U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) { - return 0x000000aa; + return 0x000000aaU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) { - return 0x000000ab; + return 0x000000abU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) { - return 0x000000ac; + return 0x000000acU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) { - return 0x000000ad; + return 0x000000adU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) { - return 0x000000ae; + return 0x000000aeU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) { - return 0x000000b3; + return 0x000000b3U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) { - return 0x000000b4; + return 0x000000b4U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) { - return 0x000000b5; + return 0x000000b5U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) { - return 0x000000b6; + return 0x000000b6U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) { - return 0x000000b7; + return 0x000000b7U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) { - return 0x000000b8; + return 0x000000b8U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) { - return 0x000000b9; + return 0x000000b9U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) { - return 0x000000ba; + return 0x000000baU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) { - return 0x000000bb; + return 0x000000bbU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) { - return 0x000000bc; + return 0x000000bcU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) { - return 0x000000bd; + return 0x000000bdU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) { - return 0x000000be; + return 0x000000beU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) { - return 0x000000bf; + return 0x000000bfU; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) { - return 0x000000c1; + return 0x000000c1U; } static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) { - return 0x000000c2; + return 0x000000c2U; } static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) { - return 0x000000c3; + return 0x000000c3U; } static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) { - return 0x000000c4; + return 0x000000c4U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) { - return 0x000000c5; + return 0x000000c5U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) { - return 0x000000c6; + return 0x000000c6U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) { - return 0x000000c7; + return 0x000000c7U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) { - return 0x000000c8; + return 0x000000c8U; } static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) { - return 0x000000ce; + return 0x000000ceU; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) { - return 0x000000cf; + return 0x000000cfU; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) { - return 0x000000d0; + return 0x000000d0U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) { - return 0x000000d1; + return 0x000000d1U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) { - return 0x000000d2; + return 0x000000d2U; } static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) { - return 0x000000d3; + return 0x000000d3U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) { - return 0x000000d4; + return 0x000000d4U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) { - return 0x000000d5; + return 0x000000d5U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) { - return 0x000000d6; + return 0x000000d6U; } static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) { - return 0x000000d7; + return 0x000000d7U; } static inline u32 gmmu_pte_kind_generic_16bx2_v(void) { - return 0x000000fe; + return 0x000000feU; } static inline u32 gmmu_pte_kind_c32_2c_v(void) { - return 0x000000d8; + return 0x000000d8U; } static inline u32 gmmu_pte_kind_c32_2cbr_v(void) { - return 0x000000d9; + return 0x000000d9U; } static inline u32 gmmu_pte_kind_c32_2cba_v(void) { - return 0x000000da; + return 0x000000daU; } static inline u32 gmmu_pte_kind_c32_2cra_v(void) { - return 0x000000db; + return 0x000000dbU; } static inline u32 gmmu_pte_kind_c32_2bra_v(void) { - return 0x000000dc; + return 0x000000dcU; } static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) { - return 0x000000dd; + return 0x000000ddU; } static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) { - return 0x000000de; + return 0x000000deU; } static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) { - return 0x000000cc; + return 0x000000ccU; } static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) { - return 0x000000df; + return 0x000000dfU; } static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) { - return 0x000000e0; + return 0x000000e0U; } static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) { - return 0x000000e1; + return 0x000000e1U; } static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) { - return 0x000000e2; + return 0x000000e2U; } static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) { - return 0x000000e3; + return 0x000000e3U; } static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) { - return 0x0000002c; + return 0x0000002cU; } static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) { - return 0x000000e4; + return 0x000000e4U; } static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) { - return 0x000000e5; + return 0x000000e5U; } static inline u32 gmmu_pte_kind_c64_2c_v(void) { - return 0x000000e6; + return 0x000000e6U; } static inline u32 gmmu_pte_kind_c64_2cbr_v(void) { - return 0x000000e7; + return 0x000000e7U; } static inline u32 gmmu_pte_kind_c64_2cba_v(void) { - return 0x000000e8; + return 0x000000e8U; } static inline u32 gmmu_pte_kind_c64_2cra_v(void) { - return 0x000000e9; + return 0x000000e9U; } static inline u32 gmmu_pte_kind_c64_2bra_v(void) { - return 0x000000ea; + return 0x000000eaU; } static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) { - return 0x000000eb; + return 0x000000ebU; } static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) { - return 0x000000ec; + return 0x000000ecU; } static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) { - return 0x000000cd; + return 0x000000cdU; } static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) { - return 0x000000ed; + return 0x000000edU; } static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) { - return 0x000000ee; + return 0x000000eeU; } static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) { - return 0x000000ef; + return 0x000000efU; } static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) { - return 0x000000f0; + return 0x000000f0U; } static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) { - return 0x000000f1; + return 0x000000f1U; } static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) { - return 0x0000002d; + return 0x0000002dU; } static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) { - return 0x000000f2; + return 0x000000f2U; } static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) { - return 0x000000f3; + return 0x000000f3U; } static inline u32 gmmu_pte_kind_c128_2c_v(void) { - return 0x000000f4; + return 0x000000f4U; } static inline u32 gmmu_pte_kind_c128_2cr_v(void) { - return 0x000000f5; + return 0x000000f5U; } static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) { - return 0x000000f6; + return 0x000000f6U; } static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) { - return 0x000000f7; + return 0x000000f7U; } static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) { - return 0x000000f8; + return 0x000000f8U; } static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) { - return 0x000000f9; + return 0x000000f9U; } static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) { - return 0x000000fa; + return 0x000000faU; } static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) { - return 0x000000fb; + return 0x000000fbU; } static inline u32 gmmu_pte_kind_x8c24_v(void) { - return 0x000000fc; + return 0x000000fcU; } static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) { - return 0x000000fd; + return 0x000000fdU; } static inline u32 gmmu_pte_kind_smsked_message_v(void) { - return 0x000000ca; + return 0x000000caU; } static inline u32 gmmu_pte_kind_smhost_message_v(void) { - return 0x000000cb; + return 0x000000cbU; } static inline u32 gmmu_pte_kind_s8_v(void) { - return 0x0000002a; + return 0x0000002aU; } static inline u32 gmmu_pte_kind_s8_2s_v(void) { - return 0x0000002b; + return 0x0000002bU; } static inline u32 gmmu_fault_client_type_gpc_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gmmu_fault_client_type_hub_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gmmu_fault_type_unbound_inst_block_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) { - return 0x0000001f; + return 0x0000001fU; } static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) { - return 0x0000000f; + return 0x0000000fU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h index 750070ad..bdd749d0 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -58,3854 +58,3854 @@ static inline u32 gr_intr_r(void) { - return 0x00400100; + return 0x00400100U; } static inline u32 gr_intr_notify_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_intr_notify_reset_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_intr_semaphore_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_semaphore_reset_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_illegal_method_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_intr_illegal_method_reset_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_intr_illegal_notify_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_intr_illegal_notify_reset_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_intr_firmware_method_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 gr_intr_firmware_method_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_intr_firmware_method_reset_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_intr_illegal_class_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_intr_illegal_class_reset_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_intr_fecs_error_pending_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_intr_fecs_error_reset_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_intr_class_error_pending_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_intr_class_error_reset_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_intr_exception_pending_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_intr_exception_reset_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_fecs_intr_r(void) { - return 0x00400144; + return 0x00400144U; } static inline u32 gr_class_error_r(void) { - return 0x00400110; + return 0x00400110U; } static inline u32 gr_class_error_code_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_intr_nonstall_r(void) { - return 0x00400120; + return 0x00400120U; } static inline u32 gr_intr_nonstall_trap_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_intr_en_r(void) { - return 0x0040013c; + return 0x0040013cU; } static inline u32 gr_exception_r(void) { - return 0x00400108; + return 0x00400108U; } static inline u32 gr_exception_fe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_exception_gpc_m(void) { - return 0x1 << 24; + return 0x1U << 24U; } static inline u32 gr_exception_memfmt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_exception_ds_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_exception_sked_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_exception1_r(void) { - return 0x00400118; + return 0x00400118U; } static inline u32 gr_exception1_gpc_0_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_exception2_r(void) { - return 0x0040011c; + return 0x0040011cU; } static inline u32 gr_exception_en_r(void) { - return 0x00400138; + return 0x00400138U; } static inline u32 gr_exception_en_fe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_exception_en_fe_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_exception_en_gpc_m(void) { - return 0x1 << 24; + return 0x1U << 24U; } static inline u32 gr_exception_en_gpc_enabled_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 gr_exception_en_memfmt_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_exception_en_memfmt_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_exception_en_ds_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_exception_en_ds_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_exception1_en_r(void) { - return 0x00400130; + return 0x00400130U; } static inline u32 gr_exception2_en_r(void) { - return 0x00400134; + return 0x00400134U; } static inline u32 gr_gpfifo_ctl_r(void) { - return 0x00400500; + return 0x00400500U; } static inline u32 gr_gpfifo_ctl_access_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpfifo_ctl_access_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpfifo_ctl_access_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_gpfifo_status_r(void) { - return 0x00400504; + return 0x00400504U; } static inline u32 gr_trapped_addr_r(void) { - return 0x00400704; + return 0x00400704U; } static inline u32 gr_trapped_addr_mthd_v(u32 r) { - return (r >> 2) & 0xfff; + return (r >> 2U) & 0xfffU; } static inline u32 gr_trapped_addr_subch_v(u32 r) { - return (r >> 16) & 0x7; + return (r >> 16U) & 0x7U; } static inline u32 gr_trapped_data_lo_r(void) { - return 0x00400708; + return 0x00400708U; } static inline u32 gr_trapped_data_hi_r(void) { - return 0x0040070c; + return 0x0040070cU; } static inline u32 gr_status_r(void) { - return 0x00400700; + return 0x00400700U; } static inline u32 gr_status_fe_method_upper_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_status_fe_method_lower_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 gr_status_fe_method_lower_idle_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_status_fe_gi_v(u32 r) { - return (r >> 21) & 0x1; + return (r >> 21U) & 0x1U; } static inline u32 gr_status_mask_r(void) { - return 0x00400610; + return 0x00400610U; } static inline u32 gr_status_1_r(void) { - return 0x00400604; + return 0x00400604U; } static inline u32 gr_status_2_r(void) { - return 0x00400608; + return 0x00400608U; } static inline u32 gr_engine_status_r(void) { - return 0x0040060c; + return 0x0040060cU; } static inline u32 gr_engine_status_value_busy_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_pri_be0_becs_be_exception_r(void) { - return 0x00410204; + return 0x00410204U; } static inline u32 gr_pri_be0_becs_be_exception_en_r(void) { - return 0x00410208; + return 0x00410208U; } static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) { - return 0x00502c90; + return 0x00502c90U; } static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) { - return 0x00502c94; + return 0x00502c94U; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) { - return 0x00504508; + return 0x00504508U; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { - return 0x0050450c; + return 0x0050450cU; } static inline u32 gr_activity_0_r(void) { - return 0x00400380; + return 0x00400380U; } static inline u32 gr_activity_1_r(void) { - return 0x00400384; + return 0x00400384U; } static inline u32 gr_activity_2_r(void) { - return 0x00400388; + return 0x00400388U; } static inline u32 gr_activity_4_r(void) { - return 0x00400390; + return 0x00400390U; } static inline u32 gr_activity_4_gpc0_s(void) { - return 3; + return 3U; } static inline u32 gr_activity_4_gpc0_f(u32 v) { - return (v & 0x7) << 0; + return (v & 0x7U) << 0U; } static inline u32 gr_activity_4_gpc0_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 gr_activity_4_gpc0_v(u32 r) { - return (r >> 0) & 0x7; + return (r >> 0U) & 0x7U; } static inline u32 gr_activity_4_gpc0_empty_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_activity_4_gpc0_preempted_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_pri_gpc0_gcc_dbg_r(void) { - return 0x00501000; + return 0x00501000U; } static inline u32 gr_pri_gpcs_gcc_dbg_r(void) { - return 0x00419000; + return 0x00419000U; } static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) { - return 0x0050433c; + return 0x0050433cU; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) { - return 0x00419b3c; + return 0x00419b3cU; } static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_sked_activity_r(void) { - return 0x00407054; + return 0x00407054U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) { - return 0x00502c80; + return 0x00502c80U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) { - return 0x00502c84; + return 0x00502c84U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) { - return 0x00502c88; + return 0x00502c88U; } static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) { - return 0x00502c8c; + return 0x00502c8cU; } static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) { - return 0x00504500; + return 0x00504500U; } static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) { - return 0x00504d00; + return 0x00504d00U; } static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) { - return 0x00501d00; + return 0x00501d00U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) { - return 0x0041ac80; + return 0x0041ac80U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) { - return 0x0041ac84; + return 0x0041ac84U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) { - return 0x0041ac88; + return 0x0041ac88U; } static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) { - return 0x0041ac8c; + return 0x0041ac8cU; } static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) { - return 0x0041c500; + return 0x0041c500U; } static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) { - return 0x0041cd00; + return 0x0041cd00U; } static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) { - return 0x00419d00; + return 0x00419d00U; } static inline u32 gr_pri_be0_becs_be_activity0_r(void) { - return 0x00410200; + return 0x00410200U; } static inline u32 gr_pri_be1_becs_be_activity0_r(void) { - return 0x00410600; + return 0x00410600U; } static inline u32 gr_pri_bes_becs_be_activity0_r(void) { - return 0x00408a00; + return 0x00408a00U; } static inline u32 gr_pri_ds_mpipe_status_r(void) { - return 0x00405858; + return 0x00405858U; } static inline u32 gr_pri_fe_go_idle_info_r(void) { - return 0x00404194; + return 0x00404194U; } static inline u32 gr_pri_fe_chip_def_info_r(void) { - return 0x00404030; + return 0x00404030U; } static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) { - return 0x00504238; + return 0x00504238U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) { - return 0x00504358; + return 0x00504358U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) { - return 0x1 << 9; + return 0x1U << 9U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) { - return 0x1 << 13; + return 0x1U << 13U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) { - return 0x1 << 14; + return 0x1U << 14U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 24) & 0x1; + return (r >> 24U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 26) & 0x1; + return (r >> 26U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) { - return 0x0050435c; + return 0x0050435cU; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) { - return 0x00504360; + return 0x00504360U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) { - return 0x0050436c; + return 0x0050436cU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) { - return 0x00504370; + return 0x00504370U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) { - return 0x00504374; + return 0x00504374U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) { - return 0x00504638; + return 0x00504638U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) { - return (r >> 18) & 0x1; + return (r >> 18U) & 0x1U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) { - return 0x0050463c; + return 0x0050463cU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) { - return 0x00504640; + return 0x00504640U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) { - return 16; + return 16U; } static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) { - return 0x005042c4; + return 0x005042c4U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) { - return 0x00504430; + return 0x00504430U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) { - return 0x00504434; + return 0x00504434U; } static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_pri_be0_crop_status1_r(void) { - return 0x00410134; + return 0x00410134U; } static inline u32 gr_pri_bes_crop_status1_r(void) { - return 0x00408934; + return 0x00408934U; } static inline u32 gr_pri_be0_zrop_status_r(void) { - return 0x00410048; + return 0x00410048U; } static inline u32 gr_pri_be0_zrop_status2_r(void) { - return 0x0041004c; + return 0x0041004cU; } static inline u32 gr_pri_bes_zrop_status_r(void) { - return 0x00408848; + return 0x00408848U; } static inline u32 gr_pri_bes_zrop_status2_r(void) { - return 0x0040884c; + return 0x0040884cU; } static inline u32 gr_pipe_bundle_address_r(void) { - return 0x00400200; + return 0x00400200U; } static inline u32 gr_pipe_bundle_address_value_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_pipe_bundle_address_veid_f(u32 v) { - return (v & 0x3f) << 20; + return (v & 0x3fU) << 20U; } static inline u32 gr_pipe_bundle_address_veid_w(void) { - return 0; + return 0U; } static inline u32 gr_pipe_bundle_data_r(void) { - return 0x00400204; + return 0x00400204U; } static inline u32 gr_pipe_bundle_config_r(void) { - return 0x00400208; + return 0x00400208U; } static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_fe_hww_esr_r(void) { - return 0x00404000; + return 0x00404000U; } static inline u32 gr_fe_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_fe_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) { - return 0x00419eac; + return 0x00419eacU; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) { - return 0x0050472c; + return 0x0050472cU; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) { - return 0x00419eb4; + return 0x00419eb4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) { - return 0x00504734; + return 0x00504734U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_fe_go_idle_timeout_r(void) { - return 0x00404154; + return 0x00404154U; } static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) { - return 0x1800; + return 0x1800U; } static inline u32 gr_fe_object_table_r(u32 i) { - return 0x00404200 + i*4; + return 0x00404200U + i*4U; } static inline u32 gr_fe_object_table_nvclass_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_fe_tpc_fs_r(u32 i) { - return 0x0040a200 + i*4; + return 0x0040a200U + i*4U; } static inline u32 gr_pri_mme_shadow_raw_index_r(void) { - return 0x00404488; + return 0x00404488U; } static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pri_mme_shadow_raw_data_r(void) { - return 0x0040448c; + return 0x0040448cU; } static inline u32 gr_mme_hww_esr_r(void) { - return 0x00404490; + return 0x00404490U; } static inline u32 gr_mme_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_mme_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_memfmt_hww_esr_r(void) { - return 0x00404600; + return 0x00404600U; } static inline u32 gr_memfmt_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_memfmt_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_fecs_cpuctl_r(void) { - return 0x00409100; + return 0x00409100U; } static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_cpuctl_alias_r(void) { - return 0x00409130; + return 0x00409130U; } static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_dmactl_r(void) { - return 0x0040910c; + return 0x0040910cU; } static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_fecs_os_r(void) { - return 0x00409080; + return 0x00409080U; } static inline u32 gr_fecs_idlestate_r(void) { - return 0x0040904c; + return 0x0040904cU; } static inline u32 gr_fecs_mailbox0_r(void) { - return 0x00409040; + return 0x00409040U; } static inline u32 gr_fecs_mailbox1_r(void) { - return 0x00409044; + return 0x00409044U; } static inline u32 gr_fecs_irqstat_r(void) { - return 0x00409008; + return 0x00409008U; } static inline u32 gr_fecs_irqmode_r(void) { - return 0x0040900c; + return 0x0040900cU; } static inline u32 gr_fecs_irqmask_r(void) { - return 0x00409018; + return 0x00409018U; } static inline u32 gr_fecs_irqdest_r(void) { - return 0x0040901c; + return 0x0040901cU; } static inline u32 gr_fecs_curctx_r(void) { - return 0x00409050; + return 0x00409050U; } static inline u32 gr_fecs_nxtctx_r(void) { - return 0x00409054; + return 0x00409054U; } static inline u32 gr_fecs_engctl_r(void) { - return 0x004090a4; + return 0x004090a4U; } static inline u32 gr_fecs_debug1_r(void) { - return 0x00409090; + return 0x00409090U; } static inline u32 gr_fecs_debuginfo_r(void) { - return 0x00409094; + return 0x00409094U; } static inline u32 gr_fecs_icd_cmd_r(void) { - return 0x00409200; + return 0x00409200U; } static inline u32 gr_fecs_icd_cmd_opc_s(void) { - return 4; + return 4U; } static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_fecs_icd_cmd_opc_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) { - return 0xe; + return 0xeU; } static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 gr_fecs_icd_rdata_r(void) { - return 0x0040920c; + return 0x0040920cU; } static inline u32 gr_fecs_imemc_r(u32 i) { - return 0x00409180 + i*16; + return 0x00409180U + i*16U; } static inline u32 gr_fecs_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_fecs_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_fecs_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_fecs_imemd_r(u32 i) { - return 0x00409184 + i*16; + return 0x00409184U + i*16U; } static inline u32 gr_fecs_imemt_r(u32 i) { - return 0x00409188 + i*16; + return 0x00409188U + i*16U; } static inline u32 gr_fecs_imemt_tag_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_dmemc_r(u32 i) { - return 0x004091c0 + i*8; + return 0x004091c0U + i*8U; } static inline u32 gr_fecs_dmemc_offs_s(void) { - return 6; + return 6U; } static inline u32 gr_fecs_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_fecs_dmemc_offs_m(void) { - return 0x3f << 2; + return 0x3fU << 2U; } static inline u32 gr_fecs_dmemc_offs_v(u32 r) { - return (r >> 2) & 0x3f; + return (r >> 2U) & 0x3fU; } static inline u32 gr_fecs_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_fecs_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_fecs_dmemd_r(u32 i) { - return 0x004091c4 + i*8; + return 0x004091c4U + i*8U; } static inline u32 gr_fecs_dmatrfbase_r(void) { - return 0x00409110; + return 0x00409110U; } static inline u32 gr_fecs_dmatrfmoffs_r(void) { - return 0x00409114; + return 0x00409114U; } static inline u32 gr_fecs_dmatrffboffs_r(void) { - return 0x0040911c; + return 0x0040911cU; } static inline u32 gr_fecs_dmatrfcmd_r(void) { - return 0x00409118; + return 0x00409118U; } static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 gr_fecs_bootvec_r(void) { - return 0x00409104; + return 0x00409104U; } static inline u32 gr_fecs_bootvec_vec_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_falcon_hwcfg_r(void) { - return 0x00409108; + return 0x00409108U; } static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) { - return 0x0041a108; + return 0x0041a108U; } static inline u32 gr_fecs_falcon_rm_r(void) { - return 0x00409084; + return 0x00409084U; } static inline u32 gr_fecs_current_ctx_r(void) { - return 0x00409b00; + return 0x00409b00U; } static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_current_ctx_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_current_ctx_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_current_ctx_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_current_ctx_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 gr_fecs_current_ctx_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_current_ctx_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_fecs_current_ctx_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_fecs_current_ctx_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_fecs_current_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_method_data_r(void) { - return 0x00409500; + return 0x00409500U; } static inline u32 gr_fecs_method_push_r(void) { - return 0x00409504; + return 0x00409504U; } static inline u32 gr_fecs_method_push_adr_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) { - return 0x3; + return 0x3U; } static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) { - return 0x00000015; + return 0x00000015U; } static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) { - return 0x00000016; + return 0x00000016U; } static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) { - return 0x00000025; + return 0x00000025U; } static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) { - return 0x00000031; + return 0x00000031U; } static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) { - return 0x00000032; + return 0x00000032U; } static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) { - return 0x00000038; + return 0x00000038U; } static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) { - return 0x00000039; + return 0x00000039U; } static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) { - return 0x21; + return 0x21U; } static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) { - return 0x0000001a; + return 0x0000001aU; } static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) { - return 0x0000003a; + return 0x0000003aU; } static inline u32 gr_fecs_host_int_status_r(void) { - return 0x00409c18; + return 0x00409c18U; } static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_fecs_host_int_clear_r(void) { - return 0x00409c20; + return 0x00409c20U; } static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fecs_host_int_enable_r(void) { - return 0x00409c24; + return 0x00409c24U; } static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) { - return 0x00409614; + return 0x00409614U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) { - return (r >> 10) & 0x1; + return (r >> 10U) & 0x1U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) { - return 0x0040960c; + return 0x0040960cU; } static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) { - return 0x00409800 + i*4; + return 0x00409800U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) { - return 0x004098c0 + i*4; + return 0x004098c0U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) { - return 0x00409840 + i*4; + return 0x00409840U + i*4U; } static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fecs_fs_r(void) { - return 0x00409604; + return 0x00409604U; } static inline u32 gr_fecs_fs_num_available_gpcs_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_fecs_fs_num_available_gpcs_m(void) { - return 0x1f << 0; + return 0x1fU << 0U; } static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_fecs_fs_num_available_fbps_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 gr_fecs_fs_num_available_fbps_m(void) { - return 0x1f << 16; + return 0x1fU << 16U; } static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } static inline u32 gr_fecs_cfg_r(void) { - return 0x00409620; + return 0x00409620U; } static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_fecs_rc_lanes_r(void) { - return 0x00409880; + return 0x00409880U; } static inline u32 gr_fecs_rc_lanes_num_chains_s(void) { - return 6; + return 6U; } static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_fecs_rc_lanes_num_chains_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_fecs_ctxsw_status_1_r(void) { - return 0x00409400; + return 0x00409400U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) { - return 0x1 << 12; + return 0x1U << 12U; } static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 gr_fecs_arb_ctx_adr_r(void) { - return 0x00409a24; + return 0x00409a24U; } static inline u32 gr_fecs_new_ctx_r(void) { - return 0x00409b04; + return 0x00409b04U; } static inline u32 gr_fecs_new_ctx_ptr_s(void) { - return 28; + return 28U; } static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_new_ctx_ptr_m(void) { - return 0xfffffff << 0; + return 0xfffffffU << 0U; } static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_new_ctx_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_new_ctx_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_new_ctx_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_new_ctx_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_new_ctx_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_fecs_new_ctx_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_fecs_new_ctx_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_fecs_new_ctx_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_fecs_arb_ctx_ptr_r(void) { - return 0x00409a0c; + return 0x00409a0cU; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) { - return 28; + return 28U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) { - return 0xfffffff << 0; + return 0xfffffffU << 0U; } static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) { - return (r >> 0) & 0xfffffff; + return (r >> 0U) & 0xfffffffU; } static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) { - return 2; + return 2U; } static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 gr_fecs_arb_ctx_cmd_r(void) { - return 0x00409a10; + return 0x00409a10U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) { - return 5; + return 5U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) { - return 0x1f << 0; + return 0x1fU << 0U; } static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) { - return 0x00409c00; + return 0x00409c00U; } static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) { - return 0x00502c04; + return 0x00502c04U; } static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) { - return 0x00502400; + return 0x00502400U; } static inline u32 gr_fecs_ctxsw_idlestate_r(void) { - return 0x00409420; + return 0x00409420U; } static inline u32 gr_fecs_feature_override_ecc_r(void) { - return 0x00409658; + return 0x00409658U; } static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) { - return (r >> 15) & 0x1; + return (r >> 15U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) { - return (r >> 12) & 0x1; + return (r >> 12U) & 0x1U; } static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) { - return 0x00502420; + return 0x00502420U; } static inline u32 gr_rstr2d_gpc_map_r(u32 i) { - return 0x0040780c + i*4; + return 0x0040780cU + i*4U; } static inline u32 gr_rstr2d_map_table_cfg_r(void) { - return 0x004078bc; + return 0x004078bcU; } static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_pd_hww_esr_r(void) { - return 0x00406018; + return 0x00406018U; } static inline u32 gr_pd_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_pd_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) { - return 0x00406028 + i*4; + return 0x00406028U + i*4U; } static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) { - return (v & 0xf) << 4; + return (v & 0xfU) << 4U; } static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) { - return (v & 0xf) << 12; + return (v & 0xfU) << 12U; } static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) { - return (v & 0xf) << 24; + return (v & 0xfU) << 24U; } static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) { - return (v & 0xf) << 28; + return (v & 0xfU) << 28U; } static inline u32 gr_pd_ab_dist_cfg0_r(void) { - return 0x004064c0; + return 0x004064c0U; } static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_pd_ab_dist_cfg1_r(void) { - return 0x004064c4; + return 0x004064c4U; } static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) { - return 0xffff; + return 0xffffU; } static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) { - return (v & 0xffff) << 16; + return (v & 0xffffU) << 16U; } static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 gr_pd_ab_dist_cfg2_r(void) { - return 0x004064c8; + return 0x004064c8U; } static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) { - return (v & 0x1fff) << 0; + return (v & 0x1fffU) << 0U; } static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) { - return 0x00001680; + return 0x00001680U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) { - return (v & 0x1fff) << 16; + return (v & 0x1fffU) << 16U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) { - return 0x00001680; + return 0x00001680U; } static inline u32 gr_pd_dist_skip_table_r(u32 i) { - return 0x004064d0 + i*4; + return 0x004064d0U + i*4U; } static inline u32 gr_pd_dist_skip_table__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gr_ds_debug_r(void) { - return 0x00405800; + return 0x00405800U; } static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 gr_ds_zbc_color_r_r(void) { - return 0x00405804; + return 0x00405804U; } static inline u32 gr_ds_zbc_color_r_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_g_r(void) { - return 0x00405808; + return 0x00405808U; } static inline u32 gr_ds_zbc_color_g_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_b_r(void) { - return 0x0040580c; + return 0x0040580cU; } static inline u32 gr_ds_zbc_color_b_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_a_r(void) { - return 0x00405810; + return 0x00405810U; } static inline u32 gr_ds_zbc_color_a_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_color_fmt_r(void) { - return 0x00405814; + return 0x00405814U; } static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) { - return (v & 0x7f) << 0; + return (v & 0x7fU) << 0U; } static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) { - return 0x00000028; + return 0x00000028U; } static inline u32 gr_ds_zbc_z_r(void) { - return 0x00405818; + return 0x00405818U; } static inline u32 gr_ds_zbc_z_val_s(void) { - return 32; + return 32U; } static inline u32 gr_ds_zbc_z_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_ds_zbc_z_val_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 gr_ds_zbc_z_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gr_ds_zbc_z_val__init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_ds_zbc_z_val__init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_z_fmt_r(void) { - return 0x0040581c; + return 0x0040581cU; } static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_zbc_tbl_index_r(void) { - return 0x00405820; + return 0x00405820U; } static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_ds_zbc_tbl_ld_r(void) { - return 0x00405824; + return 0x00405824U; } static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ds_tga_constraintlogic_beta_r(void) { - return 0x00405830; + return 0x00405830U; } static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) { - return 0x0040585c; + return 0x0040585cU; } static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_ds_hww_esr_r(void) { - return 0x00405840; + return 0x00405840U; } static inline u32 gr_ds_hww_esr_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_ds_hww_esr_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 gr_ds_hww_esr_reset_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_ds_hww_esr_reset_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 gr_ds_hww_esr_reset_task_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_hww_esr_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_ds_hww_esr_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_ds_hww_esr_2_r(void) { - return 0x00405848; + return 0x00405848U; } static inline u32 gr_ds_hww_esr_2_reset_s(void) { - return 1; + return 1U; } static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 gr_ds_hww_esr_2_reset_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 gr_ds_hww_esr_2_reset_task_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_ds_hww_esr_2_reset_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_ds_hww_report_mask_r(void) { - return 0x00405844; + return 0x00405844U; } static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) { - return 0x80; + return 0x80U; } static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) { - return 0x400; + return 0x400U; } static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 gr_ds_hww_report_mask_2_r(void) { - return 0x0040584c; + return 0x0040584cU; } static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) { - return 0x00405870 + i*4; + return 0x00405870U + i*4U; } static inline u32 gr_scc_bundle_cb_base_r(void) { - return 0x00408004; + return 0x00408004U; } static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_scc_bundle_cb_size_r(void) { - return 0x00408008; + return 0x00408008U; } static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) { - return (v & 0x7ff) << 0; + return (v & 0x7ffU) << 0U; } static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_scc_pagepool_base_r(void) { - return 0x0040800c; + return 0x0040800cU; } static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_scc_pagepool_r(void) { - return 0x00408010; + return 0x00408010U; } static inline u32 gr_scc_pagepool_total_pages_f(u32 v) { - return (v & 0x3ff) << 0; + return (v & 0x3ffU) << 0U; } static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_scc_pagepool_max_valid_pages_s(void) { - return 10; + return 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) { - return (v & 0x3ff) << 10; + return (v & 0x3ffU) << 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_m(void) { - return 0x3ff << 10; + return 0x3ffU << 10U; } static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) { - return (r >> 10) & 0x3ff; + return (r >> 10U) & 0x3ffU; } static inline u32 gr_scc_pagepool_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_scc_init_r(void) { - return 0x0040802c; + return 0x0040802cU; } static inline u32 gr_scc_init_ram_trigger_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_scc_hww_esr_r(void) { - return 0x00408030; + return 0x00408030U; } static inline u32 gr_scc_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_scc_hww_esr_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_sked_hww_esr_r(void) { - return 0x00407020; + return 0x00407020U; } static inline u32 gr_sked_hww_esr_reset_active_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_sked_hww_esr_en_r(void) { - return 0x00407024; + return 0x00407024U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) { - return 0x1 << 25; + return 0x1U << 25U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 gr_cwd_fs_r(void) { - return 0x00405b00; + return 0x00405b00U; } static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) { - return 0x00405b60 + i*4; + return 0x00405b60U + i*4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) { - return 4; + return 4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) { - return 4; + return 4U; } static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) { - return (v & 0xf) << 4; + return (v & 0xfU) << 4U; } static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_cwd_sm_id_r(u32 i) { - return 0x00405ba0 + i*4; + return 0x00405ba0U + i*4U; } static inline u32 gr_cwd_sm_id__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpc0_fs_gpc_r(void) { - return 0x00502608; + return 0x00502608U; } static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } static inline u32 gr_gpc0_cfg_r(void) { - return 0x00502620; + return 0x00502620U; } static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpccs_rc_lanes_r(void) { - return 0x00502880; + return 0x00502880U; } static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_gpccs_rc_lane_size_r(void) { - return 0x00502910; + return 0x00502910U; } static inline u32 gr_gpccs_rc_lane_size_v_s(void) { - return 24; + return 24U; } static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_gpccs_rc_lane_size_v_m(void) { - return 0xffffff << 0; + return 0xffffffU << 0U; } static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_zcull_fs_r(void) { - return 0x00500910; + return 0x00500910U; } static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x1ffU) << 0U; } static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 gr_gpc0_zcull_ram_addr_r(void) { - return 0x00500914; + return 0x00500914U; } static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) { - return (v & 0xf) << 8; + return (v & 0xfU) << 8U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) { - return 0x00500918; + return 0x00500918U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) { - return 0x00800000; + return 0x00800000U; } static inline u32 gr_gpc0_zcull_total_ram_size_r(void) { - return 0x00500920; + return 0x00500920U; } static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) { - return 0x00500a04 + i*32; + return 0x00500a04U + i*32U; } static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) { - return 0x00500c10 + i*4; + return 0x00500c10U + i*4U; } static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) { - return 0x00500c30 + i*4; + return 0x00500c30U + i*4U; } static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) { - return 0x00504088; + return 0x00504088U; } static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) { - return 0x00504608; + return 0x00504608U; } static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_tpc0_sm_arch_r(void) { - return 0x00504330; + return 0x00504330U; } static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) { - return (r >> 8) & 0xfff; + return (r >> 8U) & 0xfffU; } static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) { - return (r >> 20) & 0xfff; + return (r >> 20U) & 0xfffU; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) { - return 0x00503018; + return 0x00503018U; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) { - return 0x005030c0; + return 0x005030c0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) { - return 0x3fffff << 0; + return 0x3fffffU << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { - return 0x00000480; + return 0x00000480U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) { - return 0x00000d10; + return 0x00000d10U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) { - return 0x005030f4; + return 0x005030f4U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) { - return 0x005030e4; + return 0x005030e4U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) { - return 0xffff << 0; + return 0xffffU << 0U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) { - return 0x005030f8; + return 0x005030f8U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) { - return 0x005030f0; + return 0x005030f0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) { - return 0x00000480; + return 0x00000480U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) { - return 0x00419e00; + return 0x00419e00U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) { - return 0x00419e04; + return 0x00419e04U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) { - return 21; + return 21U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) { - return (v & 0x1fffff) << 0; + return (v & 0x1fffffU) << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) { - return 0x1fffff << 0; + return 0x1fffffU << 0U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) { - return (r >> 0) & 0x1fffff; + return (r >> 0U) & 0x1fffffU; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) { - return 0x80; + return 0x80U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpccs_falcon_addr_r(void) { - return 0x0041a0ac; + return 0x0041a0acU; } static inline u32 gr_gpccs_falcon_addr_lsb_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 gr_gpccs_falcon_addr_lsb_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpccs_falcon_addr_msb_s(void) { - return 6; + return 6U; } static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) { - return (v & 0x3f) << 6; + return (v & 0x3fU) << 6U; } static inline u32 gr_gpccs_falcon_addr_msb_m(void) { - return 0x3f << 6; + return 0x3fU << 6U; } static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) { - return (r >> 6) & 0x3f; + return (r >> 6U) & 0x3fU; } static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpccs_falcon_addr_ext_s(void) { - return 12; + return 12U; } static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpccs_falcon_addr_ext_m(void) { - return 0xfff << 0; + return 0xfffU << 0U; } static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) { - return (r >> 0) & 0xfff; + return (r >> 0U) & 0xfffU; } static inline u32 gr_gpccs_cpuctl_r(void) { - return 0x0041a100; + return 0x0041a100U; } static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 gr_gpccs_dmactl_r(void) { - return 0x0041a10c; + return 0x0041a10cU; } static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpccs_imemc_r(u32 i) { - return 0x0041a180 + i*16; + return 0x0041a180U + i*16U; } static inline u32 gr_gpccs_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_gpccs_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpccs_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_gpccs_imemd_r(u32 i) { - return 0x0041a184 + i*16; + return 0x0041a184U + i*16U; } static inline u32 gr_gpccs_imemt_r(u32 i) { - return 0x0041a188 + i*16; + return 0x0041a188U + i*16U; } static inline u32 gr_gpccs_imemt__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 gr_gpccs_imemt_tag_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpccs_dmemc_r(u32 i) { - return 0x0041a1c0 + i*8; + return 0x0041a1c0U + i*8U; } static inline u32 gr_gpccs_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 gr_gpccs_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 gr_gpccs_dmemd_r(u32 i) { - return 0x0041a1c4 + i*8; + return 0x0041a1c4U + i*8U; } static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) { - return 0x0041a800 + i*4; + return 0x0041a800U + i*4U; } static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) { - return 0x00418e24; + return 0x00418e24U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) { - return 32; + return 32U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) { - return 0x00418e28; + return 0x00418e28U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) { - return 11; + return 11U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) { - return (v & 0x7ff) << 0; + return (v & 0x7ffU) << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) { - return 0x7ff << 0; + return 0x7ffU << 0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) { - return (r >> 0) & 0x7ff; + return (r >> 0U) & 0x7ffU; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) { - return 0x00000030; + return 0x00000030U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) { - return 0x30; + return 0x30U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) { - return 1; + return 1U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) { - return 0x005001dc; + return 0x005001dcU; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) { - return 0x000004b0; + return 0x000004b0U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) { - return 0x005001d8; + return 0x005001d8U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) { - return 0x004181e4; + return 0x004181e4U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) { - return 0x00000100; + return 0x00000100U; } static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) { - return 0x0041befc; + return 0x0041befcU; } static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) { - return 0x00418ea0 + i*4; + return 0x00418ea0U + i*4U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0x3fffffU) << 0U; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) { - return 0x3fffff << 0; + return 0x3fffffU << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) { - return 0x00418010 + i*4; + return 0x00418010U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) { - return 0x0041804c + i*4; + return 0x0041804cU + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) { - return 0x00418088 + i*4; + return 0x00418088U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) { - return 0x004180c4 + i*4; + return 0x004180c4U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) { - return 0x00418100; + return 0x00418100U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) { - return 0x00418110 + i*4; + return 0x00418110U + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) { - return 0x0041814c; + return 0x0041814cU; } static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) { - return 0x0041815c + i*4; + return 0x0041815cU + i*4U; } static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) { - return 0x00418198; + return 0x00418198U; } static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) { - return 0x00418810; + return 0x00418810U; } static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_crstr_gpc_map_r(u32 i) { - return 0x00418b08 + i*4; + return 0x00418b08U + i*4U; } static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) { - return (v & 0x1f) << 0; + return (v & 0x1fU) << 0U; } static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) { - return (v & 0x1f) << 5; + return (v & 0x1fU) << 5U; } static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) { - return (v & 0x1f) << 10; + return (v & 0x1fU) << 10U; } static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) { - return (v & 0x1f) << 15; + return (v & 0x1fU) << 15U; } static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) { - return (v & 0x1f) << 20; + return (v & 0x1fU) << 20U; } static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) { - return (v & 0x1f) << 25; + return (v & 0x1fU) << 25U; } static inline u32 gr_crstr_map_table_cfg_r(void) { - return 0x00418bb8; + return 0x00418bb8U; } static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) { - return 0x00418980 + i*4; + return 0x00418980U + i*4U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) { - return (v & 0x7) << 0; + return (v & 0x7U) << 0U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) { - return (v & 0x7) << 4; + return (v & 0x7U) << 4U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) { - return (v & 0x7) << 16; + return (v & 0x7U) << 16U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) { - return (v & 0x7) << 20; + return (v & 0x7U) << 20U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) { - return (v & 0x7) << 24; + return (v & 0x7U) << 24U; } static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) { - return (v & 0x7) << 28; + return (v & 0x7U) << 28U; } static inline u32 gr_gpcs_gpm_pd_cfg_r(void) { - return 0x00418c6c; + return 0x00418c6cU; } static inline u32 gr_gpcs_gcc_pagepool_base_r(void) { - return 0x00419004; + return 0x00419004U; } static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_gpcs_gcc_pagepool_r(void) { - return 0x00419008; + return 0x00419008U; } static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) { - return (v & 0x3ff) << 0; + return (v & 0x3ffU) << 0U; } static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) { - return 0x0041980c; + return 0x0041980cU; } static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) { - return 0x00419848; + return 0x00419848U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) { - return 0x00419c00; + return 0x00419c00U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) { - return 0x00419c2c; + return 0x00419c2cU; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) { - return 0x00419ea8; + return 0x00419ea8U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) { - return 0x00504728; + return 0x00504728U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) { - return 0x20; + return 0x20U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) { - return 0x40; + return 0x40U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) { - return 0x200; + return 0x200U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) { - return 0x800; + return 0x800U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) { - return 0x00419d0c; + return 0x00419d0cU; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { - return 0x0050450c; + return 0x0050450cU; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) { - return 0x0041ac94; + return 0x0041ac94U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { - return 0x00502c90; + return 0x00502c90U; } static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { - return 0x00504508; + return 0x00504508U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) { - return 0x00504704; + return 0x00504704U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) { - return 0x1; + return 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) { - return 0x1 << 3; + return 0x1U << 3U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) { - return 0x8; + return 0x8U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) { - return 0x00504708; + return 0x00504708U; } static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) { - return 0x0050470c; + return 0x0050470cU; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) { - return 0x00504710; + return 0x00504710U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) { - return 0x00504714; + return 0x00504714U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) { - return 0x00504718; + return 0x00504718U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) { - return 0x0050471c; + return 0x0050471cU; } static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) { - return 0x00419e90; + return 0x00419e90U; } static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) { - return 0x00419e94; + return 0x00419e94U; } static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) { - return 0x00419e80; + return 0x00419e80U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) { - return 0x00504700; + return 0x00504700U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) { - return 0x00504730; + return 0x00504730U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) { - return 0xff << 16; + return 0xffU << 16U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) { - return 0xf << 24; + return 0xfU << 24U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) { - return 0x0050460c; + return 0x0050460cU; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) { - return 0x00504738; + return 0x00504738U; } static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) { - return 0x005043a0; + return 0x005043a0U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) { - return 0x00419ba0; + return 0x00419ba0U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) { - return 0x005043b0; + return 0x005043b0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) { - return 0x00419bb0; + return 0x00419bb0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) { - return 0x0041be08; + return 0x0041be08U; } static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) { - return 0x0041bf00 + i*4; + return 0x0041bf00U + i*4U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) { - return 0x0041bfd0; + return 0x0041bfd0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) { - return (v & 0x7) << 21; + return (v & 0x7U) << 21U; } static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) { - return 0x0041bfd4; + return 0x0041bfd4U; } static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) { - return 0x0041bfb0 + i*4; + return 0x0041bfb0U + i*4U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) { - return (v & 0xff) << 16; + return (v & 0xffU) << 16U; } static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 gr_bes_zrop_settings_r(void) { - return 0x00408850; + return 0x00408850U; } static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_be0_crop_debug3_r(void) { - return 0x00410108; + return 0x00410108U; } static inline u32 gr_bes_crop_debug3_r(void) { - return 0x00408908; + return 0x00408908U; } static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 gr_bes_crop_settings_r(void) { - return 0x00408958; + return 0x00408958U; } static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) { - return 0x000000c0; + return 0x000000c0U; } static inline u32 gr_zcull_subregion_qty_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) { - return 0x00419a00; + return 0x00419a00U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) { - return 0x1 << 19; + return 0x1U << 19U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) { - return 0x00419bf0; + return 0x00419bf0U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) { - return 0x1 << 10; + return 0x1U << 10U; } static inline u32 gr_fe_pwr_mode_r(void) { - return 0x00404170; + return 0x00404170U; } static inline u32 gr_fe_pwr_mode_mode_auto_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) { - return 0x2; + return 0x2U; } static inline u32 gr_fe_pwr_mode_req_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 gr_fe_pwr_mode_req_send_f(void) { - return 0x10; + return 0x10U; } static inline u32 gr_fe_pwr_mode_req_done_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) { - return 0x00418880; + return 0x00418880U; } static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) { - return 0x3 << 3; + return 0x3U << 3U; } static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) { - return 0x3 << 5; + return 0x3U << 5U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) { - return 0x3 << 28; + return 0x3U << 28U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) { - return 0x00418890; + return 0x00418890U; } static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) { - return 0x00418894; + return 0x00418894U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) { - return 0x004188b0; + return 0x004188b0U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) { - return 0x004188b4; + return 0x004188b4U; } static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) { - return 0x004188b8; + return 0x004188b8U; } static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) { - return 0x004188ac; + return 0x004188acU; } static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) { - return 0x00419e84; + return 0x00419e84U; } static inline u32 gr_fe_gfxp_wfi_timeout_r(void) { - return 0x004041c0; + return 0x004041c0U; } static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) { - return 0x00419bd8; + return 0x00419bd8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) { - return 0x7 << 8; + return 0x7U << 8U; } static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) { - return 0x100; + return 0x100U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) { - return 0x00419ba4; + return 0x00419ba4U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) { - return 0x3 << 11; + return 0x3U << 11U; } static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 gr_gpcs_tc_debug0_r(void) { - return 0x00418708; + return 0x00418708U; } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) { - return (v & 0x1ff) << 0; + return (v & 0x1ffU) << 0U; } static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { - return 0x1ff << 0; + return 0x1ffU << 0U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h index b5fc4b63..3543f0b7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ltc_gv100.h @@ -58,562 +58,562 @@ static inline u32 ltc_pltcg_base_v(void) { - return 0x00140000; + return 0x00140000U; } static inline u32 ltc_pltcg_extent_v(void) { - return 0x0017ffff; + return 0x0017ffffU; } static inline u32 ltc_ltc0_ltss_v(void) { - return 0x00140200; + return 0x00140200U; } static inline u32 ltc_ltc0_lts0_v(void) { - return 0x00140400; + return 0x00140400U; } static inline u32 ltc_ltcs_ltss_v(void) { - return 0x0017e200; + return 0x0017e200U; } static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) { - return 0x0014046c; + return 0x0014046cU; } static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) { - return 0x00140518; + return 0x00140518U; } static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) { - return 0x0017e318; + return 0x0017e318U; } static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) { - return 0x00140494; + return 0x00140494U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) { - return (r >> 16) & 0x3; + return (r >> 16U) & 0x3U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) { - return 0x0017e26c; + return 0x0017e26cU; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) { - return 0x2; + return 0x2U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) { - return 0x4; + return 0x4U; } static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) { - return 0x0014046c; + return 0x0014046cU; } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) { - return 0x0017e270; + return 0x0017e270U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x3ffffU) << 0U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) { - return 0x0017e274; + return 0x0017e274U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x3ffffU) << 0U; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) { - return 0x0003ffff; + return 0x0003ffffU; } static inline u32 ltc_ltcs_ltss_cbc_base_r(void) { - return 0x0017e278; + return 0x0017e278U; } static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) { - return 0x0000000b; + return 0x0000000bU; } static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) { - return (r >> 0) & 0x3ffffff; + return (r >> 0U) & 0x3ffffffU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) { - return 0x0017e27c; + return 0x0017e27cU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) { - return (r >> 24) & 0x1; + return (r >> 24U) & 0x1U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) { - return (r >> 25) & 0x1; + return (r >> 25U) & 0x1U; } static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) { - return 0x0017e000; + return 0x0017e000U; } static inline u32 ltc_ltcs_ltss_cbc_param_r(void) { - return 0x0017e280; + return 0x0017e280U; } static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) { - return (r >> 24) & 0xf; + return (r >> 24U) & 0xfU; } static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) { - return (r >> 28) & 0xf; + return (r >> 28U) & 0xfU; } static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) { - return 0x0017e3f4; + return 0x0017e3f4U; } static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) { - return 0x0017e2ac; + return 0x0017e2acU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) { - return 0x0017e338; + return 0x0017e338U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) { - return 0x0017e33c + i*4; + return 0x0017e33cU + i*4U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) { - return 0x0017e34c; + return 0x0017e34cU; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) { - return 32; + return 32U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) { - return 0x0017e204; + return 0x0017e204U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) { - return 8; + return 8U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) { - return 0x0017e2b0; + return 0x0017e2b0U; } static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_g_elpg_r(void) { - return 0x0017e214; + return 0x0017e214U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_ltss_g_elpg_r(void) { - return 0x00140214; + return 0x00140214U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_g_elpg_r(void) { - return 0x00142214; + return 0x00142214U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_intr_r(void) { - return 0x0017e20c; + return 0x0017e20cU; } static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) { - return 0x1 << 30; + return 0x1U << 30U; } static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 ltc_ltc0_lts0_intr_r(void) { - return 0x0014040c; + return 0x0014040cU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) { - return 0x0014051c; + return 0x0014051cU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) { - return 0xff << 16; + return 0xffU << 16U; } static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) { - return (r >> 16) & 0xff; + return (r >> 16U) & 0xffU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) { - return 0x0017e2a0; + return 0x0017e2a0U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) { - return (r >> 8) & 0xf; + return (r >> 8U) & 0xfU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) { - return 0x300; + return 0x300U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) { - return 0x0017e2a4; + return 0x0017e2a4U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) { - return (r >> 8) & 0xf; + return (r >> 8U) & 0xfU; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) { - return 0x300; + return 0x300U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) { - return (r >> 16) & 0x1; + return (r >> 16U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) { - return (r >> 28) & 0x1; + return (r >> 28U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) { - return (r >> 29) & 0x1; + return (r >> 29U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) { - return 0x001402a0; + return 0x001402a0U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) { - return 0x001402a4; + return 0x001402a4U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) { - return 0x001422a0; + return 0x001422a0U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) { - return 0x001422a4; + return 0x001422a4U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) { - return 0x0014058c; + return 0x0014058cU; } static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) { - return (r >> 0) & 0xffff; + return (r >> 0U) & 0xffffU; } static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) { - return (r >> 16) & 0x1f; + return (r >> 16U) & 0x1fU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h index 54bd1e35..2efeac79 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h @@ -58,194 +58,194 @@ static inline u32 mc_boot_0_r(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 mc_boot_0_architecture_v(u32 r) { - return (r >> 24) & 0x1f; + return (r >> 24U) & 0x1fU; } static inline u32 mc_boot_0_implementation_v(u32 r) { - return (r >> 20) & 0xf; + return (r >> 20U) & 0xfU; } static inline u32 mc_boot_0_major_revision_v(u32 r) { - return (r >> 4) & 0xf; + return (r >> 4U) & 0xfU; } static inline u32 mc_boot_0_minor_revision_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 mc_intr_r(u32 i) { - return 0x00000100 + i*4; + return 0x00000100U + i*4U; } static inline u32 mc_intr_pfifo_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 mc_intr_hub_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 mc_intr_pgraph_pending_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 mc_intr_pmu_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 mc_intr_ltc_pending_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 mc_intr_priv_ring_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 mc_intr_pbus_pending_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 mc_intr_en_r(u32 i) { - return 0x00000140 + i*4; + return 0x00000140U + i*4U; } static inline u32 mc_intr_en_set_r(u32 i) { - return 0x00000160 + i*4; + return 0x00000160U + i*4U; } static inline u32 mc_intr_en_clear_r(u32 i) { - return 0x00000180 + i*4; + return 0x00000180U + i*4U; } static inline u32 mc_enable_r(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 mc_enable_xbar_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 mc_enable_l2_enabled_f(void) { - return 0x8; + return 0x8U; } static inline u32 mc_enable_pmedia_s(void) { - return 1; + return 1U; } static inline u32 mc_enable_pmedia_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 mc_enable_pmedia_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 mc_enable_pmedia_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 mc_enable_ce0_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 mc_enable_pfifo_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 mc_enable_pgraph_enabled_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 mc_enable_pwr_v(u32 r) { - return (r >> 13) & 0x1; + return (r >> 13U) & 0x1U; } static inline u32 mc_enable_pwr_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 mc_enable_pwr_enabled_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 mc_enable_pfb_enabled_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 mc_enable_ce2_m(void) { - return 0x1 << 21; + return 0x1U << 21U; } static inline u32 mc_enable_ce2_enabled_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 mc_enable_blg_enabled_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 mc_enable_perfmon_enabled_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 mc_enable_hub_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 mc_intr_ltc_r(void) { - return 0x000001c0; + return 0x000001c0U; } static inline u32 mc_enable_pb_r(void) { - return 0x00000204; + return 0x00000204U; } static inline u32 mc_enable_pb_0_s(void) { - return 1; + return 1U; } static inline u32 mc_enable_pb_0_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 mc_enable_pb_0_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 mc_enable_pb_0_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 mc_enable_pb_0_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) { - return (v & 0x1) << (0 + i*1); + return (v & 0x1U) << (0U + i*1U); } static inline u32 mc_elpg_enable_r(void) { - return 0x0000020c; + return 0x0000020cU; } static inline u32 mc_elpg_enable_xbar_enabled_f(void) { - return 0x4; + return 0x4U; } static inline u32 mc_elpg_enable_pfb_enabled_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 mc_elpg_enable_hub_enabled_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 mc_elpg_enable_l2_enabled_f(void) { - return 0x8; + return 0x8U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h index f0fc0773..2d98b914 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h @@ -58,594 +58,594 @@ static inline u32 pbdma_gp_entry1_r(void) { - return 0x10000004; + return 0x10000004U; } static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pbdma_gp_entry1_length_f(u32 v) { - return (v & 0x1fffff) << 10; + return (v & 0x1fffffU) << 10U; } static inline u32 pbdma_gp_entry1_length_v(u32 r) { - return (r >> 10) & 0x1fffff; + return (r >> 10U) & 0x1fffffU; } static inline u32 pbdma_gp_base_r(u32 i) { - return 0x00040048 + i*8192; + return 0x00040048U + i*8192U; } static inline u32 pbdma_gp_base__size_1_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 pbdma_gp_base_offset_f(u32 v) { - return (v & 0x1fffffff) << 3; + return (v & 0x1fffffffU) << 3U; } static inline u32 pbdma_gp_base_rsvd_s(void) { - return 3; + return 3U; } static inline u32 pbdma_gp_base_hi_r(u32 i) { - return 0x0004004c + i*8192; + return 0x0004004cU + i*8192U; } static inline u32 pbdma_gp_base_hi_offset_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) { - return (v & 0x1f) << 16; + return (v & 0x1fU) << 16U; } static inline u32 pbdma_gp_fetch_r(u32 i) { - return 0x00040050 + i*8192; + return 0x00040050U + i*8192U; } static inline u32 pbdma_gp_get_r(u32 i) { - return 0x00040014 + i*8192; + return 0x00040014U + i*8192U; } static inline u32 pbdma_gp_put_r(u32 i) { - return 0x00040000 + i*8192; + return 0x00040000U + i*8192U; } static inline u32 pbdma_pb_fetch_r(u32 i) { - return 0x00040054 + i*8192; + return 0x00040054U + i*8192U; } static inline u32 pbdma_pb_fetch_hi_r(u32 i) { - return 0x00040058 + i*8192; + return 0x00040058U + i*8192U; } static inline u32 pbdma_get_r(u32 i) { - return 0x00040018 + i*8192; + return 0x00040018U + i*8192U; } static inline u32 pbdma_get_hi_r(u32 i) { - return 0x0004001c + i*8192; + return 0x0004001cU + i*8192U; } static inline u32 pbdma_put_r(u32 i) { - return 0x0004005c + i*8192; + return 0x0004005cU + i*8192U; } static inline u32 pbdma_put_hi_r(u32 i) { - return 0x00040060 + i*8192; + return 0x00040060U + i*8192U; } static inline u32 pbdma_pb_header_r(u32 i) { - return 0x00040084 + i*8192; + return 0x00040084U + i*8192U; } static inline u32 pbdma_pb_header_priv_user_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_method_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_subchannel_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_level_main_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_pb_header_first_true_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_pb_header_type_inc_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_pb_header_type_non_inc_f(void) { - return 0x60000000; + return 0x60000000U; } static inline u32 pbdma_hdr_shadow_r(u32 i) { - return 0x00040118 + i*8192; + return 0x00040118U + i*8192U; } static inline u32 pbdma_subdevice_r(u32 i) { - return 0x00040094 + i*8192; + return 0x00040094U + i*8192U; } static inline u32 pbdma_subdevice_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 pbdma_subdevice_status_active_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 pbdma_subdevice_channel_dma_enable_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_method0_r(u32 i) { - return 0x000400c0 + i*8192; + return 0x000400c0U + i*8192U; } static inline u32 pbdma_method0_fifo_size_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 pbdma_method0_addr_f(u32 v) { - return (v & 0xfff) << 2; + return (v & 0xfffU) << 2U; } static inline u32 pbdma_method0_addr_v(u32 r) { - return (r >> 2) & 0xfff; + return (r >> 2U) & 0xfffU; } static inline u32 pbdma_method0_subch_v(u32 r) { - return (r >> 16) & 0x7; + return (r >> 16U) & 0x7U; } static inline u32 pbdma_method0_first_true_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_method0_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_method1_r(u32 i) { - return 0x000400c8 + i*8192; + return 0x000400c8U + i*8192U; } static inline u32 pbdma_method2_r(u32 i) { - return 0x000400d0 + i*8192; + return 0x000400d0U + i*8192U; } static inline u32 pbdma_method3_r(u32 i) { - return 0x000400d8 + i*8192; + return 0x000400d8U + i*8192U; } static inline u32 pbdma_data0_r(u32 i) { - return 0x000400c4 + i*8192; + return 0x000400c4U + i*8192U; } static inline u32 pbdma_acquire_r(u32 i) { - return 0x00040030 + i*8192; + return 0x00040030U + i*8192U; } static inline u32 pbdma_acquire_retry_man_2_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_acquire_retry_exp_2_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_acquire_timeout_exp_f(u32 v) { - return (v & 0xf) << 11; + return (v & 0xfU) << 11U; } static inline u32 pbdma_acquire_timeout_exp_max_v(void) { - return 0x0000000f; + return 0x0000000fU; } static inline u32 pbdma_acquire_timeout_exp_max_f(void) { - return 0x7800; + return 0x7800U; } static inline u32 pbdma_acquire_timeout_man_f(u32 v) { - return (v & 0xffff) << 15; + return (v & 0xffffU) << 15U; } static inline u32 pbdma_acquire_timeout_man_max_v(void) { - return 0x0000ffff; + return 0x0000ffffU; } static inline u32 pbdma_acquire_timeout_man_max_f(void) { - return 0x7fff8000; + return 0x7fff8000U; } static inline u32 pbdma_acquire_timeout_en_enable_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_acquire_timeout_en_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_status_r(u32 i) { - return 0x00040100 + i*8192; + return 0x00040100U + i*8192U; } static inline u32 pbdma_channel_r(u32 i) { - return 0x00040120 + i*8192; + return 0x00040120U + i*8192U; } static inline u32 pbdma_signature_r(u32 i) { - return 0x00040010 + i*8192; + return 0x00040010U + i*8192U; } static inline u32 pbdma_signature_hw_valid_f(void) { - return 0xface; + return 0xfaceU; } static inline u32 pbdma_signature_sw_zero_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_userd_r(u32 i) { - return 0x00040008 + i*8192; + return 0x00040008U + i*8192U; } static inline u32 pbdma_userd_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_userd_target_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 pbdma_userd_addr_f(u32 v) { - return (v & 0x7fffff) << 9; + return (v & 0x7fffffU) << 9U; } static inline u32 pbdma_config_r(u32 i) { - return 0x000400f4 + i*8192; + return 0x000400f4U + i*8192U; } static inline u32 pbdma_config_l2_evict_first_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_l2_evict_normal_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_config_l2_evict_last_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_config_ce_split_enable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_ce_split_disable_f(void) { - return 0x10; + return 0x10U; } static inline u32 pbdma_config_auth_level_non_privileged_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_auth_level_privileged_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_config_userd_writeback_disable_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_config_userd_writeback_enable_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 pbdma_userd_hi_r(u32 i) { - return 0x0004000c + i*8192; + return 0x0004000cU + i*8192U; } static inline u32 pbdma_userd_hi_addr_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pbdma_hce_ctrl_r(u32 i) { - return 0x000400e4 + i*8192; + return 0x000400e4U + i*8192U; } static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) { - return 0x20; + return 0x20U; } static inline u32 pbdma_intr_0_r(u32 i) { - return 0x00040108 + i*8192; + return 0x00040108U + i*8192U; } static inline u32 pbdma_intr_0_memreq_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pbdma_intr_0_memreq_pending_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) { - return 0x2; + return 0x2U; } static inline u32 pbdma_intr_0_memack_extra_pending_f(void) { - return 0x4; + return 0x4U; } static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) { - return 0x8; + return 0x8U; } static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) { - return 0x10; + return 0x10U; } static inline u32 pbdma_intr_0_memflush_pending_f(void) { - return 0x20; + return 0x20U; } static inline u32 pbdma_intr_0_memop_pending_f(void) { - return 0x40; + return 0x40U; } static inline u32 pbdma_intr_0_lbconnect_pending_f(void) { - return 0x80; + return 0x80U; } static inline u32 pbdma_intr_0_lbreq_pending_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) { - return 0x200; + return 0x200U; } static inline u32 pbdma_intr_0_lback_extra_pending_f(void) { - return 0x400; + return 0x400U; } static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) { - return 0x800; + return 0x800U; } static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) { - return 0x1000; + return 0x1000U; } static inline u32 pbdma_intr_0_gpfifo_pending_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 pbdma_intr_0_gpptr_pending_f(void) { - return 0x4000; + return 0x4000U; } static inline u32 pbdma_intr_0_gpentry_pending_f(void) { - return 0x8000; + return 0x8000U; } static inline u32 pbdma_intr_0_gpcrc_pending_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 pbdma_intr_0_pbptr_pending_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 pbdma_intr_0_pbentry_pending_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 pbdma_intr_0_pbcrc_pending_f(void) { - return 0x80000; + return 0x80000U; } static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) { - return 0x100000; + return 0x100000U; } static inline u32 pbdma_intr_0_method_pending_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 pbdma_intr_0_methodcrc_pending_f(void) { - return 0x400000; + return 0x400000U; } static inline u32 pbdma_intr_0_device_pending_f(void) { - return 0x800000; + return 0x800000U; } static inline u32 pbdma_intr_0_eng_reset_pending_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 pbdma_intr_0_semaphore_pending_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 pbdma_intr_0_acquire_pending_f(void) { - return 0x4000000; + return 0x4000000U; } static inline u32 pbdma_intr_0_pri_pending_f(void) { - return 0x8000000; + return 0x8000000U; } static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_intr_0_pbseg_pending_f(void) { - return 0x40000000; + return 0x40000000U; } static inline u32 pbdma_intr_0_signature_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_intr_1_r(u32 i) { - return 0x00040148 + i*8192; + return 0x00040148U + i*8192U; } static inline u32 pbdma_intr_1_ctxnotvalid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_intr_en_0_r(u32 i) { - return 0x0004010c + i*8192; + return 0x0004010cU + i*8192U; } static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_en_1_r(u32 i) { - return 0x0004014c + i*8192; + return 0x0004014cU + i*8192U; } static inline u32 pbdma_intr_stall_r(u32 i) { - return 0x0004013c + i*8192; + return 0x0004013cU + i*8192U; } static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) { - return 0x100; + return 0x100U; } static inline u32 pbdma_intr_stall_1_r(u32 i) { - return 0x00040140 + i*8192; + return 0x00040140U + i*8192U; } static inline u32 pbdma_udma_nop_r(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pbdma_runlist_timeslice_r(u32 i) { - return 0x000400f8 + i*8192; + return 0x000400f8U + i*8192U; } static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) { - return 0x80; + return 0x80U; } static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) { - return 0x3000; + return 0x3000U; } static inline u32 pbdma_runlist_timeslice_enable_true_f(void) { - return 0x10000000; + return 0x10000000U; } static inline u32 pbdma_target_r(u32 i) { - return 0x000400ac + i*8192; + return 0x000400acU + i*8192U; } static inline u32 pbdma_target_engine_sw_f(void) { - return 0x1f; + return 0x1fU; } static inline u32 pbdma_target_eng_ctx_valid_true_f(void) { - return 0x10000; + return 0x10000U; } static inline u32 pbdma_target_eng_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_ce_ctx_valid_true_f(void) { - return 0x20000; + return 0x20000U; } static inline u32 pbdma_target_ce_ctx_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) { - return 0x1000000; + return 0x1000000U; } static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) { - return 0x2000000; + return 0x2000000U; } static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) { - return 0x3000000; + return 0x3000000U; } static inline u32 pbdma_target_should_send_tsg_event_true_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pbdma_target_should_send_tsg_event_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_set_channel_info_r(u32 i) { - return 0x000400fc + i*8192; + return 0x000400fcU + i*8192U; } static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) { - return 0x0; + return 0x0U; } static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) { - return 0x1; + return 0x1U; } static inline u32 pbdma_set_channel_info_veid_f(u32 v) { - return (v & 0x3f) << 8; + return (v & 0x3fU) << 8U; } static inline u32 pbdma_timeout_r(u32 i) { - return 0x0004012c + i*8192; + return 0x0004012cU + i*8192U; } static inline u32 pbdma_timeout_period_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 pbdma_timeout_period_max_f(void) { - return 0xffffffff; + return 0xffffffffU; } static inline u32 pbdma_timeout_period_init_f(void) { - return 0x10000; + return 0x10000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h index d9c8a348..4fbe37cb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_perf_gv100.h @@ -58,154 +58,154 @@ static inline u32 perf_pmasys_control_r(void) { - return 0x0024a000; + return 0x0024a000U; } static inline u32 perf_pmasys_control_membuf_status_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) { - return 0x10; + return 0x10U; } static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) { - return (r >> 5) & 0x1; + return (r >> 5U) & 0x1U; } static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) { - return 0x20; + return 0x20U; } static inline u32 perf_pmasys_mem_block_r(void) { - return 0x0024a070; + return 0x0024a070U; } static inline u32 perf_pmasys_mem_block_base_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 perf_pmasys_mem_block_target_f(u32 v) { - return (v & 0x3) << 28; + return (v & 0x3U) << 28U; } static inline u32 perf_pmasys_mem_block_target_v(u32 r) { - return (r >> 28) & 0x3; + return (r >> 28U) & 0x3U; } static inline u32 perf_pmasys_mem_block_target_lfb_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 perf_pmasys_mem_block_target_lfb_f(void) { - return 0x0; + return 0x0U; } static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 perf_pmasys_mem_block_valid_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 perf_pmasys_mem_block_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 perf_pmasys_mem_block_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_mem_block_valid_true_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 perf_pmasys_mem_block_valid_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 perf_pmasys_mem_block_valid_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 perf_pmasys_outbase_r(void) { - return 0x0024a074; + return 0x0024a074U; } static inline u32 perf_pmasys_outbase_ptr_f(u32 v) { - return (v & 0x7ffffff) << 5; + return (v & 0x7ffffffU) << 5U; } static inline u32 perf_pmasys_outbaseupper_r(void) { - return 0x0024a078; + return 0x0024a078U; } static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 perf_pmasys_outsize_r(void) { - return 0x0024a07c; + return 0x0024a07cU; } static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) { - return (v & 0x7ffffff) << 5; + return (v & 0x7ffffffU) << 5U; } static inline u32 perf_pmasys_mem_bytes_r(void) { - return 0x0024a084; + return 0x0024a084U; } static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 perf_pmasys_mem_bump_r(void) { - return 0x0024a088; + return 0x0024a088U; } static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xfffffffU) << 4U; } static inline u32 perf_pmasys_enginestatus_r(void) { - return 0x0024a0a4; + return 0x0024a0a4U; } static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) { - return 0x10; + return 0x10U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h index 3250bf3e..8f005a22 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pram_gv100.h @@ -58,6 +58,6 @@ static inline u32 pram_data032_r(u32 i) { - return 0x00700000 + i*4; + return 0x00700000U + i*4U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h index ca9da11d..5eca93cc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h @@ -58,110 +58,110 @@ static inline u32 pri_ringmaster_command_r(void) { - return 0x0012004c; + return 0x0012004cU; } static inline u32 pri_ringmaster_command_cmd_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 pri_ringmaster_command_cmd_v(u32 r) { - return (r >> 0) & 0x3f; + return (r >> 0U) & 0x3fU; } static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) { - return 0x2; + return 0x2U; } static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) { - return 0x3; + return 0x3U; } static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) { - return 0x0; + return 0x0U; } static inline u32 pri_ringmaster_command_data_r(void) { - return 0x00120048; + return 0x00120048U; } static inline u32 pri_ringmaster_start_results_r(void) { - return 0x00120050; + return 0x00120050U; } static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 pri_ringmaster_intr_status0_r(void) { - return 0x00120058; + return 0x00120058U; } static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) { - return (r >> 1) & 0x1; + return (r >> 1U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 pri_ringmaster_intr_status1_r(void) { - return 0x0012005c; + return 0x0012005cU; } static inline u32 pri_ringmaster_global_ctl_r(void) { - return 0x00120060; + return 0x00120060U; } static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) { - return 0x0; + return 0x0U; } static inline u32 pri_ringmaster_enum_fbp_r(void) { - return 0x00120074; + return 0x00120074U; } static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 pri_ringmaster_enum_gpc_r(void) { - return 0x00120078; + return 0x00120078U; } static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 pri_ringmaster_enum_ltc_r(void) { - return 0x0012006c; + return 0x0012006cU; } static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h index 70cf0461..fc522d51 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h @@ -58,22 +58,22 @@ static inline u32 pri_ringstation_gpc_master_config_r(u32 i) { - return 0x00128300 + i*4; + return 0x00128300U + i*4U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) { - return 0x00128120; + return 0x00128120U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) { - return 0x00128124; + return 0x00128124U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) { - return 0x00128128; + return 0x00128128U; } static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) { - return 0x0012812c; + return 0x0012812cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h index 741e5bc2..885ea30a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h @@ -58,34 +58,34 @@ static inline u32 pri_ringstation_sys_master_config_r(u32 i) { - return 0x00122300 + i*4; + return 0x00122300U + i*4U; } static inline u32 pri_ringstation_sys_decode_config_r(void) { - return 0x00122204; + return 0x00122204U; } static inline u32 pri_ringstation_sys_decode_config_ring_m(void) { - return 0x7 << 0; + return 0x7U << 0U; } static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) { - return 0x1; + return 0x1U; } static inline u32 pri_ringstation_sys_priv_error_adr_r(void) { - return 0x00122120; + return 0x00122120U; } static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) { - return 0x00122124; + return 0x00122124U; } static inline u32 pri_ringstation_sys_priv_error_info_r(void) { - return 0x00122128; + return 0x00122128U; } static inline u32 pri_ringstation_sys_priv_error_code_r(void) { - return 0x0012212c; + return 0x0012212cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h index ca851cd4..52a7dfc4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h @@ -58,110 +58,110 @@ static inline u32 proj_gpc_base_v(void) { - return 0x00500000; + return 0x00500000U; } static inline u32 proj_gpc_shared_base_v(void) { - return 0x00418000; + return 0x00418000U; } static inline u32 proj_gpc_stride_v(void) { - return 0x00008000; + return 0x00008000U; } static inline u32 proj_ltc_stride_v(void) { - return 0x00002000; + return 0x00002000U; } static inline u32 proj_lts_stride_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 proj_fbpa_stride_v(void) { - return 0x00004000; + return 0x00004000U; } static inline u32 proj_ppc_in_gpc_base_v(void) { - return 0x00003000; + return 0x00003000U; } static inline u32 proj_ppc_in_gpc_stride_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 proj_rop_base_v(void) { - return 0x00410000; + return 0x00410000U; } static inline u32 proj_rop_shared_base_v(void) { - return 0x00408800; + return 0x00408800U; } static inline u32 proj_rop_stride_v(void) { - return 0x00000400; + return 0x00000400U; } static inline u32 proj_tpc_in_gpc_base_v(void) { - return 0x00004000; + return 0x00004000U; } static inline u32 proj_tpc_in_gpc_stride_v(void) { - return 0x00000800; + return 0x00000800U; } static inline u32 proj_tpc_in_gpc_shared_base_v(void) { - return 0x00001800; + return 0x00001800U; } static inline u32 proj_host_num_engines_v(void) { - return 0x0000000f; + return 0x0000000fU; } static inline u32 proj_host_num_pbdma_v(void) { - return 0x0000000e; + return 0x0000000eU; } static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 proj_scal_litter_num_fbps_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 proj_scal_litter_num_fbpas_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 proj_scal_litter_num_gpcs_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 proj_scal_litter_num_zcull_banks_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 proj_scal_max_gpcs_v(void) { - return 0x00000020; + return 0x00000020U; } static inline u32 proj_scal_max_tpc_per_gpc_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 proj_sm_stride_v(void) { - return 0x00000080; + return 0x00000080U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h index b85c37aa..4b0b0326 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pwr_gv100.h @@ -58,878 +58,878 @@ static inline u32 pwr_falcon_irqsset_r(void) { - return 0x0010a000; + return 0x0010a000U; } static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) { - return 0x40; + return 0x40U; } static inline u32 pwr_falcon_irqsclr_r(void) { - return 0x0010a004; + return 0x0010a004U; } static inline u32 pwr_falcon_irqstat_r(void) { - return 0x0010a008; + return 0x0010a008U; } static inline u32 pwr_falcon_irqstat_halt_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 pwr_falcon_irqstat_exterr_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) { - return 0x40; + return 0x40U; } static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) { - return 0x800; + return 0x800U; } static inline u32 pwr_falcon_irqmode_r(void) { - return 0x0010a00c; + return 0x0010a00cU; } static inline u32 pwr_falcon_irqmset_r(void) { - return 0x0010a010; + return 0x0010a010U; } static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqmset_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqmset_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqmclr_r(void) { - return 0x0010a014; + return 0x0010a014U; } static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqmask_r(void) { - return 0x0010a018; + return 0x0010a018U; } static inline u32 pwr_falcon_irqdest_r(void) { - return 0x0010a01c; + return 0x0010a01cU; } static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) { - return (v & 0x1) << 3; + return (v & 0x1U) << 3U; } static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) { - return (v & 0x1) << 9; + return (v & 0x1U) << 9U; } static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) { - return (v & 0x1) << 12; + return (v & 0x1U) << 12U; } static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) { - return (v & 0x1) << 13; + return (v & 0x1U) << 13U; } static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) { - return (v & 0x1) << 14; + return (v & 0x1U) << 14U; } static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) { - return (v & 0x1) << 17; + return (v & 0x1U) << 17U; } static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) { - return (v & 0x1) << 18; + return (v & 0x1U) << 18U; } static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) { - return (v & 0x1) << 19; + return (v & 0x1U) << 19U; } static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) { - return (v & 0x1) << 21; + return (v & 0x1U) << 21U; } static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) { - return (v & 0x1) << 22; + return (v & 0x1U) << 22U; } static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) { - return (v & 0x1) << 23; + return (v & 0x1U) << 23U; } static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) { - return (v & 0x1) << 27; + return (v & 0x1U) << 27U; } static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) { - return (v & 0x1) << 28; + return (v & 0x1U) << 28U; } static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) { - return (v & 0x1) << 29; + return (v & 0x1U) << 29U; } static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 pwr_falcon_curctx_r(void) { - return 0x0010a050; + return 0x0010a050U; } static inline u32 pwr_falcon_nxtctx_r(void) { - return 0x0010a054; + return 0x0010a054U; } static inline u32 pwr_falcon_mailbox0_r(void) { - return 0x0010a040; + return 0x0010a040U; } static inline u32 pwr_falcon_mailbox1_r(void) { - return 0x0010a044; + return 0x0010a044U; } static inline u32 pwr_falcon_itfen_r(void) { - return 0x0010a048; + return 0x0010a048U; } static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_falcon_idlestate_r(void) { - return 0x0010a04c; + return 0x0010a04cU; } static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) { - return (r >> 1) & 0x7fff; + return (r >> 1U) & 0x7fffU; } static inline u32 pwr_falcon_os_r(void) { - return 0x0010a080; + return 0x0010a080U; } static inline u32 pwr_falcon_engctl_r(void) { - return 0x0010a0a4; + return 0x0010a0a4U; } static inline u32 pwr_falcon_cpuctl_r(void) { - return 0x0010a100; + return 0x0010a100U; } static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) { - return (v & 0x1) << 6; + return (v & 0x1U) << 6U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) { - return 0x1 << 6; + return 0x1U << 6U; } static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 6U) & 0x1U; } static inline u32 pwr_falcon_cpuctl_alias_r(void) { - return 0x0010a130; + return 0x0010a130U; } static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 pwr_pmu_scpctl_stat_r(void) { - return 0x0010ac08; + return 0x0010ac08U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) { - return (v & 0x1) << 20; + return (v & 0x1U) << 20U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) { - return 0x1 << 20; + return 0x1U << 20U; } static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) { - return (r >> 20) & 0x1; + return (r >> 20U) & 0x1U; } static inline u32 pwr_falcon_imemc_r(u32 i) { - return 0x0010a180 + i*16; + return 0x0010a180U + i*16U; } static inline u32 pwr_falcon_imemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 pwr_falcon_imemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_imemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_imemd_r(u32 i) { - return 0x0010a184 + i*16; + return 0x0010a184U + i*16U; } static inline u32 pwr_falcon_imemt_r(u32 i) { - return 0x0010a188 + i*16; + return 0x0010a188U + i*16U; } static inline u32 pwr_falcon_sctl_r(void) { - return 0x0010a240; + return 0x0010a240U; } static inline u32 pwr_falcon_mmu_phys_sec_r(void) { - return 0x00100ce4; + return 0x00100ce4U; } static inline u32 pwr_falcon_bootvec_r(void) { - return 0x0010a104; + return 0x0010a104U; } static inline u32 pwr_falcon_bootvec_vec_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_falcon_dmactl_r(void) { - return 0x0010a10c; + return 0x0010a10cU; } static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_falcon_hwcfg_r(void) { - return 0x0010a108; + return 0x0010a108U; } static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) { - return (r >> 0) & 0x1ff; + return (r >> 0U) & 0x1ffU; } static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) { - return (r >> 9) & 0x1ff; + return (r >> 9U) & 0x1ffU; } static inline u32 pwr_falcon_dmatrfbase_r(void) { - return 0x0010a110; + return 0x0010a110U; } static inline u32 pwr_falcon_dmatrfbase1_r(void) { - return 0x0010a128; + return 0x0010a128U; } static inline u32 pwr_falcon_dmatrfmoffs_r(void) { - return 0x0010a114; + return 0x0010a114U; } static inline u32 pwr_falcon_dmatrfcmd_r(void) { - return 0x0010a118; + return 0x0010a118U; } static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) { - return (v & 0x7) << 8; + return (v & 0x7U) << 8U; } static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) { - return (v & 0x7) << 12; + return (v & 0x7U) << 12U; } static inline u32 pwr_falcon_dmatrffboffs_r(void) { - return 0x0010a11c; + return 0x0010a11cU; } static inline u32 pwr_falcon_exterraddr_r(void) { - return 0x0010a168; + return 0x0010a168U; } static inline u32 pwr_falcon_exterrstat_r(void) { - return 0x0010a16c; + return 0x0010a16cU; } static inline u32 pwr_falcon_exterrstat_valid_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 pwr_falcon_exterrstat_valid_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 pwr_pmu_falcon_icd_cmd_r(void) { - return 0x0010a200; + return 0x0010a200U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) { - return 4; + return 4U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0U) & 0xfU; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) { - return 0x8; + return 0x8U; } static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) { - return 0xe; + return 0xeU; } static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 pwr_pmu_falcon_icd_rdata_r(void) { - return 0x0010a20c; + return 0x0010a20cU; } static inline u32 pwr_falcon_dmemc_r(u32 i) { - return 0x0010a1c0 + i*8; + return 0x0010a1c0U + i*8U; } static inline u32 pwr_falcon_dmemc_offs_f(u32 v) { - return (v & 0x3f) << 2; + return (v & 0x3fU) << 2U; } static inline u32 pwr_falcon_dmemc_offs_m(void) { - return 0x3f << 2; + return 0x3fU << 2U; } static inline u32 pwr_falcon_dmemc_blk_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0xffU) << 8U; } static inline u32 pwr_falcon_dmemc_blk_m(void) { - return 0xff << 8; + return 0xffU << 8U; } static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) { - return (v & 0x1) << 25; + return (v & 0x1U) << 25U; } static inline u32 pwr_falcon_dmemd_r(u32 i) { - return 0x0010a1c4 + i*8; + return 0x0010a1c4U + i*8U; } static inline u32 pwr_pmu_new_instblk_r(void) { - return 0x0010a480; + return 0x0010a480U; } static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) { - return (v & 0xfffffff) << 0; + return (v & 0xfffffffU) << 0U; } static inline u32 pwr_pmu_new_instblk_target_fb_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) { - return 0x20000000; + return 0x20000000U; } static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) { - return 0x30000000; + return 0x30000000U; } static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) { - return (v & 0x1) << 30; + return (v & 0x1U) << 30U; } static inline u32 pwr_pmu_mutex_id_r(void) { - return 0x0010a488; + return 0x0010a488U; } static inline u32 pwr_pmu_mutex_id_value_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pwr_pmu_mutex_id_value_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) { - return 0x000000ff; + return 0x000000ffU; } static inline u32 pwr_pmu_mutex_id_release_r(void) { - return 0x0010a48c; + return 0x0010a48cU; } static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pwr_pmu_mutex_id_release_value_m(void) { - return 0xff << 0; + return 0xffU << 0U; } static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_mutex_r(u32 i) { - return 0x0010a580 + i*4; + return 0x0010a580U + i*4U; } static inline u32 pwr_pmu_mutex__size_1_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 pwr_pmu_mutex_value_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 pwr_pmu_mutex_value_v(u32 r) { - return (r >> 0) & 0xff; + return (r >> 0U) & 0xffU; } static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_queue_head_r(u32 i) { - return 0x0010a800 + i*4; + return 0x0010a800U + i*4U; } static inline u32 pwr_pmu_queue_head__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pwr_pmu_queue_head_address_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_queue_head_address_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_queue_tail_r(u32 i) { - return 0x0010a820 + i*4; + return 0x0010a820U + i*4U; } static inline u32 pwr_pmu_queue_tail__size_1_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 pwr_pmu_queue_tail_address_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_queue_tail_address_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_msgq_head_r(void) { - return 0x0010a4c8; + return 0x0010a4c8U; } static inline u32 pwr_pmu_msgq_head_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_msgq_head_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_msgq_tail_r(void) { - return 0x0010a4cc; + return 0x0010a4ccU; } static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) { - return (r >> 0) & 0xffffffff; + return (r >> 0U) & 0xffffffffU; } static inline u32 pwr_pmu_idle_mask_r(u32 i) { - return 0x0010a504 + i*16; + return 0x0010a504U + i*16U; } static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) { - return 0x200000; + return 0x200000U; } static inline u32 pwr_pmu_idle_count_r(u32 i) { - return 0x0010a508 + i*16; + return 0x0010a508U + i*16U; } static inline u32 pwr_pmu_idle_count_value_f(u32 v) { - return (v & 0x7fffffff) << 0; + return (v & 0x7fffffffU) << 0U; } static inline u32 pwr_pmu_idle_count_value_v(u32 r) { - return (r >> 0) & 0x7fffffff; + return (r >> 0U) & 0x7fffffffU; } static inline u32 pwr_pmu_idle_count_reset_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 pwr_pmu_idle_ctrl_r(u32 i) { - return 0x0010a50c + i*16; + return 0x0010a50cU + i*16U; } static inline u32 pwr_pmu_idle_ctrl_value_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) { - return 0x2; + return 0x2U; } static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) { - return 0x3; + return 0x3U; } static inline u32 pwr_pmu_idle_ctrl_filter_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) { - return 0x0010a9f0 + i*8; + return 0x0010a9f0U + i*8U; } static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) { - return 0x0010a9f4 + i*8; + return 0x0010a9f4U + i*8U; } static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) { - return 0x0010aa30 + i*8; + return 0x0010aa30U + i*8U; } static inline u32 pwr_pmu_debug_r(u32 i) { - return 0x0010a5c0 + i*4; + return 0x0010a5c0U + i*4U; } static inline u32 pwr_pmu_debug__size_1_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 pwr_pmu_mailbox_r(u32 i) { - return 0x0010a450 + i*4; + return 0x0010a450U + i*4U; } static inline u32 pwr_pmu_mailbox__size_1_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 pwr_pmu_bar0_addr_r(void) { - return 0x0010a7a0; + return 0x0010a7a0U; } static inline u32 pwr_pmu_bar0_data_r(void) { - return 0x0010a7a4; + return 0x0010a7a4U; } static inline u32 pwr_pmu_bar0_ctl_r(void) { - return 0x0010a7ac; + return 0x0010a7acU; } static inline u32 pwr_pmu_bar0_timeout_r(void) { - return 0x0010a7a8; + return 0x0010a7a8U; } static inline u32 pwr_pmu_bar0_fecs_error_r(void) { - return 0x0010a988; + return 0x0010a988U; } static inline u32 pwr_pmu_bar0_error_status_r(void) { - return 0x0010a7b0; + return 0x0010a7b0U; } static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) { - return 0x0010a6c0 + i*4; + return 0x0010a6c0U + i*4U; } static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) { - return 0x0010a6e8 + i*4; + return 0x0010a6e8U + i*4U; } static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) { - return 0x0010a710 + i*4; + return 0x0010a710U + i*4U; } static inline u32 pwr_pmu_pg_intren_r(u32 i) { - return 0x0010a760 + i*4; + return 0x0010a760U + i*4U; } static inline u32 pwr_fbif_transcfg_r(u32 i) { - return 0x0010ae00 + i*4; + return 0x0010ae00U + i*4U; } static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) { - return 0x1; + return 0x1U; } static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) { - return 0x2; + return 0x2U; } static inline u32 pwr_fbif_transcfg_mem_type_s(void) { - return 1; + return 1U; } static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 pwr_fbif_transcfg_mem_type_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) { - return 0x0; + return 0x0U; } static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) { - return 0x4; + return 0x4U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h index 3a5bf6cb..6b3e8aa6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h @@ -58,619 +58,619 @@ static inline u32 ram_in_ramfc_s(void) { - return 4096; + return 4096U; } static inline u32 ram_in_ramfc_w(void) { - return 0; + return 0U; } static inline u32 ram_in_page_dir_base_target_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_page_dir_base_target_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) { - return 0x2; + return 0x2U; } static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) { - return 0x3; + return 0x3U; } static inline u32 ram_in_page_dir_base_vol_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_vol_true_f(void) { - return 0x4; + return 0x4U; } static inline u32 ram_in_page_dir_base_vol_false_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) { - return 0x10; + return 0x10U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) { - return 0x1 << 5; + return 0x1U << 5U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) { - return 0x20; + return 0x20U; } static inline u32 ram_in_big_page_size_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 ram_in_big_page_size_m(void) { - return 0x1 << 11; + return 0x1U << 11U; } static inline u32 ram_in_big_page_size_w(void) { - return 128; + return 128U; } static inline u32 ram_in_big_page_size_128kb_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_big_page_size_64kb_f(void) { - return 0x800; + return 0x800U; } static inline u32 ram_in_page_dir_base_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_page_dir_base_lo_w(void) { - return 128; + return 128U; } static inline u32 ram_in_page_dir_base_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_page_dir_base_hi_w(void) { - return 129; + return 129U; } static inline u32 ram_in_engine_cs_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_cs_wfi_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_cs_wfi_f(void) { - return 0x0; + return 0x0U; } static inline u32 ram_in_engine_cs_fg_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_engine_cs_fg_f(void) { - return 0x8; + return 0x8U; } static inline u32 ram_in_engine_wfi_mode_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 ram_in_engine_wfi_mode_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_mode_physical_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_wfi_mode_virtual_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_engine_wfi_target_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_engine_wfi_target_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_in_engine_wfi_target_local_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_engine_wfi_ptr_lo_w(void) { - return 132; + return 132U; } static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ram_in_engine_wfi_ptr_hi_w(void) { - return 133; + return 133U; } static inline u32 ram_in_engine_wfi_veid_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 ram_in_engine_wfi_veid_w(void) { - return 134; + return 134U; } static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) { - return 136; + return 136U; } static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) { - return 137; + return 137U; } static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) { - return (v & 0x3) << (0 + i*0); + return (v & 0x3U) << (0U + i*0U); } static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) { - return (v & 0x1) << (2 + i*0); + return (v & 0x1U) << (2U + i*0U); } static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) { - return (v & 0x1) << (4 + i*0); + return (v & 0x1U) << (4U + i*0U); } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) { - return (v & 0x1) << (5 + i*0); + return (v & 0x1U) << (5U + i*0U); } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) { - return (v & 0x1) << (10 + i*0); + return (v & 0x1U) << (10U + i*0U); } static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) { - return (v & 0x1) << (11 + i*0); + return (v & 0x1U) << (11U + i*0U); } static inline u32 ram_in_sc_big_page_size__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_big_page_size_64kb_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) { - return (v & 0xfffff) << (12 + i*0); + return (v & 0xfffffU) << (12U + i*0U); } static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) { - return (v & 0xffffffff) << (0 + i*0); + return (v & 0xffffffffU) << (0U + i*0U); } static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0x3U) << 0U; } static inline u32 ram_in_sc_page_dir_base_target_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) { - return (v & 0x1) << 5; + return (v & 0x1U) << 5U; } static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) { - return (v & 0x1) << 10; + return (v & 0x1U) << 10U; } static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_big_page_size_0_f(u32 v) { - return (v & 0x1) << 11; + return (v & 0x1U) << 11U; } static inline u32 ram_in_sc_big_page_size_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) { - return 168; + return 168U; } static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) { - return 169; + return 169U; } static inline u32 ram_in_base_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 ram_in_alloc_size_v(void) { - return 0x00001000; + return 0x00001000U; } static inline u32 ram_fc_size_val_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ram_fc_gp_put_w(void) { - return 0; + return 0U; } static inline u32 ram_fc_userd_w(void) { - return 2; + return 2U; } static inline u32 ram_fc_userd_hi_w(void) { - return 3; + return 3U; } static inline u32 ram_fc_signature_w(void) { - return 4; + return 4U; } static inline u32 ram_fc_gp_get_w(void) { - return 5; + return 5U; } static inline u32 ram_fc_pb_get_w(void) { - return 6; + return 6U; } static inline u32 ram_fc_pb_get_hi_w(void) { - return 7; + return 7U; } static inline u32 ram_fc_pb_top_level_get_w(void) { - return 8; + return 8U; } static inline u32 ram_fc_pb_top_level_get_hi_w(void) { - return 9; + return 9U; } static inline u32 ram_fc_acquire_w(void) { - return 12; + return 12U; } static inline u32 ram_fc_sem_addr_hi_w(void) { - return 14; + return 14U; } static inline u32 ram_fc_sem_addr_lo_w(void) { - return 15; + return 15U; } static inline u32 ram_fc_sem_payload_lo_w(void) { - return 16; + return 16U; } static inline u32 ram_fc_sem_payload_hi_w(void) { - return 39; + return 39U; } static inline u32 ram_fc_sem_execute_w(void) { - return 17; + return 17U; } static inline u32 ram_fc_gp_base_w(void) { - return 18; + return 18U; } static inline u32 ram_fc_gp_base_hi_w(void) { - return 19; + return 19U; } static inline u32 ram_fc_gp_fetch_w(void) { - return 20; + return 20U; } static inline u32 ram_fc_pb_fetch_w(void) { - return 21; + return 21U; } static inline u32 ram_fc_pb_fetch_hi_w(void) { - return 22; + return 22U; } static inline u32 ram_fc_pb_put_w(void) { - return 23; + return 23U; } static inline u32 ram_fc_pb_put_hi_w(void) { - return 24; + return 24U; } static inline u32 ram_fc_pb_header_w(void) { - return 33; + return 33U; } static inline u32 ram_fc_pb_count_w(void) { - return 34; + return 34U; } static inline u32 ram_fc_subdevice_w(void) { - return 37; + return 37U; } static inline u32 ram_fc_target_w(void) { - return 43; + return 43U; } static inline u32 ram_fc_hce_ctrl_w(void) { - return 57; + return 57U; } static inline u32 ram_fc_chid_w(void) { - return 58; + return 58U; } static inline u32 ram_fc_chid_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_fc_chid_id_w(void) { - return 0; + return 0U; } static inline u32 ram_fc_config_w(void) { - return 61; + return 61U; } static inline u32 ram_fc_runlist_timeslice_w(void) { - return 62; + return 62U; } static inline u32 ram_fc_set_channel_info_w(void) { - return 63; + return 63U; } static inline u32 ram_userd_base_shift_v(void) { - return 0x00000009; + return 0x00000009U; } static inline u32 ram_userd_chan_size_v(void) { - return 0x00000200; + return 0x00000200U; } static inline u32 ram_userd_put_w(void) { - return 16; + return 16U; } static inline u32 ram_userd_get_w(void) { - return 17; + return 17U; } static inline u32 ram_userd_ref_w(void) { - return 18; + return 18U; } static inline u32 ram_userd_put_hi_w(void) { - return 19; + return 19U; } static inline u32 ram_userd_ref_threshold_w(void) { - return 20; + return 20U; } static inline u32 ram_userd_top_level_get_w(void) { - return 22; + return 22U; } static inline u32 ram_userd_top_level_get_hi_w(void) { - return 23; + return 23U; } static inline u32 ram_userd_get_hi_w(void) { - return 24; + return 24U; } static inline u32 ram_userd_gp_get_w(void) { - return 34; + return 34U; } static inline u32 ram_userd_gp_put_w(void) { - return 35; + return 35U; } static inline u32 ram_userd_gp_top_level_get_w(void) { - return 22; + return 22U; } static inline u32 ram_userd_gp_top_level_get_hi_w(void) { - return 23; + return 23U; } static inline u32 ram_rl_entry_size_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 ram_rl_entry_type_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 ram_rl_entry_type_channel_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_type_tsg_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_id_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) { - return (v & 0x1) << 1; + return (v & 0x1U) << 1U; } static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) { - return (v & 0x3) << 4; + return (v & 0x3U) << 4U; } static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) { @@ -682,94 +682,94 @@ static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void) } static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) { - return (v & 0x3) << 6; + return (v & 0x3U) << 6U; } static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xffffffU) << 8U; } static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_rl_entry_chid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) { - return (v & 0xfffff) << 12; + return (v & 0xfffffU) << 12U; } static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) { - return (v & 0xff) << 24; + return (v & 0xffU) << 24U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_tsg_length_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0xffU) << 0U; } static inline u32 ram_rl_entry_tsg_length_init_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 ram_rl_entry_tsg_length_min_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 ram_rl_entry_tsg_length_max_v(void) { - return 0x00000080; + return 0x00000080U; } static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) { - return (v & 0xfff) << 0; + return (v & 0xfffU) << 0U; } static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) { - return 0x0000000c; + return 0x0000000cU; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h index 2834acf8..2ea71ef1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_therm_gv100.h @@ -58,242 +58,242 @@ static inline u32 therm_weight_1_r(void) { - return 0x00020024; + return 0x00020024U; } static inline u32 therm_config1_r(void) { - return 0x00020050; + return 0x00020050U; } static inline u32 therm_config2_r(void) { - return 0x00020130; + return 0x00020130U; } static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) { - return (v & 0x1) << 24; + return (v & 0x1U) << 24U; } static inline u32 therm_config2_grad_enable_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 therm_gate_ctrl_r(u32 i) { - return 0x00020200 + i*4; + return 0x00020200U + i*4U; } static inline u32 therm_gate_ctrl_eng_clk_m(void) { - return 0x3 << 0; + return 0x3U << 0U; } static inline u32 therm_gate_ctrl_eng_clk_run_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) { - return 0x2; + return 0x2U; } static inline u32 therm_gate_ctrl_blk_clk_m(void) { - return 0x3 << 2; + return 0x3U << 2U; } static inline u32 therm_gate_ctrl_blk_clk_run_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) { - return 0x4; + return 0x4U; } static inline u32 therm_gate_ctrl_idle_holdoff_m(void) { - return 0x1 << 4; + return 0x1U << 4U; } static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) { - return 0x10; + return 0x10U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) { - return (v & 0x1f) << 8; + return (v & 0x1fU) << 8U; } static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) { - return 0x1f << 8; + return 0x1fU << 8U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) { - return (v & 0x7) << 13; + return (v & 0x7U) << 13U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) { - return 0x7 << 13; + return 0x7U << 13U; } static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) { - return (v & 0xf) << 16; + return (v & 0xfU) << 16U; } static inline u32 therm_gate_ctrl_eng_delay_before_m(void) { - return 0xf << 16; + return 0xfU << 16U; } static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) { - return (v & 0xf) << 20; + return (v & 0xfU) << 20U; } static inline u32 therm_gate_ctrl_eng_delay_after_m(void) { - return 0xf << 20; + return 0xfU << 20U; } static inline u32 therm_fecs_idle_filter_r(void) { - return 0x00020288; + return 0x00020288U; } static inline u32 therm_fecs_idle_filter_value_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 therm_hubmmu_idle_filter_r(void) { - return 0x0002028c; + return 0x0002028cU; } static inline u32 therm_hubmmu_idle_filter_value_m(void) { - return 0xffffffff << 0; + return 0xffffffffU << 0U; } static inline u32 therm_clk_slowdown_r(u32 i) { - return 0x00020160 + i*4; + return 0x00020160U + i*4U; } static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) { - return (v & 0x3f) << 16; + return (v & 0x3fU) << 16U; } static inline u32 therm_clk_slowdown_idle_factor_m(void) { - return 0x3f << 16; + return 0x3fU << 16U; } static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) { - return (r >> 16) & 0x3f; + return (r >> 16U) & 0x3fU; } static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_grad_stepping_table_r(u32 i) { - return 0x000202c8 + i*4; + return 0x000202c8U + i*4U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) { - return (v & 0x3f) << 0; + return (v & 0x3fU) << 0U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) { - return 0x3f << 0; + return 0x3fU << 0U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) { - return 0x2; + return 0x2U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) { - return 0x6; + return 0x6U; } static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) { - return 0xe; + return 0xeU; } static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) { - return (v & 0x3f) << 6; + return (v & 0x3fU) << 6U; } static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) { - return 0x3f << 6; + return 0x3fU << 6U; } static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) { - return (v & 0x3f) << 12; + return (v & 0x3fU) << 12U; } static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) { - return 0x3f << 12; + return 0x3fU << 12U; } static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) { - return (v & 0x3f) << 18; + return (v & 0x3fU) << 18U; } static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) { - return 0x3f << 18; + return 0x3fU << 18U; } static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) { - return (v & 0x3f) << 24; + return (v & 0x3fU) << 24U; } static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) { - return 0x3f << 24; + return 0x3fU << 24U; } static inline u32 therm_grad_stepping0_r(void) { - return 0x000202c0; + return 0x000202c0U; } static inline u32 therm_grad_stepping0_feature_s(void) { - return 1; + return 1U; } static inline u32 therm_grad_stepping0_feature_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 therm_grad_stepping0_feature_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 therm_grad_stepping0_feature_v(u32 r) { - return (r >> 0) & 0x1; + return (r >> 0U) & 0x1U; } static inline u32 therm_grad_stepping0_feature_enable_f(void) { - return 0x1; + return 0x1U; } static inline u32 therm_grad_stepping1_r(void) { - return 0x000202c4; + return 0x000202c4U; } static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x1ffffU) << 0U; } static inline u32 therm_clk_timing_r(u32 i) { - return 0x000203c0 + i*4; + return 0x000203c0U + i*4U; } static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) { - return (v & 0x1) << 16; + return (v & 0x1U) << 16U; } static inline u32 therm_clk_timing_grad_slowdown_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) { - return 0x10000; + return 0x10000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h index d53deb15..9d76e241 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_timer_gv100.h @@ -58,58 +58,58 @@ static inline u32 timer_pri_timeout_r(void) { - return 0x00009080; + return 0x00009080U; } static inline u32 timer_pri_timeout_period_f(u32 v) { - return (v & 0xffffff) << 0; + return (v & 0xffffffU) << 0U; } static inline u32 timer_pri_timeout_period_m(void) { - return 0xffffff << 0; + return 0xffffffU << 0U; } static inline u32 timer_pri_timeout_period_v(u32 r) { - return (r >> 0) & 0xffffff; + return (r >> 0U) & 0xffffffU; } static inline u32 timer_pri_timeout_en_f(u32 v) { - return (v & 0x1) << 31; + return (v & 0x1U) << 31U; } static inline u32 timer_pri_timeout_en_m(void) { - return 0x1 << 31; + return 0x1U << 31U; } static inline u32 timer_pri_timeout_en_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 timer_pri_timeout_en_en_enabled_f(void) { - return 0x80000000; + return 0x80000000U; } static inline u32 timer_pri_timeout_en_en_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 timer_pri_timeout_save_0_r(void) { - return 0x00009084; + return 0x00009084U; } static inline u32 timer_pri_timeout_save_1_r(void) { - return 0x00009088; + return 0x00009088U; } static inline u32 timer_pri_timeout_fecs_errcode_r(void) { - return 0x0000908c; + return 0x0000908cU; } static inline u32 timer_time_0_r(void) { - return 0x00009400; + return 0x00009400U; } static inline u32 timer_time_1_r(void) { - return 0x00009410; + return 0x00009410U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h index 35b3ab33..da297b72 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h @@ -58,178 +58,178 @@ static inline u32 top_num_gpcs_r(void) { - return 0x00022430; + return 0x00022430U; } static inline u32 top_num_gpcs_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_tpc_per_gpc_r(void) { - return 0x00022434; + return 0x00022434U; } static inline u32 top_tpc_per_gpc_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_num_fbps_r(void) { - return 0x00022438; + return 0x00022438U; } static inline u32 top_num_fbps_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_ltc_per_fbp_r(void) { - return 0x00022450; + return 0x00022450U; } static inline u32 top_ltc_per_fbp_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_slices_per_ltc_r(void) { - return 0x0002245c; + return 0x0002245cU; } static inline u32 top_slices_per_ltc_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_num_ltcs_r(void) { - return 0x00022454; + return 0x00022454U; } static inline u32 top_num_ces_r(void) { - return 0x00022444; + return 0x00022444U; } static inline u32 top_num_ces_value_v(u32 r) { - return (r >> 0) & 0x1f; + return (r >> 0U) & 0x1fU; } static inline u32 top_device_info_r(u32 i) { - return 0x00022700 + i*4; + return 0x00022700U + i*4U; } static inline u32 top_device_info__size_1_v(void) { - return 0x00000040; + return 0x00000040U; } static inline u32 top_device_info_chain_v(u32 r) { - return (r >> 31) & 0x1; + return (r >> 31U) & 0x1U; } static inline u32 top_device_info_chain_enable_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 top_device_info_engine_enum_v(u32 r) { - return (r >> 26) & 0xf; + return (r >> 26U) & 0xfU; } static inline u32 top_device_info_runlist_enum_v(u32 r) { - return (r >> 21) & 0xf; + return (r >> 21U) & 0xfU; } static inline u32 top_device_info_intr_enum_v(u32 r) { - return (r >> 15) & 0x1f; + return (r >> 15U) & 0x1fU; } static inline u32 top_device_info_reset_enum_v(u32 r) { - return (r >> 9) & 0x1f; + return (r >> 9U) & 0x1fU; } static inline u32 top_device_info_type_enum_v(u32 r) { - return (r >> 2) & 0x1fffffff; + return (r >> 2U) & 0x1fffffffU; } static inline u32 top_device_info_type_enum_graphics_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_type_enum_graphics_f(void) { - return 0x0; + return 0x0U; } static inline u32 top_device_info_type_enum_copy2_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 top_device_info_type_enum_copy2_f(void) { - return 0xc; + return 0xcU; } static inline u32 top_device_info_type_enum_lce_v(void) { - return 0x00000013; + return 0x00000013U; } static inline u32 top_device_info_type_enum_lce_f(void) { - return 0x4c; + return 0x4cU; } static inline u32 top_device_info_engine_v(u32 r) { - return (r >> 5) & 0x1; + return (r >> 5U) & 0x1U; } static inline u32 top_device_info_runlist_v(u32 r) { - return (r >> 4) & 0x1; + return (r >> 4U) & 0x1U; } static inline u32 top_device_info_intr_v(u32 r) { - return (r >> 3) & 0x1; + return (r >> 3U) & 0x1U; } static inline u32 top_device_info_reset_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 top_device_info_entry_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0U) & 0x3U; } static inline u32 top_device_info_entry_not_valid_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_entry_enum_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 top_device_info_entry_data_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 top_device_info_data_type_v(u32 r) { - return (r >> 30) & 0x1; + return (r >> 30U) & 0x1U; } static inline u32 top_device_info_data_type_enum2_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 top_device_info_data_inst_id_v(u32 r) { - return (r >> 26) & 0xf; + return (r >> 26U) & 0xfU; } static inline u32 top_device_info_data_pri_base_v(u32 r) { - return (r >> 12) & 0xfff; + return (r >> 12U) & 0xfffU; } static inline u32 top_device_info_data_pri_base_align_v(void) { - return 0x0000000c; + return 0x0000000cU; } static inline u32 top_device_info_data_fault_id_enum_v(u32 r) { - return (r >> 3) & 0x7f; + return (r >> 3U) & 0x7fU; } static inline u32 top_device_info_data_fault_id_v(u32 r) { - return (r >> 2) & 0x1; + return (r >> 2U) & 0x1U; } static inline u32 top_device_info_data_fault_id_valid_v(void) { - return 0x00000001; + return 0x00000001U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h index d49c9eed..7b1d861e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_usermode_gv100.h @@ -58,38 +58,38 @@ static inline u32 usermode_cfg0_r(void) { - return 0x00810000; + return 0x00810000U; } static inline u32 usermode_cfg0_class_id_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xffffU) << 0U; } static inline u32 usermode_cfg0_class_id_value_v(void) { - return 0x0000c361; + return 0x0000c361U; } static inline u32 usermode_time_0_r(void) { - return 0x00810080; + return 0x00810080U; } static inline u32 usermode_time_0_nsec_f(u32 v) { - return (v & 0x7ffffff) << 5; + return (v & 0x7ffffffU) << 5U; } static inline u32 usermode_time_1_r(void) { - return 0x00810084; + return 0x00810084U; } static inline u32 usermode_time_1_nsec_f(u32 v) { - return (v & 0x1fffffff) << 0; + return (v & 0x1fffffffU) << 0U; } static inline u32 usermode_notify_channel_pending_r(void) { - return 0x00810090; + return 0x00810090U; } static inline u32 usermode_notify_channel_pending_id_f(u32 v) { - return (v & 0xffffffff) << 0; + return (v & 0xffffffffU) << 0U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h index 8680c11a..4296e043 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xp_gv100.h @@ -58,86 +58,86 @@ static inline u32 xp_dl_mgr_r(u32 i) { - return 0x0008b8c0 + i*4; + return 0x0008b8c0U + i*4U; } static inline u32 xp_dl_mgr_safe_timing_f(u32 v) { - return (v & 0x1) << 2; + return (v & 0x1U) << 2U; } static inline u32 xp_pl_link_config_r(u32 i) { - return 0x0008c040 + i*4; + return 0x0008c040U + i*4U; } static inline u32 xp_pl_link_config_ltssm_status_f(u32 v) { - return (v & 0x1) << 4; + return (v & 0x1U) << 4U; } static inline u32 xp_pl_link_config_ltssm_status_idle_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v) { - return (v & 0xf) << 0; + return (v & 0xfU) << 0U; } static inline u32 xp_pl_link_config_ltssm_directive_m(void) { - return 0xf << 0; + return 0xfU << 0U; } static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 xp_pl_link_config_max_link_rate_f(u32 v) { - return (v & 0x3) << 18; + return (v & 0x3U) << 18U; } static inline u32 xp_pl_link_config_max_link_rate_m(void) { - return 0x3 << 18; + return 0x3U << 18U; } static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void) { - return 0x00000000; + return 0x00000000U; } static inline u32 xp_pl_link_config_target_tx_width_f(u32 v) { - return (v & 0x7) << 20; + return (v & 0x7U) << 20U; } static inline u32 xp_pl_link_config_target_tx_width_m(void) { - return 0x7 << 20; + return 0x7U << 20U; } static inline u32 xp_pl_link_config_target_tx_width_x1_v(void) { - return 0x00000007; + return 0x00000007U; } static inline u32 xp_pl_link_config_target_tx_width_x2_v(void) { - return 0x00000006; + return 0x00000006U; } static inline u32 xp_pl_link_config_target_tx_width_x4_v(void) { - return 0x00000005; + return 0x00000005U; } static inline u32 xp_pl_link_config_target_tx_width_x8_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 xp_pl_link_config_target_tx_width_x16_v(void) { - return 0x00000000; + return 0x00000000U; } #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h index 534f66b3..fc7aa72e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_xve_gv100.h @@ -58,150 +58,150 @@ static inline u32 xve_rom_ctrl_r(void) { - return 0x00000050; + return 0x00000050U; } static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v) { - return (v & 0x1) << 0; + return (v & 0x1U) << 0U; } static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void) { - return 0x0; + return 0x0U; } static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void) { - return 0x1; + return 0x1U; } static inline u32 xve_link_control_status_r(void) { - return 0x00000088; + return 0x00000088U; } static inline u32 xve_link_control_status_link_speed_m(void) { - return 0xf << 16; + return 0xfU << 16U; } static inline u32 xve_link_control_status_link_speed_v(u32 r) { - return (r >> 16) & 0xf; + return (r >> 16U) & 0xfU; } static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void) { - return 0x00000003; + return 0x00000003U; } static inline u32 xve_link_control_status_link_width_m(void) { - return 0x3f << 20; + return 0x3fU << 20U; } static inline u32 xve_link_control_status_link_width_v(u32 r) { - return (r >> 20) & 0x3f; + return (r >> 20U) & 0x3fU; } static inline u32 xve_link_control_status_link_width_x1_v(void) { - return 0x00000001; + return 0x00000001U; } static inline u32 xve_link_control_status_link_width_x2_v(void) { - return 0x00000002; + return 0x00000002U; } static inline u32 xve_link_control_status_link_width_x4_v(void) { - return 0x00000004; + return 0x00000004U; } static inline u32 xve_link_control_status_link_width_x8_v(void) { - return 0x00000008; + return 0x00000008U; } static inline u32 xve_link_control_status_link_width_x16_v(void) { - return 0x00000010; + return 0x00000010U; } static inline u32 xve_priv_xv_r(void) { - return 0x00000150; + return 0x00000150U; } static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v) { - return (v & 0x1) << 7; + return (v & 0x1U) << 7U; } static inline u32 xve_priv_xv_cya_l0s_enable_m(void) { - return 0x1 << 7; + return 0x1U << 7U; } static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r) { - return (r >> 7) & 0x1; + return (r >> 7U) & 0x1U; } static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v) { - return (v & 0x1) << 8; + return (v & 0x1U) << 8U; } static inline u32 xve_priv_xv_cya_l1_enable_m(void) { - return 0x1 << 8; + return 0x1U << 8U; } static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r) { - return (r >> 8) & 0x1; + return (r >> 8U) & 0x1U; } static inline u32 xve_cya_2_r(void) { - return 0x00000704; + return 0x00000704U; } static inline u32 xve_reset_r(void) { - return 0x00000718; + return 0x00000718U; } static inline u32 xve_reset_reset_m(void) { - return 0x1 << 0; + return 0x1U << 0U; } static inline u32 xve_reset_gpu_on_sw_reset_m(void) { - return 0x1 << 1; + return 0x1U << 1U; } static inline u32 xve_reset_counter_en_m(void) { - return 0x1 << 2; + return 0x1U << 2U; } static inline u32 xve_reset_counter_val_f(u32 v) { - return (v & 0x7ff) << 4; + return (v & 0x7ffU) << 4U; } static inline u32 xve_reset_counter_val_m(void) { - return 0x7ff << 4; + return 0x7ffU << 4U; } static inline u32 xve_reset_counter_val_v(u32 r) { - return (r >> 4) & 0x7ff; + return (r >> 4U) & 0x7ffU; } static inline u32 xve_reset_clock_on_sw_reset_m(void) { - return 0x1 << 15; + return 0x1U << 15U; } static inline u32 xve_reset_clock_counter_en_m(void) { - return 0x1 << 16; + return 0x1U << 16U; } static inline u32 xve_reset_clock_counter_val_f(u32 v) { - return (v & 0x7ff) << 17; + return (v & 0x7ffU) << 17U; } static inline u32 xve_reset_clock_counter_val_m(void) { - return 0x7ff << 17; + return 0x7ffU << 17U; } static inline u32 xve_reset_clock_counter_val_v(u32 r) { - return (r >> 17) & 0x7ff; + return (r >> 17U) & 0x7ffU; } #endif -- cgit v1.2.2 From a693acc5b45020b359bf11f0370b7dd63d4f994c Mon Sep 17 00:00:00 2001 From: Timo Alho Date: Thu, 12 Oct 2017 10:22:48 -0700 Subject: Revert "gpu: nvgpu: gv11b: disable cycle stat" This reverts commit 6647e5c9569258fbf3db096275a79f86f86ed3a6. Bug 200352825 Change-Id: Ia44d61eafce78f99be2271e0afaf69cd5c102080 Signed-off-by: Timo Alho Reviewed-on: https://git-master.nvidia.com/r/1577920 Reviewed-by: svc-mobile-coverity Reviewed-by: Terje Bergstrom Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Srikar Srimath Tirumala --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index c3f19fa2..da683af6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1688,7 +1688,12 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, void gr_gv11b_init_cyclestats(struct gk20a *g) { #if defined(CONFIG_GK20A_CYCLE_STATS) - /* TODO: waiting for cycle stats to be implemented for gv11b */ + g->gpu_characteristics.flags |= + NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS; + g->gpu_characteristics.flags |= + NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT; +#else + (void)g; #endif } -- cgit v1.2.2 From 506f891f76800b059e960a195bb0da4c71cb2e16 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 5 Jul 2017 22:55:39 -0700 Subject: gpu: nvgpu: gv11b: add syncpt shim ro map For sync-point read map, create read only map per vm and share with all channels that are using same vm. Now restrict rw map to single syncpoint shim memory range. JIRA GPUT19X-2 Change-Id: Ibd0b82d1cdb8861e1dbb073b27da1f9c9ab1d2ab Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1514339 Reviewed-by: svc-mobile-coverity Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 48 ++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 5fe40663..b8798033 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1664,33 +1664,41 @@ void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf) { - struct page **pages; u32 nr_pages; - u32 i; int err = 0; struct gk20a *g = c->g; + struct vm_gk20a *vm = c->vm; /* - * Add rw mapping for entire syncpt shim for current channel vm - * TODO : This needs to replaced with a new mecahnism where - * only current syncpoint range will be rw and other sync - * points range is read only for current channel vm. Also share - * these mapping accross channels if they share same vm - */ - nr_pages = DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE); - pages = nvgpu_kzalloc(g, sizeof(struct page *) * nr_pages); - for (i = 0; i < nr_pages; i++) - pages[i] = phys_to_page(g->syncpt_unit_base + - PAGE_SIZE * i); - __nvgpu_mem_create_from_pages(g, syncpt_buf, pages, nr_pages); - nvgpu_kfree(g, pages); + * Add ro map for complete sync point shim range in vm + * All channels sharing same vm will share same ro mapping. + * Create rw map for current channel sync point + */ + if (!vm->syncpt_ro_map_gpu_va) { + vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(c->vm, + &g->syncpt_mem, g->syncpt_unit_size, + 0, gk20a_mem_flag_read_only, + false, APERTURE_SYSMEM); + + if (!vm->syncpt_ro_map_gpu_va) { + nvgpu_err(g, "failed to ro map syncpt buffer"); + nvgpu_dma_free(g, &g->syncpt_mem); + err = -ENOMEM; + } + } + + nr_pages = DIV_ROUND_UP(g->syncpt_size, PAGE_SIZE); + __nvgpu_mem_create_from_phys(g, syncpt_buf, + (g->syncpt_unit_base + + nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id)), + nr_pages); syncpt_buf->gpu_va = nvgpu_gmmu_map(c->vm, syncpt_buf, - g->syncpt_unit_size, 0, gk20a_mem_flag_none, + g->syncpt_size, 0, gk20a_mem_flag_none, false, APERTURE_SYSMEM); if (!syncpt_buf->gpu_va) { - nvgpu_err(c->g, "failed to map syncpt buffer"); - nvgpu_dma_free(c->g, syncpt_buf); + nvgpu_err(g, "failed to map syncpt buffer"); + nvgpu_dma_free(g, syncpt_buf); err = -ENOMEM; } return err; @@ -1740,11 +1748,9 @@ u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, bool wfi_cmd, struct priv_cmd_entry *cmd, - u32 id, u64 gpu_va_base) + u32 id, u64 gpu_va) { u32 off = cmd->off; - u64 gpu_va = gpu_va_base + - nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(id); gk20a_dbg_fn(""); -- cgit v1.2.2 From b0092ea95c6e1f695912cdb0b13767f3881cb22f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 27 Sep 2017 15:05:50 -0700 Subject: gpu: nvgpu: gv11b: Abstract IO aperture accessors Implement T19x specific usermode aperture initialization functions. Move usermode_regs field to nvgpu_os_linux_t19x, because it is Linux specific. JIRA NVGPU-259 Change-Id: I9d6ce243a692ab48209d468288ed85f89fb26770 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1569699 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 2 + drivers/gpu/nvgpu/common/linux/io_t19x.c | 29 ++++++++++ drivers/gpu/nvgpu/common/linux/module_t19x.c | 62 ++++++++++++++++++++++ drivers/gpu/nvgpu/fifo_t19x.h | 1 - drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 10 ---- drivers/gpu/nvgpu/include/nvgpu/io_t19x.h | 29 ++++++++++ drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h | 26 +++++++++ .../gpu/nvgpu/include/nvgpu/linux/module_t19x.h | 27 ++++++++++ .../gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h | 26 +++++++++ .../nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 7 +-- 10 files changed, 205 insertions(+), 14 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/linux/io_t19x.c create mode 100644 drivers/gpu/nvgpu/common/linux/module_t19x.c create mode 100644 drivers/gpu/nvgpu/include/nvgpu/io_t19x.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 1ca21fb5..cc304df6 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -3,6 +3,8 @@ nvgpu-t19x := ../../../../nvgpu-t19x/drivers/gpu/nvgpu nvgpu-y += \ $(nvgpu-t19x)/common/mm/gmmu_t19x.o \ $(nvgpu-t19x)/common/linux/ioctl_tsg_t19x.o \ + $(nvgpu-t19x)/common/linux/io_t19x.o \ + $(nvgpu-t19x)/common/linux/module_t19x.o \ $(nvgpu-t19x)/gv11b/gv11b.o \ $(nvgpu-t19x)/gv11b/mc_gv11b.o \ $(nvgpu-t19x)/gv11b/ltc_gv11b.o \ diff --git a/drivers/gpu/nvgpu/common/linux/io_t19x.c b/drivers/gpu/nvgpu/common/linux/io_t19x.c new file mode 100644 index 00000000..5c6b76ba --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/io_t19x.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include "common/linux/os_linux.h" +#include "gk20a/gk20a.h" + +#include + +void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + void __iomem *reg = l->t19x.usermode_regs + (r - usermode_cfg0_r()); + + writel_relaxed(v, reg); + gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); +} diff --git a/drivers/gpu/nvgpu/common/linux/module_t19x.c b/drivers/gpu/nvgpu/common/linux/module_t19x.c new file mode 100644 index 00000000..f0e3d438 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/module_t19x.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include + +#include "common/linux/os_linux.h" + +/* + * Locks out the driver from accessing GPU registers. This prevents access to + * thse registers after the GPU has been clock or power gated. This should help + * find annoying bugs where register reads and writes are silently dropped + * after the GPU has been turned off. On older chips these reads and writes can + * also lock the entire CPU up. + */ +void t19x_lockout_registers(struct gk20a *g) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + l->t19x.usermode_regs = NULL; +} + +/* + * Undoes t19x_lockout_registers(). + */ +void t19x_restore_registers(struct gk20a *g) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + l->t19x.usermode_regs = l->t19x.usermode_regs_saved; +} + +void t19x_remove_support(struct gk20a *g) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + if (l->t19x.usermode_regs) { + l->t19x.usermode_regs = NULL; + } +} + +void t19x_init_support(struct gk20a *g) +{ + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + + l->t19x.usermode_regs = l->regs + usermode_cfg0_r(); + l->t19x.usermode_regs_saved = l->t19x.usermode_regs; +} diff --git a/drivers/gpu/nvgpu/fifo_t19x.h b/drivers/gpu/nvgpu/fifo_t19x.h index 6d508304..7274d1fe 100644 --- a/drivers/gpu/nvgpu/fifo_t19x.h +++ b/drivers/gpu/nvgpu/fifo_t19x.h @@ -24,7 +24,6 @@ #define _FIFO_T19X_H_ struct fifo_t19x { - void __iomem *usermode_regs; u32 max_subctx_count; }; diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b8798033..e9830c0e 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -61,15 +61,6 @@ static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, struct channel_gk20a *ch, struct nvgpu_mem *mem); -static inline void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) -{ - struct fifo_gk20a *f = &g->fifo; - void __iomem *reg = f->t19x.usermode_regs + (r - usermode_cfg0_r()); - - writel_relaxed(v, reg); - gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); -} - void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { @@ -1787,7 +1778,6 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g) { struct fifo_gk20a *f = &g->fifo; - f->t19x.usermode_regs = g->regs + usermode_cfg0_r(); f->t19x.max_subctx_count = gr_pri_fe_chip_def_info_max_veid_count_init_v(); return 0; diff --git a/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h new file mode 100644 index 00000000..f8c7dbbd --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __NVGPU_IO_T19X_H__ +#define __NVGPU_IO_T19X_H__ + +#ifdef __KERNEL__ +#include "linux/io_t19x.h" +#endif + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h new file mode 100644 index 00000000..f71a6ecf --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVGPU_IO_T19X_LINUX_H__ +#define __NVGPU_IO_T19X_LINUX_H__ + +#include + +struct gk20a; + +void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v); + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h new file mode 100644 index 00000000..a105c6dc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __NVGPU_MODULE_T19X_H__ +#define __NVGPU_MODULE_T19X_H__ + +struct gk20a; + +void t19x_init_support(struct gk20a *g); +void t19x_remove_support(struct gk20a *g); +void t19x_lockout_registers(struct gk20a *g); +void t19x_restore_registers(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h new file mode 100644 index 00000000..a306bfb8 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef NVGPU_OS_LINUX_T19X_H +#define NVGPU_OS_LINUX_T19X_H + +#include + +struct nvgpu_os_linux_t19x { + void __iomem *usermode_regs; + void __iomem *usermode_regs_saved; +}; + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 396359c3..6adbd46b 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -23,6 +23,7 @@ #include "gk20a/gk20a.h" #include "gk20a/platform_gk20a.h" #include "vgpu/clk_vgpu.h" +#include "common/linux/os_linux.h" #include #include @@ -33,7 +34,7 @@ static int gv11b_vgpu_probe(struct device *dev) struct gk20a_platform *platform = dev_get_drvdata(dev); struct resource *r; void __iomem *regs; - struct fifo_gk20a *f = &platform->g->fifo; + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(platform->g); int ret; r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usermode"); @@ -46,12 +47,12 @@ static int gv11b_vgpu_probe(struct device *dev) dev_err(dev, "failed to map usermode regs\n"); return PTR_ERR(regs); } - f->t19x.usermode_regs = regs; + l->t19x.usermode_regs = regs; #ifdef CONFIG_TEGRA_GK20A_NVHOST ret = nvgpu_get_nvhost_dev(platform->g); if (ret) { - f->t19x.usermode_regs = NULL; + l->t19x.usermode_regs = NULL; return ret; } #endif -- cgit v1.2.2 From 7612e412151c676c4e7af08839bd98d879a25dea Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 2 Oct 2017 16:37:50 -0700 Subject: gpu: nvgpu: gvxx: add hw defines for pbdma info Generated following hw definitions to dump relevant data: pbdma_gp_shadow_0_r pbdma_gp_shadow_1_r Bug 2003671 Change-Id: If2d0557b3c2896747793ff2afad875206e25c6d8 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1572183 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h | 8 ++++++++ drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h index 2d98b914..66a0737c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pbdma_gv100.h @@ -172,6 +172,14 @@ static inline u32 pbdma_hdr_shadow_r(u32 i) { return 0x00040118U + i*8192U; } +static inline u32 pbdma_gp_shadow_0_r(u32 i) +{ + return 0x00040110U + i*8192U; +} +static inline u32 pbdma_gp_shadow_1_r(u32 i) +{ + return 0x00040114U + i*8192U; +} static inline u32 pbdma_subdevice_r(u32 i) { return 0x00040094U + i*8192U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index 74ff4002..9b9017ee 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h @@ -172,6 +172,14 @@ static inline u32 pbdma_hdr_shadow_r(u32 i) { return 0x00040118U + i*8192U; } +static inline u32 pbdma_gp_shadow_0_r(u32 i) +{ + return 0x00040110U + i*8192U; +} +static inline u32 pbdma_gp_shadow_1_r(u32 i) +{ + return 0x00040114U + i*8192U; +} static inline u32 pbdma_subdevice_r(u32 i) { return 0x00040094U + i*8192U; -- cgit v1.2.2 From 4b8dc71de5696679f13f8863bc5775a23e786b34 Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 6 Oct 2017 15:38:11 -0700 Subject: gpu: nvgpu: vgpu: flatten out t19x vgpu hal Instead of calling the native HAL init function then adding multiple layers of modification for VGPU, flatten out the sequence so that all entry points are set statically and visible in a single file. JIRA ESRM-30 Change-Id: I8d277aaccb0e63b2d504e7aba32eb31ef82f4ec0 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1574619 Reviewed-by: svc-mobile-coverity Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.h | 3 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 16 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h | 5 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c | 10 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h | 4 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 618 ++++++++++++++++++++++++- 7 files changed, 619 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4a289d8f..4241145a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -94,7 +94,7 @@ #include #include -static int gv11b_get_litter_value(struct gk20a *g, int value) +int gv11b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; switch (value) { diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.h b/drivers/gpu/nvgpu/gv11b/hal_gv11b.h index 0fdda6f3..668353dc 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.h @@ -1,7 +1,7 @@ /* * GV11B Tegra HAL interface * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,4 +27,5 @@ struct gk20a; int gv11b_init_hal(struct gk20a *gops); +int gv11b_get_litter_value(struct gk20a *g, int value); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c index ff13b11f..048a4c64 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -21,14 +21,10 @@ */ #include -#include #include "vgpu/vgpu.h" -#include "vgpu_fifo_gv11b.h" -#include "vgpu_subctx_gv11b.h" - -static int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) +int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) { struct fifo_gk20a *f = &g->fifo; int err; @@ -43,13 +39,3 @@ static int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) return 0; } - -void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops) -{ - vgpu_gp10b_init_fifo_ops(gops); - - gops->fifo.init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw; - gops->fifo.free_channel_ctx_header = vgpu_gv11b_free_subctx_header; - /* TODO: implement it for CE fault */ - gops->fifo.tsg_verify_status_faulted = NULL; -} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h index b3c7f729..03404542 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h @@ -23,8 +23,7 @@ #ifndef _VGPU_FIFO_GV11B_H_ #define _VGPU_FIFO_GV11B_H_ -struct gpu_ops; - -void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops); +struct gk20a; +int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c index a3d1cd90..89952221 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c @@ -22,12 +22,10 @@ #include #include -#include -#include "vgpu_gr_gv11b.h" #include "vgpu_subctx_gv11b.h" -static int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) +int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) { int err; @@ -41,9 +39,3 @@ static int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) return err; } - -void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops) -{ - vgpu_gp10b_init_gr_ops(gops); - gops->gr.commit_inst = vgpu_gr_gv11b_commit_inst; -} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h index 933aa06b..562198ca 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h @@ -23,6 +23,8 @@ #ifndef _VGPU_GR_GV11B_H_ #define _VGPU_GR_GV11B_H_ -void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops); +struct channel_gk20a; + +int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 34f1198f..aa661d66 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -23,27 +23,627 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include #include +#include #include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include #include "vgpu_gr_gv11b.h" #include "vgpu_fifo_gv11b.h" +#include "vgpu_subctx_gv11b.h" + +#include +#include +#include +#include +#include + +static const struct gpu_ops vgpu_gv11b_ops = { + .ltc = { + .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, + .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = vgpu_ltc_init_fs_state, + .init_comptags = vgpu_ltc_init_comptags, + .cbc_ctrl = NULL, + .isr = gv11b_ltc_isr, + .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, + .set_enabled = gp10b_ltc_set_enabled, + }, + .ce2 = { + .isr_stall = gv11b_ce_isr, + .isr_nonstall = gp10b_ce_nonstall_isr, + .get_num_pce = vgpu_ce_get_num_pce, + }, + .gr = { + .init_gpc_mmu = gr_gv11b_init_gpc_mmu, + .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, + .cb_size_default = gr_gv11b_cb_size_default, + .calc_global_ctx_buffer_size = + gr_gv11b_calc_global_ctx_buffer_size, + .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, + .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, + .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, + .commit_global_pagepool = gr_gp10b_commit_global_pagepool, + .handle_sw_method = gr_gv11b_handle_sw_method, + .set_alpha_circular_buffer_size = + gr_gv11b_set_alpha_circular_buffer_size, + .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, + .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, + .is_valid_class = gr_gv11b_is_valid_class, + .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, + .is_valid_compute_class = gr_gv11b_is_valid_compute_class, + .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, + .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, + .init_fs_state = vgpu_gm20b_init_fs_state, + .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, + .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, + .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, + .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, + .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, + .free_channel_ctx = vgpu_gr_free_channel_ctx, + .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, + .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, + .get_zcull_info = vgpu_gr_get_zcull_info, + .is_tpc_addr = gr_gm20b_is_tpc_addr, + .get_tpc_num = gr_gm20b_get_tpc_num, + .detect_sm_arch = vgpu_gr_detect_sm_arch, + .add_zbc_color = gr_gp10b_add_zbc_color, + .add_zbc_depth = gr_gp10b_add_zbc_depth, + .zbc_set_table = vgpu_gr_add_zbc, + .zbc_query_table = vgpu_gr_query_zbc, + .pmu_save_zbc = gk20a_pmu_save_zbc, + .add_zbc = gr_gk20a_add_zbc, + .pagepool_default_size = gr_gv11b_pagepool_default_size, + .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, + .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, + .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx, + .update_ctxsw_preemption_mode = + gr_gp10b_update_ctxsw_preemption_mode, + .dump_gr_regs = NULL, + .update_pc_sampling = gr_gm20b_update_pc_sampling, + .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, + .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp, + .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc, + .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, + .get_max_fbps_count = vgpu_gr_get_max_fbps_count, + .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, + .wait_empty = gr_gv11b_wait_empty, + .init_cyclestats = gr_gv11b_init_cyclestats, + .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, + .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, + .bpt_reg_info = gv11b_gr_bpt_reg_info, + .get_access_map = gr_gv11b_get_access_map, + .handle_fecs_error = gr_gv11b_handle_fecs_error, + .handle_sm_exception = gr_gk20a_handle_sm_exception, + .handle_tex_exception = gr_gv11b_handle_tex_exception, + .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, + .enable_exceptions = gr_gv11b_enable_exceptions, + .get_lrf_tex_ltc_dram_override = get_ecc_override_val, + .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, + .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, + .record_sm_error_state = gv11b_gr_record_sm_error_state, + .update_sm_error_state = gv11b_gr_update_sm_error_state, + .clear_sm_error_state = vgpu_gr_clear_sm_error_state, + .suspend_contexts = vgpu_gr_suspend_contexts, + .resume_contexts = vgpu_gr_resume_contexts, + .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, + .fuse_override = gp10b_gr_fuse_override, + .init_sm_id_table = gr_gv11b_init_sm_id_table, + .load_smid_config = gr_gv11b_load_smid_config, + .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, + .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, + .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, + .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, + .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, + .setup_rop_mapping = gr_gv11b_setup_rop_mapping, + .program_zcull_mapping = gr_gv11b_program_zcull_mapping, + .commit_global_timeslice = gr_gv11b_commit_global_timeslice, + .commit_inst = vgpu_gr_gv11b_commit_inst, + .write_zcull_ptr = gr_gv11b_write_zcull_ptr, + .write_pm_ptr = gr_gv11b_write_pm_ptr, + .init_elcg_mode = gr_gv11b_init_elcg_mode, + .load_tpc_mask = gr_gv11b_load_tpc_mask, + .inval_icache = gr_gk20a_inval_icache, + .trigger_suspend = gv11b_gr_sm_trigger_suspend, + .wait_for_pause = gr_gk20a_wait_for_pause, + .resume_from_pause = gv11b_gr_resume_from_pause, + .clear_sm_errors = gr_gk20a_clear_sm_errors, + .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, + .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, + .sm_debugger_attached = gv11b_gr_sm_debugger_attached, + .suspend_single_sm = gv11b_gr_suspend_single_sm, + .suspend_all_sms = gv11b_gr_suspend_all_sms, + .resume_single_sm = gv11b_gr_resume_single_sm, + .resume_all_sms = gv11b_gr_resume_all_sms, + .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, + .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, + .get_sm_no_lock_down_hww_global_esr_mask = + gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, + .lock_down_sm = gv11b_gr_lock_down_sm, + .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, + .clear_sm_hww = gv11b_gr_clear_sm_hww, + .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, + .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, + .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .set_boosted_ctx = NULL, + .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, + .set_czf_bypass = NULL, + .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, + .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, + .init_preemption_state = NULL, + .update_boosted_ctx = NULL, + .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, + .create_gr_sysfs = gr_gv11b_create_sysfs, + .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode, + .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, + .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, + .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, + .zbc_s_query_table = gr_gv11b_zbc_s_query_table, + .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, + .restore_context_header = gv11b_restore_context_header, + .handle_gpc_gpcmmu_exception = + gr_gv11b_handle_gpc_gpcmmu_exception, + .add_zbc_type_s = gr_gv11b_add_zbc_type_s, + .get_egpc_base = gv11b_gr_get_egpc_base, + .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, + .handle_gpc_gpccs_exception = + gr_gv11b_handle_gpc_gpccs_exception, + .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, + .access_smpc_reg = gv11b_gr_access_smpc_reg, + .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, + .add_zbc_s = gr_gv11b_add_zbc_stencil, + .handle_gcc_exception = gr_gv11b_handle_gcc_exception, + .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, + .handle_tpc_sm_ecc_exception = + gr_gv11b_handle_tpc_sm_ecc_exception, + .decode_egpc_addr = gv11b_gr_decode_egpc_addr, + .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, + }, + .fb = { + .reset = gv11b_fb_reset, + .init_hw = gk20a_fb_init_hw, + .init_fs_state = gv11b_fb_init_fs_state, + .init_cbc = gv11b_fb_init_cbc, + .set_mmu_page_size = gm20b_fb_set_mmu_page_size, + .set_use_full_comp_tag_line = + gm20b_fb_set_use_full_comp_tag_line, + .compression_page_size = gp10b_fb_compression_page_size, + .compressible_page_size = gp10b_fb_compressible_page_size, + .vpr_info_fetch = gm20b_fb_vpr_info_fetch, + .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .read_wpr_info = gm20b_fb_read_wpr_info, + .is_debug_mode_enabled = NULL, + .set_debug_mode = vgpu_mm_mmu_set_debug_mode, + .tlb_invalidate = vgpu_mm_tlb_invalidate, + .hub_isr = gv11b_fb_hub_isr, + }, + .clock_gating = { + .slcg_bus_load_gating_prod = + gv11b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gv11b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gv11b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gv11b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gv11b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gv11b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gv11b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gv11b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gv11b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gv11b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gv11b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gv11b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gv11b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gv11b_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gv11b_blcg_ce_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gv11b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gv11b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gv11b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gv11b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gv11b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gv11b_blcg_pwr_csb_load_gating_prod, + .blcg_pmu_load_gating_prod = + gv11b_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gv11b_blcg_xbar_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gv11b_pg_gr_load_gating_prod, + }, + .fifo = { + .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw, + .bind_channel = vgpu_channel_bind, + .unbind_channel = vgpu_channel_unbind, + .disable_channel = vgpu_channel_disable, + .enable_channel = vgpu_channel_enable, + .alloc_inst = vgpu_channel_alloc_inst, + .free_inst = vgpu_channel_free_inst, + .setup_ramfc = vgpu_channel_setup_ramfc, + .channel_set_priority = vgpu_channel_set_priority, + .channel_set_timeslice = vgpu_channel_set_timeslice, + .default_timeslice_us = vgpu_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gv11b_userd_gp_get, + .userd_gp_put = gv11b_userd_gp_put, + .userd_pb_get = gv11b_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = vgpu_fifo_preempt_channel, + .preempt_tsg = vgpu_fifo_preempt_tsg, + .enable_tsg = gk20a_enable_tsg, + .disable_tsg = gk20a_disable_tsg, + .tsg_verify_channel_status = NULL, + .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, + /* TODO: implement it for CE fault */ + .tsg_verify_status_faulted = NULL, + .update_runlist = vgpu_fifo_update_runlist, + .trigger_mmu_fault = NULL, + .get_mmu_fault_info = NULL, + .wait_engine_idle = vgpu_fifo_wait_engine_idle, + .get_num_fifos = gv11b_fifo_get_num_fifos, + .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, + .set_runlist_interleave = vgpu_fifo_set_runlist_interleave, + .tsg_set_timeslice = vgpu_tsg_set_timeslice, + .tsg_open = vgpu_tsg_open, + .force_reset_ch = vgpu_fifo_force_reset_ch, + .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, + .device_info_data_parse = gp10b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = vgpu_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, + .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gv11b_dump_eng_status, + .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, + .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, + .is_preempt_pending = gv11b_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, + .handle_sched_error = gv11b_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, + .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, + .deinit_eng_method_buffers = + gv11b_fifo_deinit_eng_method_buffers, + .tsg_bind_channel = vgpu_tsg_bind_channel, + .tsg_unbind_channel = vgpu_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, +#endif + .resetup_ramfc = NULL, + .reschedule_runlist = NULL, + .device_info_fault_id = top_device_info_data_fault_id_enum_v, + .free_channel_ctx_header = vgpu_gv11b_free_subctx_header, + .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + }, + .gr_ctx = { + .get_netlist_name = gr_gv11b_get_netlist_name, + .is_fw_defined = gr_gv11b_is_firmware_defined, + }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = NULL, + .free_user_buffer = NULL, + .mmap_user_buffer = NULL, + .init = NULL, + .deinit = NULL, + .enable = NULL, + .disable = NULL, + .is_enabled = NULL, + .reset = NULL, + .flush = NULL, + .poll = NULL, + .bind_channel = NULL, + .unbind_channel = NULL, + .max_entries = NULL, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + /* FIXME: add support for sparse mappings */ + .support_sparse = NULL, + .gmmu_map = vgpu_gp10b_locked_gmmu_map, + .gmmu_unmap = vgpu_locked_gmmu_unmap, + .vm_bind_channel = vgpu_vm_bind_channel, + .fb_flush = vgpu_mm_fb_flush, + .l2_invalidate = vgpu_mm_l2_invalidate, + .l2_flush = vgpu_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gm20b_gpu_phys_addr, + .get_iommu_bit = gk20a_mm_get_iommu_bit, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, + .is_bar1_supported = gv11b_mm_is_bar1_supported, + .init_inst_block = gv11b_init_inst_block, + .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gv11b_mm_remove_bar2_vm, + .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + }, + .therm = { + .init_therm_setup_hw = gp10b_init_therm_setup_hw, + .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, + }, + .pmu = { + .pmu_setup_elpg = gp10b_pmu_setup_elpg, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .write_dmatrfbase = gp10b_write_dmatrfbase, + .pmu_elpg_statistics = gp106_pmu_elpg_statistics, + .pmu_pg_init_param = gv11b_pg_gr_init, + .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, + .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, + .dump_secure_fuses = pmu_dump_security_fuses_gp10b, + .reset_engine = gp106_pmu_engine_reset, + .is_engine_in_reset = gp106_pmu_is_engine_in_reset, + .pmu_nsbootstrap = gv11b_pmu_bootstrap, + .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask, + .is_pmu_supported = gv11b_is_pmu_supported, + }, + .regops = { + .get_global_whitelist_ranges = + gv11b_get_global_whitelist_ranges, + .get_global_whitelist_ranges_count = + gv11b_get_global_whitelist_ranges_count, + .get_context_whitelist_ranges = + gv11b_get_context_whitelist_ranges, + .get_context_whitelist_ranges_count = + gv11b_get_context_whitelist_ranges_count, + .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist, + .get_runcontrol_whitelist_count = + gv11b_get_runcontrol_whitelist_count, + .get_runcontrol_whitelist_ranges = + gv11b_get_runcontrol_whitelist_ranges, + .get_runcontrol_whitelist_ranges_count = + gv11b_get_runcontrol_whitelist_ranges_count, + .get_qctl_whitelist = gv11b_get_qctl_whitelist, + .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count, + .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges, + .get_qctl_whitelist_ranges_count = + gv11b_get_qctl_whitelist_ranges_count, + .apply_smpc_war = gv11b_apply_smpc_war, + }, + .mc = { + .intr_enable = mc_gv11b_intr_enable, + .intr_unit_config = mc_gp10b_intr_unit_config, + .isr_stall = mc_gp10b_isr_stall, + .intr_stall = mc_gp10b_intr_stall, + .intr_stall_pause = mc_gp10b_intr_stall_pause, + .intr_stall_resume = mc_gp10b_intr_stall_resume, + .intr_nonstall = mc_gp10b_intr_nonstall, + .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, + .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .enable = gk20a_mc_enable, + .disable = gk20a_mc_disable, + .reset = gk20a_mc_reset, + .boot_0 = gk20a_mc_boot_0, + .is_intr1_pending = mc_gp10b_is_intr1_pending, + .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, + }, + .debug = { + .show_dump = NULL, + }, + .dbg_session_ops = { + .exec_reg_ops = vgpu_exec_regops, + .dbg_set_powergate = vgpu_dbg_set_powergate, + .check_and_set_global_reservation = + vgpu_check_and_set_global_reservation, + .check_and_set_context_reservation = + vgpu_check_and_set_context_reservation, + .release_profiler_reservation = + vgpu_release_profiler_reservation, + .perfbuffer_enable = vgpu_perfbuffer_enable, + .perfbuffer_disable = vgpu_perfbuffer_disable, + }, + .bus = { + .init_hw = gk20a_bus_init_hw, + .isr = gk20a_bus_isr, + .read_ptimer = vgpu_read_ptimer, + .get_timestamps_zipper = vgpu_get_timestamps_zipper, + .bar1_bind = NULL, + }, +#if defined(CONFIG_GK20A_CYCLE_STATS) + .css = { + .enable_snapshot = vgpu_css_enable_snapshot_buffer, + .disable_snapshot = vgpu_css_release_snapshot_buffer, + .check_data_available = vgpu_css_flush_snapshots, + .set_handled_snapshots = NULL, + .allocate_perfmon_ids = NULL, + .release_perfmon_ids = NULL, + }, +#endif + .falcon = { + .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, + }, + .priv_ring = { + .isr = gp10b_priv_ring_isr, + }, + .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, + .get_litter_value = gv11b_get_litter_value, +}; int vgpu_gv11b_init_hal(struct gk20a *g) { - int err; + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + u32 val; + bool priv_security; + + gops->ltc = vgpu_gv11b_ops.ltc; + gops->ce2 = vgpu_gv11b_ops.ce2; + gops->gr = vgpu_gv11b_ops.gr; + gops->fb = vgpu_gv11b_ops.fb; + gops->clock_gating = vgpu_gv11b_ops.clock_gating; + gops->fifo = vgpu_gv11b_ops.fifo; + gops->gr_ctx = vgpu_gv11b_ops.gr_ctx; + gops->mm = vgpu_gv11b_ops.mm; + gops->fecs_trace = vgpu_gv11b_ops.fecs_trace; + gops->therm = vgpu_gv11b_ops.therm; + gops->pmu = vgpu_gv11b_ops.pmu; + gops->regops = vgpu_gv11b_ops.regops; + gops->mc = vgpu_gv11b_ops.mc; + gops->debug = vgpu_gv11b_ops.debug; + gops->dbg_session_ops = vgpu_gv11b_ops.dbg_session_ops; + gops->bus = vgpu_gv11b_ops.bus; +#if defined(CONFIG_GK20A_CYCLE_STATS) + gops->css = vgpu_gv11b_ops.css; +#endif + gops->falcon = vgpu_gv11b_ops.falcon; + gops->priv_ring = vgpu_gv11b_ops.priv_ring; + + /* Lone functions */ + gops->chip_init_gpu_characteristics = + vgpu_gv11b_ops.chip_init_gpu_characteristics; + gops->get_litter_value = vgpu_gv11b_ops.get_litter_value; + + val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); + if (val) { + priv_security = true; + pr_err("priv security is enabled\n"); + } else { + priv_security = false; + pr_err("priv security is disabled\n"); + } + __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security); + + /* priv security dependent ops */ + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + /* Add in ops from gm20b acr */ + gops->pmu.prepare_ucode = gp106_prepare_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn, + gops->pmu.get_wpr = gm20b_wpr_info, + gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, + gops->pmu.pmu_populate_loader_cfg = + gp106_pmu_populate_loader_cfg, + gops->pmu.flcn_populate_bl_dmem_desc = + gp106_flcn_populate_bl_dmem_desc, + gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, + gops->pmu.falcon_clear_halt_interrupt_status = + clear_halt_interrupt_status, + gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1, + + gops->pmu.init_wpr_region = gm20b_pmu_init_acr; + gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; + gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap, + gops->pmu.is_priv_load = gv11b_is_priv_load, + + gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; + } else { + /* Inherit from gk20a */ + gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, + + gops->pmu.load_lsfalcon_ucode = NULL; + gops->pmu.init_wpr_region = NULL; + gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; - gk20a_dbg_fn(""); + gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; + } - err = gv11b_init_hal(g); - if (err) - return err; + __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); + gv11b_init_uncompressed_kind_map(); + gv11b_init_kind_attr(); + g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; - vgpu_init_hal_common(g); - vgpu_gp10b_init_mm_ops(&g->ops); + g->name = "gv11b"; - vgpu_gv11b_init_gr_ops(&g->ops); - vgpu_gv11b_init_fifo_ops(&g->ops); + c->twod_class = FERMI_TWOD_A; + c->threed_class = VOLTA_A; + c->compute_class = VOLTA_COMPUTE_A; + c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = VOLTA_DMA_COPY_A; return 0; } -- cgit v1.2.2 From 0c40a3e034cd9450859dfe713c4d1ca134b77b7e Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sat, 14 Oct 2017 07:53:06 -0700 Subject: gpu: nvgpu: Initialize usermode regs for Volta dGPU Initialize usermode registers also for Volta GPU behind PCIe. Change-Id: Id621a74838839e4d98dfd0828c1ea5a0d54baa2d Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1579121 Reviewed-by: David Martinez Nieto Tested-by: David Martinez Nieto GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/common/linux/pci_t19x.c | 24 ++++++++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h | 23 +++++++++++++++++++++++ 3 files changed, 48 insertions(+) create mode 100644 drivers/gpu/nvgpu/common/linux/pci_t19x.c create mode 100644 drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index cc304df6..bd703d4b 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -5,6 +5,7 @@ nvgpu-y += \ $(nvgpu-t19x)/common/linux/ioctl_tsg_t19x.o \ $(nvgpu-t19x)/common/linux/io_t19x.o \ $(nvgpu-t19x)/common/linux/module_t19x.o \ + $(nvgpu-t19x)/common/linux/pci_t19x.o \ $(nvgpu-t19x)/gv11b/gv11b.o \ $(nvgpu-t19x)/gv11b/mc_gv11b.o \ $(nvgpu-t19x)/gv11b/ltc_gv11b.o \ diff --git a/drivers/gpu/nvgpu/common/linux/pci_t19x.c b/drivers/gpu/nvgpu/common/linux/pci_t19x.c new file mode 100644 index 00000000..54efd68e --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/pci_t19x.c @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include + +#include "common/linux/os_linux.h" + +void t19x_nvgpu_pci_init_support(struct nvgpu_os_linux *l) +{ + l->t19x.usermode_regs = l->regs + usermode_cfg0_r(); + l->t19x.usermode_regs_saved = l->t19x.usermode_regs; +} diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h new file mode 100644 index 00000000..c94176cc --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __NVGPU_PCI_T19X_H__ +#define __NVGPU_PCI_T19X_H__ + +struct nvgpu_os_linux; + +void t19x_nvgpu_pci_init_support(struct nvgpu_os_linux *l); + +#endif -- cgit v1.2.2 From e78cd6c42aec3ae18f12420fd8eb4cb58d09da2d Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 12 Oct 2017 11:35:32 -0700 Subject: gpu: nvgpu: add missing hal defines Due to lack of GVS coverage some defines were left out in GV100, this change adds them back JIRA: NVGPUGV100-9 Change-Id: I2f5778529dcad535bb56c33c38c097415dbf11e5 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1577998 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 36 +++++++++++++++++++--- .../nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | 28 +++++++++++++++++ 2 files changed, 59 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 7f7ab785..7457c185 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -91,6 +91,8 @@ #include "gv100/fb_gv100.h" #include "gv100/fifo_gv100.h" #include "gv11b/fifo_gv11b.h" +#include "gv11b/regops_gv11b.h" + #include "gv11b/gv11b_gating_reglist.h" #include "gv11b/regops_gv11b.h" #include "gv11b/subctx_gv11b.h" @@ -100,6 +102,7 @@ #include "gv100/fb_gv100.h" #include "gv100/mm_gv100.h" +#include #include #include @@ -156,6 +159,9 @@ static int gv100_get_litter_value(struct gk20a *g, int value) case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; + case GPU_LIT_PPC_IN_GPC_SHARED_BASE: + ret = proj_ppc_in_gpc_shared_base_v(); + break; case GPU_LIT_ROP_BASE: ret = proj_rop_base_v(); break; @@ -180,13 +186,30 @@ static int gv100_get_litter_value(struct gk20a *g, int value) case GPU_LIT_NUM_FBPAS: ret = proj_scal_litter_num_fbpas_v(); break; + case GPU_LIT_FBPA_SHARED_BASE: + ret = proj_fbpa_shared_base_v(); + break; + case GPU_LIT_FBPA_BASE: + ret = proj_fbpa_base_v(); + break; case GPU_LIT_FBPA_STRIDE: ret = proj_fbpa_stride_v(); break; case GPU_LIT_SM_PRI_STRIDE: ret = proj_sm_stride_v(); break; - + case GPU_LIT_SMPC_PRI_BASE: + ret = proj_smpc_base_v(); + break; + case GPU_LIT_SMPC_PRI_SHARED_BASE: + ret = proj_smpc_shared_base_v(); + break; + case GPU_LIT_SMPC_PRI_UNIQUE_BASE: + ret = proj_smpc_unique_base_v(); + break; + case GPU_LIT_SMPC_PRI_STRIDE: + ret = proj_smpc_stride_v(); + break; default: break; } @@ -553,12 +576,10 @@ static const struct gpu_ops gv100_ops = { .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, .pmu_pg_init_param = gp106_pg_param_init, .reset_engine = gp106_pmu_engine_reset, - .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg, .write_dmatrfbase = gp10b_write_dmatrfbase, .pmu_mutex_size = pwr_pmu_mutex__size_1_v, .is_engine_in_reset = gp106_pmu_is_engine_in_reset, .pmu_get_queue_tail = pwr_pmu_queue_tail_r, - .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, }, .clk = { .init_clk_support = gp106_init_clk_support, @@ -572,6 +593,9 @@ static const struct gpu_ops gv100_ops = { .get_arbiter_clk_default = gp106_get_arbiter_clk_default, .get_current_pstate = nvgpu_clk_arb_get_current_pstate, }, + .regops = { + .apply_smpc_war = gv11b_apply_smpc_war, + }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -601,13 +625,14 @@ static const struct gpu_ops gv100_ops = { nvgpu_check_and_set_context_reservation, .release_profiler_reservation = nvgpu_release_profiler_reservation, - .perfbuffer_enable = gk20a_perfbuf_enable_locked, - .perfbuffer_disable = gk20a_perfbuf_disable_locked, + .perfbuffer_enable = NULL, + .perfbuffer_disable = NULL, }, .bus = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .read_ptimer = gk20a_read_ptimer, + .get_timestamps_zipper = nvgpu_get_timestamps_zipper, .bar1_bind = NULL, }, #if defined(CONFIG_GK20A_CYCLE_STATS) @@ -662,6 +687,7 @@ int gv100_init_hal(struct gk20a *g) gops->pramin = gv100_ops.pramin; gops->therm = gv100_ops.therm; gops->pmu = gv100_ops.pmu; + gops->regops = gv100_ops.regops; gops->mc = gv100_ops.mc; gops->debug = gv100_ops.debug; gops->dbg_session_ops = gv100_ops.dbg_session_ops; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h index 52a7dfc4..dc4c377d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h @@ -76,6 +76,14 @@ static inline u32 proj_lts_stride_v(void) { return 0x00000200U; } +static inline u32 proj_fbpa_base_v(void) +{ + return 0x00900000U; +} +static inline u32 proj_fbpa_shared_base_v(void) +{ + return 0x009a0000U; +} static inline u32 proj_fbpa_stride_v(void) { return 0x00004000U; @@ -84,6 +92,10 @@ static inline u32 proj_ppc_in_gpc_base_v(void) { return 0x00003000U; } +static inline u32 proj_ppc_in_gpc_shared_base_v(void) +{ + return 0x00003e00U; +} static inline u32 proj_ppc_in_gpc_stride_v(void) { return 0x00000200U; @@ -112,6 +124,22 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) { return 0x00001800U; } +static inline u32 proj_smpc_base_v(void) +{ + return 0x00000200U; +} +static inline u32 proj_smpc_shared_base_v(void) +{ + return 0x00000300U; +} +static inline u32 proj_smpc_unique_base_v(void) +{ + return 0x00000600U; +} +static inline u32 proj_smpc_stride_v(void) +{ + return 0x00000100U; +} static inline u32 proj_host_num_engines_v(void) { return 0x0000000fU; -- cgit v1.2.2 From 99cae3dff71433c21f85bb7f03e42050db8a33dc Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 13 Oct 2017 08:12:58 -0700 Subject: gpu: nvgpu: gv11b: Use internal nvgpu_warpstate Replace use of ioctl structure warpstate with internal nvgpu_warptate. JIRA NVGPU-259 Change-Id: I003c15152042e566124c04d6124e515e36157c88 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1578683 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index da683af6..aac6cba3 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2504,7 +2504,7 @@ int gv11b_gr_sm_trigger_suspend(struct gk20a *g) return 0; } -void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) +void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state) { /* Check if we have at least one valid warp * get paused state on maxwell diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 3f06fe77..dbaee5a7 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -44,6 +44,7 @@ struct gk20a; struct zbc_entry; struct zbc_query_params; struct channel_ctx_gk20a; +struct nvgpu_warpstate; enum { VOLTA_CHANNEL_GPFIFO_A = 0xC36F, @@ -158,7 +159,7 @@ int gr_gv11b_init_fs_state(struct gk20a *g); void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, u32 *esr_sm_sel); int gv11b_gr_sm_trigger_suspend(struct gk20a *g); -void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state); +void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); int gv11b_gr_update_sm_error_state(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id, struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state); -- cgit v1.2.2 From 3fc7c5f75ef4a6399e060d8cbfd4d7dc40c82588 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 16 Oct 2017 14:56:22 -0700 Subject: gpu: nvgpu: gv11b: Use nvgpu_rwsem as TSG channel lock Use abstract nvgpu_rwsem as TSG channel list lock instead of the Linux specific rw_semaphore. JIRA NVGPU-259 Change-Id: I5f6c918464315e3d140bea0c61a619c3712619c1 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1579934 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index e9830c0e..7bb3d654 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -545,11 +545,11 @@ static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg) struct gk20a *g = tsg->g; struct channel_gk20a *ch; - down_read(&tsg->ch_list_lock); + nvgpu_rwsem_down_read(&tsg->ch_list_lock); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { gv11b_reset_eng_faulted_ch(g, ch->chid); } - up_read(&tsg->ch_list_lock); + nvgpu_rwsem_up_read(&tsg->ch_list_lock); } static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 chid) @@ -566,11 +566,11 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) struct gk20a *g = tsg->g; struct channel_gk20a *ch; - down_read(&tsg->ch_list_lock); + nvgpu_rwsem_down_read(&tsg->ch_list_lock); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { gv11b_reset_pbdma_faulted_ch(g, ch->chid); } - up_read(&tsg->ch_list_lock); + nvgpu_rwsem_up_read(&tsg->ch_list_lock); } void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, @@ -799,11 +799,11 @@ int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg) struct gk20a *g = tsg->g; struct channel_gk20a *ch; - down_read(&tsg->ch_list_lock); + nvgpu_rwsem_down_read(&tsg->ch_list_lock); nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) { g->ops.fifo.enable_channel(ch); } - up_read(&tsg->ch_list_lock); + nvgpu_rwsem_up_read(&tsg->ch_list_lock); return 0; } -- cgit v1.2.2 From 201ccbfa8503daee9562a22f50a5b626fe4cc6a1 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 16 Oct 2017 12:14:29 -0700 Subject: gpu: nvgpu: gv11b: update dbg ops Updated following hal functions for gv11b and reused them for gv100: perfbuffer_enable perfbuffer_disable These changes are needed because of following reasons: 1. Register offsets for perf_pmasys_* are changed for gv11b/gv100 from gk20a. 2. Updated memory type for perf_pmasys_mem_block_target to sys_ncoh_f(). Bug 200327596 Change-Id: Ia672ac561917c8ed36caea9cc7e74b7fc7ce8188 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1571074 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 5 +- drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c | 98 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.h | 28 ++++++++++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 5 +- 5 files changed, 133 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index bd703d4b..8f1d42da 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -7,6 +7,7 @@ nvgpu-y += \ $(nvgpu-t19x)/common/linux/module_t19x.o \ $(nvgpu-t19x)/common/linux/pci_t19x.o \ $(nvgpu-t19x)/gv11b/gv11b.o \ + $(nvgpu-t19x)/gv11b/dbg_gpu_gv11b.o \ $(nvgpu-t19x)/gv11b/mc_gv11b.o \ $(nvgpu-t19x)/gv11b/ltc_gv11b.o \ $(nvgpu-t19x)/gv11b/hal_gv11b.o \ diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 7457c185..2ece7be8 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -76,6 +76,7 @@ #include "gp10b/mm_gp10b.h" #include "gp10b/pmu_gp10b.h" +#include "gv11b/dbg_gpu_gv11b.h" #include "gv11b/hal_gv11b.h" #include "gv11b/gr_gv11b.h" #include "gv11b/mc_gv11b.h" @@ -625,8 +626,8 @@ static const struct gpu_ops gv100_ops = { nvgpu_check_and_set_context_reservation, .release_profiler_reservation = nvgpu_release_profiler_reservation, - .perfbuffer_enable = NULL, - .perfbuffer_disable = NULL, + .perfbuffer_enable = gv11b_perfbuf_enable_locked, + .perfbuffer_disable = gv11b_perfbuf_disable_locked, }, .bus = { .init_hw = gk20a_bus_init_hw, diff --git a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c new file mode 100644 index 00000000..ad50025f --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c @@ -0,0 +1,98 @@ +/* + * Tegra GV11B GPU Debugger/Profiler Driver + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include +#include "gk20a/gk20a.h" +#include + +int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size) +{ + struct mm_gk20a *mm = &g->mm; + u32 virt_addr_lo; + u32 virt_addr_hi; + u32 inst_pa_page; + int err; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); + err = gk20a_busy(g); + if (err) { + nvgpu_err(g, "failed to poweron"); + return err; + } + + err = gk20a_alloc_inst_block(g, &mm->perfbuf.inst_block); + if (err) + return err; + + g->ops.mm.init_inst_block(&mm->perfbuf.inst_block, mm->perfbuf.vm, 0); + + virt_addr_lo = u64_lo32(offset); + virt_addr_hi = u64_hi32(offset); + + gk20a_writel(g, perf_pmasys_outbase_r(), virt_addr_lo); + gk20a_writel(g, perf_pmasys_outbaseupper_r(), + perf_pmasys_outbaseupper_ptr_f(virt_addr_hi)); + gk20a_writel(g, perf_pmasys_outsize_r(), size); + + /* this field is aligned to 4K */ + inst_pa_page = gk20a_mm_inst_block_addr(g, + &mm->perfbuf.inst_block) >> 12; + + gk20a_writel(g, perf_pmasys_mem_block_r(), + perf_pmasys_mem_block_base_f(inst_pa_page) | + perf_pmasys_mem_block_valid_true_f() | + perf_pmasys_mem_block_target_sys_ncoh_f()); + + gk20a_idle(g); + return 0; +} + +/* must be called with dbg_sessions_lock held */ +int gv11b_perfbuf_disable_locked(struct gk20a *g) +{ + int err; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); + err = gk20a_busy(g); + if (err) { + nvgpu_err(g, "failed to poweron"); + return err; + } + + gk20a_writel(g, perf_pmasys_outbase_r(), 0); + gk20a_writel(g, perf_pmasys_outbaseupper_r(), + perf_pmasys_outbaseupper_ptr_f(0)); + gk20a_writel(g, perf_pmasys_outsize_r(), 0); + + gk20a_writel(g, perf_pmasys_mem_block_r(), + perf_pmasys_mem_block_base_f(0) | + perf_pmasys_mem_block_valid_false_f() | + perf_pmasys_mem_block_target_f(0)); + + gk20a_idle(g); + + return 0; +} diff --git a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.h b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.h new file mode 100644 index 00000000..88771a49 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef DBG_GPU_GV11B_H +#define DBG_GPU_GV11B_H + +int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size); +int gv11b_perfbuf_disable_locked(struct gk20a *g); + +#endif /* DBG_GPU_GV11B_H */ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4241145a..e7e2be54 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -66,6 +66,7 @@ #include "gp106/pmu_gp106.h" #include "gp106/acr_gp106.h" +#include "dbg_gpu_gv11b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" @@ -633,8 +634,8 @@ static const struct gpu_ops gv11b_ops = { nvgpu_check_and_set_context_reservation, .release_profiler_reservation = nvgpu_release_profiler_reservation, - .perfbuffer_enable = NULL, - .perfbuffer_disable = NULL, + .perfbuffer_enable = gv11b_perfbuf_enable_locked, + .perfbuffer_disable = gv11b_perfbuf_disable_locked, }, .bus = { .init_hw = gk20a_bus_init_hw, -- cgit v1.2.2 From 62e133029d5a89e07e3ba5e96475c0960c0bc3dd Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 16 Oct 2017 12:38:46 -0700 Subject: gpu: nvgpu: Refactoring nvgpu_vm functions Change required for equivalent change on nvgpu. This is required since a few HALs were added that must be populated for all chips. This patch adds those HAL definitions for gv11b, gv100, and the vgpu. JIRA NVGPU-30 JIRA NVGPU-138 Change-Id: I65374764350a5cacce8624b15d98947fada35a4a Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1579865 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 2ece7be8..9d033d6d 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -535,6 +535,8 @@ static const struct gpu_ops gv100_ops = { .is_bar1_supported = gv11b_mm_is_bar1_supported, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .get_kind_invalid = gm20b_get_kind_invalid, + .get_kind_pitch = gm20b_get_kind_pitch, .init_bar2_vm = gb10b_init_bar2_vm, .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e7e2be54..328398d9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -549,6 +549,8 @@ static const struct gpu_ops gv11b_ops = { .is_bar1_supported = gv11b_mm_is_bar1_supported, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .get_kind_invalid = gm20b_get_kind_invalid, + .get_kind_pitch = gm20b_get_kind_pitch, .init_bar2_vm = gb10b_init_bar2_vm, .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index aa661d66..80ed59a2 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -436,6 +436,8 @@ static const struct gpu_ops vgpu_gv11b_ops = { .is_bar1_supported = gv11b_mm_is_bar1_supported, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .get_kind_invalid = gm20b_get_kind_invalid, + .get_kind_pitch = gm20b_get_kind_pitch, .init_bar2_vm = gb10b_init_bar2_vm, .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, -- cgit v1.2.2 From 98b08b413bb5ef082719bf2907629ab00137ec81 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 17 Oct 2017 11:09:22 -0700 Subject: gpu: nvgpu: Use sched_ctrl from nvgpu_os_linux Sched has been moved to be part of Linux implementation, and at the same time sched_ctrl has been moved to be part of nvgpu_os_linux. JIRA NVGPU-259 Change-Id: I4c1869628ad716bcd903ba99db926a8f8723828d Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1580650 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c index 87fbf010..797115ac 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c @@ -20,11 +20,13 @@ #include "gv11b/fifo_gv11b.h" #include "gv11b/subctx_gv11b.h" #include "ioctl_tsg_t19x.h" +#include "common/linux/os_linux.h" static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g, struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg) { - struct gk20a_sched_ctrl *sched = &g->sched_ctrl; + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + struct gk20a_sched_ctrl *sched = &l->sched_ctrl; struct channel_gk20a *ch; int err = 0; -- cgit v1.2.2 From 387ecf8a6360f463a129ab569aaef921fe0a2b0e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 18 Oct 2017 11:40:46 -0700 Subject: gpu: nvgpu: gv1xx: Remove HAL for restore_context_header gr restore_context_header is not required any more after enabling per context va mode for subcontext. Cleaning-up unused function pointers from gv100 and gv11b HAL. Change-Id: I65cc7d12d3c96726d323defd99726c3e259e7e63 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1581432 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 18 ------------------ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 -- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 - drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 - 5 files changed, 23 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9d033d6d..f20d2dcf 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -387,7 +387,6 @@ static const struct gpu_ops gv100_ops = { .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, .zbc_s_query_table = gr_gv11b_zbc_s_query_table, .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, - .restore_context_header = gv11b_restore_context_header, .handle_gpc_gpcmmu_exception = gr_gv11b_handle_gpc_gpcmmu_exception, .add_zbc_type_s = gr_gv11b_add_zbc_type_s, diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index aac6cba3..154088d6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2306,24 +2306,6 @@ int gr_gv11b_commit_global_timeslice(struct gk20a *g, return 0; } -void gv11b_restore_context_header(struct gk20a *g, - struct nvgpu_mem *ctxheader) -{ - u32 va_lo, va_hi; - struct gr_gk20a *gr = &g->gr; - - va_hi = nvgpu_mem_rd(g, ctxheader, - ctxsw_prog_main_image_context_buffer_ptr_hi_o()); - va_lo = nvgpu_mem_rd(g, ctxheader, - ctxsw_prog_main_image_context_buffer_ptr_o()); - nvgpu_mem_wr_n(g, ctxheader, 0, - gr->ctx_vars.local_golden_image, - gr->ctx_vars.golden_image_size); - nvgpu_mem_wr(g, ctxheader, - ctxsw_prog_main_image_context_buffer_ptr_hi_o(), va_hi); - nvgpu_mem_wr(g, ctxheader, - ctxsw_prog_main_image_context_buffer_ptr_o(), va_lo); -} void gr_gv11b_write_zcull_ptr(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va) { diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index dbaee5a7..ed469abd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -145,8 +145,6 @@ int gr_gv11b_load_smid_config(struct gk20a *g); int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c, bool patch); -void gv11b_restore_context_header(struct gk20a *g, - struct nvgpu_mem *ctxheader); void gr_gv11b_write_zcull_ptr(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va); void gr_gv11b_write_pm_ptr(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 328398d9..168def5c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -349,7 +349,6 @@ static const struct gpu_ops gv11b_ops = { .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, .zbc_s_query_table = gr_gv11b_zbc_s_query_table, .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, - .restore_context_header = gv11b_restore_context_header, .handle_gpc_gpcmmu_exception = gr_gv11b_handle_gpc_gpcmmu_exception, .add_zbc_type_s = gr_gv11b_add_zbc_type_s, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 80ed59a2..9226206a 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -232,7 +232,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, .zbc_s_query_table = gr_gv11b_zbc_s_query_table, .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, - .restore_context_header = gv11b_restore_context_header, .handle_gpc_gpcmmu_exception = gr_gv11b_handle_gpc_gpcmmu_exception, .add_zbc_type_s = gr_gv11b_add_zbc_type_s, -- cgit v1.2.2 From ed8ac6e005d95e051bd03a182bbe0aa09a3c2266 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 16 Oct 2017 12:24:59 -0700 Subject: gpu: nvgpu: fix smid generation of perf tables SMID tables were generated according with the local tpc and the pagepool and cb buffers from a different chip and did not take performance in consideration, which made compute kernels hang with CTAs on the fly. This change ensures we are using the right sizes and adds proper enumeration of smids. JIRA: NVGPUGV100-36 bug 2004378 Change-Id: Ic8f50c325d6d6720cca41d9740ae4f5f51e1100a Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1581664 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/gv100/gr_gv100.c | 289 ++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/gr_gv100.h | 36 +++++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 10 +- 4 files changed, 331 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv100/gr_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/gr_gv100.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 8f1d42da..d6d60147 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -28,6 +28,7 @@ nvgpu-y += \ $(nvgpu-t19x)/gv100/fb_gv100.o \ $(nvgpu-t19x)/gv100/bios_gv100.o \ $(nvgpu-t19x)/gv100/fifo_gv100.o \ + $(nvgpu-t19x)/gv100/gr_gv100.o \ $(nvgpu-t19x)/gv100/hal_gv100.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c new file mode 100644 index 00000000..4b2038ba --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -0,0 +1,289 @@ +/* + * GV100 GPU GR + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gk20a/gr_gk20a.h" + +#include "gv100/gr_gv100.h" +#include "gv11b/subctx_gv11b.h" + +#include +#include + +/* + * Estimate performance if the given logical TPC in the given logical GPC were + * removed. + */ +static int gr_gv100_scg_estimate_perf(struct gk20a *g, + unsigned long *gpc_tpc_mask, + u32 disable_gpc_id, u32 disable_tpc_id, + int *perf) +{ + struct gr_gk20a *gr = &g->gr; + int err = 0; + u32 scale_factor = 512UL; /* Use fx23.9 */ + u32 pix_scale = 1024*1024UL; /* Pix perf in [29:20] */ + u32 world_scale = 1024UL; /* World performance in [19:10] */ + u32 tpc_scale = 1; /* TPC balancing in [9:0] */ + u32 scg_num_pes = 0; + u32 min_scg_gpc_pix_perf = scale_factor; /* Init perf as maximum */ + u32 average_tpcs = 0; /* Average of # of TPCs per GPC */ + u32 deviation; /* absolute diff between TPC# and + * average_tpcs, averaged across GPCs + */ + u32 norm_tpc_deviation; /* deviation/max_tpc_per_gpc */ + u32 tpc_balance; + u32 scg_gpc_pix_perf; + u32 scg_world_perf; + u32 gpc_id; + u32 pes_id; + int diff; + bool is_tpc_removed_gpc = false; + bool is_tpc_removed_pes = false; + u32 max_tpc_gpc = 0; + u32 num_tpc_mask; + u32 *num_tpc_gpc = nvgpu_kzalloc(g, sizeof(u32) * + nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS)); + + if (!num_tpc_gpc) + return -ENOMEM; + + /* Calculate pix-perf-reduction-rate per GPC and find bottleneck TPC */ + for (gpc_id = 0; gpc_id < gr->gpc_count; gpc_id++) { + num_tpc_mask = gpc_tpc_mask[gpc_id]; + + if ((gpc_id == disable_gpc_id) && num_tpc_mask & + (0x1 << disable_tpc_id)) { + /* Safety check if a TPC is removed twice */ + if (is_tpc_removed_gpc) { + err = -EINVAL; + goto free_resources; + } + /* Remove logical TPC from set */ + num_tpc_mask &= ~(0x1 << disable_tpc_id); + is_tpc_removed_gpc = true; + } + + /* track balancing of tpcs across gpcs */ + num_tpc_gpc[gpc_id] = hweight32(num_tpc_mask); + average_tpcs += num_tpc_gpc[gpc_id]; + + /* save the maximum numer of gpcs */ + max_tpc_gpc = num_tpc_gpc[gpc_id] > max_tpc_gpc ? + num_tpc_gpc[gpc_id] : max_tpc_gpc; + + /* + * Calculate ratio between TPC count and post-FS and post-SCG + * + * ratio represents relative throughput of the GPC + */ + scg_gpc_pix_perf = scale_factor * num_tpc_gpc[gpc_id] / + gr->gpc_tpc_count[gpc_id]; + + if (min_scg_gpc_pix_perf > scg_gpc_pix_perf) + min_scg_gpc_pix_perf = scg_gpc_pix_perf; + + /* Calculate # of surviving PES */ + for (pes_id = 0; pes_id < gr->gpc_ppc_count[gpc_id]; pes_id++) { + /* Count the number of TPC on the set */ + num_tpc_mask = gr->pes_tpc_mask[pes_id][gpc_id] & + gpc_tpc_mask[gpc_id]; + + if ((gpc_id == disable_gpc_id) && (num_tpc_mask & + (0x1 << disable_tpc_id))) { + + if (is_tpc_removed_pes) { + err = -EINVAL; + goto free_resources; + } + num_tpc_mask &= ~(0x1 << disable_tpc_id); + is_tpc_removed_pes = true; + } + if (hweight32(num_tpc_mask)) + scg_num_pes++; + } + } + + if (!is_tpc_removed_gpc || !is_tpc_removed_pes) { + err = -EINVAL; + goto free_resources; + } + + if (max_tpc_gpc == 0) { + *perf = 0; + goto free_resources; + } + + /* Now calculate perf */ + scg_world_perf = (scale_factor * scg_num_pes) / gr->ppc_count; + deviation = 0; + average_tpcs = scale_factor * average_tpcs / gr->gpc_count; + for (gpc_id =0; gpc_id < gr->gpc_count; gpc_id++) { + diff = average_tpcs - scale_factor * num_tpc_gpc[gpc_id]; + if (diff < 0) + diff = -diff; + deviation += diff; + } + + deviation /= gr->gpc_count; + + norm_tpc_deviation = deviation / max_tpc_gpc; + + tpc_balance = scale_factor - norm_tpc_deviation; + + if ((tpc_balance > scale_factor) || + (scg_world_perf > scale_factor) || + (min_scg_gpc_pix_perf > scale_factor) || + (norm_tpc_deviation > scale_factor)) { + err = -EINVAL; + goto free_resources; + } + + *perf = (pix_scale * min_scg_gpc_pix_perf) + + (world_scale * scg_world_perf) + + (tpc_scale * tpc_balance); +free_resources: + nvgpu_kfree(g, num_tpc_gpc); + return err; +} + +void gr_gv100_bundle_cb_defaults(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + + gr->bundle_cb_default_size = + gr_scc_bundle_cb_size_div_256b__prod_v(); + gr->min_gpm_fifo_depth = + gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(); + gr->bundle_cb_token_limit = + gr_pd_ab_dist_cfg2_token_limit_init_v(); +} + +void gr_gv100_cb_size_default(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + + if (!gr->attrib_cb_default_size) + gr->attrib_cb_default_size = + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); + gr->alpha_cb_default_size = + gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); +} + +void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) +{ +} + +void gr_gv100_init_sm_id_table(struct gk20a *g) +{ + u32 gpc, tpc, sm, pes, gtpc; + u32 sm_id = 0; + u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); + u32 num_sm = sm_per_tpc * g->gr.tpc_count; + int perf, maxperf; + int err; + unsigned long *gpc_tpc_mask; + u32 *tpc_table, *gpc_table; + + gpc_table = nvgpu_kzalloc(g, g->gr.tpc_count * sizeof(u32)); + tpc_table = nvgpu_kzalloc(g, g->gr.tpc_count * sizeof(u32)); + gpc_tpc_mask = nvgpu_kzalloc(g, sizeof(unsigned long) * + nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS)); + + if (!gpc_table || !tpc_table || !gpc_tpc_mask) { + nvgpu_err(g, "Error allocating memory for sm tables"); + goto exit_build_table; + } + + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) + for (pes = 0; pes < g->gr.gpc_ppc_count[gpc]; pes++) + gpc_tpc_mask[gpc] |= g->gr.pes_tpc_mask[pes][gpc]; + + for (gtpc = 0; gtpc < g->gr.tpc_count; gtpc++) { + maxperf = -1; + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + for_each_set_bit(tpc, &gpc_tpc_mask[gpc], + g->gr.gpc_tpc_count[gpc]) { + perf = -1; + err = gr_gv100_scg_estimate_perf(g, + gpc_tpc_mask, gpc, tpc, &perf); + + if (err) { + nvgpu_err(g, + "Error while estimating perf"); + goto exit_build_table; + } + + if (perf >= maxperf) { + maxperf = perf; + gpc_table[gtpc] = gpc; + tpc_table[gtpc] = tpc; + } + } + } + gpc_tpc_mask[gpc_table[gtpc]] &= ~(0x1 << tpc_table[gtpc]); + } + + for (tpc = 0, sm_id = 0; sm_id < num_sm; tpc++, sm_id += sm_per_tpc) { + for (sm = 0; sm < sm_per_tpc; sm++) { + g->gr.sm_to_cluster[sm_id + sm].gpc_index = + gpc_table[tpc]; + g->gr.sm_to_cluster[sm_id + sm].tpc_index = + tpc_table[tpc]; + g->gr.sm_to_cluster[sm_id + sm].sm_index = sm; + g->gr.sm_to_cluster[sm_id + sm].global_tpc_index = tpc; + } + } + + g->gr.no_of_sm = num_sm; + nvgpu_log_info(g, " total number of sm = %d", g->gr.no_of_sm); +exit_build_table: + nvgpu_kfree(g, gpc_table); + nvgpu_kfree(g, tpc_table); + nvgpu_kfree(g, gpc_tpc_mask); +} + +void gr_gv100_load_tpc_mask(struct gk20a *g) +{ + u64 pes_tpc_mask = 0x0ULL; + u32 gpc, pes; + u32 num_tpc_per_gpc = nvgpu_get_litter_value(g, + GPU_LIT_NUM_TPC_PER_GPC); + + /* gv100 has 6 GPC and 7 TPC/GPC */ + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + for (pes = 0; pes < g->gr.pe_count_per_gpc; pes++) { + pes_tpc_mask |= (u64) g->gr.pes_tpc_mask[pes][gpc] << + (num_tpc_per_gpc * gpc); + } + } + + nvgpu_log_info(g, "pes_tpc_mask: %016llx\n", pes_tpc_mask); + gk20a_writel(g, gr_fe_tpc_fs_r(0), u64_lo32(pes_tpc_mask)); + gk20a_writel(g, gr_fe_tpc_fs_r(1), u64_hi32(pes_tpc_mask)); +} diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h new file mode 100644 index 00000000..460b05ae --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h @@ -0,0 +1,36 @@ +/* + * GV100 GPU GR + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVGPU_GR_GV100_H_ +#define _NVGPU_GR_GV100_H_ + +void gr_gv100_bundle_cb_defaults(struct gk20a *g); +void gr_gv100_cb_size_default(struct gk20a *g); +void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); +void gr_gv100_init_sm_id_table(struct gk20a *g); +void gr_gv100_program_sm_id_numbering(struct gk20a *g, + u32 gpc, u32 tpc, u32 smid); +int gr_gv100_load_smid_config(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index f20d2dcf..cefaf1ae 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -78,7 +78,7 @@ #include "gv11b/dbg_gpu_gv11b.h" #include "gv11b/hal_gv11b.h" -#include "gv11b/gr_gv11b.h" +#include "gv100/gr_gv100.h" #include "gv11b/mc_gv11b.h" #include "gv11b/ltc_gv11b.h" #include "gv11b/gv11b.h" @@ -263,8 +263,8 @@ static const struct gpu_ops gv100_ops = { }, .gr = { .init_gpc_mmu = gr_gv11b_init_gpc_mmu, - .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, - .cb_size_default = gr_gv11b_cb_size_default, + .bundle_cb_defaults = gr_gv100_bundle_cb_defaults, + .cb_size_default = gr_gv100_cb_size_default, .calc_global_ctx_buffer_size = gr_gv11b_calc_global_ctx_buffer_size, .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, @@ -285,7 +285,7 @@ static const struct gpu_ops gv100_ops = { .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, - .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, + .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask, .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, .free_channel_ctx = gk20a_free_channel_ctx, .alloc_obj_ctx = gk20a_alloc_obj_ctx, @@ -335,7 +335,7 @@ static const struct gpu_ops gv100_ops = { .resume_contexts = gr_gk20a_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, .fuse_override = gp10b_gr_fuse_override, - .init_sm_id_table = gr_gv11b_init_sm_id_table, + .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, -- cgit v1.2.2 From cf70c925cd3d8e6c83feee04316b080d5f258afc Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 22 Jun 2017 16:28:19 -0700 Subject: gpu: nvgpu: gv11b: update css ops Updated following hal functions for css gv11b and reused them for gv100: enable_snapshot disable_snapshot check_data_available These changes are needed because of following reasons: 1. Register offsets for perf_pmasys_* are changed for gv11b/gv100 from gk20a. 2. Updated memory type for perf_pmasys_mem_block_target based on memory aperture used for hwpm inst_block. Bug 200327596 Change-Id: I500d17670e2f389d8d0e77884374bcc3504a41f8 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1507546 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 7 +- drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c | 206 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/css_gr_gv11b.h | 34 ++++++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 7 +- 5 files changed, 249 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/css_gr_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index d6d60147..c6958bec 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -7,6 +7,7 @@ nvgpu-y += \ $(nvgpu-t19x)/common/linux/module_t19x.o \ $(nvgpu-t19x)/common/linux/pci_t19x.o \ $(nvgpu-t19x)/gv11b/gv11b.o \ + $(nvgpu-t19x)/gv11b/css_gr_gv11b.o \ $(nvgpu-t19x)/gv11b/dbg_gpu_gv11b.o \ $(nvgpu-t19x)/gv11b/mc_gv11b.o \ $(nvgpu-t19x)/gv11b/ltc_gv11b.o \ diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cefaf1ae..2007eee0 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -76,6 +76,7 @@ #include "gp10b/mm_gp10b.h" #include "gp10b/pmu_gp10b.h" +#include "gv11b/css_gr_gv11b.h" #include "gv11b/dbg_gpu_gv11b.h" #include "gv11b/hal_gv11b.h" #include "gv100/gr_gv100.h" @@ -639,9 +640,9 @@ static const struct gpu_ops gv100_ops = { }, #if defined(CONFIG_GK20A_CYCLE_STATS) .css = { - .enable_snapshot = css_hw_enable_snapshot, - .disable_snapshot = css_hw_disable_snapshot, - .check_data_available = css_hw_check_data_available, + .enable_snapshot = gv11b_css_hw_enable_snapshot, + .disable_snapshot = gv11b_css_hw_disable_snapshot, + .check_data_available = gv11b_css_hw_check_data_available, .set_handled_snapshots = css_hw_set_handled_snapshots, .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, .release_perfmon_ids = css_gr_release_perfmon_ids, diff --git a/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c new file mode 100644 index 00000000..6afd92fa --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c @@ -0,0 +1,206 @@ +/* + * GV11B Cycle stats snapshots support + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gk20a/css_gr_gk20a.h" +#include "css_gr_gv11b.h" + +#include +#include + +#include +#include + + +/* reports whether the hw queue overflowed */ +static inline bool css_hw_get_overflow_status(struct gk20a *g) +{ + const u32 st = perf_pmasys_control_membuf_status_overflowed_f(); + return st == (gk20a_readl(g, perf_pmasys_control_r()) & st); +} + +/* returns how many pending snapshot entries are pending */ +static inline u32 css_hw_get_pending_snapshots(struct gk20a *g) +{ + return gk20a_readl(g, perf_pmasys_mem_bytes_r()) / + sizeof(struct gk20a_cs_snapshot_fifo_entry); +} + +/* informs hw how many snapshots have been processed (frees up fifo space) */ +static inline void gv11b_css_hw_set_handled_snapshots(struct gk20a *g, u32 done) +{ + if (done > 0) { + gk20a_writel(g, perf_pmasys_mem_bump_r(), + done * sizeof(struct gk20a_cs_snapshot_fifo_entry)); + } +} + +/* disable streaming to memory */ +static void gv11b_css_hw_reset_streaming(struct gk20a *g) +{ + u32 engine_status; + + /* reset the perfmon */ + g->ops.mc.reset(g, mc_enable_perfmon_enabled_f()); + + /* RBUFEMPTY must be set -- otherwise we'll pick up */ + /* snapshot that have been queued up from earlier */ + engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r()); + + /* turn off writes */ + gk20a_writel(g, perf_pmasys_control_r(), + perf_pmasys_control_membuf_clear_status_doit_f()); + + /* pointing all pending snapshots as handled */ + gv11b_css_hw_set_handled_snapshots(g, css_hw_get_pending_snapshots(g)); +} + +int gv11b_css_hw_enable_snapshot(struct channel_gk20a *ch, + struct gk20a_cs_snapshot_client *cs_client) +{ + struct gk20a *g = ch->g; + struct gr_gk20a *gr = &g->gr; + struct gk20a_cs_snapshot *data = gr->cs_data; + u32 snapshot_size = cs_client->snapshot_size; + int ret; + + u32 virt_addr_lo; + u32 virt_addr_hi; + u32 inst_pa_page; + + if (data->hw_snapshot) + return 0; + + if (snapshot_size < CSS_MIN_HW_SNAPSHOT_SIZE) + snapshot_size = CSS_MIN_HW_SNAPSHOT_SIZE; + + ret = nvgpu_dma_alloc_map_sys(g->mm.pmu.vm, snapshot_size, + &data->hw_memdesc); + if (ret) + return ret; + + /* perf output buffer may not cross a 4GB boundary - with a separate */ + /* va smaller than that, it won't but check anyway */ + if (!data->hw_memdesc.cpu_va || + data->hw_memdesc.size < snapshot_size || + data->hw_memdesc.gpu_va + u64_lo32(snapshot_size) > SZ_4G) { + ret = -EFAULT; + goto failed_allocation; + } + + data->hw_snapshot = + (struct gk20a_cs_snapshot_fifo_entry *)data->hw_memdesc.cpu_va; + data->hw_end = data->hw_snapshot + + snapshot_size / sizeof(struct gk20a_cs_snapshot_fifo_entry); + data->hw_get = data->hw_snapshot; + memset(data->hw_snapshot, 0xff, snapshot_size); + + virt_addr_lo = u64_lo32(data->hw_memdesc.gpu_va); + virt_addr_hi = u64_hi32(data->hw_memdesc.gpu_va); + + gv11b_css_hw_reset_streaming(g); + + gk20a_writel(g, perf_pmasys_outbase_r(), virt_addr_lo); + gk20a_writel(g, perf_pmasys_outbaseupper_r(), + perf_pmasys_outbaseupper_ptr_f(virt_addr_hi)); + gk20a_writel(g, perf_pmasys_outsize_r(), snapshot_size); + + /* this field is aligned to 4K */ + inst_pa_page = gk20a_mm_inst_block_addr(g, + &g->mm.hwpm.inst_block) >> 12; + + gk20a_writel(g, perf_pmasys_mem_block_r(), + perf_pmasys_mem_block_base_f(inst_pa_page) | + perf_pmasys_mem_block_valid_true_f() | + nvgpu_aperture_mask(g, &g->mm.hwpm.inst_block, + perf_pmasys_mem_block_target_sys_ncoh_f(), + perf_pmasys_mem_block_target_lfb_f())); + + + gk20a_dbg_info("cyclestats: buffer for hardware snapshots enabled\n"); + + return 0; + +failed_allocation: + if (data->hw_memdesc.size) { + nvgpu_dma_unmap_free(g->mm.pmu.vm, &data->hw_memdesc); + memset(&data->hw_memdesc, 0, sizeof(data->hw_memdesc)); + } + data->hw_snapshot = NULL; + + return ret; +} + +void gv11b_css_hw_disable_snapshot(struct gr_gk20a *gr) +{ + struct gk20a *g = gr->g; + struct gk20a_cs_snapshot *data = gr->cs_data; + + if (!data->hw_snapshot) + return; + + gv11b_css_hw_reset_streaming(g); + + gk20a_writel(g, perf_pmasys_outbase_r(), 0); + gk20a_writel(g, perf_pmasys_outbaseupper_r(), + perf_pmasys_outbaseupper_ptr_f(0)); + gk20a_writel(g, perf_pmasys_outsize_r(), 0); + + gk20a_writel(g, perf_pmasys_mem_block_r(), + perf_pmasys_mem_block_base_f(0) | + perf_pmasys_mem_block_valid_false_f() | + perf_pmasys_mem_block_target_f(0)); + + nvgpu_dma_unmap_free(g->mm.pmu.vm, &data->hw_memdesc); + memset(&data->hw_memdesc, 0, sizeof(data->hw_memdesc)); + data->hw_snapshot = NULL; + + gk20a_dbg_info("cyclestats: buffer for hardware snapshots disabled\n"); +} + +int gv11b_css_hw_check_data_available(struct channel_gk20a *ch, u32 *pending, + bool *hw_overflow) +{ + struct gk20a *g = ch->g; + struct gr_gk20a *gr = &g->gr; + struct gk20a_cs_snapshot *css = gr->cs_data; + + if (!css->hw_snapshot) + return -EINVAL; + + *pending = css_hw_get_pending_snapshots(g); + if (!*pending) + return 0; + + *hw_overflow = css_hw_get_overflow_status(g); + return 0; +} diff --git a/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.h new file mode 100644 index 00000000..6b11a62e --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.h @@ -0,0 +1,34 @@ +/* + * GV11B Cycle stats snapshots support + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef CSS_GR_GV11B_H +#define CSS_GR_GV11B_H + +int gv11b_css_hw_enable_snapshot(struct channel_gk20a *ch, + struct gk20a_cs_snapshot_client *cs_client); +void gv11b_css_hw_disable_snapshot(struct gr_gk20a *gr); +int gv11b_css_hw_check_data_available(struct channel_gk20a *ch, u32 *pending, + bool *hw_overflow); + +#endif /* CSS_GR_GV11B_H */ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 168def5c..22beabf7 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -68,6 +68,7 @@ #include "dbg_gpu_gv11b.h" #include "hal_gv11b.h" +#include "css_gr_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" #include "ltc_gv11b.h" @@ -647,9 +648,9 @@ static const struct gpu_ops gv11b_ops = { }, #if defined(CONFIG_GK20A_CYCLE_STATS) .css = { - .enable_snapshot = css_hw_enable_snapshot, - .disable_snapshot = css_hw_disable_snapshot, - .check_data_available = css_hw_check_data_available, + .enable_snapshot = gv11b_css_hw_enable_snapshot, + .disable_snapshot = gv11b_css_hw_disable_snapshot, + .check_data_available = gv11b_css_hw_check_data_available, .set_handled_snapshots = css_hw_set_handled_snapshots, .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, .release_perfmon_ids = css_gr_release_perfmon_ids, -- cgit v1.2.2 From 324cf7b49e83f9641fde7ba97958b085da615d78 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 20 Oct 2017 12:38:37 -0700 Subject: gpu: nvgpu: gv11b: memory aperture for perfbuf Updated perf_pmasys_mem_block_target in perf_pmasys_mem_block based on memory aperture used for perfbuf inst_block. Bug 200327596 Change-Id: Ic3df332a2248c5ea2d6d38ceab8ba04c618ffefc Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1582788 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c index ad50025f..2fdfc8f4 100644 --- a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c @@ -64,7 +64,9 @@ int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size) gk20a_writel(g, perf_pmasys_mem_block_r(), perf_pmasys_mem_block_base_f(inst_pa_page) | perf_pmasys_mem_block_valid_true_f() | - perf_pmasys_mem_block_target_sys_ncoh_f()); + nvgpu_aperture_mask(g, &mm->perfbuf.inst_block, ++ perf_pmasys_mem_block_target_sys_ncoh_f(), ++ perf_pmasys_mem_block_target_lfb_f())); gk20a_idle(g); return 0; -- cgit v1.2.2 From 2904e3ac0081d4e898378f6ba667658c85547368 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 4 Oct 2017 19:41:04 +0530 Subject: gpu: nvgpu: gv100 memory unlock support - Added method to load mem unlock binary into nvdec falcon & execute to perform mem unlock if VPR enabled. - Updated .mem_unlock gv100 HAL to point method gv100_fb_memory_unlock(). - Updated .mem_unlock gv11b HAL to NULL. - Added vpr info hw registers - Added nvdec enable hw register Change-Id: Ia4bf820ae103baede679d300d1d390fd748c919a Signed-off-by: Mahantesh Kumbar (cherry picked from commit 2e176ad9d47316bf4d001692a2ae07e6c1fb1ccb) Reviewed-on: https://git-master.nvidia.com/r/1573101 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 124 +++++++++++++++++++++ drivers/gpu/nvgpu/gv100/fb_gv100.h | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | 36 ++++++ .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h | 8 ++ 6 files changed, 171 insertions(+) diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c index bcb6d740..0a2939bf 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -28,14 +28,25 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include #include "gk20a/gk20a.h" #include "gv100/fb_gv100.h" +#include "gm20b/acr_gm20b.h" #include +#include +#include #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ +#define MEM_UNLOCK_TIMEOUT 3500 /* msec */ void gv100_fb_reset(struct gk20a *g) { @@ -58,3 +69,116 @@ void gv100_fb_reset(struct gk20a *g) val &= ~fb_mmu_priv_level_mask_write_violation_m(); gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); } + +int gv100_fb_memory_unlock(struct gk20a *g) +{ + struct nvgpu_firmware *mem_unlock_fw = NULL; + struct bin_hdr *hsbin_hdr = NULL; + struct acr_fw_header *fw_hdr = NULL; + u32 *mem_unlock_ucode = NULL; + u32 *mem_unlock_ucode_header = NULL; + u32 sec_imem_dest = 0; + u32 val = 0; + int err = 0; + + nvgpu_log_fn(g, " "); + + /* Check vpr enable status */ + val = gk20a_readl(g, fb_mmu_vpr_info_r()); + val &= ~fb_mmu_vpr_info_index_m(); + val |= fb_mmu_vpr_info_index_cya_lo_v(); + gk20a_writel(g, fb_mmu_vpr_info_r(), val); + val = gk20a_readl(g, fb_mmu_vpr_info_r()); + if (!(val & fb_mmu_vpr_info_cya_lo_in_use_m())) { + nvgpu_log_info(g, "mem unlock not required on this SKU, skipping"); + goto exit; + } + + /* get mem unlock ucode binary */ + mem_unlock_fw = nvgpu_request_firmware(g, "mem_unlock.bin", 0); + if (!mem_unlock_fw) { + nvgpu_err(g, "mem unlock ucode get fail"); + err = -ENOENT; + goto exit; + } + + /* Enable nvdec */ + g->ops.mc.enable(g, mc_enable_nvdec_enabled_f()); + + /* nvdec falcon reset */ + nvgpu_flcn_reset(&g->nvdec_flcn); + + hsbin_hdr = (struct bin_hdr *)mem_unlock_fw->data; + fw_hdr = (struct acr_fw_header *)(mem_unlock_fw->data + + hsbin_hdr->header_offset); + + mem_unlock_ucode_header = (u32 *)(mem_unlock_fw->data + + fw_hdr->hdr_offset); + mem_unlock_ucode = (u32 *)(mem_unlock_fw->data + + hsbin_hdr->data_offset); + + /* Patch Ucode singnatures */ + if (acr_ucode_patch_sig(g, mem_unlock_ucode, + (u32 *)(mem_unlock_fw->data + fw_hdr->sig_prod_offset), + (u32 *)(mem_unlock_fw->data + fw_hdr->sig_dbg_offset), + (u32 *)(mem_unlock_fw->data + fw_hdr->patch_loc), + (u32 *)(mem_unlock_fw->data + fw_hdr->patch_sig)) < 0) { + nvgpu_err(g, "mem unlock patch signatures fail"); + err = -EPERM; + goto exit; + } + + /* Clear interrupts */ + nvgpu_flcn_set_irq(&g->nvdec_flcn, false, 0x0, 0x0); + + /* Copy Non Secure IMEM code */ + nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, 0, + (u8 *)&mem_unlock_ucode[ + mem_unlock_ucode_header[OS_CODE_OFFSET] >> 2], + mem_unlock_ucode_header[OS_CODE_SIZE], 0, false, + GET_IMEM_TAG(mem_unlock_ucode_header[OS_CODE_OFFSET])); + + /* Put secure code after non-secure block */ + sec_imem_dest = GET_NEXT_BLOCK(mem_unlock_ucode_header[OS_CODE_SIZE]); + + nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, sec_imem_dest, + (u8 *)&mem_unlock_ucode[ + mem_unlock_ucode_header[APP_0_CODE_OFFSET] >> 2], + mem_unlock_ucode_header[APP_0_CODE_SIZE], 0, true, + GET_IMEM_TAG(mem_unlock_ucode_header[APP_0_CODE_OFFSET])); + + /* load DMEM: ensure that signatures are patched */ + nvgpu_flcn_copy_to_dmem(&g->nvdec_flcn, 0, (u8 *)&mem_unlock_ucode[ + mem_unlock_ucode_header[OS_DATA_OFFSET] >> 2], + mem_unlock_ucode_header[OS_DATA_SIZE], 0); + + nvgpu_log_info(g, "nvdec sctl reg %x\n", + gk20a_readl(g, g->nvdec_flcn.flcn_base + + falcon_falcon_sctl_r())); + + /* set BOOTVEC to start of non-secure code */ + nvgpu_flcn_bootstrap(&g->nvdec_flcn, 0); + + /* wait for complete & halt */ + nvgpu_flcn_wait_for_halt(&g->nvdec_flcn, MEM_UNLOCK_TIMEOUT); + + /* check mem unlock status */ + val = nvgpu_flcn_mailbox_read(&g->nvdec_flcn, 0); + if (val) { + nvgpu_err(g, "memory unlock failed, err %x", val); + err = -1; + goto exit; + } + + nvgpu_log_info(g, "nvdec sctl reg %x\n", + gk20a_readl(g, g->nvdec_flcn.flcn_base + + falcon_falcon_sctl_r())); + +exit: + if (mem_unlock_fw) + nvgpu_release_firmware(g, mem_unlock_fw); + + nvgpu_log_fn(g, "done, status - %d", err); + + return err; +} diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h index d5a36661..b6db262a 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.h +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h @@ -28,4 +28,5 @@ struct gk20a; void gv100_fb_reset(struct gk20a *g); +int gv100_fb_memory_unlock(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 2007eee0..4e05f22b 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -421,6 +421,7 @@ static const struct gpu_ops gv100_ops = { .set_debug_mode = gm20b_fb_set_debug_mode, .tlb_invalidate = gk20a_fb_tlb_invalidate, .hub_isr = gv11b_fb_hub_isr, + .mem_unlock = gv100_fb_memory_unlock, }, .fifo = { .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 22beabf7..729727c9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -385,6 +385,7 @@ static const struct gpu_ops gv11b_ops = { .set_debug_mode = gm20b_fb_set_debug_mode, .tlb_invalidate = gk20a_fb_tlb_invalidate, .hub_isr = gv11b_fb_hub_isr, + .mem_unlock = NULL, }, .clock_gating = { .slcg_bus_load_gating_prod = diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h index 3bba3fb8..a4fcd1e6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -460,6 +460,42 @@ static inline u32 fb_mmu_vpr_info_r(void) { return 0x00100cd0U; } +static inline u32 fb_mmu_vpr_info_index_f(u32 v) +{ + return (v & 0x3U) << 0U; +} +static inline u32 fb_mmu_vpr_info_index_v(u32 r) +{ + return (r >> 0U) & 0x3U; +} +static inline u32 fb_mmu_vpr_info_index_m(void) +{ + return 0x3U << 0U; +} +static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void) +{ + return 0x00000000U; +} +static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void) +{ + return 0x00000001U; +} +static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void) +{ + return 0x00000002U; +} +static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void) +{ + return 0x00000003U; +} +static inline u32 fb_mmu_vpr_info_cya_lo_in_use_m(void) +{ + return 0x1U << 4U; +} +static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) +{ + return (v & 0x1U) << 2U; +} static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) { return (r >> 2U) & 0x1U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h index 2efeac79..f367991e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h @@ -196,6 +196,14 @@ static inline u32 mc_enable_hub_enabled_f(void) { return 0x20000000U; } +static inline u32 mc_enable_nvdec_disabled_v(void) +{ + return 0x00000000U; +} +static inline u32 mc_enable_nvdec_enabled_f(void) +{ + return 0x8000U; +} static inline u32 mc_intr_ltc_r(void) { return 0x000001c0U; -- cgit v1.2.2 From 6114553413297dbcae637bc50ef2ff2a6c0858d1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 19 Oct 2017 10:12:24 -0700 Subject: gpu: nvgpu: gv100: fix timeout handling GV100 has a larger vidmem size and a slower sideband to sysmem so timeouts need to be adjusted to avoid false positives. JIRA: NVGPUGV100-36 Change-Id: I3cbc19aa1158c89bc48ae1fa6ec4bc755cd9389d Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1582092 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/fifo_gv100.c | 8 ++++++++ drivers/gpu/nvgpu/gv100/fifo_gv100.h | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 6 ++++-- drivers/gpu/nvgpu/gv100/mm_gv100.c | 13 +++++++++++++ drivers/gpu/nvgpu/gv100/mm_gv100.h | 1 + drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 11 ++++++++--- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 2 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 8 files changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c index e19301e6..79862f6b 100644 --- a/drivers/gpu/nvgpu/gv100/fifo_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c @@ -26,7 +26,15 @@ #include +#define DEFAULT_FIFO_PREEMPT_TIMEOUT 0x3FFFFFUL + u32 gv100_fifo_get_num_fifos(struct gk20a *g) { return ccsr_channel__size_1_v(); } + +u32 gv100_fifo_get_preempt_timeout(struct gk20a *g) +{ + return DEFAULT_FIFO_PREEMPT_TIMEOUT; +} + diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.h b/drivers/gpu/nvgpu/gv100/fifo_gv100.h index 3ffb417c..af6ad030 100644 --- a/drivers/gpu/nvgpu/gv100/fifo_gv100.h +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.h @@ -29,4 +29,5 @@ struct gk20a; u32 gv100_fifo_get_num_fifos(struct gk20a *g); +u32 gv100_fifo_get_preempt_timeout(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4e05f22b..ff852168 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -424,6 +424,7 @@ static const struct gpu_ops gv100_ops = { .mem_unlock = gv100_fb_memory_unlock, }, .fifo = { + .get_preempt_timeout = gv100_fifo_get_preempt_timeout, .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, .bind_channel = channel_gm20b_bind, .unbind_channel = channel_gv11b_unbind, @@ -470,7 +471,7 @@ static const struct gpu_ops gv100_ops = { .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, .is_preempt_pending = gv11b_fifo_is_preempt_pending, .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, - .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, + .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, .handle_sched_error = gv11b_fifo_handle_sched_error, .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, @@ -523,7 +524,7 @@ static const struct gpu_ops gv100_ops = { .vm_bind_channel = gk20a_vm_bind_channel, .fb_flush = gk20a_mm_fb_flush, .l2_invalidate = gk20a_mm_l2_invalidate, - .l2_flush = gv11b_mm_l2_flush, + .l2_flush = gk20a_mm_l2_flush, .cbc_clean = gk20a_mm_cbc_clean, .set_big_page_size = gm20b_mm_set_big_page_size, .get_big_page_sizes = gm20b_mm_get_big_page_sizes, @@ -542,6 +543,7 @@ static const struct gpu_ops gv100_ops = { .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + .get_flush_retries = gv100_mm_get_flush_retries, }, .pramin = { .enter = gk20a_pramin_enter, diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c index 93688206..1b46faae 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.c +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c @@ -40,3 +40,16 @@ size_t gv100_mm_get_vidmem_size(struct gk20a *g) return bytes; } + +u32 gv100_mm_get_flush_retries(struct gk20a *g, enum nvgpu_flush_op op) +{ + switch (op) { + /* GV100 has a large FB so it needs larger timeouts */ + case NVGPU_FLUSH_FB: + return 2000; + case NVGPU_FLUSH_L2_FLUSH: + return 2000; + default: + return 200; /* Default retry timer */ + } +} diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h index eba724f9..ea896503 100644 --- a/drivers/gpu/nvgpu/gv100/mm_gv100.h +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h @@ -28,5 +28,6 @@ struct gk20a; size_t gv100_mm_get_vidmem_size(struct gk20a *g); +u32 gv100_mm_get_flush_retries(struct gk20a *g, enum nvgpu_flush_op op); #endif diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 7bb3d654..4a03e6d9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -372,6 +372,11 @@ u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g) return intr_0_error_mask; } +u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g) +{ + return gk20a_get_gr_idle_timeout(g); +} + static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, u32 pbdma_id, unsigned int timeout_rc_type) { @@ -405,7 +410,7 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); } - nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + nvgpu_timeout_init(g, &timeout, g->ops.fifo.get_preempt_timeout(g), NVGPU_TIMER_CPU_TIMER); /* Verify that ch/tsg is no longer on the pbdma */ @@ -465,7 +470,7 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, u32 ctx_stat; int ret = -EBUSY; - nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + nvgpu_timeout_init(g, &timeout, g->ops.fifo.get_preempt_timeout(g), NVGPU_TIMER_CPU_TIMER); /* Check if ch/tsg has saved off the engine or if ctxsw is hung */ @@ -686,7 +691,7 @@ static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g, u32 delay = GR_IDLE_CHECK_DEFAULT; int ret = -EBUSY; - nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + nvgpu_timeout_init(g, &timeout, g->ops.fifo.get_preempt_timeout(g), NVGPU_TIMER_CPU_TIMER); do { if (!((gk20a_readl(g, fifo_runlist_preempt_r())) & diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index f622aba8..fc1ddf83 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -113,5 +113,5 @@ u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); int gv11b_init_fifo_setup_hw(struct gk20a *g); void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch); - +u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 729727c9..5b10b7d2 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -438,6 +438,7 @@ static const struct gpu_ops gv11b_ops = { gr_gv11b_pg_gr_load_gating_prod, }, .fifo = { + .get_preempt_timeout = gv11b_fifo_get_preempt_timeout, .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, .bind_channel = channel_gm20b_bind, .unbind_channel = channel_gv11b_unbind, -- cgit v1.2.2 From d436ed36ae684986540f745a2eca7a1009be5780 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 20 Oct 2017 09:35:37 -0700 Subject: gpu: nvgpu: gv10x: alloc fault buffer in sysmem With coherency issues solved, it is no longer needed to allocate the fault buffer in vidmem as a workaround. JIRA: NVGPUGV100-36 Change-Id: I1c83e9bac61f27b75f38fce963899485afeed009 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1582769 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index e452462e..6df29cb0 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -118,7 +118,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, fb_size = (g->ops.fifo.get_num_fifos(g) + 1) * gmmu_fault_buf_size_v(); - err = nvgpu_dma_alloc_map(vm, fb_size, + err = nvgpu_dma_alloc_map_sys(vm, fb_size, &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); if (err) { nvgpu_err(g, @@ -131,7 +131,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, HW_FAULT_BUF_STATUS_ALLOC_TRUE; *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY; - err = nvgpu_dma_alloc_map(vm, fb_size, + err = nvgpu_dma_alloc_map_sys(vm, fb_size, &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); if (err) { nvgpu_err(g, -- cgit v1.2.2 From f8c2b77e4f64fcb4adc889bfc0bd4b9ad368ecc6 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 20 Oct 2017 14:58:13 -0700 Subject: gpu: nvgpu: Add gv10x regops whitelist Add regops whitelists for GV100 JIRA: NVGPUGV100-36 Change-Id: Ifeb286e2e8df056ba9afdd32f457bacf1b4813fc Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1582835 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 24 +- drivers/gpu/nvgpu/gv100/regops_gv100.c | 463 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/regops_gv100.h | 42 +++ 4 files changed, 528 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv100/regops_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/regops_gv100.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index c6958bec..0909a010 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -30,6 +30,7 @@ nvgpu-y += \ $(nvgpu-t19x)/gv100/bios_gv100.o \ $(nvgpu-t19x)/gv100/fifo_gv100.o \ $(nvgpu-t19x)/gv100/gr_gv100.o \ + $(nvgpu-t19x)/gv100/regops_gv100.o \ $(nvgpu-t19x)/gv100/hal_gv100.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index ff852168..3a8dc4b1 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -96,7 +96,7 @@ #include "gv11b/regops_gv11b.h" #include "gv11b/gv11b_gating_reglist.h" -#include "gv11b/regops_gv11b.h" +#include "gv100/regops_gv100.h" #include "gv11b/subctx_gv11b.h" #include "gv100.h" @@ -600,7 +600,27 @@ static const struct gpu_ops gv100_ops = { .get_current_pstate = nvgpu_clk_arb_get_current_pstate, }, .regops = { - .apply_smpc_war = gv11b_apply_smpc_war, + .get_global_whitelist_ranges = + gv100_get_global_whitelist_ranges, + .get_global_whitelist_ranges_count = + gv100_get_global_whitelist_ranges_count, + .get_context_whitelist_ranges = + gv100_get_context_whitelist_ranges, + .get_context_whitelist_ranges_count = + gv100_get_context_whitelist_ranges_count, + .get_runcontrol_whitelist = gv100_get_runcontrol_whitelist, + .get_runcontrol_whitelist_count = + gv100_get_runcontrol_whitelist_count, + .get_runcontrol_whitelist_ranges = + gv100_get_runcontrol_whitelist_ranges, + .get_runcontrol_whitelist_ranges_count = + gv100_get_runcontrol_whitelist_ranges_count, + .get_qctl_whitelist = gv100_get_qctl_whitelist, + .get_qctl_whitelist_count = gv100_get_qctl_whitelist_count, + .get_qctl_whitelist_ranges = gv100_get_qctl_whitelist_ranges, + .get_qctl_whitelist_ranges_count = + gv100_get_qctl_whitelist_ranges_count, + .apply_smpc_war = gv100_apply_smpc_war, }, .mc = { .intr_enable = mc_gv11b_intr_enable, diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.c b/drivers/gpu/nvgpu/gv100/regops_gv100.c new file mode 100644 index 00000000..00f05418 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.c @@ -0,0 +1,463 @@ +/* + * Tegra GV100 GPU Driver Register Ops + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gk20a/gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/regops_gk20a.h" +#include "regops_gv100.h" + +static const struct regop_offset_range gv100_global_whitelist_ranges[] = { + { 0x000004f0, 1}, + { 0x00001a00, 3}, + { 0x00002800, 128}, + { 0x00009400, 1}, + { 0x00009410, 1}, + { 0x00009480, 1}, + { 0x00020200, 24}, + { 0x00021c00, 4}, + { 0x00021c14, 3}, + { 0x00021c24, 1}, + { 0x00021c2c, 69}, + { 0x00021d44, 1}, + { 0x00021d4c, 1}, + { 0x00021d54, 1}, + { 0x00021d5c, 1}, + { 0x00021d64, 2}, + { 0x00021d70, 16}, + { 0x00022430, 7}, + { 0x00022450, 1}, + { 0x0002245c, 2}, + { 0x00070000, 5}, + { 0x000884e0, 1}, + { 0x0008e00c, 1}, + { 0x00100c18, 3}, + { 0x00100c84, 1}, + { 0x00104038, 1}, + { 0x0010a0a8, 1}, + { 0x0010a4f0, 1}, + { 0x0010e490, 1}, + { 0x0013cc14, 1}, + { 0x00140028, 1}, + { 0x00140280, 1}, + { 0x001402a0, 1}, + { 0x00140350, 1}, + { 0x00140480, 1}, + { 0x001404a0, 1}, + { 0x00140550, 1}, + { 0x00142028, 1}, + { 0x00142280, 1}, + { 0x001422a0, 1}, + { 0x00142350, 1}, + { 0x00142480, 1}, + { 0x001424a0, 1}, + { 0x00142550, 1}, + { 0x0017e028, 1}, + { 0x0017e280, 1}, + { 0x0017e294, 1}, + { 0x0017e29c, 2}, + { 0x0017e2ac, 1}, + { 0x0017e350, 1}, + { 0x0017e39c, 1}, + { 0x0017e480, 1}, + { 0x0017e4a0, 1}, + { 0x0017e550, 1}, + { 0x00180040, 41}, + { 0x001800ec, 10}, + { 0x00180240, 41}, + { 0x001802ec, 10}, + { 0x00180440, 41}, + { 0x001804ec, 10}, + { 0x00180640, 41}, + { 0x001806ec, 10}, + { 0x00180840, 41}, + { 0x001808ec, 10}, + { 0x00180a40, 41}, + { 0x00180aec, 10}, + { 0x00180c40, 41}, + { 0x00180cec, 10}, + { 0x00180e40, 41}, + { 0x00180eec, 10}, + { 0x001a0040, 41}, + { 0x001a00ec, 10}, + { 0x001a0240, 41}, + { 0x001a02ec, 10}, + { 0x001a0440, 41}, + { 0x001a04ec, 10}, + { 0x001a0640, 41}, + { 0x001a06ec, 10}, + { 0x001a0840, 41}, + { 0x001a08ec, 10}, + { 0x001a0a40, 41}, + { 0x001a0aec, 10}, + { 0x001a0c40, 41}, + { 0x001a0cec, 10}, + { 0x001a0e40, 41}, + { 0x001a0eec, 10}, + { 0x001b0040, 41}, + { 0x001b00ec, 10}, + { 0x001b0240, 41}, + { 0x001b02ec, 10}, + { 0x001b0440, 41}, + { 0x001b04ec, 10}, + { 0x001b0640, 41}, + { 0x001b06ec, 10}, + { 0x001b0840, 41}, + { 0x001b08ec, 10}, + { 0x001b0a40, 41}, + { 0x001b0aec, 10}, + { 0x001b0c40, 41}, + { 0x001b0cec, 10}, + { 0x001b0e40, 41}, + { 0x001b0eec, 10}, + { 0x001b4000, 1}, + { 0x001b4008, 1}, + { 0x001b4010, 3}, + { 0x001b4020, 3}, + { 0x001b4030, 3}, + { 0x001b4040, 3}, + { 0x001b4050, 3}, + { 0x001b4060, 4}, + { 0x001b4074, 7}, + { 0x001b4094, 3}, + { 0x001b40a4, 1}, + { 0x001b4100, 6}, + { 0x001b4128, 1}, + { 0x001b8000, 1}, + { 0x001b8008, 1}, + { 0x001b8010, 2}, + { 0x001bc000, 1}, + { 0x001bc008, 1}, + { 0x001bc010, 2}, + { 0x001be000, 1}, + { 0x001be008, 1}, + { 0x001be010, 2}, + { 0x00400500, 1}, + { 0x0040415c, 1}, + { 0x00404468, 1}, + { 0x00404498, 1}, + { 0x00405800, 1}, + { 0x00405840, 2}, + { 0x00405850, 1}, + { 0x00405908, 1}, + { 0x00405b40, 1}, + { 0x00405b50, 1}, + { 0x00406024, 5}, + { 0x00407010, 1}, + { 0x00407808, 1}, + { 0x0040803c, 1}, + { 0x00408804, 1}, + { 0x0040880c, 1}, + { 0x00408900, 2}, + { 0x00408910, 1}, + { 0x00408944, 1}, + { 0x00408984, 1}, + { 0x004090a8, 1}, + { 0x004098a0, 1}, + { 0x00409b00, 1}, + { 0x0041000c, 1}, + { 0x00410110, 1}, + { 0x00410184, 1}, + { 0x0041040c, 1}, + { 0x00410510, 1}, + { 0x00410584, 1}, + { 0x00418000, 1}, + { 0x00418008, 1}, + { 0x00418380, 2}, + { 0x00418400, 2}, + { 0x004184a0, 1}, + { 0x00418604, 1}, + { 0x00418680, 1}, + { 0x00418704, 1}, + { 0x00418714, 1}, + { 0x00418800, 1}, + { 0x0041881c, 1}, + { 0x00418830, 1}, + { 0x00418884, 1}, + { 0x004188b0, 1}, + { 0x004188c8, 3}, + { 0x004188fc, 1}, + { 0x00418b04, 1}, + { 0x00418c04, 1}, + { 0x00418c10, 8}, + { 0x00418c88, 1}, + { 0x00418d00, 1}, + { 0x00418e00, 1}, + { 0x00418e08, 1}, + { 0x00418e34, 1}, + { 0x00418e40, 4}, + { 0x00418e58, 16}, + { 0x00418f08, 1}, + { 0x00419000, 1}, + { 0x0041900c, 1}, + { 0x00419018, 1}, + { 0x00419854, 1}, + { 0x00419864, 1}, + { 0x00419a04, 2}, + { 0x00419a14, 1}, + { 0x00419ab0, 1}, + { 0x00419ab8, 3}, + { 0x00419c0c, 1}, + { 0x00419c8c, 2}, + { 0x00419d00, 1}, + { 0x00419d08, 2}, + { 0x00419e00, 11}, + { 0x00419e34, 2}, + { 0x00419e44, 11}, + { 0x00419e74, 10}, + { 0x00419ea4, 1}, + { 0x00419eac, 2}, + { 0x00419ee8, 1}, + { 0x00419ef0, 28}, + { 0x00419f70, 1}, + { 0x00419f78, 2}, + { 0x00419f98, 2}, + { 0x0041a02c, 2}, + { 0x0041a0a8, 1}, + { 0x0041a8a0, 3}, + { 0x0041b014, 1}, + { 0x0041b0a0, 1}, + { 0x0041b0cc, 1}, + { 0x0041b1dc, 1}, + { 0x0041be0c, 3}, + { 0x0041bea0, 1}, + { 0x0041becc, 1}, + { 0x0041bfdc, 1}, + { 0x0041c054, 1}, + { 0x0041c2b0, 1}, + { 0x0041c2b8, 3}, + { 0x0041c40c, 1}, + { 0x0041c48c, 2}, + { 0x0041c500, 1}, + { 0x0041c508, 2}, + { 0x0041c600, 11}, + { 0x0041c634, 2}, + { 0x0041c644, 11}, + { 0x0041c674, 10}, + { 0x0041c6a4, 1}, + { 0x0041c6ac, 2}, + { 0x0041c6e8, 1}, + { 0x0041c6f0, 28}, + { 0x0041c770, 1}, + { 0x0041c778, 2}, + { 0x0041c798, 2}, + { 0x0041c854, 1}, + { 0x0041cab0, 1}, + { 0x0041cab8, 3}, + { 0x0041cc0c, 1}, + { 0x0041cc8c, 2}, + { 0x0041cd00, 1}, + { 0x0041cd08, 2}, + { 0x0041ce00, 11}, + { 0x0041ce34, 2}, + { 0x0041ce44, 11}, + { 0x0041ce74, 10}, + { 0x0041cea4, 1}, + { 0x0041ceac, 2}, + { 0x0041cee8, 1}, + { 0x0041cef0, 28}, + { 0x0041cf70, 1}, + { 0x0041cf78, 2}, + { 0x0041cf98, 2}, + { 0x00500384, 1}, + { 0x005004a0, 1}, + { 0x00500604, 1}, + { 0x00500680, 1}, + { 0x00500714, 1}, + { 0x0050081c, 1}, + { 0x00500884, 1}, + { 0x005008b0, 1}, + { 0x005008c8, 3}, + { 0x005008fc, 1}, + { 0x00500b04, 1}, + { 0x00500c04, 1}, + { 0x00500c10, 8}, + { 0x00500c88, 1}, + { 0x00500d00, 1}, + { 0x00500e08, 1}, + { 0x00500f08, 1}, + { 0x00501000, 1}, + { 0x0050100c, 1}, + { 0x00501018, 1}, + { 0x00501854, 1}, + { 0x00501ab0, 1}, + { 0x00501ab8, 3}, + { 0x00501c0c, 1}, + { 0x00501c8c, 2}, + { 0x00501d00, 1}, + { 0x00501d08, 2}, + { 0x00501e00, 11}, + { 0x00501e34, 2}, + { 0x00501e44, 11}, + { 0x00501e74, 10}, + { 0x00501ea4, 1}, + { 0x00501eac, 2}, + { 0x00501ee8, 1}, + { 0x00501ef0, 28}, + { 0x00501f70, 1}, + { 0x00501f78, 2}, + { 0x00501f98, 2}, + { 0x0050202c, 2}, + { 0x005020a8, 1}, + { 0x005028a0, 3}, + { 0x00503014, 1}, + { 0x005030a0, 1}, + { 0x005030cc, 1}, + { 0x005031dc, 1}, + { 0x00503e14, 1}, + { 0x00503ea0, 1}, + { 0x00503ecc, 1}, + { 0x00503fdc, 1}, + { 0x00504054, 1}, + { 0x005042b0, 1}, + { 0x005042b8, 3}, + { 0x0050440c, 1}, + { 0x0050448c, 2}, + { 0x00504500, 1}, + { 0x00504508, 2}, + { 0x00504600, 11}, + { 0x00504634, 2}, + { 0x00504644, 11}, + { 0x00504674, 10}, + { 0x005046a4, 1}, + { 0x005046ac, 2}, + { 0x005046e8, 1}, + { 0x005046f0, 28}, + { 0x00504770, 1}, + { 0x00504778, 2}, + { 0x00504798, 2}, + { 0x00504854, 1}, + { 0x00504ab0, 1}, + { 0x00504ab8, 3}, + { 0x00504c0c, 1}, + { 0x00504c8c, 2}, + { 0x00504d00, 1}, + { 0x00504d08, 2}, + { 0x00504e00, 11}, + { 0x00504e34, 2}, + { 0x00504e44, 11}, + { 0x00504e74, 10}, + { 0x00504ea4, 1}, + { 0x00504eac, 2}, + { 0x00504ee8, 1}, + { 0x00504ef0, 28}, + { 0x00504f70, 1}, + { 0x00504f78, 2}, + { 0x00504f98, 2}, + { 0x00900100, 1}, + { 0x009a0100, 1},}; + + +static const u32 gv100_global_whitelist_ranges_count = + ARRAY_SIZE(gv100_global_whitelist_ranges); + +/* context */ + +/* runcontrol */ +static const u32 gv100_runcontrol_whitelist[] = { +}; +static const u32 gv100_runcontrol_whitelist_count = + ARRAY_SIZE(gv100_runcontrol_whitelist); + +static const struct regop_offset_range gv100_runcontrol_whitelist_ranges[] = { +}; +static const u32 gv100_runcontrol_whitelist_ranges_count = + ARRAY_SIZE(gv100_runcontrol_whitelist_ranges); + + +/* quad ctl */ +static const u32 gv100_qctl_whitelist[] = { +}; +static const u32 gv100_qctl_whitelist_count = + ARRAY_SIZE(gv100_qctl_whitelist); + +static const struct regop_offset_range gv100_qctl_whitelist_ranges[] = { +}; +static const u32 gv100_qctl_whitelist_ranges_count = + ARRAY_SIZE(gv100_qctl_whitelist_ranges); + +const struct regop_offset_range *gv100_get_global_whitelist_ranges(void) +{ + return gv100_global_whitelist_ranges; +} + +int gv100_get_global_whitelist_ranges_count(void) +{ + return gv100_global_whitelist_ranges_count; +} + +const struct regop_offset_range *gv100_get_context_whitelist_ranges(void) +{ + return gv100_global_whitelist_ranges; +} + +int gv100_get_context_whitelist_ranges_count(void) +{ + return gv100_global_whitelist_ranges_count; +} + +const u32 *gv100_get_runcontrol_whitelist(void) +{ + return gv100_runcontrol_whitelist; +} + +int gv100_get_runcontrol_whitelist_count(void) +{ + return gv100_runcontrol_whitelist_count; +} + +const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void) +{ + return gv100_runcontrol_whitelist_ranges; +} + +int gv100_get_runcontrol_whitelist_ranges_count(void) +{ + return gv100_runcontrol_whitelist_ranges_count; +} + +const u32 *gv100_get_qctl_whitelist(void) +{ + return gv100_qctl_whitelist; +} + +int gv100_get_qctl_whitelist_count(void) +{ + return gv100_qctl_whitelist_count; +} + +const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void) +{ + return gv100_qctl_whitelist_ranges; +} + +int gv100_get_qctl_whitelist_ranges_count(void) +{ + return gv100_qctl_whitelist_ranges_count; +} + +int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s) +{ + /* Not needed on gv100 */ + return 0; +} diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.h b/drivers/gpu/nvgpu/gv100/regops_gv100.h new file mode 100644 index 00000000..06e5b8e1 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.h @@ -0,0 +1,42 @@ +/* + * + * Tegra GV100 GPU Driver Register Ops + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __REGOPS_GV100_H_ +#define __REGOPS_GV100_H_ + +const struct regop_offset_range *gv100_get_global_whitelist_ranges(void); +int gv100_get_global_whitelist_ranges_count(void); +const struct regop_offset_range *gv100_get_context_whitelist_ranges(void); +int gv100_get_context_whitelist_ranges_count(void); +const u32 *gv100_get_runcontrol_whitelist(void); +int gv100_get_runcontrol_whitelist_count(void); +const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void); +int gv100_get_runcontrol_whitelist_ranges_count(void); +const u32 *gv100_get_qctl_whitelist(void); +int gv100_get_qctl_whitelist_count(void); +const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void); +int gv100_get_qctl_whitelist_ranges_count(void); +int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s); + +#endif /* __REGOPS_GV11B_H_ */ -- cgit v1.2.2 From 8b100734e08e887eb363ced2c9455fa874e6e6a2 Mon Sep 17 00:00:00 2001 From: Sachin Nikam Date: Fri, 13 Oct 2017 10:32:27 +0530 Subject: NVIDIA-REVIEWERS: refresh for nvgpu-t19x - Added Bug field - Updated the Maintainers and Files Bug 200347794 Change-Id: I3eb8e0136227c78000b9feddeca52c2b7e1b05bc Signed-off-by: Sachin Nikam Reviewed-on: https://git-master.nvidia.com/r/1578273 --- NVIDIA-REVIEWERS | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/NVIDIA-REVIEWERS b/NVIDIA-REVIEWERS index d5de0d05..ead0979d 100644 --- a/NVIDIA-REVIEWERS +++ b/NVIDIA-REVIEWERS @@ -10,6 +10,7 @@ Descriptions of section entries (copied from MAINTAINERS): P: Person (obsolete) M: Mail patches to: FullName L: Mailing list that is relevant to this area + B: NvBugs Module Name W: Web-page with status/info Q: Patchwork web based patch tracking system site T: SCM tree type and location. Type is one of: git, hg, quilt, stgit, topgit. @@ -50,10 +51,16 @@ so much easier [Ed] Maintainers List (try to look for most precise areas first) - ----------------------------------- +---------------------------------------------------------------------- GPU -M: Terje Bergstrom -L: sw-mobile-nvgpu-core@exchange.nvidia.com -S: Supported -F: drivers/* -F: include/* +M: Vijayakumar Subbu +M: Terje Bergstrom +L: sw-mobile-nvgpu-core@exchange.nvidia.com +B: Mobile_Android_Kernel +B: Mobile_Linux_Kernel +B: Embedded Resource Manager - Linux +S: Supported +F: drivers/gpu/nvgpu/* +F: include/* +F: ../../gpu-firmware-private/ + -- cgit v1.2.2 From 1b6669957330312f0336bc207a64668782129048 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 20 Oct 2017 14:49:01 -0700 Subject: gpu: nvgpu: gvxx: enhance class error debug info Generated following hw definitions for gv100 and gv11b to dump relevant data in gk20a_gr_handle_class_error: gr_trapped_addr_mme_generated_v gr_trapped_addr_datahigh_v gr_trapped_addr_priv_v gr_trapped_data_lo_r gr_trapped_data_mme_r gr_trapped_data_mme_pc_v Bug 2003671 Change-Id: I055c693458625e1cdbbcdaa63ee4b0efd3697015 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1582848 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 24 ++++++++++++++++++++++ .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 24 ++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h index bdd749d0..09cbc793 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h @@ -284,6 +284,22 @@ static inline u32 gr_trapped_addr_subch_v(u32 r) { return (r >> 16U) & 0x7U; } +static inline u32 gr_trapped_addr_mme_generated_v(u32 r) +{ + return (r >> 20U) & 0x1U; +} +static inline u32 gr_trapped_addr_datahigh_v(u32 r) +{ + return (r >> 24U) & 0x1U; +} +static inline u32 gr_trapped_addr_priv_v(u32 r) +{ + return (r >> 28U) & 0x1U; +} +static inline u32 gr_trapped_addr_status_v(u32 r) +{ + return (r >> 31U) & 0x1U; +} static inline u32 gr_trapped_data_lo_r(void) { return 0x00400708U; @@ -292,6 +308,14 @@ static inline u32 gr_trapped_data_hi_r(void) { return 0x0040070cU; } +static inline u32 gr_trapped_data_mme_r(void) +{ + return 0x00400710U; +} +static inline u32 gr_trapped_data_mme_pc_v(u32 r) +{ + return (r >> 0U) & 0xfffU; +} static inline u32 gr_status_r(void) { return 0x00400700U; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 3bdf2de2..692b7ba3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -284,6 +284,22 @@ static inline u32 gr_trapped_addr_subch_v(u32 r) { return (r >> 16U) & 0x7U; } +static inline u32 gr_trapped_addr_mme_generated_v(u32 r) +{ + return (r >> 20U) & 0x1U; +} +static inline u32 gr_trapped_addr_datahigh_v(u32 r) +{ + return (r >> 24U) & 0x1U; +} +static inline u32 gr_trapped_addr_priv_v(u32 r) +{ + return (r >> 28U) & 0x1U; +} +static inline u32 gr_trapped_addr_status_v(u32 r) +{ + return (r >> 31U) & 0x1U; +} static inline u32 gr_trapped_data_lo_r(void) { return 0x00400708U; @@ -292,6 +308,14 @@ static inline u32 gr_trapped_data_hi_r(void) { return 0x0040070cU; } +static inline u32 gr_trapped_data_mme_r(void) +{ + return 0x00400710U; +} +static inline u32 gr_trapped_data_mme_pc_v(u32 r) +{ + return (r >> 0U) & 0xfffU; +} static inline u32 gr_status_r(void) { return 0x00400700U; -- cgit v1.2.2 From 0956d26143b5313f590fcaf008a2182a08b9967c Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 20 Oct 2017 14:52:43 -0700 Subject: gpu: nvgpu: gv11b: sync hw header defines with generator Updated hw_therm_gv11b related defines to sync with tool generated output. Change-Id: I9c6e879636730eda1c4608d6e18f47c3fe55893e Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1582849 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h index ce265901..8f8981e8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h @@ -242,7 +242,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) } static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) { - return 0x200; + return 0x200U; } static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) { @@ -254,7 +254,7 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) } static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) { - return 0x2000; + return 0x2000U; } static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) { @@ -266,7 +266,7 @@ static inline u32 therm_gate_ctrl_eng_delay_before_m(void) } static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) { - return 0x40000; + return 0x40000U; } static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) { @@ -278,7 +278,7 @@ static inline u32 therm_gate_ctrl_eng_delay_after_m(void) } static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_fecs_idle_filter_r(void) { @@ -290,7 +290,7 @@ static inline u32 therm_fecs_idle_filter_value_m(void) } static inline u32 therm_fecs_idle_filter_value__prod_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_hubmmu_idle_filter_r(void) { @@ -302,7 +302,7 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void) } static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) { - return 0x0; + return 0x0U; } static inline u32 therm_clk_slowdown_r(u32 i) { -- cgit v1.2.2 From 86e1c3278fab9c7b335962549ba8f0860ef9f119 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Mon, 23 Oct 2017 14:12:41 +0530 Subject: gpu: nvgpu: gv11b: use correct acr_dmem_desc ver. gv11b should use acr_dmem_desc_v1 instead of acr_dmem_desc. JIRA GPUT19X-5 Change-Id: I3ccae72541607aec12e25845ea4cb875ff11d67c Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1583642 Reviewed-by: Supriya Sharatkumar Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index 984d31da..e2454f85 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c @@ -177,7 +177,7 @@ int gv11b_bootstrap_hs_flcn(struct gk20a *g) acr_ucode_header_t210_load[2]); bl_dmem_desc->data_size = acr_ucode_header_t210_load[3]; } else - acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0; + acr->acr_dmem_desc_v1->nonwpr_ucode_blob_size = 0; status = pmu_exec_gen_bl(g, bl_dmem_desc, 1); if (status != 0) { err = status; -- cgit v1.2.2 From df4e88a21d51d5e098b66c3094fa91ae633777e5 Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Fri, 4 Aug 2017 17:32:02 -0700 Subject: gpu: nvgpu: vgpu: add support for gv11b syncpoints In t19x, gv11b semaphore read and write operations are translated to host1x syncpoint read and write operations using semaphore syncpoint shim aperture. Implement relevant vgpu hal functions for this in fifo hal. Jira EVLR-1571 Change-Id: I6296cc6e592ea991e1c01bc9662d02fb063ff3c7 Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1516367 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 18 ++++- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 76 ++++++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h | 2 + drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- include/linux/tegra_vgpu_t19x.h | 10 +++ 5 files changed, 105 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 6adbd46b..d48d1308 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -26,6 +26,8 @@ #include "common/linux/os_linux.h" #include +#include + #include static int gv11b_vgpu_probe(struct device *dev) @@ -35,6 +37,7 @@ static int gv11b_vgpu_probe(struct device *dev) struct resource *r; void __iomem *regs; struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(platform->g); + struct gk20a *g = platform->g; int ret; r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usermode"); @@ -50,11 +53,22 @@ static int gv11b_vgpu_probe(struct device *dev) l->t19x.usermode_regs = regs; #ifdef CONFIG_TEGRA_GK20A_NVHOST - ret = nvgpu_get_nvhost_dev(platform->g); + ret = nvgpu_get_nvhost_dev(g); if (ret) { l->t19x.usermode_regs = NULL; return ret; } + + ret = nvgpu_nvhost_syncpt_unit_interface_get_aperture(g->nvhost_dev, + &g->syncpt_unit_base, + &g->syncpt_unit_size); + if (ret) { + dev_err(dev, "Failed to get syncpt interface"); + return -ENOSYS; + } + g->syncpt_size = nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(1); + nvgpu_info(g, "syncpt_unit_base %llx syncpt_unit_size %zx size %x\n", + g->syncpt_unit_base, g->syncpt_unit_size, g->syncpt_size); #endif vgpu_init_clk_support(platform->g); @@ -62,7 +76,7 @@ static int gv11b_vgpu_probe(struct device *dev) } struct gk20a_platform gv11b_vgpu_tegra_platform = { - .has_syncpoints = false, + .has_syncpoints = true, .aggressive_sync_destroy_thresh = 64, /* power management configuration */ diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c index 048a4c64..ae9d52a7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -23,6 +23,82 @@ #include #include "vgpu/vgpu.h" +#include "gv11b/fifo_gv11b.h" +#include + +#include + +#ifdef CONFIG_TEGRA_GK20A_NVHOST +int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf) +{ + int err; + struct gk20a *g = c->g; + struct vm_gk20a *vm = c->vm; + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_map_syncpt_params *p = &msg.params.t19x.map_syncpt; + + /* + * Add ro map for complete sync point shim range in vm. + * All channels sharing same vm will share same ro mapping. + * Create rw map for current channel sync point. + */ + if (!vm->syncpt_ro_map_gpu_va) { + vm->syncpt_ro_map_gpu_va = __nvgpu_vm_alloc_va(vm, + g->syncpt_unit_size, + gmmu_page_size_kernel); + if (!vm->syncpt_ro_map_gpu_va) { + nvgpu_err(g, "allocating read-only va space failed"); + return -ENOMEM; + } + + msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT; + msg.handle = vgpu_get_handle(g); + p->as_handle = c->vm->handle; + p->gpu_va = vm->syncpt_ro_map_gpu_va; + p->len = g->syncpt_unit_size; + p->offset = 0; + p->prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (err) { + nvgpu_err(g, + "mapping read-only va space failed err %d", + err); + __nvgpu_vm_free_va(c->vm, vm->syncpt_ro_map_gpu_va, + gmmu_page_size_kernel); + vm->syncpt_ro_map_gpu_va = 0; + return err; + } + } + + syncpt_buf->gpu_va = __nvgpu_vm_alloc_va(c->vm, g->syncpt_size, + gmmu_page_size_kernel); + if (!syncpt_buf->gpu_va) { + nvgpu_err(g, "allocating syncpt va space failed"); + return -ENOMEM; + } + + msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT; + msg.handle = vgpu_get_handle(g); + p->as_handle = c->vm->handle; + p->gpu_va = syncpt_buf->gpu_va; + p->len = g->syncpt_size; + p->offset = + nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id); + p->prot = TEGRA_VGPU_MAP_PROT_NONE; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (err) { + nvgpu_err(g, "mapping syncpt va space failed err %d", err); + __nvgpu_vm_free_va(c->vm, syncpt_buf->gpu_va, + gmmu_page_size_kernel); + return err; + } + + return 0; +} +#endif /* CONFIG_TEGRA_GK20A_NVHOST */ int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h index 03404542..bea935d3 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h @@ -26,4 +26,6 @@ struct gk20a; int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g); +int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 9226206a..2cd8018c 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -378,7 +378,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .tsg_bind_channel = vgpu_tsg_bind_channel, .tsg_unbind_channel = vgpu_tsg_unbind_channel, #ifdef CONFIG_TEGRA_GK20A_NVHOST - .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, + .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, diff --git a/include/linux/tegra_vgpu_t19x.h b/include/linux/tegra_vgpu_t19x.h index c2814f16..fe39230e 100644 --- a/include/linux/tegra_vgpu_t19x.h +++ b/include/linux/tegra_vgpu_t19x.h @@ -16,6 +16,7 @@ #define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100 #define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101 +#define TEGRA_VGPU_CMD_MAP_SYNCPT 102 struct tegra_vgpu_alloc_ctx_header_params { u64 ch_handle; @@ -26,9 +27,18 @@ struct tegra_vgpu_free_ctx_header_params { u64 ch_handle; }; +struct tegra_vgpu_map_syncpt_params { + u64 as_handle; + u64 gpu_va; + u64 len; + u64 offset; + u8 prot; +}; + union tegra_vgpu_t19x_params { struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; struct tegra_vgpu_free_ctx_header_params free_ctx_header; + struct tegra_vgpu_map_syncpt_params map_syncpt; }; #define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100 -- cgit v1.2.2 From 0899e11d4bb630381607a0c245f72476e2e9209e Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 6 Oct 2017 17:20:12 -0700 Subject: gpu: nvgpu: Cleanup generic MM code t19x changes necessary for change in core MM code. JIRA NVGPU-30 Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1577265 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 4 ++-- drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c | 3 +-- drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c | 3 +-- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 5 +++-- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 7 ++++--- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 3 ++- 8 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 3a8dc4b1..1ae424df 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -535,6 +535,7 @@ static const struct gpu_ops gv100_ops = { .init_pdb = gp10b_mm_init_pdb, .init_mm_setup_hw = gv11b_init_mm_setup_hw, .is_bar1_supported = gv11b_mm_is_bar1_supported, + .alloc_inst_block = gk20a_alloc_inst_block, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = gv11b_mm_mmu_fault_pending, .get_kind_invalid = gm20b_get_kind_invalid, diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index e2454f85..b245dbc6 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "acr_gv11b.h" @@ -211,7 +212,7 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu, pwr_falcon_itfen_ctxen_enable_f()); gk20a_writel(g, pwr_pmu_new_instblk_r(), pwr_pmu_new_instblk_ptr_f( - gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | + nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | pwr_pmu_new_instblk_valid_f(1) | pwr_pmu_new_instblk_target_sys_ncoh_f()); @@ -291,4 +292,3 @@ int gv11b_init_pmu_setup_hw1(struct gk20a *g, return err; return 0; } - diff --git a/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c index 6afd92fa..bf3383fd 100644 --- a/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c @@ -135,8 +135,7 @@ int gv11b_css_hw_enable_snapshot(struct channel_gk20a *ch, gk20a_writel(g, perf_pmasys_outsize_r(), snapshot_size); /* this field is aligned to 4K */ - inst_pa_page = gk20a_mm_inst_block_addr(g, - &g->mm.hwpm.inst_block) >> 12; + inst_pa_page = nvgpu_inst_block_addr(g, &g->mm.hwpm.inst_block) >> 12; gk20a_writel(g, perf_pmasys_mem_block_r(), perf_pmasys_mem_block_base_f(inst_pa_page) | diff --git a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c index 2fdfc8f4..a02c2ddd 100644 --- a/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/dbg_gpu_gv11b.c @@ -58,8 +58,7 @@ int gv11b_perfbuf_enable_locked(struct gk20a *g, u64 offset, u32 size) gk20a_writel(g, perf_pmasys_outsize_r(), size); /* this field is aligned to 4K */ - inst_pa_page = gk20a_mm_inst_block_addr(g, - &mm->perfbuf.inst_block) >> 12; + inst_pa_page = nvgpu_inst_block_addr(g, &mm->perfbuf.inst_block) >> 12; gk20a_writel(g, perf_pmasys_mem_block_r(), perf_pmasys_mem_block_base_f(inst_pa_page) | diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 4a03e6d9..dc3b641a 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -34,6 +34,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -112,9 +113,9 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) runlist[0] = runlist_entry | ram_rl_entry_chan_userd_ptr_lo_f(addr_lo); runlist[1] = ram_rl_entry_chan_userd_ptr_hi_f(addr_hi); - addr_lo = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)) >> + addr_lo = u64_lo32(nvgpu_inst_block_addr(g, &c->inst_block)) >> ram_rl_entry_chan_inst_ptr_align_shift_v(); - addr_hi = u64_hi32(gk20a_mm_inst_block_addr(g, &c->inst_block)); + addr_hi = u64_hi32(nvgpu_inst_block_addr(g, &c->inst_block)); runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) | ram_rl_entry_chid_f(c->chid); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 5b10b7d2..46323cf9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -549,6 +549,7 @@ static const struct gpu_ops gv11b_ops = { .init_pdb = gp10b_mm_init_pdb, .init_mm_setup_hw = gv11b_init_mm_setup_hw, .is_bar1_supported = gv11b_mm_is_bar1_supported, + .alloc_inst_block = gk20a_alloc_inst_block, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = gv11b_mm_mmu_fault_pending, .get_kind_invalid = gm20b_get_kind_invalid, diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 6df29cb0..fdc506ac 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/mm_gk20a.h" @@ -54,7 +55,7 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct gk20a *g = gk20a_from_vm(vm); gk20a_dbg_info("inst block phys = 0x%llx, kv = 0x%p", - gk20a_mm_inst_block_addr(g, inst_block), inst_block->cpu_va); + nvgpu_inst_block_addr(g, inst_block), inst_block->cpu_va); g->ops.mm.init_pdb(g, inst_block, vm); @@ -191,7 +192,7 @@ void gv11b_mm_remove_bar2_vm(struct gk20a *g) gv11b_mm_mmu_hw_fault_buf_deinit(g); - gk20a_free_inst_block(g, &mm->bar2.inst_block); + nvgpu_free_inst_block(g, &mm->bar2.inst_block); nvgpu_vm_put(mm->bar2.vm); } @@ -282,7 +283,7 @@ int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; - u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block); + u64 inst_pa = nvgpu_inst_block_addr(g, inst_block); u32 reg_val; struct nvgpu_timeout timeout; u32 delay = GR_IDLE_CHECK_DEFAULT; diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 74ed9165..2c7b6457 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" @@ -104,7 +105,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) gk20a_writel(g, pwr_pmu_new_instblk_r(), pwr_pmu_new_instblk_ptr_f( - gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB) + nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> ALIGN_4KB) | pwr_pmu_new_instblk_valid_f(1) | pwr_pmu_new_instblk_target_sys_ncoh_f()); -- cgit v1.2.2 From c6ccb5f2a1e9a8999436f6c28ed5c416c5418ae3 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 23 Oct 2017 10:20:12 -0700 Subject: gpu: nvgpu: gv11b: use scg perf for smid numbering For SCG to work, smid numbering needs to be done based on scg performance of tpcs. For gv11b and gv11b vgpu, reuse gv100 function "gr_gv100_init_sm_id_table" to do this. Used local variable "index" to avoid multiple computations in the function: gr_gv100_init_sm_id_table index = sm_id + sm Add deug info for printing initialized gpc/tpc/sm/global_tpc indexs. Bug 1842197 Change-Id: Ibf10f47f10a8ca58b86c307a22e159b2cc0d0f43 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1583916 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_gv100.c | 19 +++++++++++++------ drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 27 --------------------------- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 +++- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 4 +++- 5 files changed, 19 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 4b2038ba..8a4b88b4 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -251,12 +251,19 @@ void gr_gv100_init_sm_id_table(struct gk20a *g) for (tpc = 0, sm_id = 0; sm_id < num_sm; tpc++, sm_id += sm_per_tpc) { for (sm = 0; sm < sm_per_tpc; sm++) { - g->gr.sm_to_cluster[sm_id + sm].gpc_index = - gpc_table[tpc]; - g->gr.sm_to_cluster[sm_id + sm].tpc_index = - tpc_table[tpc]; - g->gr.sm_to_cluster[sm_id + sm].sm_index = sm; - g->gr.sm_to_cluster[sm_id + sm].global_tpc_index = tpc; + u32 index = sm_id + sm; + + g->gr.sm_to_cluster[index].gpc_index = gpc_table[tpc]; + g->gr.sm_to_cluster[index].tpc_index = tpc_table[tpc]; + g->gr.sm_to_cluster[index].sm_index = sm; + g->gr.sm_to_cluster[index].global_tpc_index = tpc; + nvgpu_log_info(g, + "gpc : %d tpc %d sm_index %d global_index: %d", + g->gr.sm_to_cluster[index].gpc_index, + g->gr.sm_to_cluster[index].tpc_index, + g->gr.sm_to_cluster[index].sm_index, + g->gr.sm_to_cluster[index].global_tpc_index); + } } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 154088d6..fc894908 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2125,33 +2125,6 @@ void gr_gv11b_detect_sm_arch(struct gk20a *g) gr_gpc0_tpc0_sm_arch_warp_count_v(v); } -void gr_gv11b_init_sm_id_table(struct gk20a *g) -{ - u32 gpc, tpc, sm; - u32 sm_id = 0; - u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); - - /* TODO populate smids based on power efficiency */ - for (tpc = 0; tpc < g->gr.max_tpc_per_gpc_count; tpc++) { - for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { - - if (tpc >= g->gr.gpc_tpc_count[gpc]) - continue; - - for (sm = 0; sm < sm_per_tpc; sm++) { - g->gr.sm_to_cluster[sm_id].tpc_index = tpc; - g->gr.sm_to_cluster[sm_id].gpc_index = gpc; - g->gr.sm_to_cluster[sm_id].sm_index = sm_id % 2; - g->gr.sm_to_cluster[sm_id].global_tpc_index = - tpc; - sm_id++; - } - } - } - g->gr.no_of_sm = sm_id; - nvgpu_log_info(g, " total number of sm = %d", g->gr.no_of_sm); -} - void gr_gv11b_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid) { diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index ed469abd..e469d142 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -138,7 +138,6 @@ int gr_gv11b_handle_fecs_error(struct gk20a *g, int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr); int gr_gv11b_init_sw_veid_bundle(struct gk20a *g); void gr_gv11b_detect_sm_arch(struct gk20a *g); -void gr_gv11b_init_sm_id_table(struct gk20a *g); void gr_gv11b_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); int gr_gv11b_load_smid_config(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 46323cf9..8e4cdab8 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -66,6 +66,8 @@ #include "gp106/pmu_gp106.h" #include "gp106/acr_gp106.h" +#include "gv100/gr_gv100.h" + #include "dbg_gpu_gv11b.h" #include "hal_gv11b.h" #include "css_gr_gv11b.h" @@ -298,7 +300,7 @@ static const struct gpu_ops gv11b_ops = { .resume_contexts = gr_gk20a_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, .fuse_override = gp10b_gr_fuse_override, - .init_sm_id_table = gr_gv11b_init_sm_id_table, + .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 2cd8018c..7f6df820 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -74,6 +74,8 @@ #include #include +#include + #include #include "vgpu_gr_gv11b.h" @@ -180,7 +182,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .resume_contexts = vgpu_gr_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, .fuse_override = gp10b_gr_fuse_override, - .init_sm_id_table = gr_gv11b_init_sm_id_table, + .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, -- cgit v1.2.2 From 42ee5493de0ca8b0d24cbb08755b6fec2defe62f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 21 Sep 2017 11:21:49 -0700 Subject: gpu: nvgpu: gv11b: update clock gating prod settings Updated clock gating prod settings for HW CL 39314184 i.e. snap_0913 and VDK_R11 Change-Id: Iae6fd9e95ee5e1ec20bafbb24cd761bdce8fdc5f Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1565683 Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c index ff4880c4..e648fa41 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c @@ -100,6 +100,13 @@ static const struct gating_desc gv11b_slcg_gr[] = { {.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe}, {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, + {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, + {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, + {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, + {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, + {.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe}, + {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, + {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, -- cgit v1.2.2 From 914ded175c7e0517f506cb8ba03807227b88866f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 21 Sep 2017 12:00:41 -0700 Subject: gpu: nvgpu: gv11b: update regops whitelist Updated regops whitelist for HW CL 39314184 i.e. snap_0913 and VDK_R11 Change-Id: Ie22f0a000c4bb151023a92e0d7e877bbceb157f2 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1565684 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/regops_gv11b.c | 444 ++++++++++++++++++++++----------- 1 file changed, 296 insertions(+), 148 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c index a29322b7..c356785e 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c @@ -122,107 +122,133 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00180b20, 2}, { 0x00180c40, 41}, { 0x00180cec, 1}, - { 0x00180cf8, 7}, + { 0x00180cf8, 2}, + { 0x00180d04, 4}, { 0x00180d20, 2}, { 0x00180e40, 41}, { 0x00180eec, 1}, - { 0x00180ef8, 7}, + { 0x00180ef8, 2}, + { 0x00180f04, 4}, { 0x00180f20, 2}, { 0x00181040, 41}, { 0x001810ec, 1}, - { 0x001810f8, 7}, + { 0x001810f8, 2}, + { 0x00181104, 4}, { 0x00181120, 2}, { 0x00181240, 41}, { 0x001812ec, 1}, - { 0x001812f8, 7}, + { 0x001812f8, 2}, + { 0x00181304, 4}, { 0x00181320, 2}, { 0x00181440, 41}, { 0x001814ec, 1}, - { 0x001814f8, 7}, + { 0x001814f8, 2}, + { 0x00181504, 4}, { 0x00181520, 2}, { 0x00181640, 41}, { 0x001816ec, 1}, - { 0x001816f8, 7}, + { 0x001816f8, 2}, + { 0x00181704, 4}, { 0x00181720, 2}, { 0x00181840, 41}, { 0x001818ec, 1}, - { 0x001818f8, 7}, + { 0x001818f8, 2}, + { 0x00181904, 4}, { 0x00181920, 2}, { 0x00181a40, 41}, { 0x00181aec, 1}, - { 0x00181af8, 7}, + { 0x00181af8, 2}, + { 0x00181b04, 4}, { 0x00181b20, 2}, { 0x00181c40, 41}, { 0x00181cec, 1}, - { 0x00181cf8, 7}, + { 0x00181cf8, 2}, + { 0x00181d04, 4}, { 0x00181d20, 2}, { 0x00181e40, 41}, { 0x00181eec, 1}, - { 0x00181ef8, 7}, + { 0x00181ef8, 2}, + { 0x00181f04, 4}, { 0x00181f20, 2}, { 0x00182040, 41}, { 0x001820ec, 1}, - { 0x001820f8, 7}, + { 0x001820f8, 2}, + { 0x00182104, 4}, { 0x00182120, 2}, { 0x00182240, 41}, { 0x001822ec, 1}, - { 0x001822f8, 7}, + { 0x001822f8, 2}, + { 0x00182304, 4}, { 0x00182320, 2}, { 0x00182440, 41}, { 0x001824ec, 1}, - { 0x001824f8, 7}, + { 0x001824f8, 2}, + { 0x00182504, 4}, { 0x00182520, 2}, { 0x00182640, 41}, { 0x001826ec, 1}, - { 0x001826f8, 7}, + { 0x001826f8, 2}, + { 0x00182704, 4}, { 0x00182720, 2}, { 0x00182840, 41}, { 0x001828ec, 1}, - { 0x001828f8, 7}, + { 0x001828f8, 2}, + { 0x00182904, 4}, { 0x00182920, 2}, { 0x00182a40, 41}, { 0x00182aec, 1}, - { 0x00182af8, 7}, + { 0x00182af8, 2}, + { 0x00182b04, 4}, { 0x00182b20, 2}, { 0x00182c40, 41}, { 0x00182cec, 1}, - { 0x00182cf8, 7}, + { 0x00182cf8, 2}, + { 0x00182d04, 4}, { 0x00182d20, 2}, { 0x00182e40, 41}, { 0x00182eec, 1}, - { 0x00182ef8, 7}, + { 0x00182ef8, 2}, + { 0x00182f04, 4}, { 0x00182f20, 2}, { 0x00183040, 41}, { 0x001830ec, 1}, - { 0x001830f8, 7}, + { 0x001830f8, 2}, + { 0x00183104, 4}, { 0x00183120, 2}, { 0x00183240, 41}, { 0x001832ec, 1}, - { 0x001832f8, 7}, + { 0x001832f8, 2}, + { 0x00183304, 4}, { 0x00183320, 2}, { 0x00183440, 41}, { 0x001834ec, 1}, - { 0x001834f8, 7}, + { 0x001834f8, 2}, + { 0x00183504, 4}, { 0x00183520, 2}, { 0x00183640, 41}, { 0x001836ec, 1}, - { 0x001836f8, 7}, + { 0x001836f8, 2}, + { 0x00183704, 4}, { 0x00183720, 2}, { 0x00183840, 41}, { 0x001838ec, 1}, - { 0x001838f8, 7}, + { 0x001838f8, 2}, + { 0x00183904, 4}, { 0x00183920, 2}, { 0x00183a40, 41}, { 0x00183aec, 1}, - { 0x00183af8, 7}, + { 0x00183af8, 2}, + { 0x00183b04, 4}, { 0x00183b20, 2}, { 0x00183c40, 41}, { 0x00183cec, 1}, - { 0x00183cf8, 7}, + { 0x00183cf8, 2}, + { 0x00183d04, 4}, { 0x00183d20, 2}, { 0x00183e40, 41}, { 0x00183eec, 1}, - { 0x00183ef8, 7}, + { 0x00183ef8, 2}, + { 0x00183f04, 4}, { 0x00183f20, 2}, { 0x001c80a8, 1}, { 0x001c9100, 1}, @@ -248,115 +274,143 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00200720, 2}, { 0x00200840, 41}, { 0x002008ec, 1}, - { 0x002008f8, 7}, + { 0x002008f8, 2}, + { 0x00200904, 4}, { 0x00200920, 2}, { 0x00200a40, 41}, { 0x00200aec, 1}, - { 0x00200af8, 7}, + { 0x00200af8, 2}, + { 0x00200b04, 4}, { 0x00200b20, 2}, { 0x00200c40, 41}, { 0x00200cec, 1}, - { 0x00200cf8, 7}, + { 0x00200cf8, 2}, + { 0x00200d04, 4}, { 0x00200d20, 2}, { 0x00200e40, 41}, { 0x00200eec, 1}, - { 0x00200ef8, 7}, + { 0x00200ef8, 2}, + { 0x00200f04, 4}, { 0x00200f20, 2}, { 0x00201040, 41}, { 0x002010ec, 1}, - { 0x002010f8, 7}, + { 0x002010f8, 2}, + { 0x00201104, 4}, { 0x00201120, 2}, { 0x00201240, 41}, { 0x002012ec, 1}, - { 0x002012f8, 7}, + { 0x002012f8, 2}, + { 0x00201304, 4}, { 0x00201320, 2}, { 0x00201440, 41}, { 0x002014ec, 1}, - { 0x002014f8, 7}, + { 0x002014f8, 2}, + { 0x00201504, 4}, { 0x00201520, 2}, { 0x00201640, 41}, { 0x002016ec, 1}, - { 0x002016f8, 7}, + { 0x002016f8, 2}, + { 0x00201704, 4}, { 0x00201720, 2}, { 0x00201840, 41}, { 0x002018ec, 1}, - { 0x002018f8, 7}, + { 0x002018f8, 2}, + { 0x00201904, 4}, { 0x00201920, 2}, { 0x00201a40, 41}, { 0x00201aec, 1}, - { 0x00201af8, 7}, + { 0x00201af8, 2}, + { 0x00201b04, 4}, { 0x00201b20, 2}, { 0x00201c40, 41}, { 0x00201cec, 1}, - { 0x00201cf8, 7}, + { 0x00201cf8, 2}, + { 0x00201d04, 4}, { 0x00201d20, 2}, { 0x00201e40, 41}, { 0x00201eec, 1}, - { 0x00201ef8, 7}, + { 0x00201ef8, 2}, + { 0x00201f04, 4}, { 0x00201f20, 2}, { 0x00202040, 41}, { 0x002020ec, 1}, - { 0x002020f8, 7}, + { 0x002020f8, 2}, + { 0x00202104, 4}, { 0x00202120, 2}, { 0x00202240, 41}, { 0x002022ec, 1}, - { 0x002022f8, 7}, + { 0x002022f8, 2}, + { 0x00202304, 4}, { 0x00202320, 2}, { 0x00202440, 41}, { 0x002024ec, 1}, - { 0x002024f8, 7}, + { 0x002024f8, 2}, + { 0x00202504, 4}, { 0x00202520, 2}, { 0x00202640, 41}, { 0x002026ec, 1}, - { 0x002026f8, 7}, + { 0x002026f8, 2}, + { 0x00202704, 4}, { 0x00202720, 2}, { 0x00202840, 41}, { 0x002028ec, 1}, - { 0x002028f8, 7}, + { 0x002028f8, 2}, + { 0x00202904, 4}, { 0x00202920, 2}, { 0x00202a40, 41}, { 0x00202aec, 1}, - { 0x00202af8, 7}, + { 0x00202af8, 2}, + { 0x00202b04, 4}, { 0x00202b20, 2}, { 0x00202c40, 41}, { 0x00202cec, 1}, - { 0x00202cf8, 7}, + { 0x00202cf8, 2}, + { 0x00202d04, 4}, { 0x00202d20, 2}, { 0x00202e40, 41}, { 0x00202eec, 1}, - { 0x00202ef8, 7}, + { 0x00202ef8, 2}, + { 0x00202f04, 4}, { 0x00202f20, 2}, { 0x00203040, 41}, { 0x002030ec, 1}, - { 0x002030f8, 7}, + { 0x002030f8, 2}, + { 0x00203104, 4}, { 0x00203120, 2}, { 0x00203240, 41}, { 0x002032ec, 1}, - { 0x002032f8, 7}, + { 0x002032f8, 2}, + { 0x00203304, 4}, { 0x00203320, 2}, { 0x00203440, 41}, { 0x002034ec, 1}, - { 0x002034f8, 7}, + { 0x002034f8, 2}, + { 0x00203504, 4}, { 0x00203520, 2}, { 0x00203640, 41}, { 0x002036ec, 1}, - { 0x002036f8, 7}, + { 0x002036f8, 2}, + { 0x00203704, 4}, { 0x00203720, 2}, { 0x00203840, 41}, { 0x002038ec, 1}, - { 0x002038f8, 7}, + { 0x002038f8, 2}, + { 0x00203904, 4}, { 0x00203920, 2}, { 0x00203a40, 41}, { 0x00203aec, 1}, - { 0x00203af8, 7}, + { 0x00203af8, 2}, + { 0x00203b04, 4}, { 0x00203b20, 2}, { 0x00203c40, 41}, { 0x00203cec, 1}, - { 0x00203cf8, 7}, + { 0x00203cf8, 2}, + { 0x00203d04, 4}, { 0x00203d20, 2}, { 0x00203e40, 41}, { 0x00203eec, 1}, - { 0x00203ef8, 7}, + { 0x00203ef8, 2}, + { 0x00203f04, 4}, { 0x00203f20, 2}, { 0x00240040, 41}, { 0x002400ec, 1}, @@ -384,107 +438,133 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00240b20, 2}, { 0x00240c40, 41}, { 0x00240cec, 1}, - { 0x00240cf8, 7}, + { 0x00240cf8, 2}, + { 0x00240d04, 4}, { 0x00240d20, 2}, { 0x00240e40, 41}, { 0x00240eec, 1}, - { 0x00240ef8, 7}, + { 0x00240ef8, 2}, + { 0x00240f04, 4}, { 0x00240f20, 2}, { 0x00241040, 41}, { 0x002410ec, 1}, - { 0x002410f8, 7}, + { 0x002410f8, 2}, + { 0x00241104, 4}, { 0x00241120, 2}, { 0x00241240, 41}, { 0x002412ec, 1}, - { 0x002412f8, 7}, + { 0x002412f8, 2}, + { 0x00241304, 4}, { 0x00241320, 2}, { 0x00241440, 41}, { 0x002414ec, 1}, - { 0x002414f8, 7}, + { 0x002414f8, 2}, + { 0x00241504, 4}, { 0x00241520, 2}, { 0x00241640, 41}, { 0x002416ec, 1}, - { 0x002416f8, 7}, + { 0x002416f8, 2}, + { 0x00241704, 4}, { 0x00241720, 2}, { 0x00241840, 41}, { 0x002418ec, 1}, - { 0x002418f8, 7}, + { 0x002418f8, 2}, + { 0x00241904, 4}, { 0x00241920, 2}, { 0x00241a40, 41}, { 0x00241aec, 1}, - { 0x00241af8, 7}, + { 0x00241af8, 2}, + { 0x00241b04, 4}, { 0x00241b20, 2}, { 0x00241c40, 41}, { 0x00241cec, 1}, - { 0x00241cf8, 7}, + { 0x00241cf8, 2}, + { 0x00241d04, 4}, { 0x00241d20, 2}, { 0x00241e40, 41}, { 0x00241eec, 1}, - { 0x00241ef8, 7}, + { 0x00241ef8, 2}, + { 0x00241f04, 4}, { 0x00241f20, 2}, { 0x00242040, 41}, { 0x002420ec, 1}, - { 0x002420f8, 7}, + { 0x002420f8, 2}, + { 0x00242104, 4}, { 0x00242120, 2}, { 0x00242240, 41}, { 0x002422ec, 1}, - { 0x002422f8, 7}, + { 0x002422f8, 2}, + { 0x00242304, 4}, { 0x00242320, 2}, { 0x00242440, 41}, { 0x002424ec, 1}, - { 0x002424f8, 7}, + { 0x002424f8, 2}, + { 0x00242504, 4}, { 0x00242520, 2}, { 0x00242640, 41}, { 0x002426ec, 1}, - { 0x002426f8, 7}, + { 0x002426f8, 2}, + { 0x00242704, 4}, { 0x00242720, 2}, { 0x00242840, 41}, { 0x002428ec, 1}, - { 0x002428f8, 7}, + { 0x002428f8, 2}, + { 0x00242904, 4}, { 0x00242920, 2}, { 0x00242a40, 41}, { 0x00242aec, 1}, - { 0x00242af8, 7}, + { 0x00242af8, 2}, + { 0x00242b04, 4}, { 0x00242b20, 2}, { 0x00242c40, 41}, { 0x00242cec, 1}, - { 0x00242cf8, 7}, + { 0x00242cf8, 2}, + { 0x00242d04, 4}, { 0x00242d20, 2}, { 0x00242e40, 41}, { 0x00242eec, 1}, - { 0x00242ef8, 7}, + { 0x00242ef8, 2}, + { 0x00242f04, 4}, { 0x00242f20, 2}, { 0x00243040, 41}, { 0x002430ec, 1}, - { 0x002430f8, 7}, + { 0x002430f8, 2}, + { 0x00243104, 4}, { 0x00243120, 2}, { 0x00243240, 41}, { 0x002432ec, 1}, - { 0x002432f8, 7}, + { 0x002432f8, 2}, + { 0x00243304, 4}, { 0x00243320, 2}, { 0x00243440, 41}, { 0x002434ec, 1}, - { 0x002434f8, 7}, + { 0x002434f8, 2}, + { 0x00243504, 4}, { 0x00243520, 2}, { 0x00243640, 41}, { 0x002436ec, 1}, - { 0x002436f8, 7}, + { 0x002436f8, 2}, + { 0x00243704, 4}, { 0x00243720, 2}, { 0x00243840, 41}, { 0x002438ec, 1}, - { 0x002438f8, 7}, + { 0x002438f8, 2}, + { 0x00243904, 4}, { 0x00243920, 2}, { 0x00243a40, 41}, { 0x00243aec, 1}, - { 0x00243af8, 7}, + { 0x00243af8, 2}, + { 0x00243b04, 4}, { 0x00243b20, 2}, { 0x00243c40, 41}, { 0x00243cec, 1}, - { 0x00243cf8, 7}, + { 0x00243cf8, 2}, + { 0x00243d04, 4}, { 0x00243d20, 2}, { 0x00243e40, 41}, { 0x00243eec, 1}, - { 0x00243ef8, 7}, + { 0x00243ef8, 2}, + { 0x00243f04, 4}, { 0x00243f20, 2}, { 0x00244000, 1}, { 0x00244008, 1}, @@ -508,22 +588,26 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00250040, 25}, { 0x002500c8, 7}, { 0x002500ec, 1}, - { 0x002500f8, 7}, + { 0x002500f8, 2}, + { 0x00250104, 4}, { 0x00250120, 2}, { 0x00250240, 25}, { 0x002502c8, 7}, { 0x002502ec, 1}, - { 0x002502f8, 7}, + { 0x002502f8, 2}, + { 0x00250304, 4}, { 0x00250320, 2}, { 0x00250840, 25}, { 0x002508c8, 7}, { 0x002508ec, 1}, - { 0x002508f8, 7}, + { 0x002508f8, 2}, + { 0x00250904, 4}, { 0x00250920, 2}, { 0x00250a40, 25}, { 0x00250ac8, 7}, { 0x00250aec, 1}, - { 0x00250af8, 7}, + { 0x00250af8, 2}, + { 0x00250b04, 4}, { 0x00250b20, 2}, { 0x00251800, 3}, { 0x00251810, 2}, @@ -532,322 +616,386 @@ static const struct regop_offset_range gv11b_global_whitelist_ranges[] = { { 0x00278040, 25}, { 0x002780c8, 7}, { 0x002780ec, 1}, - { 0x002780f8, 7}, + { 0x002780f8, 2}, + { 0x00278104, 4}, { 0x00278120, 2}, { 0x00278240, 25}, { 0x002782c8, 7}, { 0x002782ec, 1}, - { 0x002782f8, 7}, + { 0x002782f8, 2}, + { 0x00278304, 4}, { 0x00278320, 2}, { 0x00278440, 25}, { 0x002784c8, 7}, { 0x002784ec, 1}, - { 0x002784f8, 7}, + { 0x002784f8, 2}, + { 0x00278504, 4}, { 0x00278520, 2}, { 0x00278640, 25}, { 0x002786c8, 7}, { 0x002786ec, 1}, - { 0x002786f8, 7}, + { 0x002786f8, 2}, + { 0x00278704, 4}, { 0x00278720, 2}, { 0x00278840, 25}, { 0x002788c8, 7}, { 0x002788ec, 1}, - { 0x002788f8, 7}, + { 0x002788f8, 2}, + { 0x00278904, 4}, { 0x00278920, 2}, { 0x00278a40, 25}, { 0x00278ac8, 7}, { 0x00278aec, 1}, - { 0x00278af8, 7}, + { 0x00278af8, 2}, + { 0x00278b04, 4}, { 0x00278b20, 2}, { 0x00278c40, 25}, { 0x00278cc8, 7}, { 0x00278cec, 1}, - { 0x00278cf8, 7}, + { 0x00278cf8, 2}, + { 0x00278d04, 4}, { 0x00278d20, 2}, { 0x00278e40, 25}, { 0x00278ec8, 7}, { 0x00278eec, 1}, - { 0x00278ef8, 7}, + { 0x00278ef8, 2}, + { 0x00278f04, 4}, { 0x00278f20, 2}, { 0x00279040, 25}, { 0x002790c8, 7}, { 0x002790ec, 1}, - { 0x002790f8, 7}, + { 0x002790f8, 2}, + { 0x00279104, 4}, { 0x00279120, 2}, { 0x00279240, 25}, { 0x002792c8, 7}, { 0x002792ec, 1}, - { 0x002792f8, 7}, + { 0x002792f8, 2}, + { 0x00279304, 4}, { 0x00279320, 2}, { 0x00279440, 25}, { 0x002794c8, 7}, { 0x002794ec, 1}, - { 0x002794f8, 7}, + { 0x002794f8, 2}, + { 0x00279504, 4}, { 0x00279520, 2}, { 0x00279640, 25}, { 0x002796c8, 7}, { 0x002796ec, 1}, - { 0x002796f8, 7}, + { 0x002796f8, 2}, + { 0x00279704, 4}, { 0x00279720, 2}, { 0x00279840, 25}, { 0x002798c8, 7}, { 0x002798ec, 1}, - { 0x002798f8, 7}, + { 0x002798f8, 2}, + { 0x00279904, 4}, { 0x00279920, 2}, { 0x00279a40, 25}, { 0x00279ac8, 7}, { 0x00279aec, 1}, - { 0x00279af8, 7}, + { 0x00279af8, 2}, + { 0x00279b04, 4}, { 0x00279b20, 2}, { 0x00279c40, 25}, { 0x00279cc8, 7}, { 0x00279cec, 1}, - { 0x00279cf8, 7}, + { 0x00279cf8, 2}, + { 0x00279d04, 4}, { 0x00279d20, 2}, { 0x00279e40, 25}, { 0x00279ec8, 7}, { 0x00279eec, 1}, - { 0x00279ef8, 7}, + { 0x00279ef8, 2}, + { 0x00279f04, 4}, { 0x00279f20, 2}, { 0x0027a040, 25}, { 0x0027a0c8, 7}, { 0x0027a0ec, 1}, - { 0x0027a0f8, 7}, + { 0x0027a0f8, 2}, + { 0x0027a104, 4}, { 0x0027a120, 2}, { 0x0027a240, 25}, { 0x0027a2c8, 7}, { 0x0027a2ec, 1}, - { 0x0027a2f8, 7}, + { 0x0027a2f8, 2}, + { 0x0027a304, 4}, { 0x0027a320, 2}, { 0x0027a440, 25}, { 0x0027a4c8, 7}, { 0x0027a4ec, 1}, - { 0x0027a4f8, 7}, + { 0x0027a4f8, 2}, + { 0x0027a504, 4}, { 0x0027a520, 2}, { 0x0027a640, 25}, { 0x0027a6c8, 7}, { 0x0027a6ec, 1}, - { 0x0027a6f8, 7}, + { 0x0027a6f8, 2}, + { 0x0027a704, 4}, { 0x0027a720, 2}, { 0x0027a840, 25}, { 0x0027a8c8, 7}, { 0x0027a8ec, 1}, - { 0x0027a8f8, 7}, + { 0x0027a8f8, 2}, + { 0x0027a904, 4}, { 0x0027a920, 2}, { 0x0027aa40, 25}, { 0x0027aac8, 7}, { 0x0027aaec, 1}, - { 0x0027aaf8, 7}, + { 0x0027aaf8, 2}, + { 0x0027ab04, 4}, { 0x0027ab20, 2}, { 0x0027ac40, 25}, { 0x0027acc8, 7}, { 0x0027acec, 1}, - { 0x0027acf8, 7}, + { 0x0027acf8, 2}, + { 0x0027ad04, 4}, { 0x0027ad20, 2}, { 0x0027ae40, 25}, { 0x0027aec8, 7}, { 0x0027aeec, 1}, - { 0x0027aef8, 7}, + { 0x0027aef8, 2}, + { 0x0027af04, 4}, { 0x0027af20, 2}, { 0x0027b040, 25}, { 0x0027b0c8, 7}, { 0x0027b0ec, 1}, - { 0x0027b0f8, 7}, + { 0x0027b0f8, 2}, + { 0x0027b104, 4}, { 0x0027b120, 2}, { 0x0027b240, 25}, { 0x0027b2c8, 7}, { 0x0027b2ec, 1}, - { 0x0027b2f8, 7}, + { 0x0027b2f8, 2}, + { 0x0027b304, 4}, { 0x0027b320, 2}, { 0x0027b440, 25}, { 0x0027b4c8, 7}, { 0x0027b4ec, 1}, - { 0x0027b4f8, 7}, + { 0x0027b4f8, 2}, + { 0x0027b504, 4}, { 0x0027b520, 2}, { 0x0027b640, 25}, { 0x0027b6c8, 7}, { 0x0027b6ec, 1}, - { 0x0027b6f8, 7}, + { 0x0027b6f8, 2}, + { 0x0027b704, 4}, { 0x0027b720, 2}, { 0x0027b840, 25}, { 0x0027b8c8, 7}, { 0x0027b8ec, 1}, - { 0x0027b8f8, 7}, + { 0x0027b8f8, 2}, + { 0x0027b904, 4}, { 0x0027b920, 2}, { 0x0027ba40, 25}, { 0x0027bac8, 7}, { 0x0027baec, 1}, - { 0x0027baf8, 7}, + { 0x0027baf8, 2}, + { 0x0027bb04, 4}, { 0x0027bb20, 2}, { 0x0027bc40, 25}, { 0x0027bcc8, 7}, { 0x0027bcec, 1}, - { 0x0027bcf8, 7}, + { 0x0027bcf8, 2}, + { 0x0027bd04, 4}, { 0x0027bd20, 2}, { 0x0027be40, 25}, { 0x0027bec8, 7}, { 0x0027beec, 1}, - { 0x0027bef8, 7}, + { 0x0027bef8, 2}, + { 0x0027bf04, 4}, { 0x0027bf20, 2}, { 0x0027c040, 25}, { 0x0027c0c8, 7}, { 0x0027c0ec, 1}, - { 0x0027c0f8, 7}, + { 0x0027c0f8, 2}, + { 0x0027c104, 4}, { 0x0027c120, 2}, { 0x0027c240, 25}, { 0x0027c2c8, 7}, { 0x0027c2ec, 1}, - { 0x0027c2f8, 7}, + { 0x0027c2f8, 2}, + { 0x0027c304, 4}, { 0x0027c320, 2}, { 0x0027c440, 25}, { 0x0027c4c8, 7}, { 0x0027c4ec, 1}, - { 0x0027c4f8, 7}, + { 0x0027c4f8, 2}, + { 0x0027c504, 4}, { 0x0027c520, 2}, { 0x0027c640, 25}, { 0x0027c6c8, 7}, { 0x0027c6ec, 1}, - { 0x0027c6f8, 7}, + { 0x0027c6f8, 2}, + { 0x0027c704, 4}, { 0x0027c720, 2}, { 0x0027c840, 25}, { 0x0027c8c8, 7}, { 0x0027c8ec, 1}, - { 0x0027c8f8, 7}, + { 0x0027c8f8, 2}, + { 0x0027c904, 4}, { 0x0027c920, 2}, { 0x0027ca40, 25}, { 0x0027cac8, 7}, { 0x0027caec, 1}, - { 0x0027caf8, 7}, + { 0x0027caf8, 2}, + { 0x0027cb04, 4}, { 0x0027cb20, 2}, { 0x0027cc40, 25}, { 0x0027ccc8, 7}, { 0x0027ccec, 1}, - { 0x0027ccf8, 7}, + { 0x0027ccf8, 2}, + { 0x0027cd04, 4}, { 0x0027cd20, 2}, { 0x0027ce40, 25}, { 0x0027cec8, 7}, { 0x0027ceec, 1}, - { 0x0027cef8, 7}, + { 0x0027cef8, 2}, + { 0x0027cf04, 4}, { 0x0027cf20, 2}, { 0x0027d040, 25}, { 0x0027d0c8, 7}, { 0x0027d0ec, 1}, - { 0x0027d0f8, 7}, + { 0x0027d0f8, 2}, + { 0x0027d104, 4}, { 0x0027d120, 2}, { 0x0027d240, 25}, { 0x0027d2c8, 7}, { 0x0027d2ec, 1}, - { 0x0027d2f8, 7}, + { 0x0027d2f8, 2}, + { 0x0027d304, 4}, { 0x0027d320, 2}, { 0x0027d440, 25}, { 0x0027d4c8, 7}, { 0x0027d4ec, 1}, - { 0x0027d4f8, 7}, + { 0x0027d4f8, 2}, + { 0x0027d504, 4}, { 0x0027d520, 2}, { 0x0027d640, 25}, { 0x0027d6c8, 7}, { 0x0027d6ec, 1}, - { 0x0027d6f8, 7}, + { 0x0027d6f8, 2}, + { 0x0027d704, 4}, { 0x0027d720, 2}, { 0x0027d840, 25}, { 0x0027d8c8, 7}, { 0x0027d8ec, 1}, - { 0x0027d8f8, 7}, + { 0x0027d8f8, 2}, + { 0x0027d904, 4}, { 0x0027d920, 2}, { 0x0027da40, 25}, { 0x0027dac8, 7}, { 0x0027daec, 1}, - { 0x0027daf8, 7}, + { 0x0027daf8, 2}, + { 0x0027db04, 4}, { 0x0027db20, 2}, { 0x0027dc40, 25}, { 0x0027dcc8, 7}, { 0x0027dcec, 1}, - { 0x0027dcf8, 7}, + { 0x0027dcf8, 2}, + { 0x0027dd04, 4}, { 0x0027dd20, 2}, { 0x0027de40, 25}, { 0x0027dec8, 7}, { 0x0027deec, 1}, - { 0x0027def8, 7}, + { 0x0027def8, 2}, + { 0x0027df04, 4}, { 0x0027df20, 2}, { 0x0027e040, 25}, { 0x0027e0c8, 7}, { 0x0027e0ec, 1}, - { 0x0027e0f8, 7}, + { 0x0027e0f8, 2}, + { 0x0027e104, 4}, { 0x0027e120, 2}, { 0x0027e240, 25}, { 0x0027e2c8, 7}, { 0x0027e2ec, 1}, - { 0x0027e2f8, 7}, + { 0x0027e2f8, 2}, + { 0x0027e304, 4}, { 0x0027e320, 2}, { 0x0027e440, 25}, { 0x0027e4c8, 7}, { 0x0027e4ec, 1}, - { 0x0027e4f8, 7}, + { 0x0027e4f8, 2}, + { 0x0027e504, 4}, { 0x0027e520, 2}, { 0x0027e640, 25}, { 0x0027e6c8, 7}, { 0x0027e6ec, 1}, - { 0x0027e6f8, 7}, + { 0x0027e6f8, 2}, + { 0x0027e704, 4}, { 0x0027e720, 2}, { 0x0027e840, 25}, { 0x0027e8c8, 7}, { 0x0027e8ec, 1}, - { 0x0027e8f8, 7}, + { 0x0027e8f8, 2}, + { 0x0027e904, 4}, { 0x0027e920, 2}, { 0x0027ea40, 25}, { 0x0027eac8, 7}, { 0x0027eaec, 1}, - { 0x0027eaf8, 7}, + { 0x0027eaf8, 2}, + { 0x0027eb04, 4}, { 0x0027eb20, 2}, { 0x0027ec40, 25}, { 0x0027ecc8, 7}, { 0x0027ecec, 1}, - { 0x0027ecf8, 7}, + { 0x0027ecf8, 2}, + { 0x0027ed04, 4}, { 0x0027ed20, 2}, { 0x0027ee40, 25}, { 0x0027eec8, 7}, { 0x0027eeec, 1}, - { 0x0027eef8, 7}, + { 0x0027eef8, 2}, + { 0x0027ef04, 4}, { 0x0027ef20, 2}, { 0x0027f040, 25}, { 0x0027f0c8, 7}, { 0x0027f0ec, 1}, - { 0x0027f0f8, 7}, + { 0x0027f0f8, 2}, + { 0x0027f104, 4}, { 0x0027f120, 2}, { 0x0027f240, 25}, { 0x0027f2c8, 7}, { 0x0027f2ec, 1}, - { 0x0027f2f8, 7}, + { 0x0027f2f8, 2}, + { 0x0027f304, 4}, { 0x0027f320, 2}, { 0x0027f440, 25}, { 0x0027f4c8, 7}, { 0x0027f4ec, 1}, - { 0x0027f4f8, 7}, + { 0x0027f4f8, 2}, + { 0x0027f504, 4}, { 0x0027f520, 2}, { 0x0027f640, 25}, { 0x0027f6c8, 7}, { 0x0027f6ec, 1}, - { 0x0027f6f8, 7}, + { 0x0027f6f8, 2}, + { 0x0027f704, 4}, { 0x0027f720, 2}, { 0x0027f840, 25}, { 0x0027f8c8, 7}, { 0x0027f8ec, 1}, - { 0x0027f8f8, 7}, + { 0x0027f8f8, 2}, + { 0x0027f904, 4}, { 0x0027f920, 2}, { 0x0027fa40, 25}, { 0x0027fac8, 7}, { 0x0027faec, 1}, - { 0x0027faf8, 7}, + { 0x0027faf8, 2}, + { 0x0027fb04, 4}, { 0x0027fb20, 2}, { 0x0027fc40, 25}, { 0x0027fcc8, 7}, { 0x0027fcec, 1}, - { 0x0027fcf8, 7}, + { 0x0027fcf8, 2}, + { 0x0027fd04, 4}, { 0x0027fd20, 2}, { 0x0027fe40, 25}, { 0x0027fec8, 7}, { 0x0027feec, 1}, - { 0x0027fef8, 7}, + { 0x0027fef8, 2}, + { 0x0027ff04, 4}, { 0x0027ff20, 2}, { 0x00400500, 1}, { 0x0040415c, 1}, -- cgit v1.2.2 From 1cbb5ea0235f15180b1d4299499cab85db23c5ce Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 13 Oct 2017 17:15:46 -0700 Subject: gpu: nvgpu: init_cyclestats fixes - in the native case, replace calls for init_cyclestats with the gm20b version, as each chip had identical versions of the code. - in the virtual case, use the vgpu version of the function in order to get the new max_css_buffer_size characteristic set to the mempool size. JIRA ESRM-54 Bug 200296210 Change-Id: I475876cb392978fb1350ede58e37d0962ae095c3 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1578934 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 +- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 13 ------------- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- 5 files changed, 3 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 1ae424df..e8be1a43 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -316,7 +316,7 @@ static const struct gpu_ops gv100_ops = { .get_max_fbps_count = gr_gm20b_get_max_fbps_count, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .wait_empty = gr_gv11b_wait_empty, - .init_cyclestats = gr_gv11b_init_cyclestats, + .init_cyclestats = gr_gm20b_init_cyclestats, .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, .bpt_reg_info = gv11b_gr_bpt_reg_info, diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index fc894908..59a04d2c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1684,19 +1684,6 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch); } - -void gr_gv11b_init_cyclestats(struct gk20a *g) -{ -#if defined(CONFIG_GK20A_CYCLE_STATS) - g->gpu_characteristics.flags |= - NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS; - g->gpu_characteristics.flags |= - NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT; -#else - (void)g; -#endif -} - void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) { #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index e469d142..71975e24 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -124,7 +124,6 @@ int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, bool patch); -void gr_gv11b_init_cyclestats(struct gk20a *g); void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); void gr_gv11b_get_access_map(struct gk20a *g, u32 **whitelist, int *num_entries); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 8e4cdab8..400c2ad0 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -280,7 +280,7 @@ static const struct gpu_ops gv11b_ops = { .get_max_fbps_count = gr_gm20b_get_max_fbps_count, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .wait_empty = gr_gv11b_wait_empty, - .init_cyclestats = gr_gv11b_init_cyclestats, + .init_cyclestats = gr_gm20b_init_cyclestats, .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, .bpt_reg_info = gv11b_gr_bpt_reg_info, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 7f6df820..80d0ae54 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -162,7 +162,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_max_fbps_count = vgpu_gr_get_max_fbps_count, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .wait_empty = gr_gv11b_wait_empty, - .init_cyclestats = gr_gv11b_init_cyclestats, + .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, .bpt_reg_info = gv11b_gr_bpt_reg_info, -- cgit v1.2.2 From 33c707d60b116845c953b91c2693a82a4d1eb968 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 25 Oct 2017 14:33:05 -0700 Subject: gpu: nvgpu: Linux specific sm_error_state_record Create an nvgpu internal nvgpu_gr_sm_error_state to store and propagate SM error state within driver. Use nvgpu_dbg_gpu_sm_error_state_record only in Linux code. JIRA NVGPU-259 Change-Id: Ia2b347d0054365bdc790b4d6f2653a568935bdb0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1585646 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 59a04d2c..2f33301d 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2516,7 +2516,7 @@ void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state) int gv11b_gr_update_sm_error_state(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id, - struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state) + struct nvgpu_gr_sm_error_state *sm_error_state) { u32 gpc, tpc, sm, offset; struct gr_gk20a *gr = &g->gr; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 71975e24..feebef44 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -45,6 +45,7 @@ struct zbc_entry; struct zbc_query_params; struct channel_ctx_gk20a; struct nvgpu_warpstate; +struct nvgpu_gr_sm_error_state; enum { VOLTA_CHANNEL_GPFIFO_A = 0xC36F, @@ -158,7 +159,7 @@ int gv11b_gr_sm_trigger_suspend(struct gk20a *g); void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); int gv11b_gr_update_sm_error_state(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id, - struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state); + struct nvgpu_gr_sm_error_state *sm_error_state); int gv11b_gr_set_sm_debug_mode(struct gk20a *g, struct channel_gk20a *ch, u64 sms, bool enable); int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc); -- cgit v1.2.2 From 938785f1525ce0ae654c2be0911e15816617995d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 23 Oct 2017 08:45:13 -0700 Subject: gpu: nvgpu: Linux specific GPU characteristics flags Make GPU characteristics flags specific to Linux code only. The rest of driver is moved to using nvgpu_is_enabled() API. JIRA NVGPU-259 Change-Id: I46a5a90bb34f170e9e755e7683be142ed6b18cce Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1583992 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c | 31 ++++++++++++++++++++++++ drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h | 23 ++++++++++++++++++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 6 ++--- drivers/gpu/nvgpu/gv11b/gv11b.c | 8 +++--- drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h | 29 ++++++++++++++++++++++ 6 files changed, 91 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c create mode 100644 drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 0909a010..2edfa1bb 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -3,6 +3,7 @@ nvgpu-t19x := ../../../../nvgpu-t19x/drivers/gpu/nvgpu nvgpu-y += \ $(nvgpu-t19x)/common/mm/gmmu_t19x.o \ $(nvgpu-t19x)/common/linux/ioctl_tsg_t19x.o \ + $(nvgpu-t19x)/common/linux/ioctl_ctrl_t19x.o \ $(nvgpu-t19x)/common/linux/io_t19x.o \ $(nvgpu-t19x)/common/linux/module_t19x.o \ $(nvgpu-t19x)/common/linux/pci_t19x.o \ diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c new file mode 100644 index 00000000..56756ac9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include + +#include "ioctl_ctrl_t19x.h" +#include "common/linux/os_linux.h" +#include "gk20a/gk20a.h" + +u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(struct gk20a *g) +{ + u64 ioctl_flags = 0; + + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS)) + ioctl_flags |= NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; + + return ioctl_flags; +} + diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h new file mode 100644 index 00000000..64141223 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_IOCTL_CTRL_T19X +#define _NVGPU_IOCTL_CTRL_T19X + +#include + +struct gk20a; + +u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index e8be1a43..e51b4446 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -107,6 +107,7 @@ #include #include #include +#include #include #include @@ -221,16 +222,13 @@ static int gv100_get_litter_value(struct gk20a *g, int value) int gv100_init_gpu_characteristics(struct gk20a *g) { - struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; - int err; err = gk20a_init_gpu_characteristics(g); if (err) return err; - gpu->flags |= - NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; + __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); return 0; } diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index c8691ad5..211755e5 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c @@ -22,6 +22,9 @@ * DEALINGS IN THE SOFTWARE. */ +#include +#include + #include "gk20a/gk20a.h" #include "gv11b/gv11b.h" @@ -29,8 +32,7 @@ int gv11b_init_gpu_characteristics(struct gk20a *g) { gk20a_init_gpu_characteristics(g); - g->gpu_characteristics.flags |= - NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS | - NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE; + __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); + __nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true); return 0; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h new file mode 100644 index 00000000..9ef1dc30 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NVGPU_ENABLED_T19X_H__ +#define __NVGPU_ENABLED_T19X_H__ + +/* subcontexts are available */ +#define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63 + +#endif -- cgit v1.2.2 From 20294264468eecc8c1a065aa83d5f1b46ff07e7e Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 23 Oct 2017 14:01:28 -0700 Subject: gpu: nvgpu: gv1xx: resize patch buffer Follow the sizing consideration in bug 1753763 to support dynamic TPC modes and subcontexts. bug 200350539 Change-Id: Ibbdbf02f9c2ea3f082c1b2810ae7176b0775d461 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1584034 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_gv100.c | 53 +++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/gr_gv100.h | 2 +- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 4 files changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 8a4b88b4..430c7cd0 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -294,3 +294,56 @@ void gr_gv100_load_tpc_mask(struct gk20a *g) gk20a_writel(g, gr_fe_tpc_fs_r(0), u64_lo32(pes_tpc_mask)); gk20a_writel(g, gr_fe_tpc_fs_r(1), u64_hi32(pes_tpc_mask)); } + +u32 gr_gv100_get_patch_slots(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + struct fifo_gk20a *f = &g->fifo; + u32 size = 0; + + /* + * CMD to update PE table + */ + size++; + + /* + * Update PE table contents + * for PE table, each patch buffer update writes 32 TPCs + */ + size += DIV_ROUND_UP(gr->tpc_count, 32); + + /* + * Update the PL table contents + * For PL table, each patch buffer update configures 4 TPCs + */ + size += DIV_ROUND_UP(gr->tpc_count, 4); + + /* + * We need this for all subcontexts + */ + size *= f->t19x.max_subctx_count; + + /* + * Add space for a partition mode change as well + * reserve two slots since DYNAMIC -> STATIC requires + * DYNAMIC -> NONE -> STATIC + */ + size += 2; + + /* + * Add current patch buffer size + */ + size += gr_gk20a_get_patch_slots(g); + + /* + * Align to 4K size + */ + size = ALIGN(size, PATCH_CTX_SLOTS_PER_PAGE); + + /* + * Increase the size to accommodate for additional TPC partition update + */ + size += 2 * PATCH_CTX_SLOTS_PER_PAGE; + + return size; +} diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h index 460b05ae..612f76f9 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h @@ -32,5 +32,5 @@ void gr_gv100_init_sm_id_table(struct gk20a *g); void gr_gv100_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); int gr_gv100_load_smid_config(struct gk20a *g); - +u32 gr_gv100_get_patch_slots(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index e51b4446..61e9e46d 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -261,6 +261,7 @@ static const struct gpu_ops gv100_ops = { .get_num_pce = gv11b_ce_get_num_pce, }, .gr = { + .get_patch_slots = gr_gv100_get_patch_slots, .init_gpc_mmu = gr_gv11b_init_gpc_mmu, .bundle_cb_defaults = gr_gv100_bundle_cb_defaults, .cb_size_default = gr_gv100_cb_size_default, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 400c2ad0..4de9786b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -227,6 +227,7 @@ static const struct gpu_ops gv11b_ops = { .get_num_pce = gv11b_ce_get_num_pce, }, .gr = { + .get_patch_slots = gr_gv100_get_patch_slots, .init_gpc_mmu = gr_gv11b_init_gpc_mmu, .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, .cb_size_default = gr_gv11b_cb_size_default, -- cgit v1.2.2 From 60f12fb2f7293bdf4142cece75f3bd9faf674aa3 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 25 Oct 2017 09:23:07 -0700 Subject: gpu: nvgpu: fix implicit declaration of nvgpu_inst_block_addr t19x changes necessary for change in core MM code. JIRA NVGPU-30 Change-Id: Id0d66543582abcef522e3182da0b01d0042f4b14 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1585476 Reviewed-by: svc-mobile-coverity Reviewed-by: Konsta Holtta Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c index bf3383fd..2eb45a88 100644 --- a/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/css_gr_gv11b.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/css_gr_gk20a.h" -- cgit v1.2.2 From 17609ab57ffca27efde17733505c1adaf57168b9 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 29 Sep 2017 14:07:22 -0600 Subject: nvgpu-t19x: use kernel overlay features Update all Kconfig files and Makefiles to rely on the kernel overlay feature. In particular, don't include any Kconfig files or Makefiles from other overlays. -I directives in CFLAGS are not yet cleaned up. Bug 1978395 Change-Id: I16386f7f1e76bd68b55f3128b25eada029ae82c1 Signed-off-by: Stephen Warren Reviewed-on: https://git-master.nvidia.com/r/1571165 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 82 +++++++++++++++++++++++----------------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 2edfa1bb..6344f7a9 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -1,45 +1,45 @@ -nvgpu-t19x := ../../../../nvgpu-t19x/drivers/gpu/nvgpu - +ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) nvgpu-y += \ - $(nvgpu-t19x)/common/mm/gmmu_t19x.o \ - $(nvgpu-t19x)/common/linux/ioctl_tsg_t19x.o \ - $(nvgpu-t19x)/common/linux/ioctl_ctrl_t19x.o \ - $(nvgpu-t19x)/common/linux/io_t19x.o \ - $(nvgpu-t19x)/common/linux/module_t19x.o \ - $(nvgpu-t19x)/common/linux/pci_t19x.o \ - $(nvgpu-t19x)/gv11b/gv11b.o \ - $(nvgpu-t19x)/gv11b/css_gr_gv11b.o \ - $(nvgpu-t19x)/gv11b/dbg_gpu_gv11b.o \ - $(nvgpu-t19x)/gv11b/mc_gv11b.o \ - $(nvgpu-t19x)/gv11b/ltc_gv11b.o \ - $(nvgpu-t19x)/gv11b/hal_gv11b.o \ - $(nvgpu-t19x)/gv11b/gv11b_gating_reglist.o \ - $(nvgpu-t19x)/gv11b/gr_gv11b.o \ - $(nvgpu-t19x)/gv11b/fb_gv11b.o \ - $(nvgpu-t19x)/gv11b/fifo_gv11b.o \ - $(nvgpu-t19x)/gv11b/mm_gv11b.o \ - $(nvgpu-t19x)/gv11b/ce_gv11b.o \ - $(nvgpu-t19x)/gv11b/gr_ctx_gv11b.o \ - $(nvgpu-t19x)/gv11b/pmu_gv11b.o \ - $(nvgpu-t19x)/gv11b/acr_gv11b.o \ - $(nvgpu-t19x)/gv11b/subctx_gv11b.o \ - $(nvgpu-t19x)/gv11b/regops_gv11b.o \ - $(nvgpu-t19x)/gv11b/therm_gv11b.o \ - $(nvgpu-t19x)/gv100/mm_gv100.o \ - $(nvgpu-t19x)/gv100/gr_ctx_gv100.o \ - $(nvgpu-t19x)/gv100/fb_gv100.o \ - $(nvgpu-t19x)/gv100/bios_gv100.o \ - $(nvgpu-t19x)/gv100/fifo_gv100.o \ - $(nvgpu-t19x)/gv100/gr_gv100.o \ - $(nvgpu-t19x)/gv100/regops_gv100.o \ - $(nvgpu-t19x)/gv100/hal_gv100.o + common/mm/gmmu_t19x.o \ + common/linux/ioctl_tsg_t19x.o \ + common/linux/ioctl_ctrl_t19x.o \ + common/linux/io_t19x.o \ + common/linux/module_t19x.o \ + common/linux/pci_t19x.o \ + gv11b/gv11b.o \ + gv11b/css_gr_gv11b.o \ + gv11b/dbg_gpu_gv11b.o \ + gv11b/mc_gv11b.o \ + gv11b/ltc_gv11b.o \ + gv11b/hal_gv11b.o \ + gv11b/gv11b_gating_reglist.o \ + gv11b/gr_gv11b.o \ + gv11b/fb_gv11b.o \ + gv11b/fifo_gv11b.o \ + gv11b/mm_gv11b.o \ + gv11b/ce_gv11b.o \ + gv11b/gr_ctx_gv11b.o \ + gv11b/pmu_gv11b.o \ + gv11b/acr_gv11b.o \ + gv11b/subctx_gv11b.o \ + gv11b/regops_gv11b.o \ + gv11b/therm_gv11b.o \ + gv100/mm_gv100.o \ + gv100/gr_ctx_gv100.o \ + gv100/fb_gv100.o \ + gv100/bios_gv100.o \ + gv100/fifo_gv100.o \ + gv100/gr_gv100.o \ + gv100/regops_gv100.o \ + gv100/hal_gv100.o -nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o -nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += $(nvgpu-t19x)/common/linux/nvhost_t19x.o +nvgpu-$(CONFIG_TEGRA_GK20A) += gv11b/platform_gv11b_tegra.o +nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += common/linux/nvhost_t19x.o nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ - $(nvgpu-t19x)/vgpu/gv11b/platform_gv11b_vgpu_tegra.o \ - $(nvgpu-t19x)/vgpu/gv11b/vgpu_hal_gv11b.o \ - $(nvgpu-t19x)/vgpu/gv11b/vgpu_gr_gv11b.o \ - $(nvgpu-t19x)/vgpu/gv11b/vgpu_fifo_gv11b.o \ - $(nvgpu-t19x)/vgpu/gv11b/vgpu_subctx_gv11b.o + vgpu/gv11b/platform_gv11b_vgpu_tegra.o \ + vgpu/gv11b/vgpu_hal_gv11b.o \ + vgpu/gv11b/vgpu_gr_gv11b.o \ + vgpu/gv11b/vgpu_fifo_gv11b.o \ + vgpu/gv11b/vgpu_subctx_gv11b.o +endif -- cgit v1.2.2 From f7d8d133bf1b58722ede620fb43fab2053f5e714 Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Wed, 25 Oct 2017 18:20:25 -0700 Subject: gpu: nvgpu: vgpu: unset verify status ctx reload Native code for verifying tsg status on ctx reload is not possible on vgpu. Unset gops->fifo.tsg_verify_status_faulted operation for vgpu for now. This needs to be implemented separately for vgpu later. Bug 200348087 Change-Id:Ib427f66e0897e37c34b882ead95ca8b84d595d72 Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1585784 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 80d0ae54..dd4dfdae 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -342,7 +342,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .enable_tsg = gk20a_enable_tsg, .disable_tsg = gk20a_disable_tsg, .tsg_verify_channel_status = NULL, - .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, + .tsg_verify_status_ctx_reload = NULL, /* TODO: implement it for CE fault */ .tsg_verify_status_faulted = NULL, .update_runlist = vgpu_fifo_update_runlist, -- cgit v1.2.2 From afd1649cfcae97e873663586d55f9a4cfd671808 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 26 Oct 2017 15:20:39 -0700 Subject: gpu: nvgpu: Move ctxsw_trace_gk20a.c to common/linux Fixups for the change of name subject in nvgpu. JIRA NVGPU-287 Change-Id: I6c19733079061a42786b94fc48db374d715ccbef Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1586548 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++ drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 ++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 61e9e46d..0950409f 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -709,7 +709,9 @@ int gv100_init_hal(struct gk20a *g) gops->fifo = gv100_ops.fifo; gops->gr_ctx = gv100_ops.gr_ctx; gops->mm = gv100_ops.mm; +#ifdef CONFIG_GK20A_CTXSW_TRACE gops->fecs_trace = gv100_ops.fecs_trace; +#endif gops->pramin = gv100_ops.pramin; gops->therm = gv100_ops.therm; gops->pmu = gv100_ops.pmu; diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index dc3b641a..d74ddacd 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1075,10 +1075,12 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, } } +#ifdef CONFIG_GK20A_CTXSW_TRACE if (refch) gk20a_ctxsw_trace_channel_reset(g, refch); else if (tsg) gk20a_ctxsw_trace_tsg_reset(g, tsg); +#endif gk20a_fifo_set_runlist_state(g, runlists_mask, RUNLIST_ENABLED, !RUNLIST_INFO_MUTEX_LOCKED); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4de9786b..39f9572c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -687,7 +687,9 @@ int gv11b_init_hal(struct gk20a *g) gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; gops->mm = gv11b_ops.mm; +#ifdef CONFIG_GK20A_CTXSW_TRACE gops->fecs_trace = gv11b_ops.fecs_trace; +#endif gops->therm = gv11b_ops.therm; gops->pmu = gv11b_ops.pmu; gops->regops = gv11b_ops.regops; -- cgit v1.2.2 From cfba56d20e27cdc591f8a89236dd1423b12754d3 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 27 Oct 2017 15:48:05 -0700 Subject: gpu: nvpgu: Define GPUIDs without referring to UAPI Define GPUIDs without referring to constants defined in . JIRA NVGPU-259 Change-Id: I719ed5dd7e03c98f556d7932df132d9a39f25a9d Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1587282 Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h index 58f4fad1..8689a535 100644 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h +++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h @@ -24,11 +24,8 @@ #ifndef _NVGPU_GPUID_T19X_H_ #define _NVGPU_GPUID_T19X_H_ -#define NVGPU_GPUID_GV11B \ - GK20A_GPUID(NVGPU_GPU_ARCH_GV110, NVGPU_GPU_IMPL_GV11B) -#define NVGPU_GPUID_GV100 \ - GK20A_GPUID(NVGPU_GPU_ARCH_GV100, NVGPU_GPU_IMPL_GV100) - +#define NVGPU_GPUID_GV11B 0x0000015B +#define NVGPU_GPUID_GV100 0x00000140 #define NVGPU_COMPAT_TEGRA_GV11B "nvidia,gv11b" #define NVGPU_COMPAT_GENERIC_GV11B "nvidia,generic-gv11b" -- cgit v1.2.2 From d69e51813a57dfae204daf87767652685117daf1 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 21 Sep 2017 16:24:04 -0700 Subject: gpu: nvgpu: gv11b: fix faulted channel's id/type Teardown function should be passed appropriate id and id_type. E.g. if a channel is marked as tsg, channel teardown/rc function should be passed it's tsgid as id and type_tsg as id_type Bug 200277163 Change-Id: I2e83561c03d515fac28cbb8ce75a9f2c7bf746ac Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1557296 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 9301ebc6..75045800 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -1376,6 +1376,7 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, unsigned int id_type; u32 num_lce, act_eng_bitmask = 0; int err = 0; + u32 id = ((u32)~0); if (!mmfault->valid) return; @@ -1417,10 +1418,13 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, nvgpu_log(g, gpu_dbg_intr, "UNBOUND INST BLOCK MMU FAULT"); } else if (mmfault->refch) { - if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) + if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) { + id = mmfault->refch->tsgid; id_type = ID_TYPE_TSG; - else + } else { + id = mmfault->chid; id_type = ID_TYPE_CHANNEL; + } } else { id_type = ID_TYPE_UNKNOWN; } @@ -1428,7 +1432,7 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, act_eng_bitmask = BIT(mmfault->faulted_engine); g->ops.fifo.teardown_ch_tsg(g, act_eng_bitmask, - mmfault->chid, id_type, RC_TYPE_MMU_FAULT, mmfault); + id, id_type, RC_TYPE_MMU_FAULT, mmfault); } else { err = gv11b_fb_fix_page_fault(g, mmfault); if (err) { -- cgit v1.2.2 From 4f24e212cbd66a58cbae9fdf810694d01f57ee5f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 22 Sep 2017 11:10:11 -0700 Subject: gpu: nvgpu: gv11b: replay invalid pte faults only Try to fix invalid pte type repalayable faults only. All other replayable faults will be cancelled so that next mmu fault for same fault address will be triggered as non-replayable fault and ch/tsg teardown will take place. Bug 1958308 Change-Id: I63b90ce7c639ee183f87db3e771f253fd04c3567 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1566576 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 27 ++++++++++++++++++---- .../nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h | 4 ++++ 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 75045800..d89018e5 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -1434,13 +1434,19 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, g->ops.fifo.teardown_ch_tsg(g, act_eng_bitmask, id, id_type, RC_TYPE_MMU_FAULT, mmfault); } else { - err = gv11b_fb_fix_page_fault(g, mmfault); - if (err) { - *invalidate_replay_val |= - fb_mmu_invalidate_replay_cancel_global_f(); + if (mmfault->fault_type == gmmu_fault_type_pte_v()) { + nvgpu_log(g, gpu_dbg_intr, "invalid pte! try to fix"); + err = gv11b_fb_fix_page_fault(g, mmfault); + if (err) + *invalidate_replay_val |= + fb_mmu_invalidate_replay_cancel_global_f(); + else + *invalidate_replay_val |= + fb_mmu_invalidate_replay_start_ack_all_f(); } else { + /* cancel faults other than invalid pte */ *invalidate_replay_val |= - fb_mmu_invalidate_replay_start_ack_all_f(); + fb_mmu_invalidate_replay_cancel_global_f(); } /* refch in mmfault is assigned at the time of copying * fault info from snap reg or bar2 fault buf @@ -1960,6 +1966,17 @@ static int gv11b_fb_fix_page_fault(struct gk20a *g, nvgpu_log(g, gpu_dbg_intr | gpu_dbg_pte, "pte: %#08x %#08x", pte[1], pte[0]); + if (pte[0] == 0x0 && pte[1] == 0x0) { + nvgpu_log(g, gpu_dbg_intr | gpu_dbg_pte, + "pte all zeros, do not set valid"); + return -1; + } + if (pte[0] & gmmu_new_pte_valid_true_f()) { + nvgpu_log(g, gpu_dbg_intr | gpu_dbg_pte, + "pte valid already set"); + return -1; + } + pte[0] |= gmmu_new_pte_valid_true_f(); if (pte[0] & gmmu_new_pte_read_only_true_f()) pte[0] &= ~(gmmu_new_pte_read_only_true_f()); diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h index c39cc2d8..0a442b1f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h @@ -1272,6 +1272,10 @@ static inline u32 gmmu_fault_type_unbound_inst_block_v(void) { return 0x00000004U; } +static inline u32 gmmu_fault_type_pte_v(void) +{ + return 0x00000002U; +} static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) { return 0x00000005U; -- cgit v1.2.2 From d393d3294ff8f1771484435d4edbb61df1e4f433 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 30 Oct 2017 13:37:27 +0530 Subject: gpu: nvgpu: use nvgpu_* APIs to allocate/free memory Use nvgpu specific nvgpu_kcalloc()/nvgpu_kfree() calls instead of linux specific kcalloc()/kfree() Jira NVGPU-259 Change-Id: I73034ea23561d1269230b9ac10360f8b171b8d41 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1588221 Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 2f33301d..568673aa 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2138,7 +2138,7 @@ int gr_gv11b_load_smid_config(struct gk20a *g) u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); int num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); - tpc_sm_id = kcalloc(gr_cwd_sm_id__size_1_v(), sizeof(u32), GFP_KERNEL); + tpc_sm_id = nvgpu_kcalloc(g, gr_cwd_sm_id__size_1_v(), sizeof(u32)); if (!tpc_sm_id) return -ENOMEM; @@ -2173,7 +2173,7 @@ int gr_gv11b_load_smid_config(struct gk20a *g) for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++) gk20a_writel(g, gr_cwd_sm_id_r(i), tpc_sm_id[i]); - kfree(tpc_sm_id); + nvgpu_kfree(g, tpc_sm_id); return 0; } -- cgit v1.2.2 From 39cc741a02067e00f0003649dcd45285eb4640a5 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sun, 29 Oct 2017 20:17:50 -0700 Subject: gpu: nvgpu: Add GPU arch and impl to common structure Add GPU architecture and implementation to a new struct nvgpu_gpu_params which is defined in common header file gk20a/gk20.h. JIRA NVGPU-259 Change-Id: Idde2caded75fcb1e03e95be11f6aa2ec33a0962b Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1588033 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c index 9f13abce..8b50125e 100644 --- a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c @@ -27,7 +27,7 @@ int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name) { - u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; + u32 ver = g->params.gpu_arch + g->params.gpu_impl; switch (ver) { case NVGPU_GPUID_GV100: -- cgit v1.2.2 From f913b7a4f9e70df8a76e7b934825ef1d9632f3a1 Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Mon, 30 Oct 2017 16:13:05 -0700 Subject: gpu: nvgpu: vgpu: modify tsg enable sequence TSG enable sequence in native has been modified due to a hardware bug requiring enabling all channels with NEXT and CTX_RELOAD set in a TSG, and then enabling rest of channels.However it is not possible to check if NEXT and CTX_RELOAD is set in vgpu. Have a separate implementation for enabling tsg sequence in vgpu till the fix for hardware bug is implemented for virtualized configuration. Bug 200348087 Change-Id: I8e6c2ba8722531563de65e51e3d6af6acb7af213 Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1588739 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao Reviewed-by: Alex Waterman Reviewed-by: Konsta Holtta Reviewed-by: Deepak Nibade GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index dd4dfdae..e7996ce7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -339,7 +339,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, .preempt_channel = vgpu_fifo_preempt_channel, .preempt_tsg = vgpu_fifo_preempt_tsg, - .enable_tsg = gk20a_enable_tsg, + .enable_tsg = vgpu_enable_tsg, .disable_tsg = gk20a_disable_tsg, .tsg_verify_channel_status = NULL, .tsg_verify_status_ctx_reload = NULL, -- cgit v1.2.2 From f472922b3582dbba78b633958a4cb7b65ddb3f03 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 31 Oct 2017 12:23:30 -0700 Subject: gpu: nvgpu: Split ctxsw_trace API into non-Linux component T19x component for similar change in the main nvgpu code. JIRA NVGPU-287 Change-Id: Ib126b3d1fb562850fbb3ab89103f2a7fdaa13306 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1589430 Reviewed-by: Terje Bergstrom Reviewed-by: svc-mobile-coverity Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 +- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 0950409f..30b8e2c3 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -30,7 +30,6 @@ #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" -#include "gk20a/ctxsw_trace_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" @@ -108,6 +107,7 @@ #include #include #include +#include #include #include diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index d74ddacd..4c3b1186 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -35,10 +35,10 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" -#include "gk20a/ctxsw_trace_gk20a.h" #include "gk20a/channel_gk20a.h" #include "gp10b/fifo_gp10b.h" diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 39f9572c..faa67f02 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -30,7 +30,6 @@ #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" -#include "gk20a/ctxsw_trace_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" @@ -90,6 +89,7 @@ #include #include #include +#include #include #include -- cgit v1.2.2 From 730ba218c1a57486f05e02cfaddf6a75e95ff498 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Fri, 27 Oct 2017 14:51:17 +0530 Subject: gpu: nvgpu: gv11b: Kernel iface for Dynamic TPC-PG This patch adds kernel interface for dynamic TPC-PG feature. User-space needs to send TPC-PG args to kernel via ioctl. Dynamic TPC-PG feature will allow every context to specify the number of TPC's it will use to run its workload. This way, graphics driver can power off non-required TPC's if a particular context has light to medium workload. JIRA GPUT19x-16 Change-Id: Id4846245a6414b719599d04784cbe2ca5282f4ad Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1575848 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c | 17 +++++++++++++++++ drivers/gpu/nvgpu/tsg_t19x.h | 12 +++++++++--- include/uapi/linux/nvgpu-t19x.h | 5 +++-- 3 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c index 797115ac..ec7501ce 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c @@ -28,6 +28,7 @@ static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g, struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); struct gk20a_sched_ctrl *sched = &l->sched_ctrl; struct channel_gk20a *ch; + struct gr_gk20a *gr = &g->gr; int err = 0; nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); @@ -48,6 +49,22 @@ static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g, err = -EINVAL; goto idle; } + + if (arg->tpc_pg_enabled && (!tsg->t19x.tpc_num_initialized)) { + if ((arg->num_active_tpcs > gr->max_tpc_count) || + !(arg->num_active_tpcs)) { + nvgpu_err(g, "Invalid num of active TPCs"); + err = -EINVAL; + goto ch_put; + } + tsg->t19x.tpc_num_initialized = true; + tsg->t19x.num_active_tpcs = arg->num_active_tpcs; + tsg->t19x.tpc_pg_enabled = true; + } else { + tsg->t19x.tpc_pg_enabled = false; + nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled"); + } + if (arg->subcontext_id < g->fifo.t19x.max_subctx_count) { ch->t19x.subctx_id = arg->subcontext_id; } else { diff --git a/drivers/gpu/nvgpu/tsg_t19x.h b/drivers/gpu/nvgpu/tsg_t19x.h index 18c00821..d1f47cc3 100644 --- a/drivers/gpu/nvgpu/tsg_t19x.h +++ b/drivers/gpu/nvgpu/tsg_t19x.h @@ -22,9 +22,15 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _NVGPU_TSG_T19X_H_ -#define _NVGPU_TSG_T19X_H_ +#ifndef __NVGPU_TSG_T19X_H__ +#define __NVGPU_TSG_T19X_H__ -#include "common/linux/ioctl_tsg_t19x.h" +#include + +struct tsg_t19x { + u32 num_active_tpcs; + u8 tpc_pg_enabled; + bool tpc_num_initialized; +}; #endif diff --git a/include/uapi/linux/nvgpu-t19x.h b/include/uapi/linux/nvgpu-t19x.h index f56bc9d7..27db97c0 100644 --- a/include/uapi/linux/nvgpu-t19x.h +++ b/include/uapi/linux/nvgpu-t19x.h @@ -44,8 +44,9 @@ struct nvgpu_tsg_bind_channel_ex_args { /* in: VEID in Volta */ __u32 subcontext_id; - - __u64 reserved[2]; + __u32 num_active_tpcs; + __u8 tpc_pg_enabled; + __u8 reserved[11]; }; #define NVGPU_TSG_IOCTL_BIND_CHANNEL_EX \ -- cgit v1.2.2 From e5c3b05bb2775236679b74194e4ac24612ef39b6 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 30 Oct 2017 19:28:43 +0530 Subject: gpu: nvgpu: use struct gk20a for create_gr_sysfs API gr_gv11b_create_sysfs() and GR HAL create_gr_sysfs() right now receive linux specific struct device But since this function is called from/declared in common code, we need to remove linux dependency from it Hence update the API and GR HAL to receive struct gk20a pointer instead of device pointer Jira NVGPU-259 Change-Id: I65d717ad9f263f0397f8efa5761c64e55c7846eb Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1588465 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 +- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index feebef44..98e7bc50 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -80,7 +80,7 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, /*zcull*/ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, u32 *zcull_map_tiles); -void gr_gv11b_create_sysfs(struct device *dev); +void gr_gv11b_create_sysfs(struct gk20a *g); bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num); bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num); diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index d2c690f4..5308f4ea 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -40,6 +40,7 @@ #include "gp10b/platform_gp10b.h" #include "common/linux/platform_gp10b_tegra.h" +#include "common/linux/os_linux.h" #include "common/linux/platform_gk20a_tegra.h" #include "gr_gv11b.h" #include "nvgpu_gpuid_t19x.h" @@ -188,9 +189,9 @@ static struct device_attribute *dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_ar static struct device_attribute *dev_attr_mmu_fillunit_ecc_corrected_err_count_array; static struct device_attribute *dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array; -void gr_gv11b_create_sysfs(struct device *dev) +void gr_gv11b_create_sysfs(struct gk20a *g) { - struct gk20a *g = get_gk20a(dev); + struct device *dev = dev_from_gk20a(g); int error = 0; /* This stat creation function is called on GR init. GR can get initialized multiple times but we only need to create the ECC @@ -199,7 +200,7 @@ void gr_gv11b_create_sysfs(struct device *dev) if (g->ecc.gr.t19x.sm_l1_tag_corrected_err_count.counters != NULL) return; - gr_gp10b_create_sysfs(dev); + gr_gp10b_create_sysfs(g); error |= gr_gp10b_ecc_stat_create(dev, 0, -- cgit v1.2.2 From d73e89f984f2f6f8da4e49a0ec3bea0bfc34cde2 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 31 Oct 2017 19:24:34 +0530 Subject: gpu: nvgpu: move platform_gk20a.h to linux Fix #includes in all the files to include platform_gk20a.h file with correct path NVGPU-316 Change-Id: Icb26d3c75076b8fdc8da992f751e1cfea22996be Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1589939 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 2 +- drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 5308f4ea..ca346d97 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -33,8 +33,8 @@ #include -#include "gk20a/platform_gk20a.h" #include "gk20a/gk20a.h" +#include "common/linux/platform_gk20a.h" #include "common/linux/clk.h" #include "gp10b/platform_gp10b.h" diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index d48d1308..fea473a7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -21,8 +21,8 @@ */ #include "gk20a/gk20a.h" -#include "gk20a/platform_gk20a.h" #include "vgpu/clk_vgpu.h" +#include "common/linux/platform_gk20a.h" #include "common/linux/os_linux.h" #include -- cgit v1.2.2 From bcd78a0be617be07234e3ef4925cecaef66f2fa4 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 31 Oct 2017 20:56:29 -0700 Subject: nvgpu: gv11b: implement railgate/unrailgate Implement gv11b platform specific rail gating functions by calling relevant powergate and unpowergate functions and linux clock frmework functions: gv11b_tegra_is_railgated gv11b_tegra_railgate gv11b_tegra_unrailgate These calls will take care of hot reset sequence required for gpu powergate and gpu unpowergate. Bug 200269361 Bug 200273571 Change-Id: Ib1825e4324d51fc508b3b5dc9e5e2fdb252eeff4 Signed-off-by: seshendra Gadagottu Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1589509 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 59 ++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index ca346d97..95d82254 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c @@ -28,11 +28,15 @@ #include #include #include +#include #include #include #include +#include +#include + #include "gk20a/gk20a.h" #include "common/linux/platform_gk20a.h" #include "common/linux/clk.h" @@ -103,18 +107,73 @@ static int gv11b_tegra_remove(struct device *dev) static bool gv11b_tegra_is_railgated(struct device *dev) { bool ret = false; +#ifdef TEGRA194_POWER_DOMAIN_GPU + struct gk20a *g = get_gk20a(dev); + + if (tegra_bpmp_running()) { + nvgpu_log(g, gpu_dbg_info, "bpmp running"); + ret = !tegra_powergate_is_powered(TEGRA194_POWER_DOMAIN_GPU); + nvgpu_log(g, gpu_dbg_info, "railgated? %s", ret ? "yes" : "no"); + } else { + nvgpu_log(g, gpu_dbg_info, "bpmp not running"); + } +#endif return ret; } static int gv11b_tegra_railgate(struct device *dev) { +#ifdef TEGRA194_POWER_DOMAIN_GPU + struct gk20a_platform *platform = gk20a_get_platform(dev); + struct gk20a *g = get_gk20a(dev); + int i; + + if (tegra_bpmp_running()) { + nvgpu_log(g, gpu_dbg_info, "bpmp running"); + if (!tegra_powergate_is_powered(TEGRA194_POWER_DOMAIN_GPU)) { + nvgpu_log(g, gpu_dbg_info, "powergate is not powered"); + return 0; + } + nvgpu_log(g, gpu_dbg_info, "clk_disable_unprepare"); + for (i = 0; i < platform->num_clks; i++) { + if (platform->clk[i]) + clk_disable_unprepare(platform->clk[i]); + } + nvgpu_log(g, gpu_dbg_info, "powergate_partition"); + tegra_powergate_partition(TEGRA194_POWER_DOMAIN_GPU); + } else { + nvgpu_log(g, gpu_dbg_info, "bpmp not running"); + } +#endif return 0; } static int gv11b_tegra_unrailgate(struct device *dev) { int ret = 0; +#ifdef TEGRA194_POWER_DOMAIN_GPU + struct gk20a_platform *platform = gk20a_get_platform(dev); + struct gk20a *g = get_gk20a(dev); + int i; + + if (tegra_bpmp_running()) { + nvgpu_log(g, gpu_dbg_info, "bpmp running"); + ret = tegra_unpowergate_partition(TEGRA194_POWER_DOMAIN_GPU); + if (ret) { + nvgpu_log(g, gpu_dbg_info, + "unpowergate partition failed"); + return ret; + } + nvgpu_log(g, gpu_dbg_info, "clk_prepare_enable"); + for (i = 0; i < platform->num_clks; i++) { + if (platform->clk[i]) + clk_prepare_enable(platform->clk[i]); + } + } else { + nvgpu_log(g, gpu_dbg_info, "bpmp not running"); + } +#endif return ret; } -- cgit v1.2.2 From 075852f042b9b3a3d48180378e6d2a709708cc41 Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Mon, 6 Nov 2017 13:44:44 +0200 Subject: gpu: nvgpu: Switch to newer NVGPU_AS_MAP_BUFFER flags Switch two cases using the old NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_* flags to the newer definitions, that is, NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE. The legacy NVGPU_MAP_BUFFER_FLAGS_* definitions have been deleted. Bug 1902982 Change-Id: Ifbd2678b10005b4af2375600888469b01dd09f4e Signed-off-by: Sami Kiminki Reviewed-on: https://git-master.nvidia.com/r/1592655 Reviewed-by: Alex Waterman Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 568673aa..22377522 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1349,7 +1349,7 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, mem->gpu_va = nvgpu_gmmu_map(vm, mem, size, - NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE, gk20a_mem_flag_none, false, mem->aperture); diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 4951d3a4..864e24f0 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -75,7 +75,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm, &ctx->mem, ctx->mem.size, - NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_FALSE, + 0, /* not GPU-cacheable */ gk20a_mem_flag_none, true, ctx->mem.aperture); if (!ctx->mem.gpu_va) { -- cgit v1.2.2 From 738bee03730a905d98361cd1260f9b79e3c12bf7 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Mon, 16 Oct 2017 08:58:59 -0700 Subject: gpu: nvgpu: vgpu: add vgpu_gv11b_tsg_bind_channel Add TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX command to pass subctx_id and runqueu_sel to RM server. Use this command in gv11b's implementation of gops->fifo.tsg_bind_channel. Jira EVLR-1751 Change-Id: I8ba69c95ea1c6bb7fa106588b6420ed543b2386b Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/1579840 Reviewed-by: svc-mobile-coverity Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 3 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 3 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c | 59 +++++++++++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h | 29 +++++++++++++ include/linux/tegra_vgpu_t19x.h | 9 ++++ 5 files changed, 101 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 6344f7a9..077dc4cf 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -41,5 +41,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ vgpu/gv11b/vgpu_hal_gv11b.o \ vgpu/gv11b/vgpu_gr_gv11b.o \ vgpu/gv11b/vgpu_fifo_gv11b.o \ - vgpu/gv11b/vgpu_subctx_gv11b.o + vgpu/gv11b/vgpu_subctx_gv11b.o \ + vgpu/gv11b/vgpu_tsg_gv11b.o endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index e7996ce7..56360af4 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -81,6 +81,7 @@ #include "vgpu_gr_gv11b.h" #include "vgpu_fifo_gv11b.h" #include "vgpu_subctx_gv11b.h" +#include "vgpu_tsg_gv11b.h" #include #include @@ -377,7 +378,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, .deinit_eng_method_buffers = gv11b_fifo_deinit_eng_method_buffers, - .tsg_bind_channel = vgpu_tsg_bind_channel, + .tsg_bind_channel = vgpu_gv11b_tsg_bind_channel, .tsg_unbind_channel = vgpu_tsg_unbind_channel, #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c new file mode 100644 index 00000000..7e70272a --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "vgpu_tsg_gv11b.h" + +int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg, + struct channel_gk20a *ch) +{ + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_tsg_bind_channel_ex_params *p = + &msg.params.t19x.tsg_bind_channel_ex; + int err; + + gk20a_dbg_fn(""); + + err = gk20a_tsg_bind_channel(tsg, ch); + if (err) + return err; + + msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX; + msg.handle = vgpu_get_handle(tsg->g); + p->tsg_id = tsg->tsgid; + p->ch_handle = ch->virt_ctx; + p->subctx_id = ch->t19x.subctx_id; + p->runqueue_sel = ch->t19x.runqueue_sel; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (err) { + nvgpu_err(tsg->g, + "vgpu_gv11b_tsg_bind_channel failed, ch %d tsgid %d", + ch->chid, tsg->tsgid); + gk20a_tsg_unbind_channel(ch); + } + + return err; +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h new file mode 100644 index 00000000..c7bb2f4e --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _VGPU_TSG_GV11B_H_ +#define _VGPU_TSG_GV11B_H_ + +int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg, + struct channel_gk20a *ch); + +#endif diff --git a/include/linux/tegra_vgpu_t19x.h b/include/linux/tegra_vgpu_t19x.h index fe39230e..38dbbf60 100644 --- a/include/linux/tegra_vgpu_t19x.h +++ b/include/linux/tegra_vgpu_t19x.h @@ -17,6 +17,7 @@ #define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100 #define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101 #define TEGRA_VGPU_CMD_MAP_SYNCPT 102 +#define TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX 103 struct tegra_vgpu_alloc_ctx_header_params { u64 ch_handle; @@ -35,10 +36,18 @@ struct tegra_vgpu_map_syncpt_params { u8 prot; }; +struct tegra_vgpu_tsg_bind_channel_ex_params { + u32 tsg_id; + u64 ch_handle; + u32 subctx_id; + u32 runqueue_sel; +}; + union tegra_vgpu_t19x_params { struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; struct tegra_vgpu_free_ctx_header_params free_ctx_header; struct tegra_vgpu_map_syncpt_params map_syncpt; + struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex; }; #define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100 -- cgit v1.2.2 From f7f325deb926e4b7253ff31389219c71b9f2148e Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Mon, 21 Aug 2017 15:38:23 -0700 Subject: gpu: nvgpu: vgpu: enable subctx for gv11b Add vgpu_gv11b_init_gpu_characteristics() and enable NVGPU_SUPPORT_TSG_SUBCONTEXTS Jira VFND-3797 Jira EVLR-1751 Change-Id: I288ac062e42ec399a302d693471b50b58c9a2653 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/1543015 Reviewed-by: Richard Zhao Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c | 40 +++++++++++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.h | 21 ++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 3 +- 4 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 077dc4cf..e8ef3688 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -38,6 +38,7 @@ nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += common/linux/nvhost_t19x.o nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ vgpu/gv11b/platform_gv11b_vgpu_tegra.o \ + vgpu/gv11b/vgpu_gv11b.o \ vgpu/gv11b/vgpu_hal_gv11b.o \ vgpu/gv11b/vgpu_gr_gv11b.o \ vgpu/gv11b/vgpu_fifo_gv11b.o \ diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c new file mode 100644 index 00000000..db3dfaf4 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" + +#include +#include + +#include "vgpu/vgpu.h" +#include "vgpu_gv11b.h" + +int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) +{ + int err; + + gk20a_dbg_fn(""); + + + nvgpu_err(g, "g->gpu_characteristics.flags=%llx", + g->gpu_characteristics.flags); + err = vgpu_init_gpu_characteristics(g); + if (err) { + nvgpu_err(g, "vgpu_init_gpu_characteristics failed, err %d\n", err); + return err; + } + + __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); + + return 0; +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.h new file mode 100644 index 00000000..9413904b --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _VGPU_GV11B_H_ +#define _VGPU_GV11B_H_ + +struct gk20a; + +int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 56360af4..5adb8ecd 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -78,6 +78,7 @@ #include +#include "vgpu_gv11b.h" #include "vgpu_gr_gv11b.h" #include "vgpu_fifo_gv11b.h" #include "vgpu_subctx_gv11b.h" @@ -551,7 +552,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .priv_ring = { .isr = gp10b_priv_ring_isr, }, - .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, + .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; -- cgit v1.2.2 From 5b368d3e46b946ed2a6b1b70ad2ac600740e582a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 7 Nov 2017 10:47:20 -0800 Subject: gpu: nvgpu: gv1xx: Move fuse override DT handling Move fuse override DT handling to Linux code. All the chip specific fuse override functions did the same thing, so delete the HAL and call the same function to read the DT overrides on all chips. Also remove the fuse override functionality from dGPU. There are no DT entries for PCIe devices, so it would've failed anyway. JIRA NVGPU-259 Change-Id: Ic672e25090cdfc207d9771ab61b6cf53185113a4 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1593693 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 - drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 - 3 files changed, 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 30b8e2c3..4ee333b5 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -334,7 +334,6 @@ static const struct gpu_ops gv100_ops = { .suspend_contexts = gr_gp10b_suspend_contexts, .resume_contexts = gr_gk20a_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, - .fuse_override = gp10b_gr_fuse_override, .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index faa67f02..ced5006d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -300,7 +300,6 @@ static const struct gpu_ops gv11b_ops = { .suspend_contexts = gr_gp10b_suspend_contexts, .resume_contexts = gr_gk20a_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, - .fuse_override = gp10b_gr_fuse_override, .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 5adb8ecd..a2c95edd 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -183,7 +183,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .suspend_contexts = vgpu_gr_suspend_contexts, .resume_contexts = vgpu_gr_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, - .fuse_override = gp10b_gr_fuse_override, .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, -- cgit v1.2.2 From c87e85af0cd812c6e1c138d4d1e48c23e3aa6bd3 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 7 Nov 2017 09:31:37 -0800 Subject: gpu: nvgpu: Return GPU classes in get_litter_value Return GPU classes in HAL get_litter_value() instead of assigning them to GPU characteristics at HAL initialization time. JIRA NVGPU-259 Change-Id: I92cbadf3bd07292a8715d30843972def879795f5 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1593691 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 26 ++++++++++++++++++-------- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 26 ++++++++++++++++++-------- 2 files changed, 36 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4ee333b5..88008e77 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -213,6 +213,24 @@ static int gv100_get_litter_value(struct gk20a *g, int value) case GPU_LIT_SMPC_PRI_STRIDE: ret = proj_smpc_stride_v(); break; + case GPU_LIT_TWOD_CLASS: + ret = FERMI_TWOD_A; + break; + case GPU_LIT_THREED_CLASS: + ret = VOLTA_A; + break; + case GPU_LIT_COMPUTE_CLASS: + ret = VOLTA_COMPUTE_A; + break; + case GPU_LIT_GPFIFO_CLASS: + ret = VOLTA_CHANNEL_GPFIFO_A; + break; + case GPU_LIT_I2M_CLASS: + ret = KEPLER_INLINE_TO_MEMORY_B; + break; + case GPU_LIT_DMA_COPY_CLASS: + ret = VOLTA_DMA_COPY_A; + break; default: break; } @@ -697,7 +715,6 @@ static const struct gpu_ops gv100_ops = { int gv100_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; gops->bios = gv100_ops.bios; gops->ltc = gv100_ops.ltc; @@ -754,12 +771,5 @@ int gv100_init_hal(struct gk20a *g) g->name = "gv10x"; - c->twod_class = FERMI_TWOD_A; - c->threed_class = VOLTA_A; - c->compute_class = VOLTA_COMPUTE_A; - c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; - c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; - c->dma_copy_class = VOLTA_DMA_COPY_A; - return 0; } diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ced5006d..681ddf3a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -196,6 +196,24 @@ int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_FBPA_SHARED_BASE: ret = 0; break; + case GPU_LIT_TWOD_CLASS: + ret = FERMI_TWOD_A; + break; + case GPU_LIT_THREED_CLASS: + ret = VOLTA_A; + break; + case GPU_LIT_COMPUTE_CLASS: + ret = VOLTA_COMPUTE_A; + break; + case GPU_LIT_GPFIFO_CLASS: + ret = VOLTA_CHANNEL_GPFIFO_A; + break; + case GPU_LIT_I2M_CLASS: + ret = KEPLER_INLINE_TO_MEMORY_B; + break; + case GPU_LIT_DMA_COPY_CLASS: + ret = VOLTA_DMA_COPY_A; + break; default: nvgpu_err(g, "Missing definition %d", value); @@ -674,7 +692,6 @@ static const struct gpu_ops gv11b_ops = { int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; u32 val; bool priv_security; @@ -760,12 +777,5 @@ int gv11b_init_hal(struct gk20a *g) g->name = "gv11b"; - c->twod_class = FERMI_TWOD_A; - c->threed_class = VOLTA_A; - c->compute_class = VOLTA_COMPUTE_A; - c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; - c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; - c->dma_copy_class = VOLTA_DMA_COPY_A; - return 0; } -- cgit v1.2.2 From 01e5b17e08cc9bde4d8bfbefb09828ae897a6df0 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 7 Nov 2017 10:06:45 -0800 Subject: gpu: nvgpu: gv11b: Move sm_arch to nvgpu_gpu_params Move sm_arch_* fields to nvgpu_gpu_params to make them available from common code without accessing Linux specific GPU characteristics. JIRA NVGPU-259 Change-Id: I8e7b542642b620f161d62954400777079065f49d Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1593692 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 22377522..9d97a61f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2104,11 +2104,11 @@ void gr_gv11b_detect_sm_arch(struct gk20a *g) { u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r()); - g->gpu_characteristics.sm_arch_spa_version = + g->params.sm_arch_spa_version = gr_gpc0_tpc0_sm_arch_spa_version_v(v); - g->gpu_characteristics.sm_arch_sm_version = + g->params.sm_arch_sm_version = gr_gpc0_tpc0_sm_arch_sm_version_v(v); - g->gpu_characteristics.sm_arch_warp_count = + g->params.sm_arch_warp_count = gr_gpc0_tpc0_sm_arch_warp_count_v(v); } -- cgit v1.2.2 From 96cb31ea105c155b0067a09924b0c734f95b4d1a Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 8 Nov 2017 14:17:59 -0800 Subject: gpu: nvgpu: gv11b: update prod settings Updated clock gating prod settings for HWCL # 39314184. This is corrected output after fixing issue in register generator tool. Bug 1994238 Change-Id: I646c4e1a134570016425367be636250205205005 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1594605 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c | 48 +++++++++++++------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c index e648fa41..9f6057ae 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b_gating_reglist.c @@ -41,7 +41,7 @@ static const struct gating_desc gv11b_slcg_bus[] = { /* slcg ce2 */ static const struct gating_desc gv11b_slcg_ce2[] = { - {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, + {.addr = 0x00104204, .prod = 0x00000040, .disable = 0x000007fe}, }; /* slcg chiplet */ @@ -66,16 +66,16 @@ static const struct gating_desc gv11b_slcg_fifo[] = { /* slcg gr */ static const struct gating_desc gv11b_slcg_gr[] = { {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, - {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00409134, .prod = 0x00020008, .disable = 0x0003fffe}, {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0000fffe}, {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, {.addr = 0x00405bf4, .prod = 0x00000000, .disable = 0x00000002}, - {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0041a134, .prod = 0x00020008, .disable = 0x0003fffe}, {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0000fffe}, {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, @@ -95,16 +95,16 @@ static const struct gating_desc gv11b_slcg_gr[] = { {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x000000ff}, {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, - {.addr = 0x00419c84, .prod = 0x0003fffe, .disable = 0x0003fffe}, + {.addr = 0x00419c84, .prod = 0x0003fff8, .disable = 0x0003fffe}, {.addr = 0x00419c8c, .prod = 0xffffff84, .disable = 0xfffffffe}, - {.addr = 0x00419c94, .prod = 0x00000240, .disable = 0x00007ffe}, + {.addr = 0x00419c94, .prod = 0x00080040, .disable = 0x000ffffe}, {.addr = 0x00419ca4, .prod = 0x00003ffe, .disable = 0x00003ffe}, {.addr = 0x00419cac, .prod = 0x0001fffe, .disable = 0x0001fffe}, {.addr = 0x00419a44, .prod = 0x00000008, .disable = 0x0000000e}, {.addr = 0x00419a4c, .prod = 0x000001f8, .disable = 0x000001fe}, {.addr = 0x00419a54, .prod = 0x0000003c, .disable = 0x0000003e}, {.addr = 0x00419a5c, .prod = 0x0000000c, .disable = 0x0000000e}, - {.addr = 0x00419a64, .prod = 0x00000186, .disable = 0x000001fe}, + {.addr = 0x00419a64, .prod = 0x000001ba, .disable = 0x000001fe}, {.addr = 0x00419a7c, .prod = 0x0000003c, .disable = 0x0000003e}, {.addr = 0x00419a84, .prod = 0x0000000c, .disable = 0x0000000e}, {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, @@ -144,20 +144,20 @@ static const struct gating_desc gv11b_slcg_priring[] = { static const struct gating_desc gv11b_slcg_pwr_csb[] = { {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, - {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, - {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, + {.addr = 0x00000a74, .prod = 0x00004040, .disable = 0x00007ffe}, + {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, }; /* slcg pmu */ static const struct gating_desc gv11b_slcg_pmu[] = { {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x0010aa74, .prod = 0x00004040, .disable = 0x00007ffe}, {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, }; /* therm gr */ static const struct gating_desc gv11b_slcg_therm[] = { - {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, + {.addr = 0x000206b8, .prod = 0x00000008, .disable = 0x0000000f}, }; /* slcg Xbar */ @@ -195,7 +195,7 @@ static const struct gating_desc gv11b_blcg_fb[] = { /* blcg fifo */ static const struct gating_desc gv11b_blcg_fifo[] = { - {.addr = 0x000026e0, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x000026e0, .prod = 0x0000c244, .disable = 0x00000000}, }; /* blcg gr */ @@ -227,23 +227,23 @@ static const struct gating_desc gv11b_blcg_gr[] = { {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x00419868, .prod = 0x00008243, .disable = 0x00000000}, {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00419c80, .prod = 0x00004048, .disable = 0x00000000}, - {.addr = 0x00419c88, .prod = 0x00004048, .disable = 0x00000000}, - {.addr = 0x00419c90, .prod = 0x00000047, .disable = 0x00000000}, + {.addr = 0x00419c80, .prod = 0x00004045, .disable = 0x00000000}, + {.addr = 0x00419c88, .prod = 0x00004043, .disable = 0x00000000}, + {.addr = 0x00419c90, .prod = 0x0000004a, .disable = 0x00000000}, {.addr = 0x00419c98, .prod = 0x00000042, .disable = 0x00000000}, {.addr = 0x00419ca0, .prod = 0x00000043, .disable = 0x00000000}, {.addr = 0x00419ca8, .prod = 0x00000003, .disable = 0x00000000}, {.addr = 0x00419cb0, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419a40, .prod = 0x00000545, .disable = 0x00000000}, - {.addr = 0x00419a48, .prod = 0x00004545, .disable = 0x00000000}, - {.addr = 0x00419a50, .prod = 0x00004545, .disable = 0x00000000}, - {.addr = 0x00419a58, .prod = 0x00004545, .disable = 0x00000000}, - {.addr = 0x00419a60, .prod = 0x00000505, .disable = 0x00000000}, - {.addr = 0x00419a68, .prod = 0x00000505, .disable = 0x00000000}, - {.addr = 0x00419a78, .prod = 0x00000505, .disable = 0x00000000}, - {.addr = 0x00419a80, .prod = 0x00004545, .disable = 0x00000000}, + {.addr = 0x00419a40, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00419a48, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00419a50, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00419a58, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00419a60, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a68, .prod = 0x00000202, .disable = 0x00000000}, + {.addr = 0x00419a78, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00419a80, .prod = 0x00000242, .disable = 0x00000000}, {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, -- cgit v1.2.2 From d99b72974d06d4b3bc577bae8dc721b7b8f3cde9 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 8 Nov 2017 15:59:31 -0800 Subject: gpu: nvgpu: gv11b: clear channel status After unbinding channel, following fields in channel status needs to be cleared manually: ccsr_channel_enable_clr_true ccsr_channel_pbdma_faulted_reset ccsr_channel_eng_faulted_reset Unbinding channel expected to clear all other channel status fields. Bug 1972365 Change-Id: Ibfd84df2f41adc2eb437a026acde3f3d618d7758 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1594671 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 4c3b1186..a3cb9292 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -260,9 +260,20 @@ void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) void channel_gv11b_unbind(struct channel_gk20a *ch) { + struct gk20a *g = ch->g; + gk20a_dbg_fn(""); - gk20a_fifo_channel_unbind(ch); + if (nvgpu_atomic_cmpxchg(&ch->bound, true, false)) { + gk20a_writel(g, ccsr_channel_inst_r(ch->chid), + ccsr_channel_inst_ptr_f(0) | + ccsr_channel_inst_bind_false_f()); + + gk20a_writel(g, ccsr_channel_r(ch->chid), + ccsr_channel_enable_clr_true_f() | + ccsr_channel_pbdma_faulted_reset_f() | + ccsr_channel_eng_faulted_reset_f()); + } } u32 gv11b_fifo_get_num_fifos(struct gk20a *g) -- cgit v1.2.2 From 98bd673a7371940f24d37ad3a6d7b426995e737e Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Fri, 15 Sep 2017 18:58:58 +0300 Subject: gpu: nvgpu: Remove PTE kind code for GV100/GV11B Remove gv11b_init_uncompressed_kind_map(), gv11b_init_kind_attr(), and the related kind setup code. They are not needed anymore. While we're doing these changes, remove a redundant assignment of g->bootstrap_owner in hal_gv100.c. Bug 1902982 Change-Id: Ib40d8f55cfbfa34143a3765c2b4913926ca021fd Signed-off-by: Sami Kiminki Reviewed-on: https://git-master.nvidia.com/r/1560931 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 5 - drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 440 -------------------------- drivers/gpu/nvgpu/gv11b/fb_gv11b.h | 2 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 - drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 - 5 files changed, 451 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 88008e77..7f2b149b 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -764,11 +764,6 @@ int gv100_init_hal(struct gk20a *g) g->pmu_lsf_pmu_wpr_init_done = 0; g->bootstrap_owner = LSF_FALCON_ID_SEC2; - gv11b_init_uncompressed_kind_map(); - gv11b_init_kind_attr(); - - g->bootstrap_owner = LSF_FALCON_ID_SEC2; - g->name = "gv10x"; return 0; diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index d89018e5..be567c26 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -31,7 +31,6 @@ #include #include "gk20a/gk20a.h" -#include "gk20a/kind_gk20a.h" #include "gk20a/mm_gk20a.h" #include "gp10b/fb_gp10b.h" @@ -262,445 +261,6 @@ static const char *const gpc_client_descs_gv11b[] = { "t1 36", "t1 37", "t1 38", "t1 39", }; -noinline_for_stack void gv11b_init_uncompressed_kind_map(void) -{ - int i; - - for (i = 0; i < 256; i++) - gk20a_uc_kind_map[i] = gmmu_pte_kind_invalid_v(); - - /* From gv11b */ - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms2_4cbra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms2_4cbra_v()] = - gmmu_pte_kind_generic_16bx2_v(); - - /* From gp10b */ - gk20a_uc_kind_map[gmmu_pte_kind_z16_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms16_2cz_v()] = - gmmu_pte_kind_z16_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_4cbra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_4cbra_v()] = - gmmu_pte_kind_generic_16bx2_v(); - - /* From gm20b */ - gk20a_uc_kind_map[gmmu_pte_kind_s8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8_2s_v()] = - gmmu_pte_kind_s8_v(); - - /* From gk20a */ - gk20a_uc_kind_map[gmmu_pte_kind_z16_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_2z_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2z_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2z_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2z_v()] = - gmmu_pte_kind_z16_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms2_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms4_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms8_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms2_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_s8z24_ms8_2cs_v()] = - gmmu_pte_kind_s8z24_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc4_2zv_v()] = - gmmu_pte_kind_v8z24_ms4_vc4_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc8_2zv_v()] = - gmmu_pte_kind_v8z24_ms8_vc8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms4_vc12_2zv_v()] = - gmmu_pte_kind_v8z24_ms4_vc12_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_v8z24_ms8_vc24_2zv_v()] = - gmmu_pte_kind_v8z24_ms8_vc24_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms2_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms2_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms4_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24s8_ms8_2cz_v()] = - gmmu_pte_kind_z24s8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms2_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms2_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms4_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_ms8_2cz_v()] = - gmmu_pte_kind_zf32_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v()] = - gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v()] = - gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v()] = - gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()] = - gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v()] = - gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v()] = - gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v()] = - gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()] = - gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_2cszv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms2_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_zf32_x24s8_ms8_2cs_v()] = - gmmu_pte_kind_zf32_x24s8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_c32_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_2cba_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_2bra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms2_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cbr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cba_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_2bra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms8_ms16_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms8_ms16_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_2cbr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_2cba_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_2bra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms2_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cbr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cba_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_2bra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms8_ms16_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms8_ms16_2cra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_2cr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms2_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms2_2cr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms4_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms4_2cr_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms8_ms16_2c_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c128_ms8_ms16_2cr_v()] = - gmmu_pte_kind_generic_16bx2_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc4_2zv_v()] = - gmmu_pte_kind_z24v8_ms4_vc4_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms4_vc12_2zv_v()] = - gmmu_pte_kind_z24v8_ms4_vc12_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc8_2zv_v()] = - gmmu_pte_kind_z24v8_ms8_vc8_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2czv_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z24v8_ms8_vc24_2zv_v()] = - gmmu_pte_kind_z24v8_ms8_vc24_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_x8c24_v()] = - gmmu_pte_kind_x8c24_v(); -} - -static noinline_for_stack bool gv11b_kind_supported(u8 k) -{ - return /* From gv11b */ - k == gmmu_pte_kind_c32_ms2_4cbra_v() - || k == gmmu_pte_kind_c64_ms2_4cbra_v() - /* From gp10b */ - || (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) - || k == gmmu_pte_kind_z16_ms16_2cz_v() - || k == gmmu_pte_kind_c32_ms4_4cbra_v() - || k == gmmu_pte_kind_c64_ms4_4cbra_v() - /* From gm20b */ - || (k == gmmu_pte_kind_smsked_message_v()) - || (k >= gmmu_pte_kind_s8_v() && - k <= gmmu_pte_kind_s8_2s_v()) - /* From gk20a */ - || gk20a_kind_work_creation(k) - || (k == gmmu_pte_kind_invalid_v()) - || (k == gmmu_pte_kind_pitch_v()) - || (k >= gmmu_pte_kind_z16_v() && - k <= gmmu_pte_kind_z16_ms8_2c_v()) - || (k >= gmmu_pte_kind_z16_2z_v() && - k <= gmmu_pte_kind_z16_ms8_2z_v()) - || (k == gmmu_pte_kind_s8z24_v()) - || (k >= gmmu_pte_kind_s8z24_2cz_v() && - k <= gmmu_pte_kind_s8z24_ms8_2cz_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_2zv_v()) - || (k == gmmu_pte_kind_z24s8_v()) - || (k >= gmmu_pte_kind_z24s8_2cz_v() && - k <= gmmu_pte_kind_z24s8_ms8_2cz_v()) - || (k == gmmu_pte_kind_zf32_v()) - || (k >= gmmu_pte_kind_zf32_2cz_v() && - k <= gmmu_pte_kind_zf32_ms8_2cz_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v() && - k <= gmmu_pte_kind_zf32_x24s8_v()) - || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && - k <= gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v()) - || (k == gmmu_pte_kind_generic_16bx2_v()) - || (k == gmmu_pte_kind_c32_2c_v()) - || (k == gmmu_pte_kind_c32_2cra_v()) - || (k == gmmu_pte_kind_c32_ms2_2c_v()) - || (k >= gmmu_pte_kind_c32_ms4_2c_v() && - k <= gmmu_pte_kind_c32_ms4_2cbr_v()) - || (k >= gmmu_pte_kind_c32_ms4_2cra_v() && - k <= gmmu_pte_kind_c64_2c_v()) - || (k == gmmu_pte_kind_c64_2cra_v()) - || (k == gmmu_pte_kind_c64_ms2_2c_v()) - || (k >= gmmu_pte_kind_c64_ms4_2c_v() && - k <= gmmu_pte_kind_c64_ms4_2cbr_v()) - || (k >= gmmu_pte_kind_c64_ms4_2cra_v() && - k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()) - || (k == gmmu_pte_kind_pitch_no_swizzle_v()); -} - -static noinline_for_stack bool gv11b_kind_z(u8 k) -{ - return /* From gv11b */ - (k == gmmu_pte_kind_c32_ms2_4cbra_v()) - || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) - /* From gp10b */ - || (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) - || (k == gmmu_pte_kind_z16_ms16_2cz_v()) - /* From gm20b */ - || (k >= gmmu_pte_kind_s8_v() && - k <= gmmu_pte_kind_s8_2s_v()) - /* From gk20a */ - || (k >= gmmu_pte_kind_z16_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()); -} - -static noinline_for_stack bool gv11b_kind_c(u8 k) -{ - return gk20a_kind_work_creation(k) - || (k == gmmu_pte_kind_pitch_v()) - || (k == gmmu_pte_kind_generic_16bx2_v()) - || (k >= gmmu_pte_kind_c32_2c_v() && - k <= gmmu_pte_kind_c32_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c32_ms4_2c_v() && - k <= gmmu_pte_kind_c64_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c64_ms4_2c_v() && - k <= gmmu_pte_kind_pitch_no_swizzle_v()); -} - -static noinline_for_stack bool gv11b_kind_compressible(u8 k) -{ - - return /* From gv11b */ - (k == gmmu_pte_kind_c32_ms2_4cbra_v()) - || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) - /* From gp10b */ - || (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) - || (k == gmmu_pte_kind_z16_ms16_2cz_v()) - || (k == gmmu_pte_kind_c32_ms4_4cbra_v()) - || (k == gmmu_pte_kind_c64_ms4_4cbra_v()) - /* From gm20b */ - || (k >= gmmu_pte_kind_s8_v() && - k <= gmmu_pte_kind_s8_2s_v()) - /* From gk20a */ - || (k >= gmmu_pte_kind_s8z24_1z_v() && - k <= gmmu_pte_kind_s8z24_ms16_4cszv_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v()) - || (k >= gmmu_pte_kind_z24s8_1z_v() && - k <= gmmu_pte_kind_z24s8_ms16_4cszv_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v()) - || (k >= gmmu_pte_kind_zf32_1z_v() && - k <= gmmu_pte_kind_zf32_ms16_2cz_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()) - || (k >= gmmu_pte_kind_zf32_x24s8_1cs_v() && - k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()) - || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && - k <= gmmu_pte_kind_c32_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c32_ms4_2c_v() && - k <= gmmu_pte_kind_c64_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c64_ms4_2c_v() && - k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); -} - -static noinline_for_stack bool gv11b_kind_zbc(u8 k) -{ - - return /* From gv11b */ - (k == gmmu_pte_kind_c32_ms2_4cbra_v()) - || (k == gmmu_pte_kind_c64_ms2_4cbra_v()) - /* From gp10b */ - || (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) - || (k == gmmu_pte_kind_z16_ms16_2cz_v()) - || (k == gmmu_pte_kind_c32_ms4_4cbra_v()) - || (k == gmmu_pte_kind_c64_ms4_4cbra_v()) - /* From gm20b */ - || (k >= gmmu_pte_kind_s8_v() && - k <= gmmu_pte_kind_s8_2s_v()) - /* From gk20a */ - || (k >= gmmu_pte_kind_z16_2c_v() && - k <= gmmu_pte_kind_z16_ms16_2c_v()) - || (k >= gmmu_pte_kind_s8z24_2cz_v() && - k <= gmmu_pte_kind_s8z24_ms16_4cszv_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2cs_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_2czv_v()) - || (k >= gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v() && - k <= gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v()) - || (k >= gmmu_pte_kind_z24s8_2cs_v() && - k <= gmmu_pte_kind_z24s8_ms16_4cszv_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2cs_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_2cs_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_2czv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_2czv_v()) - || (k >= gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v() && - k <= gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v()) - || (k >= gmmu_pte_kind_zf32_2cs_v() && - k <= gmmu_pte_kind_zf32_ms16_2cz_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v() && - k <= gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v()) - || (k >= gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v() && - k <= gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v()) - || (k >= gmmu_pte_kind_zf32_x24s8_1cs_v() && - k <= gmmu_pte_kind_zf32_x24s8_ms16_1cs_v()) - || (k >= gmmu_pte_kind_zf32_x24s8_2cszv_v() && - k <= gmmu_pte_kind_c32_2cra_v()) - || (k >= gmmu_pte_kind_c32_ms2_2c_v() && - k <= gmmu_pte_kind_c32_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c32_ms4_2c_v() && - k <= gmmu_pte_kind_c32_ms4_2cra_v()) - || (k >= gmmu_pte_kind_c32_ms8_ms16_2c_v() && - k <= gmmu_pte_kind_c64_2cra_v()) - || (k >= gmmu_pte_kind_c64_ms2_2c_v() && - k <= gmmu_pte_kind_c64_ms2_2cbr_v()) - || (k >= gmmu_pte_kind_c64_ms4_2c_v() && - k <= gmmu_pte_kind_c64_ms4_2cra_v()) - || (k >= gmmu_pte_kind_c64_ms8_ms16_2c_v() && - k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); -} - -void gv11b_init_kind_attr(void) -{ - u16 k; - - for (k = 0; k < NV_KIND_ATTR_SIZE; k++) { - if (gv11b_kind_supported((u8)k)) - gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED; - if (gv11b_kind_compressible((u8)k)) - gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE; - if (gv11b_kind_z((u8)k)) - gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z; - if (gv11b_kind_c((u8)k)) - gk20a_kind_attr[k] |= GK20A_KIND_ATTR_C; - if (gv11b_kind_zbc((u8)k)) - gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC; - } -} - u32 gv11b_fb_is_fault_buf_enabled(struct gk20a *g, unsigned int index) { diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h index 4ebee343..d9a6fa77 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.h @@ -69,6 +69,4 @@ void gv11b_fb_disable_hub_intr(struct gk20a *g, unsigned int index, unsigned int intr_type); bool gv11b_fb_mmu_fault_pending(struct gk20a *g); -noinline_for_stack void gv11b_init_uncompressed_kind_map(void); -void gv11b_init_kind_attr(void); #endif diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 681ddf3a..5d8bbbdb 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -771,8 +771,6 @@ int gv11b_init_hal(struct gk20a *g) } __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); - gv11b_init_uncompressed_kind_map(); - gv11b_init_kind_attr(); g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; g->name = "gv11b"; diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index a2c95edd..a496d3fc 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -636,8 +636,6 @@ int vgpu_gv11b_init_hal(struct gk20a *g) } __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); - gv11b_init_uncompressed_kind_map(); - gv11b_init_kind_attr(); g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; g->name = "gv11b"; -- cgit v1.2.2 From e590cf6c2c18d5bd7fca20186ded2a599c68c6c7 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 10 Nov 2017 10:59:26 -0800 Subject: gpu: nvgpu: gv11b: Do not assign GPU classes in vgpu HAL GPU class ids were moved to get_litter_value API, but vgpu was not updated to remove assigning them in HAL initialization. Remove the duplicate assignments. JIRA NVGPU-388 Change-Id: If75944517d1ea813496b1f2a12a1faf03406d8d0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1596244 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index a496d3fc..b7c7cd2f 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -558,7 +558,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { int vgpu_gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; u32 val; bool priv_security; @@ -640,12 +639,5 @@ int vgpu_gv11b_init_hal(struct gk20a *g) g->name = "gv11b"; - c->twod_class = FERMI_TWOD_A; - c->threed_class = VOLTA_A; - c->compute_class = VOLTA_COMPUTE_A; - c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; - c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; - c->dma_copy_class = VOLTA_DMA_COPY_A; - return 0; } -- cgit v1.2.2 From 0b0f80579c01a53768433ed1909d283719427429 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 10 Nov 2017 11:01:18 -0800 Subject: gpu: nvgpu: vgpu: Delete extra error print vgpu printed GPU characteristics flags at probe time. Delete the print in order to be able to remove GPU characteristics field. JIRA NVGPU-388 Change-Id: Ib08325e7a67598a4f6734f7e839d1b96ba10bd55 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1596245 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c index db3dfaf4..feac195e 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c @@ -25,9 +25,6 @@ int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) gk20a_dbg_fn(""); - - nvgpu_err(g, "g->gpu_characteristics.flags=%llx", - g->gpu_characteristics.flags); err = vgpu_init_gpu_characteristics(g); if (err) { nvgpu_err(g, "vgpu_init_gpu_characteristics failed, err %d\n", err); -- cgit v1.2.2 From d64241cb5a0ca21ae2c88419d34ad79715a4588a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 10 Nov 2017 11:41:17 -0800 Subject: gpu: nvgpu: Include UAPI explicitly Add explicit #includes for for source code files that depend on it. JIRA NVGPU-388 Change-Id: I5d834e6f3b413cee9b1e4e055d710fc9f2c8f7c2 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1596246 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c | 2 ++ drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c | 1 + drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 1 + 3 files changed, 4 insertions(+) diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c index 56756ac9..a04fb5c9 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c @@ -11,6 +11,8 @@ * more details. */ +#include + #include #include #include diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c index ec7501ce..1c96db69 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c @@ -14,6 +14,7 @@ */ #include +#include #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 9d97a61f..4da2ef59 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -26,6 +26,7 @@ #include #include #include +#include #include -- cgit v1.2.2 From 0f5202368781c5398e3d026dc408d79a37ad5aed Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Wed, 8 Nov 2017 18:32:26 -0800 Subject: gpu: nvgpu: ctx_patch_write fixes - Update commit_global_timeslice to remove unused patch parameter - Update calls to ctx_patch_write_begin/end to add update_patch_count param JIRA ESRM-74 Bug 2012077 Change-Id: Ie2e640dfa0ab7193a062a58f588575f220e5efd3 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1594791 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 29 ++++++++--------------------- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 +-- 2 files changed, 9 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 4da2ef59..3a3406f9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2214,8 +2214,7 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) -int gr_gv11b_commit_global_timeslice(struct gk20a *g, - struct channel_gk20a *c, bool patch) +int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c) { struct channel_ctx_gk20a *ch_ctx = NULL; u32 pd_ab_dist_cfg0; @@ -2230,15 +2229,6 @@ int gr_gv11b_commit_global_timeslice(struct gk20a *g, ds_debug = gk20a_readl(g, gr_ds_debug_r()); mpc_vtg_debug = gk20a_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r()); - if (patch) { - int err; - - ch_ctx = &c->ch_ctx; - err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); - if (err) - return err; - } - pe_vaf = gk20a_readl(g, gr_gpcs_tpcs_pe_vaf_r()); pe_vsc_vpc = gk20a_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); @@ -2252,17 +2242,14 @@ int gr_gv11b_commit_global_timeslice(struct gk20a *g, mpc_vtg_debug; gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, - patch); + false); gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pes_vsc_vpc_r(), - pe_vsc_vpc, patch); + pe_vsc_vpc, false); gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg0_r(), - pd_ab_dist_cfg0, patch); - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_debug_r(), ds_debug, patch); + pd_ab_dist_cfg0, false); + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_debug_r(), ds_debug, false); gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(), - mpc_vtg_debug, patch); - - if (patch) - gr_gk20a_ctx_patch_write_end(g, ch_ctx); + mpc_vtg_debug, false); return 0; } @@ -2568,7 +2555,7 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset, gr->sm_error_states[sm_id].hww_warp_esr_report_mask); } else { - err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); + err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); if (err) goto enable_ctxsw; @@ -2583,7 +2570,7 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, gr->sm_error_states[sm_id].hww_warp_esr_report_mask, true); - gr_gk20a_ctx_patch_write_end(g, ch_ctx); + gr_gk20a_ctx_patch_write_end(g, ch_ctx, false); } enable_ctxsw: diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 98e7bc50..b6ba231e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -142,8 +142,7 @@ void gr_gv11b_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); int gr_gv11b_load_smid_config(struct gk20a *g); int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); -int gr_gv11b_commit_global_timeslice(struct gk20a *g, - struct channel_gk20a *c, bool patch); +int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c); void gr_gv11b_write_zcull_ptr(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va); void gr_gv11b_write_pm_ptr(struct gk20a *g, -- cgit v1.2.2 From 4dbf6f7bd600750461d6e747c00df99999e2be2f Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 13 Nov 2017 13:05:13 +0530 Subject: gpu: nvgpu: define preemption modes in common code Use common preemption modes in common code instead of using linux specific definitions Jira NVGPU-392 Change-Id: Iff65ab4278973f2e2d7db33f6fedb561b2164c42 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1596931 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 3a3406f9..3d817d7e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1765,7 +1765,7 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, if (fault_ch) cilp_enabled = (fault_ch->ch_ctx.gr_ctx->compute_preempt_mode == - NVGPU_COMPUTE_PREEMPTION_MODE_CILP); + NVGPU_PREEMPTION_MODE_COMPUTE_CILP); gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d sm %d = 0x%08x", -- cgit v1.2.2 From b8e57243999902ac87c024a1e41abb5fa02cf22a Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 13 Nov 2017 12:05:34 -0800 Subject: gpu: nvgpu: gv11b: define final netlist Use NETD firmware on gv11b. GV11B_NETLIST_IMAGE_FW_NAME set to GK20A_NETLIST_IMAGE_D Change-Id: I0301999851ffb14713beaf61b5b2cc97efac74eb Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1597290 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: Seshendra Gadagottu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h index 679403ef..0a95ab11 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_ctx_gv11b.h @@ -26,11 +26,10 @@ #include "gk20a/gr_ctx_gk20a.h" -/* production netlist, one and only one from below */ -/* - * Define netlist for silicon only - * #define GV11B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A -*/ +/* Define netlist for silicon only */ + +#define GV11B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D + int gr_gv11b_get_netlist_name(struct gk20a *g, int index, char *name); bool gr_gv11b_is_firmware_defined(void); -- cgit v1.2.2 From f1c962daae5fdb231a8c8b0202d96c1c4e242ef1 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 8 Nov 2017 15:48:45 -0800 Subject: gpu: nvgpu: gv11b: mc_elpg_enable & soc credit init moved to bpmp -Program mc_elpg_enable and mss nvlink soc credits only when bpmp is not running or bpmp is running but underlying platorm is simulation. For simulation, bpmp does not execute hot reset sequence. As part of gpu unpowergate, bpmp will program mc_elpg_enable and also set mss nvlink soc credits after bringing mss nvlink out of reset -Remove updating mc_enable as writes to this register has no effect -Remove fifo_fb_iface_r read/write. This hack was added during initial bring up of emulation platforms Bug 2018223 Bug 200269361 Change-Id: Ie09c259e48295a93c6d15376308186152db973fa Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1594495 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 100 +++++++++++++++++-------------------- 1 file changed, 47 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index be567c26..ec487bdf 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/mm_gk20a.h" @@ -41,7 +42,6 @@ #include #include -#include #include #include @@ -53,35 +53,41 @@ static int gv11b_fb_mmu_invalidate_replay(struct gk20a *g, static void gv11b_init_nvlink_soc_credits(struct gk20a *g) { - void __iomem *soc1 = ioremap(0x01f20010, 4096); //MSS_NVLINK_1_BASE - void __iomem *soc2 = ioremap(0x01f40010, 4096); //MSS_NVLINK_2_BASE - void __iomem *soc3 = ioremap(0x01f60010, 4096); //MSS_NVLINK_3_BASE - void __iomem *soc4 = ioremap(0x01f80010, 4096); //MSS_NVLINK_4_BASE - u32 val; - - /* TODO : replace this code with proper nvlink API */ - nvgpu_info(g, "init nvlink soc credits"); - - val = readl_relaxed(soc1); - writel_relaxed(val, soc1); - val = readl_relaxed(soc1 + 4); - writel_relaxed(val, soc1 + 4); - - val = readl_relaxed(soc2); - writel_relaxed(val, soc2); - val = readl_relaxed(soc2 + 4); - writel_relaxed(val, soc2 + 4); - - val = readl_relaxed(soc3); - writel_relaxed(val, soc3); - val = readl_relaxed(soc3 + 4); - writel_relaxed(val, soc3 + 4); - - val = readl_relaxed(soc4); - writel_relaxed(val, soc4); - val = readl_relaxed(soc4 + 4); - writel_relaxed(val, soc4 + 4); - + if (nvgpu_is_bpmp_running(g) && (!nvgpu_platform_is_simulation(g))) { + nvgpu_info(g, "nvlink soc credits init done by bpmp"); + } else { + /* MSS_NVLINK_1_BASE */ + void __iomem *soc1 = ioremap(0x01f20010, 4096); + /* MSS_NVLINK_2_BASE */ + void __iomem *soc2 = ioremap(0x01f40010, 4096); + /* MSS_NVLINK_3_BASE */ + void __iomem *soc3 = ioremap(0x01f60010, 4096); + /* MSS_NVLINK_4_BASE */ + void __iomem *soc4 = ioremap(0x01f80010, 4096); + u32 val; + + nvgpu_info(g, "init nvlink soc credits"); + + val = readl_relaxed(soc1); + writel_relaxed(val, soc1); + val = readl_relaxed(soc1 + 4); + writel_relaxed(val, soc1 + 4); + + val = readl_relaxed(soc2); + writel_relaxed(val, soc2); + val = readl_relaxed(soc2 + 4); + writel_relaxed(val, soc2 + 4); + + val = readl_relaxed(soc3); + writel_relaxed(val, soc3); + val = readl_relaxed(soc3 + 4); + writel_relaxed(val, soc3 + 4); + + val = readl_relaxed(soc4); + writel_relaxed(val, soc4); + val = readl_relaxed(soc4 + 4); + writel_relaxed(val, soc4 + 4); + } } void gv11b_fb_init_fs_state(struct gk20a *g) @@ -149,33 +155,21 @@ void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) void gv11b_fb_reset(struct gk20a *g) { - u32 val; - - nvgpu_info(g, "reset gv11b fb"); - - g->ops.mc.reset(g, mc_enable_pfb_enabled_f() | - mc_enable_xbar_enabled_f() | - mc_enable_hub_enabled_f()); + if (nvgpu_is_bpmp_running(g) && (!nvgpu_platform_is_simulation(g))) { + nvgpu_log(g, gpu_dbg_info, "mc_elpg_enable set by bpmp"); + } else { + u32 mc_elpg_enable_val; - val = gk20a_readl(g, mc_elpg_enable_r()); - val |= mc_elpg_enable_xbar_enabled_f() | - mc_elpg_enable_pfb_enabled_f() | - mc_elpg_enable_hub_enabled_f(); - gk20a_writel(g, mc_elpg_enable_r(), val); + nvgpu_log(g, gpu_dbg_info, "enable xbar, pfb and hub"); + mc_elpg_enable_val = mc_elpg_enable_xbar_enabled_f() | + mc_elpg_enable_pfb_enabled_f() | + mc_elpg_enable_hub_enabled_f(); + mc_elpg_enable_val |= gk20a_readl(g, mc_elpg_enable_r()); + gk20a_writel(g, mc_elpg_enable_r(), mc_elpg_enable_val); + } /* fs hub should be out of reset by now */ gv11b_init_nvlink_soc_credits(g); - - val = gk20a_readl(g, fifo_fb_iface_r()); - nvgpu_info(g, "fifo_fb_iface val = 0x%x", val); - if (!(val & fifo_fb_iface_control_enable_f() && - val & fifo_fb_iface_status_enabled_f())) { - nvgpu_info(g, "fifo_fb_iface set control enable"); - gk20a_writel(g, fifo_fb_iface_r(), - fifo_fb_iface_control_enable_f()); - val = gk20a_readl(g, fifo_fb_iface_r()); - nvgpu_info(g, "fifo_fb_iface val = 0x%x", val); - } } static const char * const invalid_str = "invalid"; -- cgit v1.2.2 From 72b51a129fda4a89f226aad7c99f062977a07189 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 22 Sep 2017 15:07:13 -0700 Subject: gpu: nvgpu: gv11b: detect stall intr during preemption Check for interrupts or hangs while waiting for the preempt to complete. During pbdma/eng preempt done polling, any stalling interrupts relating to the runlist must be detected and handled in order for the preemption to complete. When PBDMA fault or CE fault occurs, the PBDMA will save out automatically. TSG related to the context in which the fault occurred will not be scheduled again until the fault is handled. In the case of some other issue requiring the engine to be reset, TSG will need to be manually preempted. In all cases, a PBDMA interrupt may occur prior to the PBDMA being able to switch out. SW must handle these interrupts according to the relevant handling procedure before the PBDMA preempt can complete. Opt for eng reset instead of waiting for preemption to be finished when there is any stall interrupt pending during engine context preempt completion. Bug 200277163 Bug 1945121 Change-Id: Icaef79e3046d82987b8486d15cbfc8365aa26f2e Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1522914 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto Tested-by: David Martinez Nieto Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 89 +++++++++++++++++------------------- drivers/gpu/nvgpu/gv11b/mc_gv11b.c | 20 ++++++++ drivers/gpu/nvgpu/gv11b/mc_gv11b.h | 1 + 3 files changed, 64 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index a3cb9292..f87c6dea 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -56,6 +56,7 @@ #include "fifo_gv11b.h" #include "subctx_gv11b.h" #include "gr_gv11b.h" +#include "mc_gv11b.h" #define PBDMA_SUBDEVICE_ID 1 @@ -393,45 +394,35 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, u32 pbdma_id, unsigned int timeout_rc_type) { struct nvgpu_timeout timeout; - unsigned long delay = GR_IDLE_CHECK_DEFAULT; + unsigned long delay = GR_IDLE_CHECK_DEFAULT; /* in micro seconds */ u32 pbdma_stat; u32 chan_stat; int ret = -EBUSY; - /* - * If the PBDMA has a stalling interrupt and receives a NACK, the PBDMA - * won't save out until the STALLING interrupt is cleared. Note that - * the stalling interrupt need not be directly addressed, as simply - * clearing of the interrupt bit will be sufficient to allow the PBDMA - * to save out. If the stalling interrupt was due to a SW method or - * another deterministic failure, the PBDMA will assert it when the - * channel is reloaded/resumed. Note that the fault will still be - * reported to SW. - */ - - if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { - /* called from recovery */ - u32 pbdma_intr_0, pbdma_intr_1; - - pbdma_intr_0 = gk20a_readl(g, pbdma_intr_0_r(pbdma_id)); - pbdma_intr_1 = gk20a_readl(g, pbdma_intr_1_r(pbdma_id)); - - if (pbdma_intr_0) - gk20a_writel(g, pbdma_intr_0_r(pbdma_id), pbdma_intr_0); - if (pbdma_intr_1) - gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); - } - + /* timeout in milli seconds */ nvgpu_timeout_init(g, &timeout, g->ops.fifo.get_preempt_timeout(g), NVGPU_TIMER_CPU_TIMER); + nvgpu_log(g, gpu_dbg_info, "wait preempt pbdma %d", pbdma_id); /* Verify that ch/tsg is no longer on the pbdma */ do { + /* + * If the PBDMA has a stalling interrupt and receives a NACK, + * the PBDMA won't save out until the STALLING interrupt is + * cleared. Stalling interrupt need not be directly addressed, + * as simply clearing of the interrupt bit will be sufficient + * to allow the PBDMA to save out. If the stalling interrupt + * was due to a SW method or another deterministic failure, + * the PBDMA will assert it when the channel is reloaded + * or resumed. Note that the fault will still be + * reported to SW. + */ + + gk20a_fifo_handle_pbdma_intr(g, &g->fifo, pbdma_id, RC_NO); + pbdma_stat = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id)); chan_stat = fifo_pbdma_status_chan_status_v(pbdma_stat); - gk20a_dbg_info("wait preempt pbdma"); - if (chan_stat == fifo_pbdma_status_chan_status_valid_v() || chan_stat == @@ -473,26 +464,36 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, } static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, - u32 engine_idx, u32 *reset_eng_bitmask, + u32 act_eng_id, u32 *reset_eng_bitmask, unsigned int timeout_rc_type) { struct nvgpu_timeout timeout; - unsigned long delay = GR_IDLE_CHECK_DEFAULT; + unsigned long delay = GR_IDLE_CHECK_DEFAULT; /* in micro seconds */ u32 eng_stat; u32 ctx_stat; int ret = -EBUSY; + bool stall_intr = false; + /* timeout in milli seconds */ nvgpu_timeout_init(g, &timeout, g->ops.fifo.get_preempt_timeout(g), NVGPU_TIMER_CPU_TIMER); + nvgpu_log(g, gpu_dbg_info, "wait preempt act engine id: %u", + act_eng_id); /* Check if ch/tsg has saved off the engine or if ctxsw is hung */ do { - eng_stat = gk20a_readl(g, fifo_engine_status_r(engine_idx)); + eng_stat = gk20a_readl(g, fifo_engine_status_r(act_eng_id)); ctx_stat = fifo_engine_status_ctx_status_v(eng_stat); + if (gv11b_mc_is_stall_and_eng_intr_pending(g, act_eng_id)) { + stall_intr = true; + nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, + "stall intr set, " + "preemption will not finish"); + } if (ctx_stat == fifo_engine_status_ctx_status_ctxsw_switch_v()) { - gk20a_dbg_info("engine save hasn't started yet"); + /* Eng save hasn't started yet. Continue polling */ } else if (ctx_stat == fifo_engine_status_ctx_status_valid_v() || @@ -500,14 +501,12 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, fifo_engine_status_ctx_status_ctxsw_save_v()) { if (id == fifo_engine_status_id_v(eng_stat)) { - if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { - /* called from recovery, eng seems to be hung */ - *reset_eng_bitmask |= BIT(engine_idx); + if (stall_intr || + timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* preemption will not finish */ + *reset_eng_bitmask |= BIT(act_eng_id); ret = 0; break; - } else { - gk20a_dbg_info("wait preempt engine. " - "ctx_status (valid/save)=%u", ctx_stat); } } else { /* context is not running on the engine */ @@ -520,14 +519,12 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, if (id == fifo_engine_status_next_id_v(eng_stat)) { - if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { - /* called from recovery, eng seems to be hung */ - *reset_eng_bitmask |= BIT(engine_idx); + if (stall_intr || + timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* preemption will not finish */ + *reset_eng_bitmask |= BIT(act_eng_id); ret = 0; break; - } else { - gk20a_dbg_info("wait preempt engine. " - "ctx_status (load)=%u", ctx_stat); } } else { /* context is not running on the engine */ @@ -540,7 +537,7 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, ret = 0; break; } - usleep_range(delay, delay * 2); + nvgpu_usleep_range(delay, delay * 2); delay = min_t(unsigned long, delay << 1, GR_IDLE_CHECK_MAX); } while (!nvgpu_timeout_expired_msg(&timeout, @@ -712,7 +709,7 @@ static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g, break; } - usleep_range(delay, delay * 2); + nvgpu_usleep_range(delay, delay * 2); delay = min_t(unsigned long, delay << 1, GR_IDLE_CHECK_MAX); } while (!nvgpu_timeout_expired_msg(&timeout, @@ -758,7 +755,7 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, f->runlist_info[runlist_id].reset_eng_bitmask = 0; - for_each_set_bit(act_eng_id, &runlist_served_engines, f->num_engines) { + for_each_set_bit(act_eng_id, &runlist_served_engines, f->max_engines) { func_ret = gv11b_fifo_poll_eng_ctx_status(g, tsgid, act_eng_id, &f->runlist_info[runlist_id].reset_eng_bitmask, diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c index dab304e2..74c5c4d6 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c @@ -70,3 +70,23 @@ bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) { return ((mc_intr_0 & mc_intr_hub_pending_f()) ? true : false); } + +bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id) +{ + u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); + u32 stall_intr, eng_intr_mask; + + eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); + if (mc_intr_0 & eng_intr_mask) + return true; + + stall_intr = mc_intr_pfifo_pending_f() | + mc_intr_hub_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f(); + if (mc_intr_0 & stall_intr) + return true; + + return false; +} diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h b/drivers/gpu/nvgpu/gv11b/mc_gv11b.h index de193a84..eb9d0e4e 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.h @@ -26,4 +26,5 @@ struct gk20a; void mc_gv11b_intr_enable(struct gk20a *g); bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0); +bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id); #endif -- cgit v1.2.2 From af5e4a1bf63037e7618adfa11a950244df5883f2 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 15 Nov 2017 15:10:51 +0530 Subject: gpu: nvgpu: deprecate TSG/CHANNEL_SET_PRIORITY IOCTLs TSG/CHANNEL_SET_PRIORITY IOCTLs are deprecated and user space should be using combination of timeslice and interleave levels to decide the priority Hence remove the IOCTLs and all corresponding APIs Jira NVGPU-393 Change-Id: Idce925631653784e39864223dc418a99a7e7ca3c Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1598582 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 - drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 - 3 files changed, 3 deletions(-) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 7f2b149b..4044c4b5 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -449,7 +449,6 @@ static const struct gpu_ops gv100_ops = { .alloc_inst = gk20a_fifo_alloc_inst, .free_inst = gk20a_fifo_free_inst, .setup_ramfc = channel_gv11b_setup_ramfc, - .channel_set_priority = gk20a_fifo_set_priority, .channel_set_timeslice = gk20a_fifo_set_timeslice, .default_timeslice_us = gk20a_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 5d8bbbdb..fc059caa 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -467,7 +467,6 @@ static const struct gpu_ops gv11b_ops = { .alloc_inst = gk20a_fifo_alloc_inst, .free_inst = gk20a_fifo_free_inst, .setup_ramfc = channel_gv11b_setup_ramfc, - .channel_set_priority = gk20a_fifo_set_priority, .channel_set_timeslice = gk20a_fifo_set_timeslice, .default_timeslice_us = gk20a_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index b7c7cd2f..17d6f049 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -330,7 +330,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .alloc_inst = vgpu_channel_alloc_inst, .free_inst = vgpu_channel_free_inst, .setup_ramfc = vgpu_channel_setup_ramfc, - .channel_set_priority = vgpu_channel_set_priority, .channel_set_timeslice = vgpu_channel_set_timeslice, .default_timeslice_us = vgpu_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, -- cgit v1.2.2 From 77a90d0b8d2eb1bbb207ae5f46b357f2d7cd07ab Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 14 Nov 2017 14:57:25 -0800 Subject: gpu: nvgpu: gv11b: modify dma alloc flags Call nvgpu_dma_alloc_flags_sys without NVGPU_DMA_NO_KERNEL_MAPPING flags, since it makes CMA memory handling simple in t194 and fixes error during subcontext header free: [ 340.378910] trying to free invalid coherent area: ffffffc0135ba000^M [ 340.378921] ------------[ cut here ]------------^M [ 340.378933] WARNING: CPU: 0 PID: 1618 at /code/volta/kernel/kernel-4.9/arch/arm64/mm/dma-mapping.c:1442 __arm_dma_free.isra.4+0x160/0x168^M [ 340.378950] Modules linked in: nvgpu^M [ 340.378958] ^M [ 340.378966] CPU: 0 PID: 1618 Comm: nvogtest Tainted: G W 4.9.52-tegra-g170e0c4 #20^M [ 340.378979] Hardware name: t194pre_si (DT)^M [ 340.378988] task: ffffffc018930d80 task.stack: ffffffc017e08000^M [ 340.378999] PC is at __arm_dma_free.isra.4+0x160/0x168^M [ 340.379009] LR is at __arm_dma_free.isra.4+0x160/0x168^M [ 340.379020] pc : [] lr : [] pstate: 60400045^M [ 340.379032] sp : ffffffc017e0bbe0^M [ 340.379039] x29: ffffffc017e0bbe0 x28: 00000000935ba000 ^M [ 340.379051] x27: 0000000000001000 x26: ffffffc0135b9580 ^M [ 340.379063] x25: ffffff8009ced1b0 x24: 0000000000000010 ^M [ 340.379075] x23: ffffffc070746010 x22: 0000000080000000 ^M [ 340.379088] x21: ffffffbf004d6e80 x20: ffffffc0135ba000 ^M [ 340.379100] x19: 0000000000001000 x18: ffffffffffffffff ^M [ 340.379112] x17: 0000007fa4d8fc60 x16: ffffff800823e370 ^M [ 340.379124] x15: ffffff8009cd8690 x14: ffffff8089fb34bf ^M [ 340.379135] x13: ffffff8009fb34cd x12: 0000000000000007 ^M [ 340.379147] x11: 0000000000000325 x10: 0000000005f5e0ff ^M [ 340.379159] x9 : 0000000000000326 x8 : 3331306366666666 ^M [ 340.379172] x7 : 6666203a61657261 x6 : ffffff8009fb3505 ^M [ 340.379184] x5 : 0000000000000012 x4 : 0000000000000000 ^M [ 340.379196] x3 : 0000000000010000 x2 : 0000000000040934 ^M [ 340.379207] x1 : 0000000000000000 x0 : 0000000000000036 ^M [ 340.379219] ^M [ 340.379224] ---[ end trace 9e7ab41f55eb32d2 ]---^M [ 340.379232] Call trace:^M [ 340.379241] [] __arm_dma_free.isra.4+0x160/0x168^M [ 340.379254] [] arm_dma_free+0x48/0x60^M [ 340.379827] [] nvgpu_dma_free+0x260/0x410 [nvgpu]^M [ 340.380403] [] gv11b_free_subctx_header+0x5c/0x80 [nvgpu]^M [ 340.380980] [] gk20a_free_channel_ctx+0x3c/0x150 [nvgpu]^M After changing dma alloc flags to none, this issue got fixed. Bug 1930032 Change-Id: I002236373c6a3ae5d7ec80a35f166429821662b7 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1598193 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 864e24f0..fe1aa8a5 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -65,7 +65,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) if (ctx->mem.gpu_va == 0) { ret = nvgpu_dma_alloc_flags_sys(g, - NVGPU_DMA_NO_KERNEL_MAPPING, + 0, /* No Special flags */ ctxsw_prog_fecs_header_v(), &ctx->mem); if (ret) { -- cgit v1.2.2