From b25d5d86caa049201ddcea77cf1a733a85090698 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 29 Aug 2018 09:42:41 -0700 Subject: gpu: nvgpu: Use debug sig for NVDEC if on dbg SKU Debug fused chips do not have production signature. Use debug signature for memory unlock binary. Requires also exporting a HAL for checking debug mode from PMU. Bug 200445202 Change-Id: I7f88ed6db2fe1c614fe9d4074dbf974c3817f453 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1809225 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fb/fb_gv100.c | 20 +++++++++++++++----- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 8 +------- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 + drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 6 ++++++ drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | 1 + drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 10 files changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.c b/drivers/gpu/nvgpu/common/fb/fb_gv100.c index ce51a2c6..848d6efb 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv100.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.c @@ -104,11 +104,20 @@ void gv100_fb_disable_hub_intr(struct gk20a *g) * @brief Patch signatures into ucode image */ static int gv100_fb_acr_ucode_patch_sig(struct gk20a *g, - unsigned int *p_img, - unsigned int *p_sig, - unsigned int *p_patch_loc, - unsigned int *p_patch_ind) + u32 *p_img, + u32 *p_prod_sig, + u32 *p_dbg_sig, + u32 *p_patch_loc, + u32 *p_patch_ind) { + u32 *p_sig; + + if (!g->ops.pmu.is_debug_mode_enabled(g)) { + p_sig = p_prod_sig; + } else { + p_sig = p_dbg_sig; + } + /* Patching logic. We have just one location to patch. */ p_img[(*p_patch_loc>>2)] = p_sig[(*p_patch_ind<<2)]; p_img[(*p_patch_loc>>2)+1U] = p_sig[(*p_patch_ind<<2)+1U]; @@ -158,9 +167,10 @@ int gv100_fb_memory_unlock(struct gk20a *g) mem_unlock_ucode = (u32 *)(mem_unlock_fw->data + hsbin_hdr->data_offset); - /* Patch Ucode singnatures */ + /* Patch Ucode signatures */ if (gv100_fb_acr_ucode_patch_sig(g, mem_unlock_ucode, (u32 *)(mem_unlock_fw->data + fw_hdr->sig_prod_offset), + (u32 *)(mem_unlock_fw->data + fw_hdr->sig_dbg_offset), (u32 *)(mem_unlock_fw->data + fw_hdr->patch_loc), (u32 *)(mem_unlock_fw->data + fw_hdr->patch_sig)) < 0) { nvgpu_err(g, "mem unlock patch signatures fail"); diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 93a5bb23..ac1226fc 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -1075,6 +1075,7 @@ struct gpu_ops { u32 (*get_irqdest)(struct gk20a *g); int (*alloc_super_surface)(struct gk20a *g, struct nvgpu_mem *super_surface, u32 size); + bool (*is_debug_mode_enabled)(struct gk20a *g); } pmu; struct { int (*init_debugfs)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 9725ebe7..24112dd3 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c @@ -1141,12 +1141,6 @@ err_release_acr_fw: return err; } -static u8 pmu_is_debug_mode_en(struct gk20a *g) -{ - u32 ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r()); - return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat); -} - /* * @brief Patch signatures into ucode image */ @@ -1160,7 +1154,7 @@ int acr_ucode_patch_sig(struct gk20a *g, unsigned int i, *p_sig; nvgpu_pmu_dbg(g, " "); - if (!pmu_is_debug_mode_en(g)) { + if (!g->ops.pmu.is_debug_mode_enabled(g)) { p_sig = p_prod_sig; nvgpu_pmu_dbg(g, "PRODUCTION MODE\n"); } else { diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 835d18d4..a2b23cca 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -550,6 +550,7 @@ static const struct gpu_ops gm20b_ops = { .reset_engine = gk20a_pmu_engine_reset, .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, .get_irqdest = gk20a_pmu_get_irqdest, + .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, }, .clk = { .init_clk_support = gm20b_init_clk_support, diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 38970f73..a46f8807 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c @@ -271,3 +271,9 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g) nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); } + +bool gm20b_pmu_is_debug_mode_en(struct gk20a *g) +{ + u32 ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r()); + return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U; +} diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h index ec50fb06..1923c047 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h @@ -33,5 +33,6 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g); void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags); int gm20b_pmu_init_acr(struct gk20a *g); void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); +bool gm20b_pmu_is_debug_mode_en(struct gk20a *g); #endif /*__PMU_GM20B_H_*/ diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 54648f56..78a3ea63 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -668,6 +668,7 @@ static const struct gpu_ops gp106_ops = { .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, .get_irqdest = gk20a_pmu_get_irqdest, .alloc_super_surface = NULL, + .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, }, .clk = { .init_clk_support = gp106_init_clk_support, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 8412092a..f4ae1314 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -610,6 +610,7 @@ static const struct gpu_ops gp10b_ops = { .reset_engine = gk20a_pmu_engine_reset, .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, .get_irqdest = gk20a_pmu_get_irqdest, + .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, }, .regops = { .exec_regops = exec_regops_gk20a, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 789fe8d9..339d7813 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -764,6 +764,7 @@ static const struct gpu_ops gv100_ops = { .pmu_get_queue_tail = pwr_pmu_queue_tail_r, .get_irqdest = gk20a_pmu_get_irqdest, .alloc_super_surface = nvgpu_pmu_super_surface_alloc, + .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, }, .clk = { .init_clk_support = gp106_init_clk_support, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a295f774..ff9fc8c6 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -706,6 +706,7 @@ static const struct gpu_ops gv11b_ops = { .is_pmu_supported = gv11b_is_pmu_supported, .get_irqdest = gv11b_pmu_get_irqdest, .handle_ext_irq = gv11b_pmu_handle_ext_irq, + .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, }, .regops = { .exec_regops = exec_regops_gk20a, -- cgit v1.2.2