From ae175e45edc5807131dfb1b63d3e4795e96a3f86 Mon Sep 17 00:00:00 2001 From: Divya Singhatwaria Date: Tue, 23 Jul 2019 10:43:35 +0530 Subject: gpu: nvgpu: Use TPC_PG_MASK to powergate the TPC - In GV11B, read fuse_status_opt_tpc_gpc register to read which TPCs are floorswept. - The driver will also read sysfs node: tpc_pg_mask - Based on these two values "can_tpc_powergate" will be set to true or false and mask will be used to write to fuse_ctrl_opt_tpc_gpc register to powergate the TPC. - can_tpc_powergate = true indicates that the mask value sent from userspace is valid and can be used to power gate the desired TPC - can_tpc_powergate = false indicates that the mask value sent from userspace is not valid and cannot be used to power gate the desired TPC. Bug 200532639 Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd Signed-off-by: Divya Singhatwaria Reviewed-on: https://git-master.nvidia.com/r/2159219 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.sources | 1 + drivers/gpu/nvgpu/gk20a/gk20a.c | 22 ++++--- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 5 ++ drivers/gpu/nvgpu/gp106/hal_gp106.c | 4 ++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 ++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 5 ++ drivers/gpu/nvgpu/gv11b/tpc_gv11b.c | 70 +++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/tpc_gv11b.h | 32 +++++++++++ drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 6 +- drivers/gpu/nvgpu/os/linux/module.c | 3 +- drivers/gpu/nvgpu/os/linux/platform_gk20a.h | 4 +- drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c | 25 +++++--- drivers/gpu/nvgpu/os/linux/sysfs.c | 28 ++++----- 14 files changed, 177 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/nvgpu/gv11b/tpc_gv11b.c create mode 100644 drivers/gpu/nvgpu/gv11b/tpc_gv11b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 827d7df5..bec1809b 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -330,6 +330,7 @@ nvgpu-y += \ gv11b/subctx_gv11b.o \ gv11b/regops_gv11b.o \ gv11b/ecc_gv11b.o \ + gv11b/tpc_gv11b.o \ gv100/mm_gv100.o \ gv100/gr_ctx_gv100.o \ gv100/bios_gv100.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 183da6a5..03bc8bcd 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -197,6 +197,7 @@ srcs := os/posix/nvgpu.c \ gv11b/subctx_gv11b.c \ gv11b/regops_gv11b.c \ gv11b/ecc_gv11b.c \ + gv11b/tpc_gv11b.c \ gp106/hal_gp106.c \ gp106/flcn_gp106.c \ gp106/pmu_gp106.c \ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 7ae1febc..347658b2 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -1,7 +1,7 @@ /* * GK20A Graphics * - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -126,6 +126,8 @@ int gk20a_finalize_poweron(struct gk20a *g) u32 nr_pages; #endif + u32 fuse_status; + nvgpu_log_fn(g, " "); if (g->power_on) { @@ -264,14 +266,20 @@ int gk20a_finalize_poweron(struct gk20a *g) g->ops.mc.intr_enable(g); /* - * Overwrite can_tpc_powergate to false if the chip is ES fused and - * already optimized with some TPCs already floorswept - * via fuse. We will not support TPC-PG in those cases. + * Power gate the chip as per the TPC PG mask + * and the fuse_status register. + * If TPC PG mask is invalid halt the GPU poweron. */ + g->can_tpc_powergate = false; + fuse_status = g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0); + + if (g->ops.tpc.tpc_powergate) { + err = g->ops.tpc.tpc_powergate(g, fuse_status); + } - if (g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0) != 0x0) { - g->can_tpc_powergate = false; - g->tpc_pg_mask = 0x0; + if (err) { + nvgpu_err(g, "failed to power ON GPU"); + goto done; } nvgpu_mutex_acquire(&g->tpc_pg_lock); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 24d13d43..113f6520 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -687,6 +687,9 @@ static const struct gpu_ops gm20b_ops = { .acr = { .acr_sw_init = nvgpu_gm20b_acr_sw_init, }, + .tpc = { + .tpc_powergate = NULL, + }, .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, .get_litter_value = gm20b_get_litter_value, }; @@ -737,6 +740,8 @@ int gm20b_init_hal(struct gk20a *g) gops->fuse = gm20b_ops.fuse; + gops->tpc = gm20b_ops.tpc; + gops->acr = gm20b_ops.acr; /* Lone functions */ diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 86a133d5..d033a516 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -815,6 +815,9 @@ static const struct gpu_ops gp106_ops = { .acr = { .acr_sw_init = nvgpu_gp106_acr_sw_init, }, + .tpc = { + .tpc_powergate = NULL, + }, .get_litter_value = gp106_get_litter_value, .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, }; @@ -870,6 +873,7 @@ int gp106_init_hal(struct gk20a *g) gops->falcon = gp106_ops.falcon; gops->priv_ring = gp106_ops.priv_ring; gops->fuse = gp106_ops.fuse; + gops->tpc = gp106_ops.tpc; gops->acr = gp106_ops.acr; /* Lone functions */ diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 457ae64c..6fd777c0 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -971,6 +971,9 @@ static const struct gpu_ops gv100_ops = { .acr = { .acr_sw_init = nvgpu_gp106_acr_sw_init, }, + .tpc = { + .tpc_powergate = NULL, + }, .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, .get_litter_value = gv100_get_litter_value, }; @@ -1008,6 +1011,7 @@ int gv100_init_hal(struct gk20a *g) gops->falcon = gv100_ops.falcon; gops->priv_ring = gv100_ops.priv_ring; gops->fuse = gv100_ops.fuse; + gops->tpc = gv100_ops.tpc; gops->nvlink = gv100_ops.nvlink; gops->top = gv100_ops.top; gops->acr = gv100_ops.acr; diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 6b4eeb88..2225e380 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -88,6 +88,7 @@ #include "regops_gv11b.h" #include "subctx_gv11b.h" #include "ecc_gv11b.h" +#include "tpc_gv11b.h" #include #include @@ -859,6 +860,9 @@ static const struct gpu_ops gv11b_ops = { .acr = { .acr_sw_init = nvgpu_gv11b_acr_sw_init, }, + .tpc = { + .tpc_powergate = gv11b_tpc_powergate, + }, .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; @@ -893,6 +897,7 @@ int gv11b_init_hal(struct gk20a *g) gops->falcon = gv11b_ops.falcon; gops->priv_ring = gv11b_ops.priv_ring; gops->fuse = gv11b_ops.fuse; + gops->tpc = gv11b_ops.tpc; gops->clk_arb = gv11b_ops.clk_arb; gops->acr = gv11b_ops.acr; diff --git a/drivers/gpu/nvgpu/gv11b/tpc_gv11b.c b/drivers/gpu/nvgpu/gv11b/tpc_gv11b.c new file mode 100644 index 00000000..3177870c --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/tpc_gv11b.c @@ -0,0 +1,70 @@ +/* + * GV11B TPC + * + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include +#include "tpc_gv11b.h" + +int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status) +{ + int err = 0; + + if (fuse_status == 0x0) { + g->can_tpc_powergate = true; + + } else { + /* if hardware has already floorswept any TPC + * (fuse_status != 0x0) and if TPC PG mask + * sent from userspace is 0x0 GPU will be powered on + * with the default fuse_status setting. It cannot + * un-floorsweep any TPC + * thus, set g->tpc_pg_mask to fuse_status value + */ + if (g->tpc_pg_mask == 0x0) { + g->can_tpc_powergate = true; + g->tpc_pg_mask = fuse_status; + + } else if (fuse_status == g->tpc_pg_mask) { + g->can_tpc_powergate = true; + + } else if ((fuse_status & g->tpc_pg_mask) == + fuse_status) { + g->can_tpc_powergate = true; + + } else { + /* If userspace sends a TPC PG mask such that + * it tries to un-floorsweep any TPC which is + * already powergated from hardware, then + * such mask is invalid. + * In this case set tpc pg mask to 0x0 + * Return -EINVAL here and halt GPU poweron. + */ + nvgpu_err(g, "Invalid TPC_PG mask: 0x%x", + g->tpc_pg_mask); + g->can_tpc_powergate = false; + g->tpc_pg_mask = 0x0; + err = -EINVAL; + } + } + + return err; +} diff --git a/drivers/gpu/nvgpu/gv11b/tpc_gv11b.h b/drivers/gpu/nvgpu/gv11b/tpc_gv11b.h new file mode 100644 index 00000000..e860c22d --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/tpc_gv11b.h @@ -0,0 +1,32 @@ +/* + * GV11B TPC + * + * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_TPC_GV11B_H +#define NVGPU_TPC_GV11B_H + +struct gk20a; + +int gv11b_tpc_powergate(struct gk20a *g, u32 fuse_status); + +#endif /* NVGPU_TPC_GV11B_H */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 7ed4c714..c9002f47 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -149,7 +149,7 @@ enum gk20a_cbc_op { #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) -#define MAX_TPC_PG_CONFIGS 3 +#define MAX_TPC_PG_CONFIGS 9 enum nvgpu_unit; @@ -1348,6 +1348,9 @@ struct gpu_ops { struct { void (*acr_sw_init)(struct gk20a *g, struct nvgpu_acr *acr); } acr; + struct { + int (*tpc_powergate)(struct gk20a *g, u32 fuse_status); + } tpc; void (*semaphore_wakeup)(struct gk20a *g, bool post_events); }; @@ -1615,6 +1618,7 @@ struct gk20a { u32 tpc_fs_mask_user; u32 tpc_pg_mask; + u32 tpc_count; bool can_tpc_powergate; u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS]; diff --git a/drivers/gpu/nvgpu/os/linux/module.c b/drivers/gpu/nvgpu/os/linux/module.c index 964fc651..a81d837b 100644 --- a/drivers/gpu/nvgpu/os/linux/module.c +++ b/drivers/gpu/nvgpu/os/linux/module.c @@ -1200,7 +1200,8 @@ static int nvgpu_read_fuse_overrides(struct gk20a *g) break; case GV11B_FUSE_OPT_TPC_DISABLE: if (platform->set_tpc_pg_mask != NULL) - platform->set_tpc_pg_mask(dev_from_gk20a(g), value); + platform->set_tpc_pg_mask(dev_from_gk20a(g), + value); break; default: nvgpu_err(g, "ignore unknown fuse override %08x", fuse); diff --git a/drivers/gpu/nvgpu/os/linux/platform_gk20a.h b/drivers/gpu/nvgpu/os/linux/platform_gk20a.h index 2ddadd2e..adec8607 100644 --- a/drivers/gpu/nvgpu/os/linux/platform_gk20a.h +++ b/drivers/gpu/nvgpu/os/linux/platform_gk20a.h @@ -196,8 +196,8 @@ struct gk20a_platform { /* Pre callback is called before frequency change */ void (*prescale)(struct device *dev); - /* Set TPC_PG during probe */ - void (*set_tpc_pg_mask)(struct device *dev, u32 tpc_mask); + /* Set TPC_PG_MASK during probe */ + void (*set_tpc_pg_mask)(struct device *dev, u32 tpc_pg_mask); /* Devfreq governor name. If scaling is enabled, we request * this governor to be used in scaling */ diff --git a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c index 4a94c1cd..ac1958a2 100644 --- a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c @@ -218,26 +218,29 @@ static int gv11b_tegra_suspend(struct device *dev) return 0; } -static bool is_tpc_mask_valid(struct gk20a_platform *platform, u32 tpc_mask) +static bool is_tpc_mask_valid(struct gk20a_platform *platform, u32 tpc_pg_mask) { u32 i; bool valid = false; for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) { - if (tpc_mask == platform->valid_tpc_mask[i]) + if (tpc_pg_mask == platform->valid_tpc_mask[i]) { valid = true; + break; + } } return valid; } -static void gv11b_tegra_set_tpc_pg_mask(struct device *dev, u32 tpc_mask) +static void gv11b_tegra_set_tpc_pg_mask(struct device *dev, u32 tpc_pg_mask) { struct gk20a_platform *platform = gk20a_get_platform(dev); struct gk20a *g = get_gk20a(dev); - if (is_tpc_mask_valid(platform, tpc_mask)) { - g->tpc_pg_mask = tpc_mask; + if (is_tpc_mask_valid(platform, tpc_pg_mask)) { + g->tpc_pg_mask = tpc_pg_mask; } + } struct gk20a_platform gv11b_tegra_platform = { @@ -257,9 +260,15 @@ struct gk20a_platform gv11b_tegra_platform = { .can_tpc_powergate = true, .valid_tpc_mask[0] = 0x0, .valid_tpc_mask[1] = 0x1, - .valid_tpc_mask[2] = 0x5, - - .set_tpc_pg_mask = gv11b_tegra_set_tpc_pg_mask, + .valid_tpc_mask[2] = 0x2, + .valid_tpc_mask[3] = 0x4, + .valid_tpc_mask[4] = 0x8, + .valid_tpc_mask[5] = 0x5, + .valid_tpc_mask[6] = 0x6, + .valid_tpc_mask[7] = 0x9, + .valid_tpc_mask[8] = 0xa, + + .set_tpc_pg_mask = gv11b_tegra_set_tpc_pg_mask, .can_slcg = true, .can_blcg = true, diff --git a/drivers/gpu/nvgpu/os/linux/sysfs.c b/drivers/gpu/nvgpu/os/linux/sysfs.c index 759c12e8..2ab29649 100644 --- a/drivers/gpu/nvgpu/os/linux/sysfs.c +++ b/drivers/gpu/nvgpu/os/linux/sysfs.c @@ -788,26 +788,28 @@ static ssize_t force_idle_read(struct device *dev, static DEVICE_ATTR(force_idle, ROOTRW, force_idle_read, force_idle_store); #endif -static ssize_t tpc_pg_mask_read(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct gk20a *g = get_gk20a(dev); - - return snprintf(buf, PAGE_SIZE, "%d\n", g->tpc_pg_mask); -} - static bool is_tpc_mask_valid(struct gk20a *g, u32 tpc_mask) { u32 i; bool valid = false; for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) { - if (tpc_mask == g->valid_tpc_mask[i]) + if (tpc_mask == g->valid_tpc_mask[i]) { valid = true; + break; + } } return valid; } +static ssize_t tpc_pg_mask_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gk20a *g = get_gk20a(dev); + + return snprintf(buf, PAGE_SIZE, "%d\n", g->tpc_pg_mask); +} + static ssize_t tpc_pg_mask_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -817,11 +819,6 @@ static ssize_t tpc_pg_mask_store(struct device *dev, nvgpu_mutex_acquire(&g->tpc_pg_lock); - if (!g->can_tpc_powergate) { - nvgpu_info(g, "TPC-PG not enabled for the platform"); - goto exit; - } - if (kstrtoul(buf, 10, &val) < 0) { nvgpu_err(g, "invalid value"); nvgpu_mutex_release(&g->tpc_pg_lock); @@ -839,6 +836,9 @@ static ssize_t tpc_pg_mask_store(struct device *dev, return -ENODEV; } + /* checking that the value from userspace is within + * the possible valid TPC configurations. + */ if (is_tpc_mask_valid(g, (u32)val)) { g->tpc_pg_mask = val; } else { -- cgit v1.2.2