From a8cf64019f74dd05626a911af3df079efd9c7c89 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 1 May 2017 15:31:00 -0700 Subject: gpu: nvgpu: Introduce priv ring HAL and define ISR Introduce a priv ring HAL and define ISR as the only function in it. Introduce a gp10b version of the ISR that writes error message to UART for every priv ring error, and leave the old chips with silent error handling. Bug 1846641 Change-Id: I73e38396205ac7bb7b8488b7fbca3ff67a3db3bb Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1473696 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile.nvgpu | 1 + drivers/gpu/nvgpu/gk20a/gk20a.h | 3 ++ drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 2 + drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 5 ++ drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h | 9 ++-- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 4 +- drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 +- drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c | 82 +++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h | 22 +++++++++ 10 files changed, 127 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index 59c81826..411e06cc 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu @@ -165,6 +165,7 @@ nvgpu-y += \ gp10b/therm_gp10b.o \ gp10b/fecs_trace_gp10b.o \ gp10b/gp10b_sysfs.o \ + gp10b/priv_ring_gp10b.o \ gp10b/gp10b.o \ gp106/hal_gp106.o \ gp106/mm_gp106.o \ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 03f61c33..626ed2bd 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -886,6 +886,9 @@ struct gpu_ops { struct { void (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn); } falcon; + struct { + void (*isr)(struct gk20a *g); + } priv_ring; }; struct nvgpu_bios_ucode { diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index 3dbe856d..729a277f 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c @@ -35,6 +35,7 @@ #include "dbg_gpu_gk20a.h" #include "css_gr_gk20a.h" #include "pramin_gk20a.h" +#include "priv_ring_gk20a.h" #include #include @@ -155,6 +156,7 @@ int gk20a_init_hal(struct gk20a *g) gops->pmupstate = false; gk20a_init_bus(gops); gk20a_init_mc(gops); + gk20a_init_priv_ring(gops); gk20a_init_ltc(gops); gk20a_init_gr_ops(gops); gk20a_init_fecs_trace_ops(gops); diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index 96e21d2d..2f837bfc 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c @@ -94,3 +94,8 @@ void gk20a_priv_ring_isr(struct gk20a *g) if (retry <= 0) nvgpu_warn(g, "priv ringmaster cmd ack too many retries"); } + +void gk20a_init_priv_ring(struct gpu_ops *gops) +{ + gops->priv_ring.isr = gk20a_priv_ring_isr; +} diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h index 8a6320d7..61780288 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h @@ -11,15 +11,14 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. */ #ifndef __PRIV_RING_GK20A_H__ #define __PRIV_RING_GK20A_H__ -void gk20a_enable_priv_ring(struct gk20a *g); +struct gpu_ops; + void gk20a_priv_ring_isr(struct gk20a *g); +void gk20a_enable_priv_ring(struct gk20a *g); +void gk20a_init_priv_ring(struct gpu_ops *gops); #endif /*__PRIV_RING_GK20A_H__*/ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 62cd6119..fbeed3c2 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -1,7 +1,7 @@ /* * GM20B Graphics * - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,6 +18,7 @@ #include "gk20a/css_gr_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" +#include "gk20a/priv_ring_gk20a.h" #include "ltc_gm20b.h" #include "ce2_gm20b.h" @@ -218,6 +219,7 @@ int gm20b_init_hal(struct gk20a *g) #endif gk20a_init_bus(gops); gm20b_init_mc(gops); + gk20a_init_priv_ring(gops); gm20b_init_ltc(gops); gm20b_init_gr(gops); gm20b_init_ltc(gops); diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index e39843ac..3f64283a 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -27,6 +27,7 @@ #include "gp10b/ce_gp10b.h" #include "gp10b/regops_gp10b.h" #include "gp10b/cde_gp10b.h" +#include "gp10b/priv_ring_gp10b.h" #include "gp106/fifo_gp106.h" #include "gp106/regops_gp106.h" @@ -232,6 +233,7 @@ int gp106_init_hal(struct gk20a *g) gops->pmupstate = true; gk20a_init_bus(gops); gp10b_init_mc(gops); + gp10b_init_priv_ring(gops); gp106_init_gr(gops); gp10b_init_fecs_trace_ops(gops); gp106_init_ltc(gops); diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 40e49e13..1d3ad275 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B Tegra HAL interface * - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -34,6 +34,7 @@ #include "gp10b/regops_gp10b.h" #include "gp10b/cde_gp10b.h" #include "gp10b/therm_gp10b.h" +#include "gp10b/priv_ring_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" @@ -233,6 +234,7 @@ int gp10b_init_hal(struct gk20a *g) gk20a_init_bus(gops); gp10b_init_mc(gops); + gp10b_init_priv_ring(gops); gp10b_init_gr(gops); gp10b_init_fecs_trace_ops(gops); gp10b_init_ltc(gops); diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c new file mode 100644 index 00000000..7cdbec5e --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c @@ -0,0 +1,82 @@ +/* + * GP10B priv ring + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "gk20a/gk20a.h" + +#include +#include + +#include +#include +#include +#include + +static void gp10b_priv_ring_isr(struct gk20a *g) +{ + u32 status0, status1; + u32 cmd; + s32 retry = 100; + u32 gpc; + u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); + + if (g->is_fmodel) + return; + + status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); + status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); + + nvgpu_err(g, "ringmaster intr status0: 0x%08x," + "status1: 0x%08x", status0, status1); + + if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { + nvgpu_err(g, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", + gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), + gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), + gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()), + gk20a_readl(g, pri_ringstation_sys_priv_error_code_r())); + } + + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + if (status1 & BIT(gpc)) { + nvgpu_err(g, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride), + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride), + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride), + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride)); + } + } + + cmd = gk20a_readl(g, pri_ringmaster_command_r()); + cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), + pri_ringmaster_command_cmd_ack_interrupt_f()); + gk20a_writel(g, pri_ringmaster_command_r(), cmd); + + do { + cmd = pri_ringmaster_command_cmd_v( + gk20a_readl(g, pri_ringmaster_command_r())); + nvgpu_usleep_range(20, 40); + } while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && --retry); + + if (retry <= 0) + nvgpu_warn(g, "priv ringmaster cmd ack too many retries"); +} + +void gp10b_init_priv_ring(struct gpu_ops *gops) +{ + gops->priv_ring.isr = gp10b_priv_ring_isr; +} diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h new file mode 100644 index 00000000..acd0857f --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h @@ -0,0 +1,22 @@ +/* + * GP10B PRIV ringmaster + * + * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef __PRIV_RING_GP10B_H__ +#define __PRIV_RING_GP10B_H__ + +struct gpu_ops; + +void gp10b_init_priv_ring(struct gpu_ops *gops); + +#endif /*__PRIV_RING_GP10B_H__*/ -- cgit v1.2.2