From a37cec19f0cf5212cbd472cd8d94acaa1e1cff6d Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Mon, 30 Oct 2017 15:55:11 -0700 Subject: gpu: nvgpu: vgpu: modify tsg enable sequence TSG enable sequence in native has been modified due to a hardware bug requiring enabling all channels with NEXT and CTX_RELOAD set in a TSG, and then enabling rest of channels. However it is not possible to check if NEXT and CTX_RELOAD is set in vgpu. Have a separate implementation for enabling tsg sequence in vgpu till the fix for hardware bug is implemented for virtualized configuration. Bug 200348087 Change-Id: I6bfc52138bc540c0ea0ad18a85155eeff6f9efa8 Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1588740 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | 1 + drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c | 2 +- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 2 +- drivers/gpu/nvgpu/vgpu/tsg_vgpu.c | 13 +++++++++++++ 4 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h index c5a51f97..aa95cc41 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h @@ -61,5 +61,6 @@ int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, struct channel_gk20a *ch); int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); +int vgpu_enable_tsg(struct tsg_gk20a *tsg); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c index bc6d2e69..05295fa0 100644 --- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c @@ -275,7 +275,7 @@ static const struct gpu_ops vgpu_gm20b_ops = { .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, .preempt_channel = vgpu_fifo_preempt_channel, .preempt_tsg = vgpu_fifo_preempt_tsg, - .enable_tsg = gk20a_enable_tsg, + .enable_tsg = vgpu_enable_tsg, .disable_tsg = gk20a_disable_tsg, .tsg_verify_channel_status = NULL, .tsg_verify_status_ctx_reload = NULL, diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index b8d09b88..04fb286a 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -300,7 +300,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, .preempt_channel = vgpu_fifo_preempt_channel, .preempt_tsg = vgpu_fifo_preempt_tsg, - .enable_tsg = gk20a_enable_tsg, + .enable_tsg = vgpu_enable_tsg, .disable_tsg = gk20a_disable_tsg, .tsg_verify_channel_status = NULL, .tsg_verify_status_ctx_reload = NULL, diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c index 2be102e3..94d7140e 100644 --- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c @@ -53,6 +53,19 @@ int vgpu_tsg_open(struct tsg_gk20a *tsg) return err; } +int vgpu_enable_tsg(struct tsg_gk20a *tsg) +{ + struct gk20a *g = tsg->g; + struct channel_gk20a *ch; + + nvgpu_rwsem_down_read(&tsg->ch_list_lock); + nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) + g->ops.fifo.enable_channel(ch); + nvgpu_rwsem_up_read(&tsg->ch_list_lock); + + return 0; +} + int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, struct channel_gk20a *ch) { -- cgit v1.2.2