From 96615351ad11a186f5869e56acb3c1948ab7b7cc Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 14:23:01 -0700 Subject: gpu: nvgpu: gv11b: Reorg mm HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic2c7d56e552645f2125d9c60a817967be1e8e765 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1533355 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 32 +++++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 32 ++++++++------------------------ drivers/gpu/nvgpu/gv11b/mm_gv11b.h | 17 +++++++++++++++-- 3 files changed, 54 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9f6c67c1..afc90aa7 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,6 +25,7 @@ #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -35,6 +36,7 @@ #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" +#include "gm20b/mm_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/therm_gp10b.h" @@ -44,6 +46,7 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/fb_gp10b.h" +#include "gp10b/mm_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -60,6 +63,8 @@ #include "regops_gv11b.h" #include "subctx_gv11b.h" +#include "common/linux/platform_gk20a_tegra.h" + #include #include @@ -333,6 +338,31 @@ static const struct gpu_ops gv11b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gv11b_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gv11b_gpu_phys_addr, + .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = gv11b_init_mm_setup_hw, + .is_bar1_supported = gv11b_mm_is_bar1_supported, + .init_inst_block = gv11b_init_inst_block, + .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gv11b_mm_remove_bar2_vm, + .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + }, .therm = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, @@ -429,6 +459,7 @@ int gv11b_init_hal(struct gk20a *g) gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; + gops->mm = gv11b_ops.mm; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; gops->regops = gv11b_ops.regops; @@ -453,7 +484,6 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 7ba8f74f..941a0bbe 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -34,12 +34,12 @@ #define NVGPU_L3_ALLOC_BIT BIT(36) -static bool gv11b_mm_is_bar1_supported(struct gk20a *g) +bool gv11b_mm_is_bar1_supported(struct gk20a *g) { return false; } -static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, +void gv11b_init_inst_block(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, u32 big_page_size) { struct gk20a *g = gk20a_from_vm(vm); @@ -53,12 +53,12 @@ static void gv11b_init_inst_block(struct nvgpu_mem *inst_block, g->ops.mm.set_big_page_size(g, inst_block, big_page_size); } -static bool gv11b_mm_mmu_fault_pending(struct gk20a *g) +bool gv11b_mm_mmu_fault_pending(struct gk20a *g) { return gv11b_fb_mmu_fault_pending(g); } -static void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) +void gv11b_mm_fault_info_mem_destroy(struct gk20a *g) { nvgpu_log_fn(g, " "); @@ -174,7 +174,7 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g) } } -static void gv11b_mm_remove_bar2_vm(struct gk20a *g) +void gv11b_mm_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -221,7 +221,7 @@ static int gv11b_mm_mmu_fault_setup_sw(struct gk20a *g) return err; } -static int gv11b_init_mm_setup_hw(struct gk20a *g) +int gv11b_init_mm_setup_hw(struct gk20a *g) { int err = 0; @@ -260,7 +260,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) * checking bit 36 of the phsyical address. So if a mapping should allocte lines * in the L3 this bit must be set. */ -static u64 gv11b_gpu_phys_addr(struct gk20a *g, +u64 gv11b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys) { if (attrs && attrs->t19x_attrs.l3_alloc) @@ -269,7 +269,7 @@ static u64 gv11b_gpu_phys_addr(struct gk20a *g, return phys; } -static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) +int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; @@ -318,19 +318,3 @@ static int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); return -EBUSY; } - -void gv11b_init_mm(struct gpu_ops *gops) -{ - gp10b_init_mm(gops); - gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; - gops->mm.is_bar1_supported = gv11b_mm_is_bar1_supported; - gops->mm.init_inst_block = gv11b_init_inst_block; - gops->mm.mmu_fault_pending = gv11b_mm_mmu_fault_pending; - gops->mm.l2_flush = gv11b_mm_l2_flush; - gops->mm.gpu_phys_addr = gv11b_gpu_phys_addr; - gops->mm.init_mm_setup_hw = gv11b_init_mm_setup_hw; - gops->mm.fault_info_mem_destroy = - gv11b_mm_fault_info_mem_destroy; - gops->mm.remove_bar2_vm = gv11b_mm_remove_bar2_vm; - gops->mm.init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup; -} diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h index a887c7f4..12f0fe63 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h @@ -18,7 +18,20 @@ #define HW_FAULT_BUF_STATUS_ALLOC_TRUE 1 #define HW_FAULT_BUF_STATUS_ALLOC_FALSE 0 -struct gpu_ops; +struct gk20a; +struct nvgpu_mem; +struct vm_gk20a; + +bool gv11b_mm_is_bar1_supported(struct gk20a *g); +void gv11b_init_inst_block(struct nvgpu_mem *inst_block, + struct vm_gk20a *vm, u32 big_page_size); +bool gv11b_mm_mmu_fault_pending(struct gk20a *g); +void gv11b_mm_remove_bar2_vm(struct gk20a *g); +int gv11b_init_mm_setup_hw(struct gk20a *g); +int gv11b_init_bar2_mm_hw_setup(struct gk20a *g); +void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate); +u64 gv11b_gpu_phys_addr(struct gk20a *g, + struct nvgpu_gmmu_attrs *attrs, u64 phys); +void gv11b_mm_fault_info_mem_destroy(struct gk20a *g); -void gv11b_init_mm(struct gpu_ops *gops); #endif -- cgit v1.2.2