From 8fb33d92b03b9ee2db421c69252822d09477cce5 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 14 Jan 2016 17:40:48 -0800 Subject: gpu: nvgpu: vgpu: add channel_set_priority support - add gops.fifo.channel_set_priority and move current code as native callback. - implement the callback for vgpu Bug 1701079 Change-Id: If1cd13ea4478d11d578da2f682598e0c4522bcaf Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/932829 Reviewed-by: Aingara Paramakuru GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 6 +++--- drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 + drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 32 +++++++++++++++++++++++++++++++- include/linux/tegra_vgpu.h | 9 ++++++++- 6 files changed, 45 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 45501d4f..5e5bbcb0 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c @@ -2539,8 +2539,7 @@ unsigned int gk20a_channel_poll(struct file *filep, poll_table *wait) return mask; } -static int gk20a_channel_set_priority(struct channel_gk20a *ch, - u32 priority) +int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority) { u32 timeslice_timeout; bool interleave = false; @@ -2723,6 +2722,7 @@ void gk20a_init_channel(struct gpu_ops *gops) gops->fifo.alloc_inst = channel_gk20a_alloc_inst; gops->fifo.free_inst = channel_gk20a_free_inst; gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; + gops->fifo.channel_set_priority = gk20a_channel_set_priority; } long gk20a_channel_ioctl(struct file *filp, @@ -2897,7 +2897,7 @@ long gk20a_channel_ioctl(struct file *filp, __func__, cmd); break; } - err = gk20a_channel_set_priority(ch, + err = ch->g->ops.fifo.channel_set_priority(ch, ((struct nvgpu_set_priority_args *)buf)->priority); gk20a_idle(dev); break; diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 24a2fe11..0f796ffe 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h @@ -268,5 +268,6 @@ void gk20a_channel_timeout_restart_all_channels(struct gk20a *g); int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, int timeslice_period, int *__timeslice_timeout, int *__timeslice_scale); +int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority); #endif /* CHANNEL_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 2b4c3237..a58a1eed 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -260,6 +260,7 @@ struct gpu_ops { int (*wait_engine_idle)(struct gk20a *g); u32 (*get_num_fifos)(struct gk20a *g); u32 (*get_pbdma_signature)(struct gk20a *g); + int (*channel_set_priority)(struct channel_gk20a *ch, u32 priority); } fifo; struct pmu_v { /*used for change of enum zbc update cmd id from ver 0 to ver1*/ diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 0e736373..d1deffb9 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -113,6 +113,7 @@ void gm20b_init_fifo(struct gpu_ops *gops) gops->fifo.alloc_inst = channel_gk20a_alloc_inst; gops->fifo.free_inst = channel_gk20a_free_inst; gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; + gops->fifo.channel_set_priority = gk20a_channel_set_priority; gops->fifo.preempt_channel = gk20a_fifo_preempt_channel; gops->fifo.update_runlist = gk20a_fifo_update_runlist; diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 3db215bc..e776e97c 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c @@ -194,6 +194,12 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) if (!runlist->active_channels) goto clean_up_runlist_info; + runlist->high_prio_channels = + kzalloc(DIV_ROUND_UP(f->num_channels, BITS_PER_BYTE), + GFP_KERNEL); + if (!runlist->high_prio_channels) + goto clean_up_runlist_info; + runlist_size = sizeof(u16) * f->num_channels; for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) { int err = gk20a_gmmu_alloc(g, runlist_size, &runlist->mem[i]); @@ -215,10 +221,13 @@ clean_up_runlist: for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) gk20a_gmmu_free(g, &runlist->mem[i]); +clean_up_runlist_info: + kfree(runlist->high_prio_channels); + runlist->high_prio_channels = NULL; + kfree(runlist->active_channels); runlist->active_channels = NULL; -clean_up_runlist_info: kfree(f->runlist_info); f->runlist_info = NULL; @@ -521,6 +530,26 @@ static int vgpu_fifo_wait_engine_idle(struct gk20a *g) return 0; } +static int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) +{ + struct gk20a_platform *platform = gk20a_get_platform(ch->g->dev); + struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_channel_priority_params *p = + &msg.params.channel_priority; + int err; + + gk20a_dbg_info("channel %d set priority %u", ch->hw_chid, priority); + + msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY; + msg.handle = platform->virt_handle; + p->handle = ch->virt_ctx; + p->priority = priority; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + WARN_ON(err || msg.ret); + + return err ? err : msg.ret; +} + static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, struct channel_gk20a *ch) { @@ -605,5 +634,6 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops) gops->fifo.preempt_channel = vgpu_fifo_preempt_channel; gops->fifo.update_runlist = vgpu_fifo_update_runlist; gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle; + gops->fifo.channel_set_priority = vgpu_channel_set_priority; } diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index b0e25c60..280ca9c0 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h @@ -73,7 +73,8 @@ enum { TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS, TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, - TEGRA_VGPU_CMD_REG_OPS + TEGRA_VGPU_CMD_REG_OPS, + TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY }; struct tegra_vgpu_connect_params { @@ -292,6 +293,11 @@ struct tegra_vgpu_reg_ops_params { u32 is_profiler; }; +struct tegra_vgpu_channel_priority_params { + u64 handle; + u32 priority; +}; + struct tegra_vgpu_cmd_msg { u32 cmd; int ret; @@ -319,6 +325,7 @@ struct tegra_vgpu_cmd_msg { struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; struct tegra_vgpu_sm_debug_mode sm_debug_mode; struct tegra_vgpu_reg_ops_params reg_ops; + struct tegra_vgpu_channel_priority_params channel_priority; char padding[192]; } params; }; -- cgit v1.2.2