From 8f4a590cf22fa9691953e9be0dca18b399228167 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 16 May 2017 15:10:22 +0530 Subject: gpu: nvgpu: remove TEGRA_CLK_FRAMEWORK support CONFIG_TEGRA_CLK_FRAMEWORK is no longer supported hence remove this config and all the code that is protected with this config Jira NVGPU-49 Change-Id: Ica28019e0c99e95743216e005ba2fba20357b2d5 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1483090 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Kconfig.nvgpu | 4 +- drivers/gpu/nvgpu/gk20a/clk_gk20a.h | 5 - drivers/gpu/nvgpu/gk20a/gk20a.h | 2 - drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c | 4 - drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 1 - drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 106 +------------ .../gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | 170 +-------------------- 7 files changed, 8 insertions(+), 284 deletions(-) diff --git a/drivers/gpu/nvgpu/Kconfig.nvgpu b/drivers/gpu/nvgpu/Kconfig.nvgpu index 4d7e0f12..73904a94 100644 --- a/drivers/gpu/nvgpu/Kconfig.nvgpu +++ b/drivers/gpu/nvgpu/Kconfig.nvgpu @@ -36,7 +36,7 @@ config GK20A_PERFMON decrease frequency if idle). config GK20A_DEVFREQ - depends on TEGRA_CLK_FRAMEWORK || COMMON_CLK + depends on COMMON_CLK bool "Use Devfreq" help Select this to use devfreq based scaling. @@ -104,7 +104,7 @@ config TEGRA_ACR config TEGRA_USE_NA_GPCPLL bool "Enable noise aware mode of GM20B GPCPLL on Tegra" - depends on TEGRA_CLK_FRAMEWORK || COMMON_CLK + depends on COMMON_CLK default n help Enable noise aware (NA) mode of GM20b GPCPLL. In this mode PLL output diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h index f07efa40..76f5de43 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h @@ -104,11 +104,6 @@ struct clk_gk20a { #endif struct gpu_ops; -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK -void gk20a_init_clk_ops(struct gpu_ops *gops); -#else -static inline void gk20a_init_clk_ops(struct gpu_ops *gops) {} -#endif /* APIs used for both GK20A and GM20B */ unsigned long gk20a_clk_get_rate(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 3d1e0847..217b1186 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -1275,8 +1275,6 @@ enum gk20a_nonstall_ops { gk20a_nonstall_ops_post_events = BIT(1), }; -void gk20a_init_clk_ops(struct gpu_ops *gops); - /* register accessors */ int gk20a_lockout_registers(struct gk20a *g); int gk20a_restore_registers(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c index ff9e0fc1..d7642182 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c @@ -23,7 +23,6 @@ #include #include #include -#include #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) #include #endif @@ -717,9 +716,6 @@ static ssize_t fmax_at_vmin_safe_read(struct device *dev, unsigned long gpu_fmax_at_vmin_hz = 0; struct clk *clk = g->clk.tegra_clk; -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK - clk = clk_get_parent(clk); -#endif gpu_fmax_at_vmin_hz = tegra_dvfs_get_fmax_at_vmin_safe_t(clk); return snprintf(buf, PAGE_SIZE, "%d\n", (int)(gpu_fmax_at_vmin_hz)); diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index 729a277f..8a3beb39 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c @@ -167,7 +167,6 @@ int gk20a_init_hal(struct gk20a *g) gk20a_init_mm(gops); gk20a_falcon_init_hal(gops); gk20a_init_pmu_ops(gops); - gk20a_init_clk_ops(gops); gk20a_init_regops(gops); gk20a_init_debug_ops(gops); gk20a_init_dbg_session_ops(gops); diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index d1dbf181..f1f75b74 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -22,7 +22,6 @@ #include #include #endif -#include #include #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) #include @@ -1142,7 +1141,7 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) { struct clk_gk20a *clk = &g->clk; unsigned long safe_rate; - struct clk *ref, *c; + struct clk *ref = NULL, *c; int err; gk20a_dbg_fn(""); @@ -1178,12 +1177,7 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) */ c = clk_get_parent(clk->tegra_clk); -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK - ref = clk_get_parent(clk_get_parent(c)); -#elif defined (CONFIG_COMMON_CLK) ref = clk_get_sys("gpu_ref", "gpu_ref"); -#endif - if (IS_ERR(ref)) { nvgpu_err(g, "failed to get GPCPLL reference clock"); err = -EINVAL; @@ -1474,91 +1468,6 @@ static int set_pll_freq(struct gk20a *g, int allow_slide) return err; } -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK -static int gm20b_clk_export_set_rate(void *data, unsigned long *rate) -{ - u32 old_freq; - int ret = -ENODATA; - struct gk20a *g = data; - struct clk_gk20a *clk = &g->clk; - - if (rate) { - nvgpu_mutex_acquire(&clk->clk_mutex); - old_freq = clk->gpc_pll.freq; - ret = set_pll_target(g, rate_gpu_to_gpc2clk(*rate), old_freq); - if (!ret && clk->gpc_pll.enabled && clk->clk_hw_on) - ret = set_pll_freq(g, 1); - if (!ret) - *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq); - nvgpu_mutex_release(&clk->clk_mutex); - } - return ret; -} - -static int gm20b_clk_export_enable(void *data) -{ - int ret = 0; - struct gk20a *g = data; - struct clk_gk20a *clk = &g->clk; - - nvgpu_mutex_acquire(&clk->clk_mutex); - if (!clk->gpc_pll.enabled && clk->clk_hw_on) - ret = set_pll_freq(g, 1); - nvgpu_mutex_release(&clk->clk_mutex); - return ret; -} - -static void gm20b_clk_export_disable(void *data) -{ - struct gk20a *g = data; - struct clk_gk20a *clk = &g->clk; - - nvgpu_mutex_acquire(&clk->clk_mutex); - if (clk->gpc_pll.enabled && clk->clk_hw_on) - clk_disable_gpcpll(g, 1); - nvgpu_mutex_release(&clk->clk_mutex); -} - -static void gm20b_clk_export_init(void *data, unsigned long *rate, bool *state) -{ - struct gk20a *g = data; - struct clk_gk20a *clk = &g->clk; - - nvgpu_mutex_acquire(&clk->clk_mutex); - if (state) - *state = clk->gpc_pll.enabled; - if (rate) - *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq); - nvgpu_mutex_release(&clk->clk_mutex); -} - -static struct tegra_clk_export_ops gm20b_clk_export_ops = { - .init = gm20b_clk_export_init, - .enable = gm20b_clk_export_enable, - .disable = gm20b_clk_export_disable, - .set_rate = gm20b_clk_export_set_rate, -}; - -static int gm20b_clk_register_export_ops(struct gk20a *g) -{ - int ret; - struct clk *c; - - if (gm20b_clk_export_ops.data) - return 0; - - gm20b_clk_export_ops.data = (void *)g; - c = g->clk.tegra_clk; - if (!c || !clk_get_parent(c)) - return -ENOSYS; - - ret = tegra_clk_register_export_ops(clk_get_parent(c), - &gm20b_clk_export_ops); - - return ret; -} -#endif /* CONFIG_TEGRA_CLK_FRAMEWORK */ - static int gm20b_init_clk_support(struct gk20a *g) { struct clk_gk20a *clk = &g->clk; @@ -1570,13 +1479,6 @@ static int gm20b_init_clk_support(struct gk20a *g) if (err) return err; -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK - clk->g = g; - err = gm20b_init_clk_setup_sw(g); - if (err) - return err; -#endif - nvgpu_mutex_acquire(&clk->clk_mutex); clk->clk_hw_on = true; @@ -1585,12 +1487,6 @@ static int gm20b_init_clk_support(struct gk20a *g) if (err) return err; -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK - err = gm20b_clk_register_export_ops(g); - if (err) - return err; -#endif - /* FIXME: this effectively prevents host level clock gating */ err = clk_prepare_enable(g->clk.tegra_clk); if (err) diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c index 2bb7d5cb..a8a1451a 100644 --- a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c @@ -26,12 +26,9 @@ #include #include #include -#if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS) +#if defined(CONFIG_TEGRA_DVFS) #include #endif -#if defined(CONFIG_TEGRA_CLK_FRAMEWORK) -#include -#endif #include #include #include @@ -391,137 +388,7 @@ done: #endif -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK -/* - * gk20a_tegra_railgate() - * - * Gate (disable) gk20a power rail - */ - -static int gk20a_tegra_railgate(struct device *dev) -{ - struct gk20a *g = get_gk20a(dev); - struct gk20a_platform *platform = dev_get_drvdata(dev); - int ret = 0; - - if (g->is_fmodel || - !tegra_dvfs_is_rail_up(platform->gpu_rail)) - return 0; - - tegra_mc_flush(MC_CLIENT_GPU); - - udelay(10); - - /* enable clamp */ - pmc_write(0x1, PMC_GPU_RG_CNTRL_0); - pmc_read(PMC_GPU_RG_CNTRL_0); - - udelay(10); - - platform->reset_assert(dev); - - udelay(10); - - /* - * GPCPLL is already disabled before entering this function; reference - * clocks are enabled until now - disable them just before rail gating - */ - clk_disable(platform->clk[0]); - clk_disable(platform->clk[1]); - - udelay(10); - - if (tegra_dvfs_is_rail_up(platform->gpu_rail)) { - ret = tegra_dvfs_rail_power_down(platform->gpu_rail); - if (ret) - goto err_power_off; - } else - pr_info("No GPU regulator?\n"); - - return 0; - -err_power_off: - nvgpu_err(get_gk20a(dev), "Could not railgate GPU"); - return ret; -} - - -/* - * gk20a_tegra_unrailgate() - * - * Ungate (enable) gk20a power rail - */ - -static int gk20a_tegra_unrailgate(struct device *dev) -{ - struct gk20a *g = get_gk20a(dev); - struct gk20a_platform *platform = dev_get_drvdata(dev); - int ret = 0; - bool first = false; - - if (g->is_fmodel) - return 0; - - if (!platform->gpu_rail) { - platform->gpu_rail = tegra_dvfs_get_rail_by_name("vdd_gpu"); - if (IS_ERR_OR_NULL(platform->gpu_rail)) { - WARN(1, "No GPU regulator?\n"); - return -EINVAL; - } - first = true; - } - - ret = tegra_dvfs_rail_power_up(platform->gpu_rail); - if (ret) - return ret; - - if (!first) { - ret = clk_enable(platform->clk[0]); - if (ret) { - nvgpu_err(platform->g, "could not turn on gpu pll"); - goto err_clk_on; - } - ret = clk_enable(platform->clk[1]); - if (ret) { - nvgpu_err(platform->g, "could not turn on pwr clock"); - goto err_clk_on; - } - } - - udelay(10); - - platform->reset_assert(dev); - - udelay(10); - - pmc_write(0, PMC_GPU_RG_CNTRL_0); - pmc_read(PMC_GPU_RG_CNTRL_0); - - udelay(10); - - platform->reset_deassert(dev); - - /* Flush MC after boot/railgate/SC7 */ - tegra_mc_flush(MC_CLIENT_GPU); - - udelay(10); - - tegra_mc_flush_done(MC_CLIENT_GPU); - - udelay(10); - - return 0; - -err_clk_on: - tegra_dvfs_rail_power_down(platform->gpu_rail); - - return ret; -} - -#endif - - -#if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS) +#if defined(CONFIG_TEGRA_DVFS) /* * gk20a_tegra_is_railgated() * @@ -619,17 +486,6 @@ static int gm20b_tegra_unrailgate(struct device *dev) if (g->is_fmodel) return 0; -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK - if (!platform->gpu_rail) { - platform->gpu_rail = tegra_dvfs_get_rail_by_name(GPU_RAIL_NAME); - if (IS_ERR_OR_NULL(platform->gpu_rail)) { - WARN(1, "No GPU regulator?\n"); - return -EINVAL; - } - first = true; - } -#endif - ret = tegra_dvfs_rail_power_up(platform->gpu_rail); if (ret) return ret; @@ -713,16 +569,10 @@ static struct { char *name; unsigned long default_rate; } tegra_gk20a_clocks[] = { -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK - {"PLLG_ref", UINT_MAX}, - {"pwr", 204000000}, - {"emc", UINT_MAX}, -#elif defined(CONFIG_COMMON_CLK) {"gpu_ref", UINT_MAX}, {"pll_p_out5", 204000000}, {"emc", UINT_MAX}, {"fuse", UINT_MAX}, -#endif }; @@ -1021,7 +871,7 @@ static int gk20a_tegra_suspend(struct device *dev) return 0; } -#if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_COMMON_CLK) +#if defined(CONFIG_COMMON_CLK) static long gk20a_round_clk_rate(struct device *dev, unsigned long rate) { struct gk20a_platform *platform = gk20a_get_platform(dev); @@ -1073,11 +923,6 @@ struct gk20a_platform gk20a_tegra_platform = { /* power management callbacks */ .suspend = gk20a_tegra_suspend, -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK - .railgate = gk20a_tegra_railgate, - .unrailgate = gk20a_tegra_unrailgate, - .is_railgated = gk20a_tegra_is_railgated, -#endif .busy = gk20a_tegra_busy, .idle = gk20a_tegra_idle, @@ -1085,11 +930,6 @@ struct gk20a_platform gk20a_tegra_platform = { .reset_assert = gk20a_tegra_reset_assert, .reset_deassert = gk20a_tegra_reset_deassert, -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK - .clk_round_rate = gk20a_round_clk_rate, - .get_clk_freqs = gk20a_clk_get_freqs, -#endif - /* frequency scaling configuration */ .prescale = gk20a_tegra_prescale, .postscale = gk20a_tegra_postscale, @@ -1130,7 +970,7 @@ struct gk20a_platform gm20b_tegra_platform = { /* power management callbacks */ .suspend = gk20a_tegra_suspend, -#if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_TEGRA_DVFS) +#if defined(CONFIG_TEGRA_DVFS) .railgate = gm20b_tegra_railgate, .unrailgate = gm20b_tegra_unrailgate, .is_railgated = gk20a_tegra_is_railgated, @@ -1147,7 +987,7 @@ struct gk20a_platform gm20b_tegra_platform = { .reset_deassert = gk20a_tegra_reset_deassert, #endif -#if defined(CONFIG_TEGRA_CLK_FRAMEWORK) || defined(CONFIG_COMMON_CLK) +#if defined(CONFIG_COMMON_CLK) .clk_round_rate = gk20a_round_clk_rate, .get_clk_freqs = gk20a_clk_get_freqs, #endif -- cgit v1.2.2