From 741d78ec45f6c48348743617ba5ae7163c95e49a Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 21 Sep 2016 15:02:59 +0530 Subject: gpu: nvgpu: construct/load tabels & set voltage - Read voltage tables from VBIOS & construct then send to PMU. - compare & set voltage based on mclk/gpc2clk clk, take higher voltage between two & set. JIRA DNVGPU-122 Change-Id: I23e7b101a3b1c1b6596620fc6b8319c70bd9a488 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1224365 (cherry picked from commit e0055c3ec798b8312df3fa9bf92bde8c57c6f58c) Reviewed-on: http://git-master/r/1244657 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/clk/clk.c | 33 ++++++++++++++++++++++++++++++--- drivers/gpu/nvgpu/clk/clk_mclk.c | 6 +----- drivers/gpu/nvgpu/clk/clk_mclk.h | 3 +++ drivers/gpu/nvgpu/pstate/pstate.c | 32 ++++++++++++++++++++++++++++++++ 4 files changed, 66 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index 918cd43c..ce071018 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c @@ -17,8 +17,12 @@ #include "pmuif/gpmuifvolt.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" +#include "volt/volt.h" #include "gk20a/pmu_gk20a.h" +#define BOOT_GPC2CLK_MHZ 2581 +#define BOOT_MCLK_MHZ 3003 + struct clkrpc_pmucmdhandler_params { struct nv_pmu_clk_rpc *prpccall; u32 success; @@ -382,15 +386,38 @@ int clk_set_boot_fll_clk(struct gk20a *g) { int status; struct change_fll_clk bootfllclk; + u16 gpc2clk_clkmhz = BOOT_GPC2CLK_MHZ; + u32 gpc2clk_voltuv = 0; + u16 mclk_clkmhz = BOOT_MCLK_MHZ; + u32 mclk_voltuv = 0; + u32 voltuv = 0; mutex_init(&g->clk_pmu.changeclkmutex); + clk_domain_get_f_or_v(g, CTRL_CLK_DOMAIN_GPC2CLK, &gpc2clk_clkmhz, + &gpc2clk_voltuv); + clk_domain_get_f_or_v(g, CTRL_CLK_DOMAIN_MCLK, &mclk_clkmhz, + &mclk_voltuv); + + voltuv = ((gpc2clk_voltuv) > (mclk_voltuv)) ? (gpc2clk_voltuv) + : (mclk_voltuv); + + status = volt_set_voltage(g, voltuv, voltuv); + if (status) + gk20a_err(dev_from_gk20a(g), "attempt to set boot voltage failed %d", + voltuv); + bootfllclk.api_clk_domain = CTRL_CLK_DOMAIN_GPC2CLK; - bootfllclk.clkmhz = 2581; - bootfllclk.voltuv = 825000; + bootfllclk.clkmhz = gpc2clk_clkmhz; + bootfllclk.voltuv = voltuv; status = clk_program_fllclks(g, &bootfllclk); if (status) - gk20a_err(dev_from_gk20a(g), "attemp to set boot clk failed"); + gk20a_err(dev_from_gk20a(g), "attempt to set boot gpc2clk failed"); + + status = g->clk_pmu.clk_mclk.change(g, DEFAULT_BOOT_MCLK_SPEED); + if (status) + gk20a_err(dev_from_gk20a(g), "attempt to set boot mclk failed"); + return status; } diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c index b63fab1e..7b15767b 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.c +++ b/drivers/gpu/nvgpu/clk/clk_mclk.c @@ -23,10 +23,6 @@ #define VREG_COUNT 24 -#define DEFAULT_BOOT_MCLK_SPEED gk20a_mclk_high_speed -#define MCLK_LOW_SPEED_LIMIT 405 -#define MCLK_MID_SPEED_LIMIT 810 - struct memory_link_training_pattern { u32 regaddr; u32 writeval; @@ -2220,7 +2216,7 @@ int clk_mclkseq_init_mclk_gddr5(struct gk20a *g) mclk->init = true; - return mclk->change(g, DEFAULT_BOOT_MCLK_SPEED); + return 0; } int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, enum gk20a_mclk_speed speed) diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.h b/drivers/gpu/nvgpu/clk/clk_mclk.h index edb7eb78..9d193c96 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.h +++ b/drivers/gpu/nvgpu/clk/clk_mclk.h @@ -22,6 +22,9 @@ enum gk20a_mclk_speed { gk20a_mclk_high_speed, }; +#define DEFAULT_BOOT_MCLK_SPEED gk20a_mclk_high_speed +#define MCLK_LOW_SPEED_LIMIT 405 +#define MCLK_MID_SPEED_LIMIT 810 struct clk_mclk_state { enum gk20a_mclk_speed speed; struct mutex mclk_mutex; diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c index f4cc50ab..a4787f35 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/pstate/pstate.c @@ -29,6 +29,18 @@ int gk20a_init_pstate_support(struct gk20a *g) gk20a_dbg_fn(""); + err = volt_rail_sw_setup(g); + if (err) + return err; + + err = volt_dev_sw_setup(g); + if (err) + return err; + + err = volt_policy_sw_setup(g); + if (err) + return err; + err = clk_vin_sw_setup(g); if (err) return err; @@ -72,6 +84,26 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g) gk20a_dbg_fn(""); + err = volt_rail_pmu_setup(g); + if (err) + return err; + + err = volt_dev_pmu_setup(g); + if (err) + return err; + + err = volt_policy_pmu_setup(g); + if (err) + return err; + + err = volt_pmu_send_load_cmd_to_pmu(g); + if (err) { + gk20a_err(dev_from_gk20a(g), + "Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.", + err); + return err; + } + err = vfe_var_pmu_setup(g); if (err) return err; -- cgit v1.2.2