From 71c8d62657db7ef40a30b7504632d668f4e64bc6 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 12 Nov 2015 12:13:30 -0800 Subject: gpu: nvgpu: vgpu: add set mmu debug mode support JIRA VFND-1005 Bug 1594604 Change-Id: Ic159a1aff9cee508194f1f5dff7a16eb0e47ad64 Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/833498 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aingara Paramakuru GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/mm_vgpu.c | 18 ++++++++++++++++++ include/linux/tegra_vgpu.h | 8 +++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c index bfaacff5..8af01158 100644 --- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c @@ -531,8 +531,26 @@ static void vgpu_mm_tlb_invalidate(struct vm_gk20a *vm) WARN_ON(err || msg.ret); } +static void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) +{ + struct gk20a_platform *platform = gk20a_get_platform(g->dev); + struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_mmu_debug_mode *p = &msg.params.mmu_debug_mode; + int err; + + gk20a_dbg_fn(""); + + msg.cmd = TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE; + msg.handle = platform->virt_handle; + p->enable = (u32)enable; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + WARN_ON(err || msg.ret); +} + void vgpu_init_mm_ops(struct gpu_ops *gops) { + gops->mm.is_debug_mode_enabled = NULL; + gops->mm.set_debug_mode = vgpu_mm_mmu_set_debug_mode; gops->mm.gmmu_map = vgpu_locked_gmmu_map; gops->mm.gmmu_unmap = vgpu_locked_gmmu_unmap; gops->mm.vm_remove = vgpu_vm_remove_support; diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 7587d355..b7bcc905 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h @@ -70,7 +70,8 @@ enum { TEGRA_VGPU_CMD_ZBC_SET_TABLE, TEGRA_VGPU_CMD_ZBC_QUERY_TABLE, TEGRA_VGPU_CMD_AS_MAP_EX, - TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS + TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS, + TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE }; struct tegra_vgpu_connect_params { @@ -259,6 +260,10 @@ struct tegra_vgpu_gr_bind_ctxsw_buffers_params { u32 mode; }; +struct tegra_vgpu_mmu_debug_mode { + u32 enable; +}; + struct tegra_vgpu_cmd_msg { u32 cmd; int ret; @@ -283,6 +288,7 @@ struct tegra_vgpu_cmd_msg { struct tegra_vgpu_zbc_set_table_params zbc_set_table; struct tegra_vgpu_zbc_query_table_params zbc_query_table; struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; + struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; char padding[192]; } params; }; -- cgit v1.2.2