From 64076b4b214b45fe8367e467dd6796a9bcc058a4 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 28 Jun 2017 15:59:14 -0700 Subject: gpu: nvgpu: Reorg misc HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the lone function pointers of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I30d379bf52709c8382c9d7aa87f1672ca0f89c6f Signed-off-by: Sunny He Reviewed-on: https://git-master/r/1510386 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm206/bios_gm206.c | 5 -- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 142 ++++++++++++++++++---------------- drivers/gpu/nvgpu/gp106/hal_gp106.c | 140 +++++++++++++++++---------------- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 146 ++++++++++++++++++----------------- 4 files changed, 223 insertions(+), 210 deletions(-) diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c index 13f5023a..bcc46c83 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.c +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c @@ -266,8 +266,3 @@ free_firmware: nvgpu_release_firmware(g, bios_fw); return err; } - -void gm206_init_bios_ops(struct gpu_ops *gops) -{ - gops->bios_init = gm206_bios_init; -} diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index d22caab8..4d2e56d5 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -46,72 +46,6 @@ #define PRIV_SECURITY_DISABLE 0x01 -static const struct gpu_ops gm20b_ops = { - .ltc = { - .determine_L2_size_bytes = gm20b_determine_L2_size_bytes, - .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, - .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, - .init_cbc = gm20b_ltc_init_cbc, - .init_fs_state = gm20b_ltc_init_fs_state, - .init_comptags = gm20b_ltc_init_comptags, - .cbc_ctrl = gm20b_ltc_cbc_ctrl, - .isr = gm20b_ltc_isr, - .cbc_fix_config = gm20b_ltc_cbc_fix_config, - .flush = gm20b_flush_ltc, -#ifdef CONFIG_DEBUG_FS - .sync_debugfs = gm20b_ltc_sync_debugfs, -#endif - }, - .clock_gating = { - .slcg_bus_load_gating_prod = - gm20b_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gm20b_slcg_ce2_load_gating_prod, - .slcg_chiplet_load_gating_prod = - gm20b_slcg_chiplet_load_gating_prod, - .slcg_ctxsw_firmware_load_gating_prod = - gm20b_slcg_ctxsw_firmware_load_gating_prod, - .slcg_fb_load_gating_prod = - gm20b_slcg_fb_load_gating_prod, - .slcg_fifo_load_gating_prod = - gm20b_slcg_fifo_load_gating_prod, - .slcg_gr_load_gating_prod = - gr_gm20b_slcg_gr_load_gating_prod, - .slcg_ltc_load_gating_prod = - ltc_gm20b_slcg_ltc_load_gating_prod, - .slcg_perf_load_gating_prod = - gm20b_slcg_perf_load_gating_prod, - .slcg_priring_load_gating_prod = - gm20b_slcg_priring_load_gating_prod, - .slcg_pmu_load_gating_prod = - gm20b_slcg_pmu_load_gating_prod, - .slcg_therm_load_gating_prod = - gm20b_slcg_therm_load_gating_prod, - .slcg_xbar_load_gating_prod = - gm20b_slcg_xbar_load_gating_prod, - .blcg_bus_load_gating_prod = - gm20b_blcg_bus_load_gating_prod, - .blcg_ctxsw_firmware_load_gating_prod = - gm20b_blcg_ctxsw_firmware_load_gating_prod, - .blcg_fb_load_gating_prod = - gm20b_blcg_fb_load_gating_prod, - .blcg_fifo_load_gating_prod = - gm20b_blcg_fifo_load_gating_prod, - .blcg_gr_load_gating_prod = - gm20b_blcg_gr_load_gating_prod, - .blcg_ltc_load_gating_prod = - gm20b_blcg_ltc_load_gating_prod, - .blcg_pwr_csb_load_gating_prod = - gm20b_blcg_pwr_csb_load_gating_prod, - .blcg_xbar_load_gating_prod = - gm20b_blcg_xbar_load_gating_prod, - .blcg_pmu_load_gating_prod = - gm20b_blcg_pmu_load_gating_prod, - .pg_gr_load_gating_prod = - gr_gm20b_pg_gr_load_gating_prod, - }, -}; - static int gm20b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; @@ -201,6 +135,74 @@ static int gm20b_get_litter_value(struct gk20a *g, int value) return ret; } +static const struct gpu_ops gm20b_ops = { + .ltc = { + .determine_L2_size_bytes = gm20b_determine_L2_size_bytes, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = gm20b_ltc_init_cbc, + .init_fs_state = gm20b_ltc_init_fs_state, + .init_comptags = gm20b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gm20b_ltc_isr, + .cbc_fix_config = gm20b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gm20b_ltc_sync_debugfs, +#endif + }, + .clock_gating = { + .slcg_bus_load_gating_prod = + gm20b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gm20b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gm20b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gm20b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gm20b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gm20b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gm20b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gm20b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gm20b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gm20b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gm20b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gm20b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gm20b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gm20b_blcg_bus_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gm20b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gm20b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gm20b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gm20b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gm20b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gm20b_blcg_pwr_csb_load_gating_prod, + .blcg_xbar_load_gating_prod = + gm20b_blcg_xbar_load_gating_prod, + .blcg_pmu_load_gating_prod = + gm20b_blcg_pmu_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gm20b_pg_gr_load_gating_prod, + }, + .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, + .get_litter_value = gm20b_get_litter_value, +}; + int gm20b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; @@ -209,6 +211,12 @@ int gm20b_init_hal(struct gk20a *g) gops->ltc = gm20b_ops.ltc; gops->clock_gating = gm20b_ops.clock_gating; + + /* Lone functions */ + gops->chip_init_gpu_characteristics = + gm20b_ops.chip_init_gpu_characteristics; + gops->get_litter_value = gm20b_ops.get_litter_value; + gops->securegpccs = false; gops->pmupstate = false; #ifdef CONFIG_TEGRA_ACR @@ -260,8 +268,6 @@ int gm20b_init_hal(struct gk20a *g) gk20a_init_css_ops(gops); #endif g->name = "gm20b"; - gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics; - gops->get_litter_value = gm20b_get_litter_value; c->twod_class = FERMI_TWOD_A; c->threed_class = MAXWELL_B; diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 69516d22..f31180cd 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -59,70 +59,6 @@ #include -static const struct gpu_ops gp106_ops = { - .ltc = { - .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, - .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, - .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, - .init_cbc = NULL, - .init_fs_state = gm20b_ltc_init_fs_state, - .init_comptags = gp10b_ltc_init_comptags, - .cbc_ctrl = gm20b_ltc_cbc_ctrl, - .isr = gp10b_ltc_isr, - .cbc_fix_config = NULL, - .flush = gm20b_flush_ltc, -#ifdef CONFIG_DEBUG_FS - .sync_debugfs = gp10b_ltc_sync_debugfs, -#endif - }, - .clock_gating = { - .slcg_bus_load_gating_prod = - gp106_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gp106_slcg_ce2_load_gating_prod, - .slcg_chiplet_load_gating_prod = - gp106_slcg_chiplet_load_gating_prod, - .slcg_ctxsw_firmware_load_gating_prod = - gp106_slcg_ctxsw_firmware_load_gating_prod, - .slcg_fb_load_gating_prod = - gp106_slcg_fb_load_gating_prod, - .slcg_fifo_load_gating_prod = - gp106_slcg_fifo_load_gating_prod, - .slcg_gr_load_gating_prod = - gr_gp106_slcg_gr_load_gating_prod, - .slcg_ltc_load_gating_prod = - ltc_gp106_slcg_ltc_load_gating_prod, - .slcg_perf_load_gating_prod = - gp106_slcg_perf_load_gating_prod, - .slcg_priring_load_gating_prod = - gp106_slcg_priring_load_gating_prod, - .slcg_pmu_load_gating_prod = - gp106_slcg_pmu_load_gating_prod, - .slcg_therm_load_gating_prod = - gp106_slcg_therm_load_gating_prod, - .slcg_xbar_load_gating_prod = - gp106_slcg_xbar_load_gating_prod, - .blcg_bus_load_gating_prod = - gp106_blcg_bus_load_gating_prod, - .blcg_ce_load_gating_prod = - gp106_blcg_ce_load_gating_prod, - .blcg_fb_load_gating_prod = - gp106_blcg_fb_load_gating_prod, - .blcg_fifo_load_gating_prod = - gp106_blcg_fifo_load_gating_prod, - .blcg_gr_load_gating_prod = - gp106_blcg_gr_load_gating_prod, - .blcg_ltc_load_gating_prod = - gp106_blcg_ltc_load_gating_prod, - .blcg_pmu_load_gating_prod = - gp106_blcg_pmu_load_gating_prod, - .blcg_xbar_load_gating_prod = - gp106_blcg_xbar_load_gating_prod, - .pg_gr_load_gating_prod = - gr_gp106_pg_gr_load_gating_prod, - } -}; - static int gp106_get_litter_value(struct gk20a *g, int value) { int ret = -EINVAL; @@ -241,6 +177,73 @@ static int gp106_init_gpu_characteristics(struct gk20a *g) return 0; } +static const struct gpu_ops gp106_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = gm20b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gp10b_ltc_isr, + .cbc_fix_config = NULL, + .flush = gm20b_flush_ltc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gp10b_ltc_sync_debugfs, +#endif + }, + .clock_gating = { + .slcg_bus_load_gating_prod = + gp106_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gp106_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gp106_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gp106_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gp106_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gp106_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gp106_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gp106_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gp106_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gp106_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gp106_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gp106_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gp106_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gp106_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gp106_blcg_ce_load_gating_prod, + .blcg_fb_load_gating_prod = + gp106_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gp106_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gp106_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gp106_blcg_ltc_load_gating_prod, + .blcg_pmu_load_gating_prod = + gp106_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gp106_blcg_xbar_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gp106_pg_gr_load_gating_prod, + }, + .get_litter_value = gp106_get_litter_value, + .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, + .bios_init = gm206_bios_init, +}; + int gp106_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; @@ -251,6 +254,12 @@ int gp106_init_hal(struct gk20a *g) gops->ltc = gp106_ops.ltc; gops->clock_gating = gp106_ops.clock_gating; + /* Lone functions */ + gops->get_litter_value = gp106_ops.get_litter_value; + gops->chip_init_gpu_characteristics = + gp106_ops.chip_init_gpu_characteristics; + gops->bios_init = gp106_ops.bios_init; + gops->privsecurity = 1; gops->securegpccs = 1; gops->pmupstate = true; @@ -277,13 +286,10 @@ int gp106_init_hal(struct gk20a *g) #if defined(CONFIG_GK20A_CYCLE_STATS) gk20a_init_css_ops(gops); #endif - gm206_init_bios_ops(gops); gp106_init_therm_ops(gops); gp106_init_xve_ops(gops); g->name = "gp10x"; - gops->get_litter_value = gp106_get_litter_value; - gops->chip_init_gpu_characteristics = gp106_init_gpu_characteristics; gops->gr_ctx.use_dma_for_fw_bootstrap = true; c->twod_class = FERMI_TWOD_A; diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 505dc6d7..98ff55cc 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -52,74 +52,6 @@ #include #include -static const struct gpu_ops gp10b_ops = { - .ltc = { - .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, - .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, - .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, - .init_cbc = gm20b_ltc_init_cbc, - .init_fs_state = gp10b_ltc_init_fs_state, - .init_comptags = gp10b_ltc_init_comptags, - .cbc_ctrl = gm20b_ltc_cbc_ctrl, - .isr = gp10b_ltc_isr, - .cbc_fix_config = gm20b_ltc_cbc_fix_config, - .flush = gm20b_flush_ltc, -#ifdef CONFIG_DEBUG_FS - .sync_debugfs = gp10b_ltc_sync_debugfs, -#endif - }, - .clock_gating = { - .slcg_bus_load_gating_prod = - gp10b_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gp10b_slcg_ce2_load_gating_prod, - .slcg_chiplet_load_gating_prod = - gp10b_slcg_chiplet_load_gating_prod, - .slcg_ctxsw_firmware_load_gating_prod = - gp10b_slcg_ctxsw_firmware_load_gating_prod, - .slcg_fb_load_gating_prod = - gp10b_slcg_fb_load_gating_prod, - .slcg_fifo_load_gating_prod = - gp10b_slcg_fifo_load_gating_prod, - .slcg_gr_load_gating_prod = - gr_gp10b_slcg_gr_load_gating_prod, - .slcg_ltc_load_gating_prod = - ltc_gp10b_slcg_ltc_load_gating_prod, - .slcg_perf_load_gating_prod = - gp10b_slcg_perf_load_gating_prod, - .slcg_priring_load_gating_prod = - gp10b_slcg_priring_load_gating_prod, - .slcg_pmu_load_gating_prod = - gp10b_slcg_pmu_load_gating_prod, - .slcg_therm_load_gating_prod = - gp10b_slcg_therm_load_gating_prod, - .slcg_xbar_load_gating_prod = - gp10b_slcg_xbar_load_gating_prod, - .blcg_bus_load_gating_prod = - gp10b_blcg_bus_load_gating_prod, - .blcg_ce_load_gating_prod = - gp10b_blcg_ce_load_gating_prod, - .blcg_ctxsw_firmware_load_gating_prod = - gp10b_blcg_ctxsw_firmware_load_gating_prod, - .blcg_fb_load_gating_prod = - gp10b_blcg_fb_load_gating_prod, - .blcg_fifo_load_gating_prod = - gp10b_blcg_fifo_load_gating_prod, - .blcg_gr_load_gating_prod = - gp10b_blcg_gr_load_gating_prod, - .blcg_ltc_load_gating_prod = - gp10b_blcg_ltc_load_gating_prod, - .blcg_pwr_csb_load_gating_prod = - gp10b_blcg_pwr_csb_load_gating_prod, - .blcg_pmu_load_gating_prod = - gp10b_blcg_pmu_load_gating_prod, - .blcg_xbar_load_gating_prod = - gp10b_blcg_xbar_load_gating_prod, - .pg_gr_load_gating_prod = - gr_gp10b_pg_gr_load_gating_prod, - } -}; - static int gp10b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; @@ -209,6 +141,76 @@ static int gp10b_get_litter_value(struct gk20a *g, int value) return ret; } +static const struct gpu_ops gp10b_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = gm20b_ltc_init_cbc, + .init_fs_state = gp10b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gp10b_ltc_isr, + .cbc_fix_config = gm20b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gp10b_ltc_sync_debugfs, +#endif + }, + .clock_gating = { + .slcg_bus_load_gating_prod = + gp10b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gp10b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gp10b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gp10b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gp10b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gp10b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gp10b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gp10b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gp10b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gp10b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gp10b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gp10b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gp10b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gp10b_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gp10b_blcg_ce_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gp10b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gp10b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gp10b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gp10b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gp10b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gp10b_blcg_pwr_csb_load_gating_prod, + .blcg_pmu_load_gating_prod = + gp10b_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gp10b_blcg_xbar_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gp10b_pg_gr_load_gating_prod, + }, + .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, + .get_litter_value = gp10b_get_litter_value, +}; + int gp10b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; @@ -217,6 +219,12 @@ int gp10b_init_hal(struct gk20a *g) gops->ltc = gp10b_ops.ltc; gops->clock_gating = gp10b_ops.clock_gating; + + /* Lone Functions */ + gops->chip_init_gpu_characteristics = + gp10b_ops.chip_init_gpu_characteristics; + gops->get_litter_value = gp10b_ops.get_litter_value; + gops->pmupstate = false; #ifdef CONFIG_TEGRA_ACR if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { @@ -278,8 +286,6 @@ int gp10b_init_hal(struct gk20a *g) gk20a_init_css_ops(gops); #endif g->name = "gp10b"; - gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics; - gops->get_litter_value = gp10b_get_litter_value; c->twod_class = FERMI_TWOD_A; c->threed_class = PASCAL_A; -- cgit v1.2.2