From 587a7b1e931d421b7526a0328c2c82ee78075f0c Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 8 Dec 2014 18:15:37 -0800 Subject: gpu: nvgpu: gp10b: update headers Update replayable page fault fifo, interrupt and bar2 block headers. Bug 1587825 Change-Id: Ifa0d3b640bdd5f3f6fbc7826c1d1edba494340df Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/661117 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h | 20 ++++ drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 2 +- drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 130 +++++++++++++++++++++++++- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 6 +- drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 4 + drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 34 ++++++- 6 files changed, 192 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h index e443738f..c04b01c1 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h @@ -66,10 +66,30 @@ static inline u32 bus_bar1_block_mode_virtual_f(void) { return 0x80000000; } +static inline u32 bus_bar2_block_r(void) +{ + return 0x00001714; +} +static inline u32 bus_bar2_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar2_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar2_block_mode_virtual_f(void) +{ + return 0x80000000; +} static inline u32 bus_bar1_block_ptr_shift_v(void) { return 0x0000000c; } +static inline u32 bus_bar2_block_ptr_shift_v(void) +{ + return 0x0000000c; +} static inline u32 bus_intr_0_r(void) { return 0x00001100; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h index 7872c19c..3b97c9da 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index b79758d2..d2629b08 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -178,6 +178,10 @@ static inline u32 fifo_intr_0_lb_error_reset_f(void) { return 0x1000000; } +static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void) +{ + return 0x2000000; +} static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) { return 0x8000000; @@ -526,4 +530,128 @@ static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) { return 0x00000001; } +static inline u32 fifo_replay_fault_buffer_lo_r(void) +{ + return 0x00002a70; +} +static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_hi_r(void) +{ + return 0x00002a74; +} +static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_size_r(void) +{ + return 0x00002a78; +} +static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) +{ + return 0x000000c0; +} +static inline u32 fifo_replay_fault_buffer_get_r(void) +{ + return 0x00002a7c; +} +static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_put_r(void) +{ + return 0x00002a80; +} +static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_r(void) +{ + return 0x00002a84; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void) +{ + return 0x00000001; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 0bd707db..49078f11 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1294,6 +1294,10 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) { return 0x00000004; } +static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) +{ + return 0x00000028; +} static inline u32 gr_ds_zbc_z_r(void) { return 0x00405818; diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h index 21c592da..7d153b6f 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h @@ -78,6 +78,10 @@ static inline u32 mc_intr_pfifo_pending_f(void) { return 0x100; } +static inline u32 mc_intr_replayable_fault_pending_f(void) +{ + return 0x200; +} static inline u32 mc_intr_pgraph_pending_f(void) { return 0x1000; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index 509031e5..dea53f96 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -78,6 +78,38 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) +{ + return 0x10; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) +{ + return 0x20; +} static inline u32 ram_in_big_page_size_f(u32 v) { return (v & 0x1) << 11; -- cgit v1.2.2