From 53465def649b813987ca0d4a7ced744305204b82 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 9 Feb 2017 08:17:47 -0800 Subject: gpu: nvgpu: Generalize BIOS code Most of BIOS parsing code is not specific to any particular GPU. Move most of the code to generic files, and leave only chip specific parts dealing with microcontroller boot into chip specific files. As most of the parsing is generic, they do not need to be called via HALs so remove the HALs and change the calls into direct function calls. All definitions meant to be used outside BIOS code itself are now in Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1302222 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/Makefile.nvgpu | 2 +- drivers/gpu/nvgpu/clk/clk_domain.c | 9 +- drivers/gpu/nvgpu/clk/clk_fll.c | 9 +- drivers/gpu/nvgpu/clk/clk_freq_controller.c | 19 +- drivers/gpu/nvgpu/clk/clk_mclk.c | 21 +- drivers/gpu/nvgpu/clk/clk_prog.c | 10 +- drivers/gpu/nvgpu/clk/clk_vf_point.c | 2 - drivers/gpu/nvgpu/clk/clk_vin.c | 10 +- drivers/gpu/nvgpu/common/vbios/bios.c | 748 +++++++++++++++++++ drivers/gpu/nvgpu/gk20a/gk20a.c | 4 +- drivers/gpu/nvgpu/gk20a/gk20a.h | 10 +- drivers/gpu/nvgpu/gm206/bios_gm206.c | 635 +--------------- drivers/gpu/nvgpu/gm206/bios_gm206.h | 56 +- drivers/gpu/nvgpu/gm206/hal_gm206.c | 2 +- drivers/gpu/nvgpu/gp106/bios_gp106.c | 123 ---- drivers/gpu/nvgpu/gp106/bios_gp106.h | 31 - drivers/gpu/nvgpu/gp106/hal_gp106.c | 4 +- drivers/gpu/nvgpu/include/bios.h | 992 ------------------------- drivers/gpu/nvgpu/include/nvgpu/bios.h | 1046 +++++++++++++++++++++++++++ drivers/gpu/nvgpu/lpwr/lpwr.c | 36 +- drivers/gpu/nvgpu/lpwr/rppg.c | 2 - drivers/gpu/nvgpu/perf/vfe_equ.c | 9 +- drivers/gpu/nvgpu/perf/vfe_var.c | 18 +- drivers/gpu/nvgpu/pmgr/pmgrpmu.c | 1 - drivers/gpu/nvgpu/pmgr/pwrdev.c | 8 +- drivers/gpu/nvgpu/pmgr/pwrmonitor.c | 8 +- drivers/gpu/nvgpu/pmgr/pwrpolicy.c | 8 +- drivers/gpu/nvgpu/pstate/pstate.c | 11 +- drivers/gpu/nvgpu/therm/thrmchannel.c | 8 +- drivers/gpu/nvgpu/therm/thrmdev.c | 8 +- drivers/gpu/nvgpu/therm/thrmpmu.c | 1 - drivers/gpu/nvgpu/volt/volt_dev.c | 15 +- drivers/gpu/nvgpu/volt/volt_pmu.c | 2 - drivers/gpu/nvgpu/volt/volt_policy.c | 18 +- drivers/gpu/nvgpu/volt/volt_rail.c | 16 +- 35 files changed, 1897 insertions(+), 2005 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/vbios/bios.c delete mode 100644 drivers/gpu/nvgpu/gp106/bios_gp106.c delete mode 100644 drivers/gpu/nvgpu/gp106/bios_gp106.h delete mode 100644 drivers/gpu/nvgpu/include/bios.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/bios.h diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index 4daf5adb..2b8614c3 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu @@ -33,6 +33,7 @@ nvgpu-y := \ common/mm/lockless_allocator.o \ common/nvgpu_common.o \ common/semaphore.o \ + common/vbios/bios.o \ gk20a/gk20a.o \ gk20a/sched_gk20a.o \ gk20a/as_gk20a.o \ @@ -160,7 +161,6 @@ nvgpu-y += \ gp106/fifo_gp106.o \ gp106/ltc_gp106.o \ gp106/fb_gp106.o \ - gp106/bios_gp106.o \ gp106/regops_gp106.o \ clk/clk_mclk.o \ pstate/pstate.o \ diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index b53d3708..2a614f55 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c @@ -11,14 +11,14 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "clk.h" #include "clk_fll.h" #include "clk_domain.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" @@ -261,10 +261,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) - return -EINVAL; - - clocks_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + clocks_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.clock_token, CLOCKS_TABLE); if (clocks_table_ptr == NULL) { status = -EINVAL; diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index 91cd0e20..7694e720 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c @@ -11,13 +11,13 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "clk.h" #include "clk_fll.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" @@ -234,10 +234,7 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) - return -EINVAL; - - fll_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + fll_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.clock_token, FLL_TABLE); if (fll_table_ptr == NULL) { status = -1; diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index 6fa2db5a..4b47d978 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c @@ -11,15 +11,15 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "clk.h" #include "clk_fll.h" #include "clk_domain.h" #include "clk_freq_controller.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" @@ -185,16 +185,11 @@ static u32 clk_get_freq_controller_table(struct gk20a *g, }; } freq_controller_data; - if (g->ops.bios.get_perf_table_ptrs) { - pfreq_controller_table_ptr = - (u8 *)g->ops.bios.get_perf_table_ptrs(g, - g->bios.clock_token, - FREQUENCY_CONTROLLER_TABLE); - if (pfreq_controller_table_ptr == NULL) { - status = -EINVAL; - goto done; - } - } else { + pfreq_controller_table_ptr = + (u8 *)nvgpu_bios_get_perf_table_ptrs(g, + g->bios.clock_token, + FREQUENCY_CONTROLLER_TABLE); + if (pfreq_controller_table_ptr == NULL) { status = -EINVAL; goto done; } diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c index 479fbb0e..815f55ba 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.c +++ b/drivers/gpu/nvgpu/clk/clk_mclk.c @@ -13,12 +13,10 @@ #include +#include + #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" -#include -#include "gm206/bios_gm206.h" - -#include "include/bios.h" #include #include @@ -2022,12 +2020,7 @@ static int mclk_get_memclk_table(struct gk20a *g) gk20a_dbg_info(""); - if (!(g->ops.bios.get_perf_table_ptrs && - g->ops.bios.execute_script)) { - goto done; - } - - mem_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + mem_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.perf_token, MEMORY_CLOCK_TABLE); if (mem_table_ptr == NULL) { @@ -2067,7 +2060,7 @@ static int mclk_get_memclk_table(struct gk20a *g) script_index = BIOS_GET_FIELD(memclock_base_entry.flags1, VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX); - script_ptr = gm206_bios_read_u32(g, + script_ptr = nvgpu_bios_read_u32(g, memclock_table_header.script_list_ptr + script_index * sizeof(u32)); @@ -2107,7 +2100,7 @@ static int mclk_get_memclk_table(struct gk20a *g) fb_fbpa_fbio_delay_priv_m(), fb_fbpa_fbio_delay_priv_f(shadow_idx))); - status = g->ops.bios.execute_script(g, script_ptr); + status = nvgpu_bios_execute_script(g, script_ptr); if (status < 0) { gk20a_writel(g, fb_fbpa_fbio_delay_r(), old_fbio_delay); @@ -2121,7 +2114,7 @@ static int mclk_get_memclk_table(struct gk20a *g) cmd_script_index = BIOS_GET_FIELD(memclock_base_entry.flags2, VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX); - cmd_script_ptr = gm206_bios_read_u32(g, + cmd_script_ptr = nvgpu_bios_read_u32(g, memclock_table_header.cmd_script_list_ptr + cmd_script_index * sizeof(u32)); @@ -2159,7 +2152,7 @@ static int mclk_get_memclk_table(struct gk20a *g) fb_fbpa_fbio_cmd_delay_cmd_priv_f( cmd_idx))); - status = g->ops.bios.execute_script(g, cmd_script_ptr); + status = nvgpu_bios_execute_script(g, cmd_script_ptr); if (status < 0) { gk20a_writel(g, fb_fbpa_fbio_cmd_delay_r(), old_fbio_cmd_delay); diff --git a/drivers/gpu/nvgpu/clk/clk_prog.c b/drivers/gpu/nvgpu/clk/clk_prog.c index 38654b66..b4f6a464 100644 --- a/drivers/gpu/nvgpu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/clk/clk_prog.c @@ -11,11 +11,12 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "clk.h" #include "clk_prog.h" #include "clk_vf_point.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "gm206/bios_gm206.h" @@ -180,12 +181,7 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) { - status = -EINVAL; - goto done; - } - - clkprogs_tbl_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + clkprogs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.clock_token, CLOCK_PROGRAMMING_TABLE); if (clkprogs_tbl_ptr == NULL) { status = -EINVAL; diff --git a/drivers/gpu/nvgpu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/clk/clk_vf_point.c index 58eeb6c2..f4019f9d 100644 --- a/drivers/gpu/nvgpu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/clk/clk_vf_point.c @@ -14,10 +14,8 @@ #include "gk20a/gk20a.h" #include "clk.h" #include "clk_vf_point.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c index 13358335..af388671 100644 --- a/drivers/gpu/nvgpu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/clk/clk_vin.c @@ -11,9 +11,9 @@ * more details. */ -#include "gk20a/gk20a.h" +#include -#include "include/bios.h" +#include "gk20a/gk20a.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" @@ -28,7 +28,6 @@ #include "clk.h" #include "clk_vin.h" - #include static u32 devinit_get_vin_device_table(struct gk20a *g, @@ -349,10 +348,7 @@ static u32 devinit_get_vin_device_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) - return -EINVAL; - - vin_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + vin_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.clock_token, VIN_TABLE); if (vin_table_ptr == NULL) { status = -1; diff --git a/drivers/gpu/nvgpu/common/vbios/bios.c b/drivers/gpu/nvgpu/common/vbios/bios.c new file mode 100644 index 00000000..c31f9a29 --- /dev/null +++ b/drivers/gpu/nvgpu/common/vbios/bios.c @@ -0,0 +1,748 @@ +/* + * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include "gk20a/gk20a.h" + +#define BIT_HEADER_ID 0xb8ff +#define BIT_HEADER_SIGNATURE 0x00544942 +#define PCI_EXP_ROM_SIG 0xaa55 +#define PCI_EXP_ROM_SIG_NV 0x4e56 + +#define INIT_DONE 0x71 +#define INIT_RESUME 0x72 +#define INIT_CONDITION 0x75 +#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f + +struct condition_entry { + u32 cond_addr; + u32 cond_mask; + u32 cond_compare; +} __packed; + +static u16 nvgpu_bios_rdu16(struct gk20a *g, int offset) +{ + u16 val = (g->bios.data[offset+1] << 8) + g->bios.data[offset]; + return val; +} + +static u32 nvgpu_bios_rdu32(struct gk20a *g, int offset) +{ + u32 val = (g->bios.data[offset+3] << 24) + + (g->bios.data[offset+2] << 16) + + (g->bios.data[offset+1] << 8) + + g->bios.data[offset]; + return val; +} + +struct bit { + u16 id; + u32 signature; + u16 bcd_version; + u8 header_size; + u8 token_size; + u8 token_entries; + u8 header_checksum; +} __packed; + +#define TOKEN_ID_BIOSDATA 0x42 +#define TOKEN_ID_NVINIT_PTRS 0x49 +#define TOKEN_ID_FALCON_DATA 0x70 +#define TOKEN_ID_PERF_PTRS 0x50 +#define TOKEN_ID_CLOCK_PTRS 0x43 +#define TOKEN_ID_VIRT_PTRS 0x56 +#define TOKEN_ID_MEMORY_PTRS 0x4D + + +union memory_ptrs { + struct { + u8 rsvd0[2]; + u8 mem_strap_data_count; + u16 mem_strap_xlat_tbl_ptr; + u8 rsvd1[8]; + } v1 __packed; + struct { + u8 mem_strap_data_count; + u16 mem_strap_xlat_tbl_ptr; + u8 rsvd[14]; + } v2 __packed; +}; + +struct biosdata { + u32 version; + u8 oem_version; + u8 checksum; + u16 int15callbackspost; + u16 int16callbackssystem; + u16 boardid; + u16 framecount; + u8 biosmoddate[8]; +} __packed; + +struct nvinit_ptrs { + u16 initscript_table_ptr; + u16 macro_index_table_ptr; + u16 macro_table_ptr; + u16 condition_table_ptr; + u16 io_condition_table_ptr; + u16 io_flag_condition_table_ptr; + u16 init_function_table_ptr; + u16 vbios_private_table_ptr; + u16 data_arrays_table_ptr; + u16 pcie_settings_script_ptr; + u16 devinit_tables_ptr; + u16 devinit_tables_size; + u16 bootscripts_ptr; + u16 bootscripts_size; + u16 nvlink_config_data_ptr; +} __packed; + +struct falcon_data_v2 { + u32 falcon_ucode_table_ptr; +} __packed; + +struct falcon_ucode_table_hdr_v1 { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u8 desc_version; + u8 desc_size; +} __packed; + +struct falcon_ucode_table_entry_v1 { + u8 application_id; + u8 target_id; + u32 desc_ptr; +} __packed; + +#define TARGET_ID_PMU 0x01 +#define APPLICATION_ID_DEVINIT 0x04 +#define APPLICATION_ID_PRE_OS 0x01 + +struct falcon_ucode_desc_v1 { + union { + u32 v_desc; + u32 stored_size; + } hdr_size; + u32 uncompressed_size; + u32 virtual_entry; + u32 interface_offset; + u32 imem_phys_base; + u32 imem_load_size; + u32 imem_virt_base; + u32 imem_sec_base; + u32 imem_sec_size; + u32 dmem_offset; + u32 dmem_phys_base; + u32 dmem_load_size; +} __packed; + +struct application_interface_table_hdr_v1 { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; +} __packed; + +struct application_interface_entry_v1 { + u32 id; + u32 dmem_offset; +} __packed; + +#define APPINFO_ID_DEVINIT 0x01 + +struct devinit_engine_interface { + u32 field0; + u32 field1; + u32 tables_phys_base; + u32 tables_virt_base; + u32 script_phys_base; + u32 script_virt_base; + u32 script_virt_entry; + u16 script_size; + u8 memory_strap_count; + u8 reserved; + u32 memory_information_table_virt_base; + u32 empty_script_virt_base; + u32 cond_table_virt_base; + u32 io_cond_table_virt_base; + u32 data_arrays_table_virt_base; + u32 gpio_assignment_table_virt_base; +} __packed; + +struct pci_exp_rom { + u16 sig; + u8 reserved[0x16]; + u16 pci_data_struct_ptr; + u32 size_of_block; +} __packed; + +struct pci_data_struct { + u32 sig; + u16 vendor_id; + u16 device_id; + u16 device_list_ptr; + u16 pci_data_struct_len; + u8 pci_data_struct_rev; + u8 class_code[3]; + u16 image_len; + u16 vendor_rom_rev; + u8 code_type; + u8 last_image; + u16 max_runtime_image_len; +} __packed; + +struct pci_ext_data_struct { + u32 sig; + u16 nv_pci_data_ext_rev; + u16 nv_pci_data_ext_len; + u16 sub_image_len; + u8 priv_last_image; + u8 flags; +} __packed; + +static void nvgpu_bios_parse_bit(struct gk20a *g, int offset); + +int nvgpu_bios_parse_rom(struct gk20a *g) +{ + int offset = 0; + int last = 0; + bool found = false; + unsigned int i; + + while (!last) { + struct pci_exp_rom *pci_rom; + struct pci_data_struct *pci_data; + struct pci_ext_data_struct *pci_ext_data; + + pci_rom = (struct pci_exp_rom *)&g->bios.data[offset]; + gk20a_dbg_fn("pci rom sig %04x ptr %04x block %x", + pci_rom->sig, pci_rom->pci_data_struct_ptr, + pci_rom->size_of_block); + + if (pci_rom->sig != PCI_EXP_ROM_SIG && + pci_rom->sig != PCI_EXP_ROM_SIG_NV) { + gk20a_err(g->dev, "invalid VBIOS signature"); + return -EINVAL; + } + + pci_data = + (struct pci_data_struct *) + &g->bios.data[offset + pci_rom->pci_data_struct_ptr]; + gk20a_dbg_fn("pci data sig %08x len %d image len %x type %x last %d max %08x", + pci_data->sig, pci_data->pci_data_struct_len, + pci_data->image_len, pci_data->code_type, + pci_data->last_image, + pci_data->max_runtime_image_len); + + if (pci_data->code_type == 0x3) { + pci_ext_data = (struct pci_ext_data_struct *) + &g->bios.data[(offset + + pci_rom->pci_data_struct_ptr + + pci_data->pci_data_struct_len + + 0xf) + & ~0xf]; + gk20a_dbg_fn("pci ext data sig %08x rev %x len %x sub_image_len %x priv_last %d flags %x", + pci_ext_data->sig, + pci_ext_data->nv_pci_data_ext_rev, + pci_ext_data->nv_pci_data_ext_len, + pci_ext_data->sub_image_len, + pci_ext_data->priv_last_image, + pci_ext_data->flags); + + gk20a_dbg_fn("expansion rom offset %x", + pci_data->image_len * 512); + g->bios.expansion_rom_offset = + pci_data->image_len * 512; + offset += pci_ext_data->sub_image_len * 512; + last = pci_ext_data->priv_last_image; + } else { + offset += pci_data->image_len * 512; + last = pci_data->last_image; + } + } + + gk20a_dbg_info("read bios"); + for (i = 0; i < g->bios.size - 6; i++) { + if (nvgpu_bios_rdu16(g, i) == BIT_HEADER_ID && + nvgpu_bios_rdu32(g, i+2) == BIT_HEADER_SIGNATURE) { + nvgpu_bios_parse_bit(g, i); + found = true; + } + } + + if (!found) + return -EINVAL; + else + return 0; +} + +static void nvgpu_bios_parse_biosdata(struct gk20a *g, int offset) +{ + struct biosdata biosdata; + + memcpy(&biosdata, &g->bios.data[offset], sizeof(biosdata)); + gk20a_dbg_fn("bios version %x, oem version %x", + biosdata.version, + biosdata.oem_version); + + g->gpu_characteristics.vbios_version = biosdata.version; + g->gpu_characteristics.vbios_oem_version = biosdata.oem_version; +} + +static void nvgpu_bios_parse_nvinit_ptrs(struct gk20a *g, int offset) +{ + struct nvinit_ptrs nvinit_ptrs; + + memcpy(&nvinit_ptrs, &g->bios.data[offset], sizeof(nvinit_ptrs)); + gk20a_dbg_fn("devinit ptr %x size %d", nvinit_ptrs.devinit_tables_ptr, + nvinit_ptrs.devinit_tables_size); + gk20a_dbg_fn("bootscripts ptr %x size %d", nvinit_ptrs.bootscripts_ptr, + nvinit_ptrs.bootscripts_size); + + g->bios.devinit_tables = &g->bios.data[nvinit_ptrs.devinit_tables_ptr]; + g->bios.devinit_tables_size = nvinit_ptrs.devinit_tables_size; + g->bios.bootscripts = &g->bios.data[nvinit_ptrs.bootscripts_ptr]; + g->bios.bootscripts_size = nvinit_ptrs.bootscripts_size; + g->bios.condition_table_ptr = nvinit_ptrs.condition_table_ptr; +} + +static void nvgpu_bios_parse_memory_ptrs(struct gk20a *g, int offset, u8 version) +{ + union memory_ptrs memory_ptrs; + + if ((version < 1) || (version > 2)) + return; + + memcpy(&memory_ptrs, &g->bios.data[offset], sizeof(memory_ptrs)); + + g->bios.mem_strap_data_count = (version > 1) ? memory_ptrs.v2.mem_strap_data_count : + memory_ptrs.v1.mem_strap_data_count; + g->bios.mem_strap_xlat_tbl_ptr = (version > 1) ? memory_ptrs.v2.mem_strap_xlat_tbl_ptr : + memory_ptrs.v1.mem_strap_xlat_tbl_ptr; +} + +static void nvgpu_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset) +{ + struct devinit_engine_interface interface; + + memcpy(&interface, &g->bios.devinit.dmem[dmem_offset], sizeof(interface)); + gk20a_dbg_fn("devinit tables phys %x script phys %x size %d", + interface.tables_phys_base, + interface.script_phys_base, + interface.script_size); + + g->bios.devinit_tables_phys_base = interface.tables_phys_base; + g->bios.devinit_script_phys_base = interface.script_phys_base; +} + +static int nvgpu_bios_parse_appinfo_table(struct gk20a *g, int offset) +{ + struct application_interface_table_hdr_v1 hdr; + int i; + + memcpy(&hdr, &g->bios.data[offset], sizeof(hdr)); + + gk20a_dbg_fn("appInfoHdr ver %d size %d entrySize %d entryCount %d", + hdr.version, hdr.header_size, + hdr.entry_size, hdr.entry_count); + + if (hdr.version != 1) + return 0; + + offset += sizeof(hdr); + for (i = 0; i < hdr.entry_count; i++) { + struct application_interface_entry_v1 entry; + + memcpy(&entry, &g->bios.data[offset], sizeof(entry)); + + gk20a_dbg_fn("appInfo id %d dmem_offset %d", + entry.id, entry.dmem_offset); + + if (entry.id == APPINFO_ID_DEVINIT) + nvgpu_bios_parse_devinit_appinfo(g, entry.dmem_offset); + + offset += hdr.entry_size; + } + + return 0; +} + +static int nvgpu_bios_parse_falcon_ucode_desc(struct gk20a *g, + struct nvgpu_bios_ucode *ucode, int offset) +{ + struct falcon_ucode_desc_v1 desc; + + memcpy(&desc, &g->bios.data[offset], sizeof(desc)); + gk20a_dbg_info("falcon ucode desc stored size %d uncompressed size %d", + desc.hdr_size.stored_size, desc.uncompressed_size); + gk20a_dbg_info("falcon ucode desc virtualEntry %x, interfaceOffset %x", + desc.virtual_entry, desc.interface_offset); + gk20a_dbg_info("falcon ucode IMEM phys base %x, load size %x virt base %x sec base %x sec size %x", + desc.imem_phys_base, desc.imem_load_size, + desc.imem_virt_base, desc.imem_sec_base, + desc.imem_sec_size); + gk20a_dbg_info("falcon ucode DMEM offset %d phys base %x, load size %d", + desc.dmem_offset, desc.dmem_phys_base, + desc.dmem_load_size); + + if (desc.hdr_size.stored_size != desc.uncompressed_size) { + gk20a_dbg_info("does not match"); + return -EINVAL; + } + + ucode->code_entry_point = desc.virtual_entry; + ucode->bootloader = &g->bios.data[offset] + sizeof(desc); + ucode->bootloader_phys_base = desc.imem_phys_base; + ucode->bootloader_size = desc.imem_load_size - desc.imem_sec_size; + ucode->ucode = ucode->bootloader + ucode->bootloader_size; + ucode->phys_base = ucode->bootloader_phys_base + ucode->bootloader_size; + ucode->size = desc.imem_sec_size; + ucode->dmem = ucode->bootloader + desc.dmem_offset; + ucode->dmem_phys_base = desc.dmem_phys_base; + ucode->dmem_size = desc.dmem_load_size; + + return nvgpu_bios_parse_appinfo_table(g, + offset + sizeof(desc) + + desc.dmem_offset + desc.interface_offset); +} + +static int nvgpu_bios_parse_falcon_ucode_table(struct gk20a *g, int offset) +{ + struct falcon_ucode_table_hdr_v1 hdr; + int i; + + memcpy(&hdr, &g->bios.data[offset], sizeof(hdr)); + gk20a_dbg_fn("falcon ucode table ver %d size %d entrySize %d entryCount %d descVer %d descSize %d", + hdr.version, hdr.header_size, + hdr.entry_size, hdr.entry_count, + hdr.desc_version, hdr.desc_size); + + if (hdr.version != 1) + return -EINVAL; + + offset += hdr.header_size; + + for (i = 0; i < hdr.entry_count; i++) { + struct falcon_ucode_table_entry_v1 entry; + + memcpy(&entry, &g->bios.data[offset], sizeof(entry)); + + gk20a_dbg_fn("falcon ucode table entry appid %x targetId %x descPtr %x", + entry.application_id, entry.target_id, + entry.desc_ptr); + + if (entry.target_id == TARGET_ID_PMU && + entry.application_id == APPLICATION_ID_DEVINIT) { + int err; + + err = nvgpu_bios_parse_falcon_ucode_desc(g, + &g->bios.devinit, entry.desc_ptr); + if (err) + err = nvgpu_bios_parse_falcon_ucode_desc(g, + &g->bios.devinit, + entry.desc_ptr + + g->bios.expansion_rom_offset); + + if (err) + gk20a_err(dev_from_gk20a(g), + "could not parse devinit ucode desc"); + } else if (entry.target_id == TARGET_ID_PMU && + entry.application_id == APPLICATION_ID_PRE_OS) { + int err; + + err = nvgpu_bios_parse_falcon_ucode_desc(g, + &g->bios.preos, entry.desc_ptr); + if (err) + err = nvgpu_bios_parse_falcon_ucode_desc(g, + &g->bios.preos, + entry.desc_ptr + + g->bios.expansion_rom_offset); + + if (err) + gk20a_err(dev_from_gk20a(g), + "could not parse preos ucode desc"); + } + + offset += hdr.entry_size; + } + + return 0; +} + +static void nvgpu_bios_parse_falcon_data_v2(struct gk20a *g, int offset) +{ + struct falcon_data_v2 falcon_data; + int err; + + memcpy(&falcon_data, &g->bios.data[offset], sizeof(falcon_data)); + gk20a_dbg_fn("falcon ucode table ptr %x", + falcon_data.falcon_ucode_table_ptr); + err = nvgpu_bios_parse_falcon_ucode_table(g, + falcon_data.falcon_ucode_table_ptr); + if (err) + err = nvgpu_bios_parse_falcon_ucode_table(g, + falcon_data.falcon_ucode_table_ptr + + g->bios.expansion_rom_offset); + + if (err) + gk20a_err(dev_from_gk20a(g), + "could not parse falcon ucode table"); +} + +void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g, + struct bit_token *ptoken, u8 table_id) +{ + u32 perf_table_id_offset = 0; + u8 *perf_table_ptr = NULL; + u8 data_size = 4; + + if (ptoken != NULL) { + + if (ptoken->token_id == TOKEN_ID_VIRT_PTRS) { + perf_table_id_offset = *((u16 *)&g->bios.data[ + ptoken->data_ptr + + (table_id * PERF_PTRS_WIDTH_16)]); + data_size = PERF_PTRS_WIDTH_16; + } else { + perf_table_id_offset = *((u32 *)&g->bios.data[ + ptoken->data_ptr + + (table_id * PERF_PTRS_WIDTH)]); + data_size = PERF_PTRS_WIDTH; + } + } else + return (void *)perf_table_ptr; + + if (table_id < (ptoken->data_size/data_size)) { + + gk20a_dbg_info("Perf_Tbl_ID-offset 0x%x Tbl_ID_Ptr-offset- 0x%x", + (ptoken->data_ptr + + (table_id * data_size)), + perf_table_id_offset); + + if (perf_table_id_offset != 0) { + /* check is perf_table_id_offset is > 64k */ + if (perf_table_id_offset & ~0xFFFF) + perf_table_ptr = + &g->bios.data[g->bios.expansion_rom_offset + + perf_table_id_offset]; + else + perf_table_ptr = + &g->bios.data[perf_table_id_offset]; + } else + gk20a_warn(g->dev, "PERF TABLE ID %d is NULL", + table_id); + } else + gk20a_warn(g->dev, "INVALID PERF TABLE ID - %d ", table_id); + + return (void *)perf_table_ptr; +} + +static void nvgpu_bios_parse_bit(struct gk20a *g, int offset) +{ + struct bit bit; + struct bit_token bit_token; + int i; + + gk20a_dbg_fn(""); + memcpy(&bit, &g->bios.data[offset], sizeof(bit)); + + gk20a_dbg_info("BIT header: %04x %08x", bit.id, bit.signature); + gk20a_dbg_info("tokens: %d entries * %d bytes", + bit.token_entries, bit.token_size); + + offset += bit.header_size; + for (i = 0; i < bit.token_entries; i++) { + memcpy(&bit_token, &g->bios.data[offset], sizeof(bit_token)); + + gk20a_dbg_info("BIT token id %d ptr %d size %d ver %d", + bit_token.token_id, bit_token.data_ptr, + bit_token.data_size, bit_token.data_version); + + switch (bit_token.token_id) { + case TOKEN_ID_BIOSDATA: + nvgpu_bios_parse_biosdata(g, bit_token.data_ptr); + break; + case TOKEN_ID_NVINIT_PTRS: + nvgpu_bios_parse_nvinit_ptrs(g, bit_token.data_ptr); + break; + case TOKEN_ID_FALCON_DATA: + if (bit_token.data_version == 2) + nvgpu_bios_parse_falcon_data_v2(g, + bit_token.data_ptr); + break; + case TOKEN_ID_PERF_PTRS: + g->bios.perf_token = + (struct bit_token *)&g->bios.data[offset]; + break; + case TOKEN_ID_CLOCK_PTRS: + g->bios.clock_token = + (struct bit_token *)&g->bios.data[offset]; + break; + case TOKEN_ID_VIRT_PTRS: + g->bios.virt_token = + (struct bit_token *)&g->bios.data[offset]; + break; + case TOKEN_ID_MEMORY_PTRS: + nvgpu_bios_parse_memory_ptrs(g, bit_token.data_ptr, + bit_token.data_version); + default: + break; + } + + offset += bit.token_size; + } + gk20a_dbg_fn("done"); +} + +static u32 __nvgpu_bios_readbyte(struct gk20a *g, u32 offset) +{ + return (u32) g->bios.data[offset]; +} + +u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset) +{ + return (u8) __nvgpu_bios_readbyte(g, offset); +} + +s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset) +{ + u32 val; + val = __nvgpu_bios_readbyte(g, offset); + val = val & 0x80 ? (val | ~0xff) : val; + + return (s8) val; +} + +u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset) +{ + u16 val; + + val = __nvgpu_bios_readbyte(g, offset) | + (__nvgpu_bios_readbyte(g, offset+1) << 8); + + return val; +} + +u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset) +{ + u32 val; + + val = __nvgpu_bios_readbyte(g, offset) | + (__nvgpu_bios_readbyte(g, offset+1) << 8) | + (__nvgpu_bios_readbyte(g, offset+2) << 16) | + (__nvgpu_bios_readbyte(g, offset+3) << 24); + + return val; +} + +static void nvgpu_bios_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condition, + u32 reg, u32 stride, u32 count, u32 data_table_offset) +{ + u8 i; + u32 data, strap, index; + + if (*condition) { + + strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf; + + index = g->bios.mem_strap_xlat_tbl_ptr ? + nvgpu_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr + + strap) : strap; + + for (i = 0; i < count; i++) { + data = nvgpu_bios_read_u32(g, data_table_offset + ((i * + g->bios.mem_strap_data_count + index) * + sizeof(u32))); + gk20a_writel(g, reg, data); + reg += stride; + } + } +} + +static void gp106_init_condition(struct gk20a *g, bool *condition, + u32 condition_id) +{ + struct condition_entry entry; + + entry.cond_addr = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr + + sizeof(entry)*condition_id); + entry.cond_mask = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr + + sizeof(entry)*condition_id + 4); + entry.cond_compare = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr + + sizeof(entry)*condition_id + 8); + + if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask) + != entry.cond_compare) { + *condition = false; + } +} + +int nvgpu_bios_execute_script(struct gk20a *g, u32 offset) +{ + u8 opcode; + u32 ip; + u32 operand[8]; + bool condition, end; + int status = 0; + + ip = offset; + condition = true; + end = false; + + while (!end) { + + opcode = nvgpu_bios_read_u8(g, ip++); + + switch (opcode) { + + case INIT_XMEMSEL_ZM_NV_REG_ARRAY: + operand[0] = nvgpu_bios_read_u32(g, ip); + operand[1] = nvgpu_bios_read_u8(g, ip+4); + operand[2] = nvgpu_bios_read_u8(g, ip+5); + ip += 6; + + nvgpu_bios_init_xmemsel_zm_nv_reg_array(g, &condition, + operand[0], operand[1], operand[2], ip); + ip += operand[2] * sizeof(u32) * + g->bios.mem_strap_data_count; + break; + + case INIT_CONDITION: + operand[0] = nvgpu_bios_read_u8(g, ip); + ip++; + + gp106_init_condition(g, &condition, operand[0]); + break; + + case INIT_RESUME: + condition = true; + break; + + case INIT_DONE: + end = true; + break; + + default: + gk20a_err(dev_from_gk20a(g), "opcode: 0x%02x", opcode); + end = true; + status = -EINVAL; + break; + } + } + + return status; +} diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index ee6586ae..91c82104 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -918,8 +918,8 @@ int gk20a_pm_finalize_poweron(struct device *dev) g->gpu_reset_done = true; } - if (g->ops.bios.init) - err = g->ops.bios.init(g); + if (g->ops.bios_init) + err = g->ops.bios_init(g); if (err) goto done; diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 7f2383d9..b796b2cc 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -54,7 +54,6 @@ struct acr_desc; #include "cde_gk20a.h" #include "debug_gk20a.h" #include "sched_gk20a.h" -#include "gm206/bios_gm206.h" #ifdef CONFIG_ARCH_TEGRA_18x_SOC #include "clk/clk.h" #include "clk/clk_arb.h" @@ -62,7 +61,6 @@ struct acr_desc; #include "pmgr/pmgr.h" #include "therm/thrm.h" #endif -#include "gm206/bios_gm206.h" #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0) #define WRITE_ONCE(x, val) \ @@ -751,12 +749,8 @@ struct gpu_ops { int (*chip_init_gpu_characteristics)(struct gk20a *g); int (*read_ptimer)(struct gk20a *g, u64 *value); - struct { - int (*init)(struct gk20a *g); - void *(*get_perf_table_ptrs)(struct gk20a *g, - struct bit_token *ptoken, u8 table_id); - int (*execute_script)(struct gk20a *g, u32 offset); - } bios; + int (*bios_init)(struct gk20a *g); + #if defined(CONFIG_GK20A_CYCLE_STATS) struct { int (*enable_snapshot)(struct channel_gk20a *ch, diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c index a5551f42..3d12b9ac 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.c +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c @@ -16,6 +16,8 @@ #include #include +#include + #include "gk20a/gk20a.h" #include "gm20b/fifo_gm20b.h" #include "fifo_gm206.h" @@ -27,617 +29,12 @@ #include #include -#define BIT_HEADER_ID 0xb8ff -#define BIT_HEADER_SIGNATURE 0x00544942 -#define BIOS_SIZE 0x40000 -#define PCI_EXP_ROM_SIG 0xaa55 -#define PCI_EXP_ROM_SIG_NV 0x4e56 -#define ROM_FILE_PAYLOAD_OFFSET 0xa00 #define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */ #define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */ #define BIOS_OVERLAY_NAME "bios-%04x.rom" #define BIOS_OVERLAY_NAME_FORMATTED "bios-xxxx.rom" - -static u16 gm206_bios_rdu16(struct gk20a *g, int offset) -{ - u16 val = (g->bios.data[offset+1] << 8) + g->bios.data[offset]; - return val; -} - -static u32 gm206_bios_rdu32(struct gk20a *g, int offset) -{ - u32 val = (g->bios.data[offset+3] << 24) + - (g->bios.data[offset+2] << 16) + - (g->bios.data[offset+1] << 8) + - g->bios.data[offset]; - return val; -} - -struct bit { - u16 id; - u32 signature; - u16 bcd_version; - u8 header_size; - u8 token_size; - u8 token_entries; - u8 header_checksum; -} __packed; - -#define TOKEN_ID_BIOSDATA 0x42 -#define TOKEN_ID_NVINIT_PTRS 0x49 -#define TOKEN_ID_FALCON_DATA 0x70 -#define TOKEN_ID_PERF_PTRS 0x50 -#define TOKEN_ID_CLOCK_PTRS 0x43 -#define TOKEN_ID_VIRT_PTRS 0x56 -#define TOKEN_ID_MEMORY_PTRS 0x4D - - -union memory_ptrs { - struct { - u8 rsvd0[2]; - u8 mem_strap_data_count; - u16 mem_strap_xlat_tbl_ptr; - u8 rsvd1[8]; - } v1 __packed; - struct { - u8 mem_strap_data_count; - u16 mem_strap_xlat_tbl_ptr; - u8 rsvd[14]; - } v2 __packed; -}; - -struct biosdata { - u32 version; - u8 oem_version; - u8 checksum; - u16 int15callbackspost; - u16 int16callbackssystem; - u16 boardid; - u16 framecount; - u8 biosmoddate[8]; -} __packed; - -struct nvinit_ptrs { - u16 initscript_table_ptr; - u16 macro_index_table_ptr; - u16 macro_table_ptr; - u16 condition_table_ptr; - u16 io_condition_table_ptr; - u16 io_flag_condition_table_ptr; - u16 init_function_table_ptr; - u16 vbios_private_table_ptr; - u16 data_arrays_table_ptr; - u16 pcie_settings_script_ptr; - u16 devinit_tables_ptr; - u16 devinit_tables_size; - u16 bootscripts_ptr; - u16 bootscripts_size; - u16 nvlink_config_data_ptr; -} __packed; - -struct falcon_data_v2 { - u32 falcon_ucode_table_ptr; -} __packed; - -struct falcon_ucode_table_hdr_v1 { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u8 desc_version; - u8 desc_size; -} __packed; - -struct falcon_ucode_table_entry_v1 { - u8 application_id; - u8 target_id; - u32 desc_ptr; -} __packed; - -#define TARGET_ID_PMU 0x01 -#define APPLICATION_ID_DEVINIT 0x04 -#define APPLICATION_ID_PRE_OS 0x01 - -struct falcon_ucode_desc_v1 { - union { - u32 v_desc; - u32 stored_size; - } hdr_size; - u32 uncompressed_size; - u32 virtual_entry; - u32 interface_offset; - u32 imem_phys_base; - u32 imem_load_size; - u32 imem_virt_base; - u32 imem_sec_base; - u32 imem_sec_size; - u32 dmem_offset; - u32 dmem_phys_base; - u32 dmem_load_size; -} __packed; - -struct application_interface_table_hdr_v1 { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; -} __packed; - -struct application_interface_entry_v1 { - u32 id; - u32 dmem_offset; -} __packed; - -#define APPINFO_ID_DEVINIT 0x01 - -struct devinit_engine_interface { - u32 field0; - u32 field1; - u32 tables_phys_base; - u32 tables_virt_base; - u32 script_phys_base; - u32 script_virt_base; - u32 script_virt_entry; - u16 script_size; - u8 memory_strap_count; - u8 reserved; - u32 memory_information_table_virt_base; - u32 empty_script_virt_base; - u32 cond_table_virt_base; - u32 io_cond_table_virt_base; - u32 data_arrays_table_virt_base; - u32 gpio_assignment_table_virt_base; -} __packed; - -struct pci_exp_rom { - u16 sig; - u8 reserved[0x16]; - u16 pci_data_struct_ptr; - u32 size_of_block; -} __packed; - -struct pci_data_struct { - u32 sig; - u16 vendor_id; - u16 device_id; - u16 device_list_ptr; - u16 pci_data_struct_len; - u8 pci_data_struct_rev; - u8 class_code[3]; - u16 image_len; - u16 vendor_rom_rev; - u8 code_type; - u8 last_image; - u16 max_runtime_image_len; -} __packed; - -struct pci_ext_data_struct { - u32 sig; - u16 nv_pci_data_ext_rev; - u16 nv_pci_data_ext_len; - u16 sub_image_len; - u8 priv_last_image; - u8 flags; -} __packed; - -static int gm206_bios_parse_rom(struct gk20a *g) -{ - int offset = 0; - int last = 0; - - while (!last) { - struct pci_exp_rom *pci_rom; - struct pci_data_struct *pci_data; - struct pci_ext_data_struct *pci_ext_data; - - pci_rom = (struct pci_exp_rom *)&g->bios.data[offset]; - gk20a_dbg_fn("pci rom sig %04x ptr %04x block %x", - pci_rom->sig, pci_rom->pci_data_struct_ptr, - pci_rom->size_of_block); - - if (pci_rom->sig != PCI_EXP_ROM_SIG && - pci_rom->sig != PCI_EXP_ROM_SIG_NV) { - gk20a_err(g->dev, "invalid VBIOS signature"); - return -EINVAL; - } - - pci_data = - (struct pci_data_struct *) - &g->bios.data[offset + pci_rom->pci_data_struct_ptr]; - gk20a_dbg_fn("pci data sig %08x len %d image len %x type %x last %d max %08x", - pci_data->sig, pci_data->pci_data_struct_len, - pci_data->image_len, pci_data->code_type, - pci_data->last_image, - pci_data->max_runtime_image_len); - - if (pci_data->code_type == 0x3) { - pci_ext_data = (struct pci_ext_data_struct *) - &g->bios.data[(offset + - pci_rom->pci_data_struct_ptr + - pci_data->pci_data_struct_len + - 0xf) - & ~0xf]; - gk20a_dbg_fn("pci ext data sig %08x rev %x len %x sub_image_len %x priv_last %d flags %x", - pci_ext_data->sig, - pci_ext_data->nv_pci_data_ext_rev, - pci_ext_data->nv_pci_data_ext_len, - pci_ext_data->sub_image_len, - pci_ext_data->priv_last_image, - pci_ext_data->flags); - - gk20a_dbg_fn("expansion rom offset %x", - pci_data->image_len * 512); - g->bios.expansion_rom_offset = - pci_data->image_len * 512; - offset += pci_ext_data->sub_image_len * 512; - last = pci_ext_data->priv_last_image; - } else { - offset += pci_data->image_len * 512; - last = pci_data->last_image; - } - } - - return 0; -} - -static void gm206_bios_parse_biosdata(struct gk20a *g, int offset) -{ - struct biosdata biosdata; - - memcpy(&biosdata, &g->bios.data[offset], sizeof(biosdata)); - gk20a_dbg_fn("bios version %x, oem version %x", - biosdata.version, - biosdata.oem_version); - - g->gpu_characteristics.vbios_version = biosdata.version; - g->gpu_characteristics.vbios_oem_version = biosdata.oem_version; -} - -static void gm206_bios_parse_nvinit_ptrs(struct gk20a *g, int offset) -{ - struct nvinit_ptrs nvinit_ptrs; - - memcpy(&nvinit_ptrs, &g->bios.data[offset], sizeof(nvinit_ptrs)); - gk20a_dbg_fn("devinit ptr %x size %d", nvinit_ptrs.devinit_tables_ptr, - nvinit_ptrs.devinit_tables_size); - gk20a_dbg_fn("bootscripts ptr %x size %d", nvinit_ptrs.bootscripts_ptr, - nvinit_ptrs.bootscripts_size); - - g->bios.devinit_tables = &g->bios.data[nvinit_ptrs.devinit_tables_ptr]; - g->bios.devinit_tables_size = nvinit_ptrs.devinit_tables_size; - g->bios.bootscripts = &g->bios.data[nvinit_ptrs.bootscripts_ptr]; - g->bios.bootscripts_size = nvinit_ptrs.bootscripts_size; - g->bios.condition_table_ptr = nvinit_ptrs.condition_table_ptr; -} - -static void gm206_bios_parse_memory_ptrs(struct gk20a *g, int offset, u8 version) -{ - union memory_ptrs memory_ptrs; - - if ((version < 1) || (version > 2)) - return; - - memcpy(&memory_ptrs, &g->bios.data[offset], sizeof(memory_ptrs)); - - g->bios.mem_strap_data_count = (version > 1) ? memory_ptrs.v2.mem_strap_data_count : - memory_ptrs.v1.mem_strap_data_count; - g->bios.mem_strap_xlat_tbl_ptr = (version > 1) ? memory_ptrs.v2.mem_strap_xlat_tbl_ptr : - memory_ptrs.v1.mem_strap_xlat_tbl_ptr; -} - -static void gm206_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset) -{ - struct devinit_engine_interface interface; - - memcpy(&interface, &g->bios.devinit.dmem[dmem_offset], sizeof(interface)); - gk20a_dbg_fn("devinit tables phys %x script phys %x size %d", - interface.tables_phys_base, - interface.script_phys_base, - interface.script_size); - - g->bios.devinit_tables_phys_base = interface.tables_phys_base; - g->bios.devinit_script_phys_base = interface.script_phys_base; -} - -static int gm206_bios_parse_appinfo_table(struct gk20a *g, int offset) -{ - struct application_interface_table_hdr_v1 hdr; - int i; - - memcpy(&hdr, &g->bios.data[offset], sizeof(hdr)); - - gk20a_dbg_fn("appInfoHdr ver %d size %d entrySize %d entryCount %d", - hdr.version, hdr.header_size, - hdr.entry_size, hdr.entry_count); - - if (hdr.version != 1) - return 0; - - offset += sizeof(hdr); - for (i = 0; i < hdr.entry_count; i++) { - struct application_interface_entry_v1 entry; - - memcpy(&entry, &g->bios.data[offset], sizeof(entry)); - - gk20a_dbg_fn("appInfo id %d dmem_offset %d", - entry.id, entry.dmem_offset); - - if (entry.id == APPINFO_ID_DEVINIT) - gm206_bios_parse_devinit_appinfo(g, entry.dmem_offset); - - offset += hdr.entry_size; - } - - return 0; -} - -static int gm206_bios_parse_falcon_ucode_desc(struct gk20a *g, - struct nvgpu_bios_ucode *ucode, int offset) -{ - struct falcon_ucode_desc_v1 desc; - - memcpy(&desc, &g->bios.data[offset], sizeof(desc)); - gk20a_dbg_info("falcon ucode desc stored size %d uncompressed size %d", - desc.hdr_size.stored_size, desc.uncompressed_size); - gk20a_dbg_info("falcon ucode desc virtualEntry %x, interfaceOffset %x", - desc.virtual_entry, desc.interface_offset); - gk20a_dbg_info("falcon ucode IMEM phys base %x, load size %x virt base %x sec base %x sec size %x", - desc.imem_phys_base, desc.imem_load_size, - desc.imem_virt_base, desc.imem_sec_base, - desc.imem_sec_size); - gk20a_dbg_info("falcon ucode DMEM offset %d phys base %x, load size %d", - desc.dmem_offset, desc.dmem_phys_base, - desc.dmem_load_size); - - if (desc.hdr_size.stored_size != desc.uncompressed_size) { - gk20a_dbg_info("does not match"); - return -EINVAL; - } - - ucode->code_entry_point = desc.virtual_entry; - ucode->bootloader = &g->bios.data[offset] + sizeof(desc); - ucode->bootloader_phys_base = desc.imem_phys_base; - ucode->bootloader_size = desc.imem_load_size - desc.imem_sec_size; - ucode->ucode = ucode->bootloader + ucode->bootloader_size; - ucode->phys_base = ucode->bootloader_phys_base + ucode->bootloader_size; - ucode->size = desc.imem_sec_size; - ucode->dmem = ucode->bootloader + desc.dmem_offset; - ucode->dmem_phys_base = desc.dmem_phys_base; - ucode->dmem_size = desc.dmem_load_size; - - return gm206_bios_parse_appinfo_table(g, - offset + sizeof(desc) + - desc.dmem_offset + desc.interface_offset); -} - -static int gm206_bios_parse_falcon_ucode_table(struct gk20a *g, int offset) -{ - struct falcon_ucode_table_hdr_v1 hdr; - int i; - - memcpy(&hdr, &g->bios.data[offset], sizeof(hdr)); - gk20a_dbg_fn("falcon ucode table ver %d size %d entrySize %d entryCount %d descVer %d descSize %d", - hdr.version, hdr.header_size, - hdr.entry_size, hdr.entry_count, - hdr.desc_version, hdr.desc_size); - - if (hdr.version != 1) - return -EINVAL; - - offset += hdr.header_size; - - for (i = 0; i < hdr.entry_count; i++) { - struct falcon_ucode_table_entry_v1 entry; - - memcpy(&entry, &g->bios.data[offset], sizeof(entry)); - - gk20a_dbg_fn("falcon ucode table entry appid %x targetId %x descPtr %x", - entry.application_id, entry.target_id, - entry.desc_ptr); - - if (entry.target_id == TARGET_ID_PMU && - entry.application_id == APPLICATION_ID_DEVINIT) { - int err; - - err = gm206_bios_parse_falcon_ucode_desc(g, - &g->bios.devinit, entry.desc_ptr); - if (err) - err = gm206_bios_parse_falcon_ucode_desc(g, - &g->bios.devinit, - entry.desc_ptr + - g->bios.expansion_rom_offset); - - if (err) - gk20a_err(dev_from_gk20a(g), - "could not parse devinit ucode desc"); - } else if (entry.target_id == TARGET_ID_PMU && - entry.application_id == APPLICATION_ID_PRE_OS) { - int err; - - err = gm206_bios_parse_falcon_ucode_desc(g, - &g->bios.preos, entry.desc_ptr); - if (err) - err = gm206_bios_parse_falcon_ucode_desc(g, - &g->bios.preos, - entry.desc_ptr + - g->bios.expansion_rom_offset); - - if (err) - gk20a_err(dev_from_gk20a(g), - "could not parse preos ucode desc"); - } - - offset += hdr.entry_size; - } - - return 0; -} - -static void gm206_bios_parse_falcon_data_v2(struct gk20a *g, int offset) -{ - struct falcon_data_v2 falcon_data; - int err; - - memcpy(&falcon_data, &g->bios.data[offset], sizeof(falcon_data)); - gk20a_dbg_fn("falcon ucode table ptr %x", - falcon_data.falcon_ucode_table_ptr); - err = gm206_bios_parse_falcon_ucode_table(g, - falcon_data.falcon_ucode_table_ptr); - if (err) - err = gm206_bios_parse_falcon_ucode_table(g, - falcon_data.falcon_ucode_table_ptr + - g->bios.expansion_rom_offset); - - if (err) - gk20a_err(dev_from_gk20a(g), - "could not parse falcon ucode table"); -} - -static void *gm206_bios_get_perf_table_ptrs(struct gk20a *g, - struct bit_token *ptoken, u8 table_id) -{ - u32 perf_table_id_offset = 0; - u8 *perf_table_ptr = NULL; - u8 data_size = 4; - - if (ptoken != NULL) { - - if (ptoken->token_id == TOKEN_ID_VIRT_PTRS) { - perf_table_id_offset = *((u16 *)&g->bios.data[ - ptoken->data_ptr + - (table_id * PERF_PTRS_WIDTH_16)]); - data_size = PERF_PTRS_WIDTH_16; - } else { - perf_table_id_offset = *((u32 *)&g->bios.data[ - ptoken->data_ptr + - (table_id * PERF_PTRS_WIDTH)]); - data_size = PERF_PTRS_WIDTH; - } - } else - return (void *)perf_table_ptr; - - if (table_id < (ptoken->data_size/data_size)) { - - gk20a_dbg_info("Perf_Tbl_ID-offset 0x%x Tbl_ID_Ptr-offset- 0x%x", - (ptoken->data_ptr + - (table_id * data_size)), - perf_table_id_offset); - - if (perf_table_id_offset != 0) { - /* check is perf_table_id_offset is > 64k */ - if (perf_table_id_offset & ~0xFFFF) - perf_table_ptr = - &g->bios.data[g->bios.expansion_rom_offset + - perf_table_id_offset]; - else - perf_table_ptr = - &g->bios.data[perf_table_id_offset]; - } else - gk20a_warn(g->dev, "PERF TABLE ID %d is NULL", - table_id); - } else - gk20a_warn(g->dev, "INVALID PERF TABLE ID - %d ", table_id); - - return (void *)perf_table_ptr; -} - -static void gm206_bios_parse_bit(struct gk20a *g, int offset) -{ - struct bit bit; - struct bit_token bit_token; - int i; - - gk20a_dbg_fn(""); - memcpy(&bit, &g->bios.data[offset], sizeof(bit)); - - gk20a_dbg_info("BIT header: %04x %08x", bit.id, bit.signature); - gk20a_dbg_info("tokens: %d entries * %d bytes", - bit.token_entries, bit.token_size); - - offset += bit.header_size; - for (i = 0; i < bit.token_entries; i++) { - memcpy(&bit_token, &g->bios.data[offset], sizeof(bit_token)); - - gk20a_dbg_info("BIT token id %d ptr %d size %d ver %d", - bit_token.token_id, bit_token.data_ptr, - bit_token.data_size, bit_token.data_version); - - switch (bit_token.token_id) { - case TOKEN_ID_BIOSDATA: - gm206_bios_parse_biosdata(g, bit_token.data_ptr); - break; - case TOKEN_ID_NVINIT_PTRS: - gm206_bios_parse_nvinit_ptrs(g, bit_token.data_ptr); - break; - case TOKEN_ID_FALCON_DATA: - if (bit_token.data_version == 2) - gm206_bios_parse_falcon_data_v2(g, - bit_token.data_ptr); - break; - case TOKEN_ID_PERF_PTRS: - g->bios.perf_token = - (struct bit_token *)&g->bios.data[offset]; - break; - case TOKEN_ID_CLOCK_PTRS: - g->bios.clock_token = - (struct bit_token *)&g->bios.data[offset]; - break; - case TOKEN_ID_VIRT_PTRS: - g->bios.virt_token = - (struct bit_token *)&g->bios.data[offset]; - break; - case TOKEN_ID_MEMORY_PTRS: - gm206_bios_parse_memory_ptrs(g, bit_token.data_ptr, - bit_token.data_version); - default: - break; - } - - offset += bit.token_size; - } - gk20a_dbg_fn("done"); -} - -static u32 __gm206_bios_readbyte(struct gk20a *g, u32 offset) -{ - return (u32) g->bios.data[offset]; -} - -u8 gm206_bios_read_u8(struct gk20a *g, u32 offset) -{ - return (u8) __gm206_bios_readbyte(g, offset); -} - -s8 gm206_bios_read_s8(struct gk20a *g, u32 offset) -{ - u32 val; - val = __gm206_bios_readbyte(g, offset); - val = val & 0x80 ? (val | ~0xff) : val; - - return (s8) val; -} - -u16 gm206_bios_read_u16(struct gk20a *g, u32 offset) -{ - u16 val; - - val = __gm206_bios_readbyte(g, offset) | - (__gm206_bios_readbyte(g, offset+1) << 8); - - return val; -} - -u32 gm206_bios_read_u32(struct gk20a *g, u32 offset) -{ - u32 val; - - val = __gm206_bios_readbyte(g, offset) | - (__gm206_bios_readbyte(g, offset+1) << 8) | - (__gm206_bios_readbyte(g, offset+2) << 16) | - (__gm206_bios_readbyte(g, offset+3) << 24); - - return val; -} +#define ROM_FILE_PAYLOAD_OFFSET 0xa00 +#define BIOS_SIZE 0x40000 static void upload_code(struct gk20a *g, u32 dst, u8 *src, u32 size, u8 port, bool sec) @@ -831,14 +228,13 @@ static int gm206_bios_preos(struct gk20a *g) return err; } -static int gm206_bios_init(struct gk20a *g) +int gm206_bios_init(struct gk20a *g) { unsigned int i; struct gk20a_platform *platform = dev_get_drvdata(g->dev); struct dentry *d; const struct firmware *bios_fw; int err; - bool found = 0; struct pci_dev *pdev = to_pci_dev(g->dev); char rom_name[sizeof(BIOS_OVERLAY_NAME_FORMATTED)]; @@ -880,24 +276,10 @@ static int gm206_bios_init(struct gk20a *g) g->ops.xve.enable_shadow_rom(g); } - err = gm206_bios_parse_rom(g); + err = nvgpu_bios_parse_rom(g); if (err) return err; - gk20a_dbg_info("read bios"); - for (i = 0; i < g->bios.size - 6; i++) { - if (gm206_bios_rdu16(g, i) == BIT_HEADER_ID && - gm206_bios_rdu32(g, i+2) == BIT_HEADER_SIGNATURE) { - gm206_bios_parse_bit(g, i); - found = true; - } - } - - if (!found) { - gk20a_err(g->dev, "no valid VBIOS found"); - return -EINVAL; - } - if (g->gpu_characteristics.vbios_version < platform->vbios_min_version) { gk20a_err(g->dev, "unsupported VBIOS version %08x", @@ -936,8 +318,7 @@ free_firmware: return err; } -void gm206_init_bios(struct gpu_ops *gops) +void gm206_init_bios_ops(struct gpu_ops *gops) { - gops->bios.init = gm206_bios_init; - gops->bios.get_perf_table_ptrs = gm206_bios_get_perf_table_ptrs; + gops->bios_init = gm206_bios_init; } diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.h b/drivers/gpu/nvgpu/gm206/bios_gm206.h index 6fe19fb0..090c7d24 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.h +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.h @@ -14,60 +14,10 @@ #ifndef NVGPU_BIOS_GM206_H #define NVGPU_BIOS_GM206_H -#define PERF_PTRS_WIDTH 0x4 -#define PERF_PTRS_WIDTH_16 0x2 - -#define NV_PCFG 0x88000 - -enum { - CLOCKS_TABLE = 2, - CLOCK_PROGRAMMING_TABLE, - FLL_TABLE, - VIN_TABLE, - FREQUENCY_CONTROLLER_TABLE -}; - -enum { - PERFORMANCE_TABLE = 0, - MEMORY_CLOCK_TABLE, - MEMORY_TWEAK_TABLE, - POWER_CONTROL_TABLE, - THERMAL_CONTROL_TABLE, - THERMAL_DEVICE_TABLE, - THERMAL_COOLERS_TABLE, - PERFORMANCE_SETTINGS_SCRIPT, - CONTINUOUS_VIRTUAL_BINNING_TABLE, - POWER_SENSORS_TABLE = 0xA, - POWER_CAPPING_TABLE = 0xB, - POWER_TOPOLOGY_TABLE = 0xF, - THERMAL_CHANNEL_TABLE = 0x12, - VOLTAGE_RAIL_TABLE = 26, - VOLTAGE_DEVICE_TABLE, - VOLTAGE_POLICY_TABLE, - LOWPOWER_TABLE, - LOWPOWER_GR_TABLE = 32, - LOWPOWER_MS_TABLE = 33, -}; - -enum { - VP_FIELD_TABLE = 0, - VP_FIELD_REGISTER, - VP_TRANSLATION_TABLE, -}; - -struct bit_token { - u8 token_id; - u8 data_version; - u16 data_size; - u16 data_ptr; -} __packed; - +struct gk20a; struct gpu_ops; -void gm206_init_bios(struct gpu_ops *gops); -u8 gm206_bios_read_u8(struct gk20a *g, u32 offset); -s8 gm206_bios_read_s8(struct gk20a *g, u32 offset); -u16 gm206_bios_read_u16(struct gk20a *g, u32 offset); -u32 gm206_bios_read_u32(struct gk20a *g, u32 offset); +int gm206_bios_init(struct gk20a *g); +void gm206_init_bios_ops(struct gpu_ops *gops); #endif diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.c b/drivers/gpu/nvgpu/gm206/hal_gm206.c index 8ad5a397..e2b84d81 100644 --- a/drivers/gpu/nvgpu/gm206/hal_gm206.c +++ b/drivers/gpu/nvgpu/gm206/hal_gm206.c @@ -198,7 +198,7 @@ int gm206_init_hal(struct gk20a *g) #if defined(CONFIG_GK20A_CYCLE_STATS) gk20a_init_css_ops(gops); #endif - gm206_init_bios(gops); + gm206_init_bios_ops(gops); switch(ver){ case GK20A_GPUID_GM206: gops->name = "gm206"; diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.c b/drivers/gpu/nvgpu/gp106/bios_gp106.c deleted file mode 100644 index d3e565ca..00000000 --- a/drivers/gpu/nvgpu/gp106/bios_gp106.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "gk20a/gk20a.h" -#include "gm206/bios_gm206.h" - -#include "bios_gp106.h" - -#include - -static void gp106_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condition, - u32 reg, u32 stride, u32 count, u32 data_table_offset) -{ - u8 i; - u32 data, strap, index; - - if (*condition) { - - strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf; - - index = g->bios.mem_strap_xlat_tbl_ptr ? - gm206_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr + - strap) : strap; - - for (i = 0; i < count; i++) { - data = gm206_bios_read_u32(g, data_table_offset + ((i * - g->bios.mem_strap_data_count + index) * - sizeof(u32))); - gk20a_writel(g, reg, data); - reg += stride; - } - } -} - -static void gp106_init_condition(struct gk20a *g, bool *condition, - u32 condition_id) -{ - struct condition_entry entry; - - entry.cond_addr = gm206_bios_read_u32(g, g->bios.condition_table_ptr + - sizeof(entry)*condition_id); - entry.cond_mask = gm206_bios_read_u32(g, g->bios.condition_table_ptr + - sizeof(entry)*condition_id + 4); - entry.cond_compare = gm206_bios_read_u32(g, g->bios.condition_table_ptr + - sizeof(entry)*condition_id + 8); - - if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask) - != entry.cond_compare) { - *condition = false; - } -} - -static int gp106_execute_script(struct gk20a *g, u32 offset) -{ - u8 opcode; - u32 ip; - u32 operand[8]; - bool condition, end; - int status = 0; - - ip = offset; - condition = true; - end = false; - - while (!end) { - - opcode = gm206_bios_read_u8(g, ip++); - - switch (opcode) { - - case INIT_XMEMSEL_ZM_NV_REG_ARRAY: - operand[0] = gm206_bios_read_u32(g, ip); - operand[1] = gm206_bios_read_u8(g, ip+4); - operand[2] = gm206_bios_read_u8(g, ip+5); - ip += 6; - - gp106_init_xmemsel_zm_nv_reg_array(g, &condition, - operand[0], operand[1], operand[2], ip); - ip += operand[2] * sizeof(u32) * - g->bios.mem_strap_data_count; - break; - - case INIT_CONDITION: - operand[0] = gm206_bios_read_u8(g, ip); - ip++; - - gp106_init_condition(g, &condition, operand[0]); - break; - - case INIT_RESUME: - condition = true; - break; - - case INIT_DONE: - end = true; - break; - - default: - gk20a_err(dev_from_gk20a(g), "opcode: 0x%02x", opcode); - end = true; - status = -EINVAL; - break; - } - } - - return status; -} - -void gp106_init_bios(struct gpu_ops *gops) -{ - gm206_init_bios(gops); - gops->bios.execute_script = gp106_execute_script; -} diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.h b/drivers/gpu/nvgpu/gp106/bios_gp106.h deleted file mode 100644 index f47d11ca..00000000 --- a/drivers/gpu/nvgpu/gp106/bios_gp106.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef NVGPU_BIOS_GP106_H -#define NVGPU_BIOS_GP106_H - -struct gpu_ops; - -#define INIT_DONE 0x71 -#define INIT_RESUME 0x72 -#define INIT_CONDITION 0x75 -#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f - -struct condition_entry { - u32 cond_addr; - u32 cond_mask; - u32 cond_compare; -} __packed; - -void gp106_init_bios(struct gpu_ops *gops); -#endif diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index e3874c06..cece5dd6 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -39,7 +39,7 @@ #include "gp106/clk_gp106.h" #include "gp106/clk_arb_gp106.h" -#include "gp106/bios_gp106.h" +#include "gm206/bios_gm206.h" #include "gp106/therm_gp106.h" #include "gp106/xve_gp106.h" #include "gp106/fifo_gp106.h" @@ -245,7 +245,7 @@ int gp106_init_hal(struct gk20a *g) #if defined(CONFIG_GK20A_CYCLE_STATS) gk20a_init_css_ops(gops); #endif - gp106_init_bios(gops); + gm206_init_bios_ops(gops); gp106_init_therm_ops(gops); gp106_init_xve_ops(gops); diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h deleted file mode 100644 index bcb24343..00000000 --- a/drivers/gpu/nvgpu/include/bios.h +++ /dev/null @@ -1,992 +0,0 @@ -/* - * vbios tables support - * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef NVGPU_INCLUDE_BIOS_H -#define NVGPU_INCLUDE_BIOS_H - -#include "gk20a/gk20a.h" - -#define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT) - -struct fll_descriptor_header { - u8 version; - u8 size; -} __packed; - -#define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4 -#define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6 - -struct fll_descriptor_header_10 { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u16 max_min_freq_mhz; -} __packed; - -#define FLL_DESCRIPTOR_ENTRY_10_SIZE 15 - -struct fll_descriptor_entry_10 { - u8 fll_device_type; - u8 clk_domain; - u8 fll_device_id; - u16 lut_params; - u8 vin_idx_logic; - u8 vin_idx_sram; - u16 fll_params; - u8 min_freq_vfe_idx; - u8 freq_ctrl_idx; - u16 ref_freq_mhz; - u16 ffr_cutoff_freq_mhz; -} __packed; - -#define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F -#define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 - -#define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 -#define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 - -#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C -#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2 - -struct vin_descriptor_header_10 { - u8 version; - u8 header_sizee; - u8 entry_size; - u8 entry_count; - u8 flags0; - u32 vin_cal; -} __packed; - -struct vin_descriptor_entry_10 { - u8 vin_device_type; - u8 volt_domain_vbios; - u8 vin_device_id; -} __packed; - -#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7 -#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0 - -#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8 -#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3 - -#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF -#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0 - -#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00 -#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT 10 - -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000 -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14 - -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000 -#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18 - -#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07 -struct vbios_clocks_table_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u8 clocks_hal; - u16 cntr_sampling_periodms; -} __packed; - -#define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09 -struct vbios_clocks_table_1x_entry { - u8 flags0; - u16 param0; - u32 param1; - u16 param2; -} __packed; - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1F -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER 0x01 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE 0x02 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK 0xFF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK 0xFF00 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK 0xFFFF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT 0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK 0xF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT 0 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK 0xF0 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT 4 - -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00 -#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01 - -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08 -struct vbios_clock_programming_table_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u8 slave_entry_size; - u8 slave_entry_count; - u8 vf_entry_size; - u8 vf_entry_count; -} __packed; - -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05 -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0D -struct vbios_clock_programming_table_1x_entry { - u8 flags0; - u16 freq_max_mhz; - u8 param0; - u8 param1; - u32 rsvd; - u32 rsvd1; -} __packed; - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK 0xF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO 0x00 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE 0x01 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE 0x02 - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK 0x70 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT 4 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL 0x00 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE 0x01 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL 0x02 - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK 0x80 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT 7 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE 0x00 -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE 0x01 - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK 0xFF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT 0 - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0 - -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03 -struct vbios_clock_programming_table_1x_slave_entry { - u8 clk_dom_idx; - u16 param0; -} __packed; - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_MASK 0xFF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_SHIFT 0 - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK 0x3FFF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT 0 - -#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02 -struct vbios_clock_programming_table_1x_vf_entry { - u8 vfe_idx; - u8 param0; -} __packed; - -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_MASK 0xFF -#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_SHIFT 0 - -struct vbios_vfe_3x_header_struct { - u8 version; - u8 header_size; - u8 vfe_var_entry_size; - u8 vfe_var_entry_count; - u8 vfe_equ_entry_size; - u8 vfe_equ_entry_count; - u8 polling_periodms; -} __packed; - -#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11 -#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19 -struct vbios_vfe_3x_var_entry_struct { - u8 type; - u32 out_range_min; - u32 out_range_max; - u32 param0; - u32 param1; - u32 param2; - u32 param3; -} __packed; - -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05 -#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_SHIFT 8 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_MASK 0xFF0000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_SHIFT 16 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_SHIFT 8 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_MASK 0xFF0000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_SHIFT 16 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_SHIFT 8 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_MASK 0xFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_MASK 0xFF00 -#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_SHIFT 8 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_SHIFT 0 - -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17 -#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18 - -struct vbios_vfe_3x_equ_entry_struct { - u8 type; - u8 var_idx; - u8 equ_idx_next; - u32 out_range_min; - u32 out_range_max; - u32 param0; - u32 param1; - u32 param2; - u8 param3; -} __packed; - - -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00 -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01 -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02 -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03 -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04 -#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05 - -#define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFF - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_MASK 0xFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_MASK 0xFF00 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_SHIFT 8 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_MASK 0xFFFFFFFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_MASK 0xFF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_SHIFT 0 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_MASK 0xFF00 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_SHIFT 8 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_MASK 0x70000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_SHIFT 16 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_EQUAL 0x00000000 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER_EQ 0x00000001 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER 0x00000002 - -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_MASK 0xF -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_SHIFT 0 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS 0x0 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_FREQ_MHZ 0x1 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_UV 0x2 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 -#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 - -#define NV_VFIELD_DESC_SIZE_BYTE 0x00000000 -#define NV_VFIELD_DESC_SIZE_WORD 0x00000001 -#define NV_VFIELD_DESC_SIZE_DWORD 0x00000002 -#define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18) >> 3) - -#define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000 -#define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001 -#define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002 - -#define NV_VFIELD_DESC_CODE_INVALID NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID -#define NV_VFIELD_DESC_CODE_REG NV_PMU_BIOS_VFIELD_DESC_CODE_REG -#define NV_VFIELD_DESC_CODE_INDEX_REG NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG - -#define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0) >> 5) - -#define VFIELD_ID_STRAP_IDDQ 0x09 -#define VFIELD_ID_STRAP_IDDQ_1 0x0B - -#define VFIELD_REG_HEADER_SIZE 3 -struct vfield_reg_header { - u8 version; - u8 entry_size; - u8 count; -} __packed; - -#define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10 - - -#define VFIELD_REG_ENTRY_SIZE 13 -struct vfield_reg_entry { - u8 strap_reg_desc; - u32 reg; - u32 reg_index; - u32 index; -} __packed; - -#define VFIELD_HEADER_SIZE 3 - -struct vfield_header { - u8 version; - u8 entry_size; - u8 count; -} __packed; - -#define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10 - -#define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1F) -#define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0) >> 5) -#define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00) >> 10) - -#define VFIELD_ENTRY_SIZE 3 - -struct vfield_entry { - u8 strap_id; - u16 strap_desc; -} __packed; - -#define PERF_CLK_DOMAINS_IDX_MAX (32) -#define PERF_CLK_DOMAINS_IDX_INVALID PERF_CLK_DOMAINS_IDX_MAX - -#define VBIOS_PSTATE_TABLE_VERSION_5X 0x50 -#define VBIOS_PSTATE_HEADER_5X_SIZE_10 (10) - -struct vbios_pstate_header_5x { - u8 version; - u8 header_size; - u8 base_entry_size; - u8 base_entry_count; - u8 clock_entry_size; - u8 clock_entry_count; - u8 flags0; - u8 initial_pstate; - u8 cpi_support_level; -u8 cpi_features; -} __packed; - -#define VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6 6 - -#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2 0x2 -#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3 0x3 - -struct vbios_pstate_entry_clock_5x { - u16 param0; - u32 param1; -} __packed; - -struct vbios_pstate_entry_5x { - u8 pstate_level; - u8 flags0; - u8 lpwr_entry_idx; - struct vbios_pstate_entry_clock_5x clockEntry[PERF_CLK_DOMAINS_IDX_MAX]; -} __packed; - -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_SHIFT 0 -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_MASK 0x00003FFF - -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_SHIFT 0 -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_MASK 0x00003FFF - -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT 14 -#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK 0x0FFFC000 - -#define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFF - -#define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION 0x11 - -#define VBIOS_MEMORY_CLOCK_HEADER_11_0_SIZE 16 -#define VBIOS_MEMORY_CLOCK_HEADER_11_1_SIZE 21 -#define VBIOS_MEMORY_CLOCK_HEADER_11_2_SIZE 26 - -struct vbios_memory_clock_header_1x { - u8 version; - u8 header_size; - u8 base_entry_size; - u8 strap_entry_size; - u8 strap_entry_count; - u8 entry_count; - u8 flags; - u8 fbvdd_settle_time; - u32 cfg_pwrd_val; - u16 fbvddq_high; - u16 fbvddq_low; - u32 script_list_ptr; - u8 script_list_count; - u32 cmd_script_list_ptr; - u8 cmd_script_list_count; -} __packed; - -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_2_SIZE 20 - -struct vbios_memory_clock_base_entry_11 { - u16 minimum; - u16 maximum; - u32 script_pointer; - u8 flags0; - u32 fbpa_config; - u32 fbpa_config1; - u8 flags1; - u8 ref_mpllssf_freq_delta; - u8 flags2; -} __packed; - -/* Script Pointer Index */ -/* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX 3:2*/ -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK 0xc -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT 2 -/* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX 1:0*/ -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK 0x3 -#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 - -#define VBIOS_POWER_SENSORS_VERSION_2X 0x20 -#define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008 - -struct pwr_sensors_2x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u32 ba_script_pointer; -} __packed; - -#define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015 - -struct pwr_sensors_2x_entry { - u8 flags0; - u32 class_param0; - u32 sensor_param0; - u32 sensor_param1; - u32 sensor_param2; - u32 sensor_param3; -} __packed; - -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001 - -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_MASK 0x100 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_SHIFT 8 - -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_MASK 0xFFFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_SHIFT 16 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_MASK 0xFFFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_SHIFT 16 - -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_MASK 0xFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_SHIFT 16 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_MASK 0xFFFF -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_SHIFT 0 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000 -#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16 - -#define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20 -#define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006 - -struct pwr_topology_2x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u8 rel_entry_size; - u8 num_rel_entries; -} __packed; - -#define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016 - -struct pwr_topology_2x_entry { - u8 flags0; - u8 pwr_rail; - u32 param0; - u32 curr_corr_slope; - u32 curr_corr_offset; - u32 param1; - u32 param2; -} __packed; - -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR 0x00000001 - -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFF -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0 -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00 -#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8 - -#define VBIOS_POWER_POLICY_VERSION_3X 0x30 -#define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025 - -struct pwr_policy_3x_header_struct { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u16 base_sample_period; - u16 min_client_sample_period; - u8 table_rel_entry_size; - u8 num_table_rel_entries; - u8 tgp_policy_idx; - u8 rtp_policy_idx; - u8 mxm_policy_idx; - u8 dnotifier_policy_idx; - u32 d2_limit; - u32 d3_limit; - u32 d4_limit; - u32 d5_limit; - u8 low_sampling_mult; - u8 pwr_tgt_policy_idx; - u8 pwr_tgt_floor_policy_idx; - u8 sm_bus_policy_idx; - u8 table_viol_entry_size; - u8 num_table_viol_entries; -} __packed; - -#define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002E - -struct pwr_policy_3x_entry_struct { - u8 flags0; - u8 ch_idx; - u32 limit_min; - u32 limit_rated; - u32 limit_max; - u32 param0; - u32 param1; - u32 param2; - u32 param3; - u32 limit_batt; - u8 flags1; - u8 past_length; - u8 next_length; - u16 ratio_min; - u16 ratio_max; - u8 sample_mult; - u32 filter_param; -} __packed; - -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4 - -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_MASK 0x1 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_SHIFT 0 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_MASK 0x2 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_SHIFT 1 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_MASK 0x3C -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_SHIFT 2 - -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_MASK 0xFF -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_SHIFT 0 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_MASK 0xFF00 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_SHIFT 8 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_MASK 0x10000 -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_SHIFT 16 - -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF -#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0 - -/* Voltage Rail Table */ -struct vbios_voltage_rail_table_1x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u8 volt_domain_hal; -} __packed; - -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007 -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008 -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009 -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A -#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B - -struct vbios_voltage_rail_table_1x_entry { - u32 boot_voltage_uv; - u8 rel_limit_vfe_equ_idx; - u8 alt_rel_limit_vfe_equidx; - u8 ov_limit_vfe_equ_idx; - u8 pwr_equ_idx; - u8 boot_volt_vfe_equ_idx; - u8 vmin_limit_vfe_equ_idx; - u8 volt_margin_limit_vfe_equ_idx; -} __packed; - -/* Voltage Device Table */ -struct vbios_voltage_device_table_1x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; -}; - -struct vbios_voltage_device_table_1x_entry { - u8 type; - u8 volt_domain; - u16 settle_time_us; - u32 param0; - u32 param1; - u32 param2; - u32 param3; - u32 param4; -}; - -#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00 -#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02 - -#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT 0 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24 - -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT 0 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT 24 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE \ - 0x01 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \ - 0x02 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT 0 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT 24 - -#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT 0 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT 24 - -#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_MASK \ - GENMASK(23, 0) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT 0 -#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT 24 - -/* Voltage Policy Table */ -struct vbios_voltage_policy_table_1x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u8 perf_core_vf_seq_policy_idx; -}; - -struct vbios_voltage_policy_table_1x_entry { - u8 type; - u32 param0; - u32 param1; -}; - -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 -#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 - -#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ - GENMASK(7, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0 -#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK GENMASK(8, 31) -#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT 8 - -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_MASK \ - GENMASK(7, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0 -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_MASK \ - GENMASK(15, 8) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8 -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_MASK \ - GENMASK(23, 16) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16 -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_MASK \ - GENMASK(31, 24) -#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 - -/* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ -#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ - GENMASK(15, 0) -#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \ - 0 - -#define VBIOS_THERM_DEVICE_VERSION_1X 0x10 - -#define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04 0x00000004 - -struct therm_device_1x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; -} ; - -struct therm_device_1x_entry { - u8 class_id; - u8 param0; - u8 flags; -} ; - -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01 - -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFF -#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0 - -#define VBIOS_THERM_CHANNEL_VERSION_1X 0x10 - -#define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09 0x00000009 - -struct therm_channel_1x_header { - u8 version; - u8 header_size; - u8 table_entry_size; - u8 num_table_entries; - u8 gpu_avg_pri_ch_idx; - u8 gpu_max_pri_ch_idx; - u8 board_pri_ch_idx; - u8 mem_pri_ch_idx; - u8 pwr_supply_pri_ch_idx; -}; - -struct therm_channel_1x_entry { - u8 class_id; - u8 param0; - u8 param1; - u8 param2; - u8 flags; -}; - -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01 - -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFF -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0 - -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK 0xFF -#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT 0 - -/* Frequency Controller Table */ -struct vbios_fct_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u16 sampling_period_ms; -} __packed; - -struct vbios_fct_1x_entry { - u8 flags0; - u8 clk_domain_idx; - u16 param0; - u16 param1; - u32 param2; - u32 param3; - u32 param4; - u32 param5; - u32 param6; - u32 param7; - u32 param8; -} __packed; - -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_MASK GENMASK(3, 0) -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_DISABLED 0x0 -#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_PI 0x1 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_MASK GENMASK(7, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SYS 0x00 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_LTC 0x01 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_XBAR 0x02 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC0 0x03 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC1 0x04 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC2 0x05 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC3 0x06 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC4 0x07 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC5 0x08 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPCS 0x09 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MASK GENMASK(9, 8) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_SHIFT 8 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_BCAST 0x0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MIN 0x1 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MAX 0x2 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_AVG 0x3 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_MASK GENMASK(7, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_SHIFT 0 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_MASK GENMASK(8, 8) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_SHIFT 8 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_NO 0x0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_YES 0x1 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_SHIFT 0 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_SHIFT 0 - - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_SHIFT 0 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_SHIFT 0 - - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_MASK GENMASK(31, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_SHIFT 0 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_MASK GENMASK(15, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_MASK GENMASK(31, 16) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_SHIFT 16 - -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_MASK GENMASK(15, 0) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_SHIFT 0 -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16) -#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16 - -/* LPWR Index Table */ -struct nvgpu_bios_lpwr_idx_table_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u16 base_sampling_period; -} __packed; - -struct nvgpu_bios_lpwr_idx_table_1x_entry { - u8 pcie_idx; - u8 gr_idx; - u8 ms_idx; - u8 di_idx; - u8 gc6_idx; -} __packed; - -/* LPWR MS Table*/ -struct nvgpu_bios_lpwr_ms_table_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u8 default_entry_idx; - u16 idle_threshold_us; -} __packed; - -struct nvgpu_bios_lpwr_ms_table_1x_entry { - u32 feautre_mask; - u16 dynamic_current_logic; - u16 dynamic_current_sram; -} __packed; - -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_MASK GENMASK(0, 0) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SHIFT 0 -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_MASK GENMASK(2, 2) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_SHIFT 2 -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_MASK \ - GENMASK(3, 3) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_SHIFT 3 -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_MASK GENMASK(5, 5) -#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_SHIFT 5 - -/* LPWR GR Table */ -struct nvgpu_bios_lpwr_gr_table_1x_header { - u8 version; - u8 header_size; - u8 entry_size; - u8 entry_count; - u8 default_entry_idx; - u16 idle_threshold_us; - u8 adaptive_gr_multiplier; -} __packed; - -struct nvgpu_bios_lpwr_gr_table_1x_entry { - u32 feautre_mask; -} __packed; - -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_MASK GENMASK(0, 0) -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_SHIFT 0 - -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4) -#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4 - -#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h new file mode 100644 index 00000000..c6465313 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h @@ -0,0 +1,1046 @@ +/* + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef NVGPU_BIOS_H +#define NVGPU_BIOS_H + +#include + +struct gk20a; + +#define PERF_PTRS_WIDTH 0x4 +#define PERF_PTRS_WIDTH_16 0x2 + +enum { + CLOCKS_TABLE = 2, + CLOCK_PROGRAMMING_TABLE, + FLL_TABLE, + VIN_TABLE, + FREQUENCY_CONTROLLER_TABLE +}; + +enum { + PERFORMANCE_TABLE = 0, + MEMORY_CLOCK_TABLE, + MEMORY_TWEAK_TABLE, + POWER_CONTROL_TABLE, + THERMAL_CONTROL_TABLE, + THERMAL_DEVICE_TABLE, + THERMAL_COOLERS_TABLE, + PERFORMANCE_SETTINGS_SCRIPT, + CONTINUOUS_VIRTUAL_BINNING_TABLE, + POWER_SENSORS_TABLE = 0xA, + POWER_CAPPING_TABLE = 0xB, + POWER_TOPOLOGY_TABLE = 0xF, + THERMAL_CHANNEL_TABLE = 0x12, + VOLTAGE_RAIL_TABLE = 26, + VOLTAGE_DEVICE_TABLE, + VOLTAGE_POLICY_TABLE, + LOWPOWER_TABLE, + LOWPOWER_GR_TABLE = 32, + LOWPOWER_MS_TABLE = 33, +}; + +enum { + VP_FIELD_TABLE = 0, + VP_FIELD_REGISTER, + VP_TRANSLATION_TABLE, +}; + +struct bit_token { + u8 token_id; + u8 data_version; + u16 data_size; + u16 data_ptr; +} __packed; + +#define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT) + +struct fll_descriptor_header { + u8 version; + u8 size; +} __packed; + +#define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4 +#define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6 + +struct fll_descriptor_header_10 { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u16 max_min_freq_mhz; +} __packed; + +#define FLL_DESCRIPTOR_ENTRY_10_SIZE 15 + +struct fll_descriptor_entry_10 { + u8 fll_device_type; + u8 clk_domain; + u8 fll_device_id; + u16 lut_params; + u8 vin_idx_logic; + u8 vin_idx_sram; + u16 fll_params; + u8 min_freq_vfe_idx; + u8 freq_ctrl_idx; + u16 ref_freq_mhz; + u16 ffr_cutoff_freq_mhz; +} __packed; + +#define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F +#define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 + +#define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 +#define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 + +#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C +#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2 + +struct vin_descriptor_header_10 { + u8 version; + u8 header_sizee; + u8 entry_size; + u8 entry_count; + u8 flags0; + u32 vin_cal; +} __packed; + +struct vin_descriptor_entry_10 { + u8 vin_device_type; + u8 volt_domain_vbios; + u8 vin_device_id; +} __packed; + +#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7 +#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0 + +#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8 +#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3 + +#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF +#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0 + +#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00 +#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT 10 + +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000 +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14 + +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000 +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18 + +#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07 +struct vbios_clocks_table_1x_header { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u8 clocks_hal; + u16 cntr_sampling_periodms; +} __packed; + +#define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09 +struct vbios_clocks_table_1x_entry { + u8 flags0; + u16 param0; + u32 param1; + u16 param2; +} __packed; + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1F +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER 0x01 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE 0x02 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK 0xFF +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK 0xFF00 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK 0xFFFF +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK 0xF +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT 0 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK 0xF0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT 4 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01 + +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08 +struct vbios_clock_programming_table_1x_header { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u8 slave_entry_size; + u8 slave_entry_count; + u8 vf_entry_size; + u8 vf_entry_count; +} __packed; + +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05 +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0D +struct vbios_clock_programming_table_1x_entry { + u8 flags0; + u16 freq_max_mhz; + u8 param0; + u8 param1; + u32 rsvd; + u32 rsvd1; +} __packed; + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK 0xF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO 0x00 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE 0x01 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE 0x02 + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK 0x70 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT 4 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL 0x00 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE 0x01 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL 0x02 + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK 0x80 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT 7 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE 0x00 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE 0x01 + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK 0xFF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT 0 + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0 + +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03 +struct vbios_clock_programming_table_1x_slave_entry { + u8 clk_dom_idx; + u16 param0; +} __packed; + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_MASK 0xFF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_SHIFT 0 + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK 0x3FFF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT 0 + +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02 +struct vbios_clock_programming_table_1x_vf_entry { + u8 vfe_idx; + u8 param0; +} __packed; + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_MASK 0xFF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_SHIFT 0 + +struct vbios_vfe_3x_header_struct { + u8 version; + u8 header_size; + u8 vfe_var_entry_size; + u8 vfe_var_entry_count; + u8 vfe_equ_entry_size; + u8 vfe_equ_entry_count; + u8 polling_periodms; +} __packed; + +#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11 +#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19 +struct vbios_vfe_3x_var_entry_struct { + u8 type; + u32 out_range_min; + u32 out_range_max; + u32 param0; + u32 param1; + u32 param2; + u32 param3; +} __packed; + +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_MASK 0xFF00 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_SHIFT 8 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_MASK 0xFF0000 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_SHIFT 16 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_MASK 0xFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_MASK 0xFF00 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_SHIFT 8 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_MASK 0xFF0000 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_SHIFT 16 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_MASK 0xFF00 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_SHIFT 8 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_MASK 0xFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_MASK 0xFF00 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_SHIFT 8 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17 +#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18 + +struct vbios_vfe_3x_equ_entry_struct { + u8 type; + u8 var_idx; + u8 equ_idx_next; + u32 out_range_min; + u32 out_range_max; + u32 param0; + u32 param1; + u32 param2; + u8 param3; +} __packed; + + +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05 + +#define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFF + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_MASK 0xFF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_MASK 0xFF00 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_SHIFT 8 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_MASK 0xFF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_MASK 0xFF00 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_SHIFT 8 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_MASK 0x70000 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_SHIFT 16 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_EQUAL 0x00000000 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER_EQ 0x00000001 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER 0x00000002 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_MASK 0xF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_SHIFT 0 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS 0x0 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_FREQ_MHZ 0x1 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_UV 0x2 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 + +#define NV_VFIELD_DESC_SIZE_BYTE 0x00000000 +#define NV_VFIELD_DESC_SIZE_WORD 0x00000001 +#define NV_VFIELD_DESC_SIZE_DWORD 0x00000002 +#define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18) >> 3) + +#define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000 +#define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001 +#define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002 + +#define NV_VFIELD_DESC_CODE_INVALID NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID +#define NV_VFIELD_DESC_CODE_REG NV_PMU_BIOS_VFIELD_DESC_CODE_REG +#define NV_VFIELD_DESC_CODE_INDEX_REG NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG + +#define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0) >> 5) + +#define VFIELD_ID_STRAP_IDDQ 0x09 +#define VFIELD_ID_STRAP_IDDQ_1 0x0B + +#define VFIELD_REG_HEADER_SIZE 3 +struct vfield_reg_header { + u8 version; + u8 entry_size; + u8 count; +} __packed; + +#define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10 + + +#define VFIELD_REG_ENTRY_SIZE 13 +struct vfield_reg_entry { + u8 strap_reg_desc; + u32 reg; + u32 reg_index; + u32 index; +} __packed; + +#define VFIELD_HEADER_SIZE 3 + +struct vfield_header { + u8 version; + u8 entry_size; + u8 count; +} __packed; + +#define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10 + +#define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1F) +#define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0) >> 5) +#define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00) >> 10) + +#define VFIELD_ENTRY_SIZE 3 + +struct vfield_entry { + u8 strap_id; + u16 strap_desc; +} __packed; + +#define PERF_CLK_DOMAINS_IDX_MAX (32) +#define PERF_CLK_DOMAINS_IDX_INVALID PERF_CLK_DOMAINS_IDX_MAX + +#define VBIOS_PSTATE_TABLE_VERSION_5X 0x50 +#define VBIOS_PSTATE_HEADER_5X_SIZE_10 (10) + +struct vbios_pstate_header_5x { + u8 version; + u8 header_size; + u8 base_entry_size; + u8 base_entry_count; + u8 clock_entry_size; + u8 clock_entry_count; + u8 flags0; + u8 initial_pstate; + u8 cpi_support_level; +u8 cpi_features; +} __packed; + +#define VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6 6 + +#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2 0x2 +#define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3 0x3 + +struct vbios_pstate_entry_clock_5x { + u16 param0; + u32 param1; +} __packed; + +struct vbios_pstate_entry_5x { + u8 pstate_level; + u8 flags0; + u8 lpwr_entry_idx; + struct vbios_pstate_entry_clock_5x clockEntry[PERF_CLK_DOMAINS_IDX_MAX]; +} __packed; + +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_SHIFT 0 +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM0_NOM_FREQ_MHZ_MASK 0x00003FFF + +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_SHIFT 0 +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MIN_FREQ_MHZ_MASK 0x00003FFF + +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT 14 +#define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK 0x0FFFC000 + +#define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFF + +#define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION 0x11 + +#define VBIOS_MEMORY_CLOCK_HEADER_11_0_SIZE 16 +#define VBIOS_MEMORY_CLOCK_HEADER_11_1_SIZE 21 +#define VBIOS_MEMORY_CLOCK_HEADER_11_2_SIZE 26 + +struct vbios_memory_clock_header_1x { + u8 version; + u8 header_size; + u8 base_entry_size; + u8 strap_entry_size; + u8 strap_entry_count; + u8 entry_count; + u8 flags; + u8 fbvdd_settle_time; + u32 cfg_pwrd_val; + u16 fbvddq_high; + u16 fbvddq_low; + u32 script_list_ptr; + u8 script_list_count; + u32 cmd_script_list_ptr; + u8 cmd_script_list_count; +} __packed; + +#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_2_SIZE 20 + +struct vbios_memory_clock_base_entry_11 { + u16 minimum; + u16 maximum; + u32 script_pointer; + u8 flags0; + u32 fbpa_config; + u32 fbpa_config1; + u8 flags1; + u8 ref_mpllssf_freq_delta; + u8 flags2; +} __packed; + +/* Script Pointer Index */ +/* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX 3:2*/ +#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK 0xc +#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT 2 +/* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX 1:0*/ +#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK 0x3 +#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 + +#define VBIOS_POWER_SENSORS_VERSION_2X 0x20 +#define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008 + +struct pwr_sensors_2x_header { + u8 version; + u8 header_size; + u8 table_entry_size; + u8 num_table_entries; + u32 ba_script_pointer; +} __packed; + +#define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015 + +struct pwr_sensors_2x_entry { + u8 flags0; + u32 class_param0; + u32 sensor_param0; + u32 sensor_param1; + u32 sensor_param2; + u32 sensor_param3; +} __packed; + +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001 + +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFF +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_MASK 0x100 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_USE_FXP8_8_SHIFT 8 + +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_MASK 0xFFFF +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT0_MOHM_SHIFT 0 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_MASK 0xFFFF0000 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM0_INA3221_RSHUNT1_MOHM_SHIFT 16 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_MASK 0xFFFF +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_RSHUNT2_MOHM_SHIFT 0 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_MASK 0xFFFF0000 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM1_INA3221_CONFIGURATION_SHIFT 16 + +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_MASK 0xFFFF +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_MASKENABLE_SHIFT 0 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_MASK 0xFF0000 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM2_INA3221_GPIOFUNCTION_SHIFT 16 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_MASK 0xFFFF +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_M_SHIFT 0 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000 +#define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16 + +#define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20 +#define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006 + +struct pwr_topology_2x_header { + u8 version; + u8 header_size; + u8 table_entry_size; + u8 num_table_entries; + u8 rel_entry_size; + u8 num_rel_entries; +} __packed; + +#define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016 + +struct pwr_topology_2x_entry { + u8 flags0; + u8 pwr_rail; + u32 param0; + u32 curr_corr_slope; + u32 curr_corr_offset; + u32 param1; + u32 param2; +} __packed; + +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR 0x00000001 + +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFF +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0 +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00 +#define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8 + +#define VBIOS_POWER_POLICY_VERSION_3X 0x30 +#define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025 + +struct pwr_policy_3x_header_struct { + u8 version; + u8 header_size; + u8 table_entry_size; + u8 num_table_entries; + u16 base_sample_period; + u16 min_client_sample_period; + u8 table_rel_entry_size; + u8 num_table_rel_entries; + u8 tgp_policy_idx; + u8 rtp_policy_idx; + u8 mxm_policy_idx; + u8 dnotifier_policy_idx; + u32 d2_limit; + u32 d3_limit; + u32 d4_limit; + u32 d5_limit; + u8 low_sampling_mult; + u8 pwr_tgt_policy_idx; + u8 pwr_tgt_floor_policy_idx; + u8 sm_bus_policy_idx; + u8 table_viol_entry_size; + u8 num_table_viol_entries; +} __packed; + +#define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002E + +struct pwr_policy_3x_entry_struct { + u8 flags0; + u8 ch_idx; + u32 limit_min; + u32 limit_rated; + u32 limit_max; + u32 param0; + u32 param1; + u32 param2; + u32 param3; + u32 limit_batt; + u8 flags1; + u8 past_length; + u8 next_length; + u16 ratio_min; + u16 ratio_max; + u8 sample_mult; + u32 filter_param; +} __packed; + +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4 + +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_MASK 0x1 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FULL_DEFLECTION_LIMIT_SHIFT 0 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_MASK 0x2 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_INTEGRAL_CONTROL_SHIFT 1 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_MASK 0x3C +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS1_FILTER_TYPE_SHIFT 2 + +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_MASK 0xFF +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_THRES_IDX_SHIFT 0 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_MASK 0xFF00 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_IDX_SHIFT 8 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_MASK 0x10000 +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM0_HW_THRESHOLD_LOW_THRESHOLD_USE_SHIFT 16 + +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF +#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0 + +/* Voltage Rail Table */ +struct vbios_voltage_rail_table_1x_header { + u8 version; + u8 header_size; + u8 table_entry_size; + u8 num_table_entries; + u8 volt_domain_hal; +} __packed; + +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007 +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008 +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009 +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A +#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B + +struct vbios_voltage_rail_table_1x_entry { + u32 boot_voltage_uv; + u8 rel_limit_vfe_equ_idx; + u8 alt_rel_limit_vfe_equidx; + u8 ov_limit_vfe_equ_idx; + u8 pwr_equ_idx; + u8 boot_volt_vfe_equ_idx; + u8 vmin_limit_vfe_equ_idx; + u8 volt_margin_limit_vfe_equ_idx; +} __packed; + +/* Voltage Device Table */ +struct vbios_voltage_device_table_1x_header { + u8 version; + u8 header_size; + u8 table_entry_size; + u8 num_table_entries; +}; + +struct vbios_voltage_device_table_1x_entry { + u8 type; + u8 volt_domain; + u16 settle_time_us; + u32 param0; + u32 param1; + u32 param2; + u32 param3; + u32 param4; +}; + +#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00 +#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02 + +#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \ + GENMASK(23, 0) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT 0 +#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_MASK \ + GENMASK(31, 24) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24 + +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_MASK \ + GENMASK(23, 0) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT 0 +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_MASK \ + GENMASK(31, 24) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT 24 +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00 +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE \ + 0x01 +#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \ + 0x02 +#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK \ + GENMASK(23, 0) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT 0 +#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_MASK \ + GENMASK(31, 24) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT 24 + +#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_MASK \ + GENMASK(23, 0) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT 0 +#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_MASK \ + GENMASK(31, 24) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT 24 + +#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_MASK \ + GENMASK(23, 0) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT 0 +#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_MASK \ + GENMASK(31, 24) +#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT 24 + +/* Voltage Policy Table */ +struct vbios_voltage_policy_table_1x_header { + u8 version; + u8 header_size; + u8 table_entry_size; + u8 num_table_entries; + u8 perf_core_vf_seq_policy_idx; +}; + +struct vbios_voltage_policy_table_1x_entry { + u8 type; + u32 param0; + u32 param1; +}; + +#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 +#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 +#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 +#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 + +#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ + GENMASK(7, 0) +#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0 +#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK GENMASK(8, 31) +#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT 8 + +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_MASK \ + GENMASK(7, 0) +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0 +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_MASK \ + GENMASK(15, 8) +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8 +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_MASK \ + GENMASK(23, 16) +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16 +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_MASK \ + GENMASK(31, 24) +#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24 + +/* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */ +#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \ + GENMASK(15, 0) +#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \ + 0 + +#define VBIOS_THERM_DEVICE_VERSION_1X 0x10 + +#define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04 0x00000004 + +struct therm_device_1x_header { + u8 version; + u8 header_size; + u8 table_entry_size; + u8 num_table_entries; +} ; + +struct therm_device_1x_entry { + u8 class_id; + u8 param0; + u8 flags; +} ; + +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01 + +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFF +#define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0 + +#define VBIOS_THERM_CHANNEL_VERSION_1X 0x10 + +#define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09 0x00000009 + +struct therm_channel_1x_header { + u8 version; + u8 header_size; + u8 table_entry_size; + u8 num_table_entries; + u8 gpu_avg_pri_ch_idx; + u8 gpu_max_pri_ch_idx; + u8 board_pri_ch_idx; + u8 mem_pri_ch_idx; + u8 pwr_supply_pri_ch_idx; +}; + +struct therm_channel_1x_entry { + u8 class_id; + u8 param0; + u8 param1; + u8 param2; + u8 flags; +}; + +#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01 + +#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFF +#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0 + +#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_MASK 0xFF +#define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM1_DEVICE_PROVIDER_INDEX_SHIFT 0 + +/* Frequency Controller Table */ +struct vbios_fct_1x_header { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u16 sampling_period_ms; +} __packed; + +struct vbios_fct_1x_entry { + u8 flags0; + u8 clk_domain_idx; + u16 param0; + u16 param1; + u32 param2; + u32 param3; + u32 param4; + u32 param5; + u32 param6; + u32 param7; + u32 param8; +} __packed; + +#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_MASK GENMASK(3, 0) +#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 +#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_DISABLED 0x0 +#define NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE_PI 0x1 + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_MASK GENMASK(7, 0) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SHIFT 0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_SYS 0x00 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_LTC 0x01 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_XBAR 0x02 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC0 0x03 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC1 0x04 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC2 0x05 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC3 0x06 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC4 0x07 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPC5 0x08 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID_GPCS 0x09 + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MASK GENMASK(9, 8) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_SHIFT 8 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_BCAST 0x0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MIN 0x1 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_MAX 0x2 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM0_FREQ_MODE_AVG 0x3 + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_MASK GENMASK(7, 0) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_SLOWDOWN_PCT_MIN_SHIFT 0 + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_MASK GENMASK(8, 8) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_SHIFT 8 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_NO 0x0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM1_POISON_YES 0x1 + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_MASK GENMASK(31, 0) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM2_PROP_GAIN_SHIFT 0 + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_MASK GENMASK(31, 0) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM3_INTEG_GAIN_SHIFT 0 + + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_MASK GENMASK(31, 0) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM4_INTEG_DECAY_SHIFT 0 + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_MASK GENMASK(31, 0) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM5_VOLT_DELTA_MIN_SHIFT 0 + + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_MASK GENMASK(31, 0) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM6_VOLT_DELTA_MAX_SHIFT 0 + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_MASK GENMASK(15, 0) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VF_SHIFT 0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_MASK GENMASK(31, 16) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM7_FREQ_CAP_VMIN_SHIFT 16 + +#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_MASK GENMASK(15, 0) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_POS_SHIFT 0 +#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16) +#define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16 + +/* LPWR Index Table */ +struct nvgpu_bios_lpwr_idx_table_1x_header { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u16 base_sampling_period; +} __packed; + +struct nvgpu_bios_lpwr_idx_table_1x_entry { + u8 pcie_idx; + u8 gr_idx; + u8 ms_idx; + u8 di_idx; + u8 gc6_idx; +} __packed; + +/* LPWR MS Table*/ +struct nvgpu_bios_lpwr_ms_table_1x_header { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u8 default_entry_idx; + u16 idle_threshold_us; +} __packed; + +struct nvgpu_bios_lpwr_ms_table_1x_entry { + u32 feautre_mask; + u16 dynamic_current_logic; + u16 dynamic_current_sram; +} __packed; + +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_MASK GENMASK(0, 0) +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SHIFT 0 +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_MASK GENMASK(2, 2) +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_SHIFT 2 +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_MASK \ + GENMASK(3, 3) +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_SHIFT 3 +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_MASK GENMASK(5, 5) +#define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_SHIFT 5 + +/* LPWR GR Table */ +struct nvgpu_bios_lpwr_gr_table_1x_header { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u8 default_entry_idx; + u16 idle_threshold_us; + u8 adaptive_gr_multiplier; +} __packed; + +struct nvgpu_bios_lpwr_gr_table_1x_entry { + u32 feautre_mask; +} __packed; + +#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_MASK GENMASK(0, 0) +#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_SHIFT 0 + +#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4) +#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4 +int nvgpu_bios_parse_rom(struct gk20a *g); +u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset); +s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset); +u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset); +u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset); +void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g, + struct bit_token *ptoken, u8 table_id); +int nvgpu_bios_execute_script(struct gk20a *g, u32 offset); + +#endif diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c index 1dc37cd2..9636891b 100644 --- a/drivers/gpu/nvgpu/lpwr/lpwr.c +++ b/drivers/gpu/nvgpu/lpwr/lpwr.c @@ -11,12 +11,13 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" #include "gp106/pmu_gp106.h" #include "gm206/bios_gm206.h" #include "pstate/pstate.h" -#include "include/bios.h" #include "perf/perf.h" #include "lpwr.h" @@ -30,13 +31,10 @@ static int get_lpwr_idx_table(struct gk20a *g) struct nvgpu_bios_lpwr_idx_table_1x_header header = { 0 }; struct nvgpu_bios_lpwr_idx_table_1x_entry entry = { 0 }; - if (g->ops.bios.get_perf_table_ptrs) { - lpwr_idx_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g, - g->bios.perf_token, LOWPOWER_TABLE); - if (lpwr_idx_table_ptr == NULL) - return -EINVAL; - } else - return -EINVAL; + lpwr_idx_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g, + g->bios.perf_token, LOWPOWER_TABLE); + if (lpwr_idx_table_ptr == NULL) + return -EINVAL; memcpy(&header, lpwr_idx_table_ptr, sizeof(struct nvgpu_bios_lpwr_idx_table_1x_header)); @@ -75,13 +73,10 @@ static int get_lpwr_gr_table(struct gk20a *g) struct nvgpu_bios_lpwr_gr_table_1x_header header = { 0 }; struct nvgpu_bios_lpwr_gr_table_1x_entry entry = { 0 }; - if (g->ops.bios.get_perf_table_ptrs) { - lpwr_gr_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g, - g->bios.perf_token, LOWPOWER_GR_TABLE); - if (lpwr_gr_table_ptr == NULL) - return -EINVAL; - } else - return -EINVAL; + lpwr_gr_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g, + g->bios.perf_token, LOWPOWER_GR_TABLE); + if (lpwr_gr_table_ptr == NULL) + return -EINVAL; memcpy(&header, lpwr_gr_table_ptr, sizeof(struct nvgpu_bios_lpwr_gr_table_1x_header)); @@ -122,13 +117,10 @@ static int get_lpwr_ms_table(struct gk20a *g) struct nvgpu_bios_lpwr_ms_table_1x_header header = { 0 }; struct nvgpu_bios_lpwr_ms_table_1x_entry entry = { 0 }; - if (g->ops.bios.get_perf_table_ptrs) { - lpwr_ms_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g, - g->bios.perf_token, LOWPOWER_MS_TABLE); - if (lpwr_ms_table_ptr == NULL) - return -EINVAL; - } else - return -EINVAL; + lpwr_ms_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g, + g->bios.perf_token, LOWPOWER_MS_TABLE); + if (lpwr_ms_table_ptr == NULL) + return -EINVAL; memcpy(&header, lpwr_ms_table_ptr, sizeof(struct nvgpu_bios_lpwr_ms_table_1x_header)); diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c index 3cc12840..e90fd7f9 100644 --- a/drivers/gpu/nvgpu/lpwr/rppg.c +++ b/drivers/gpu/nvgpu/lpwr/rppg.c @@ -16,8 +16,6 @@ #include "gp106/pmu_gp106.h" #include "gm206/bios_gm206.h" #include "pstate/pstate.h" -#include "include/bios.h" -#include static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg, void *param, u32 handle, u32 status) diff --git a/drivers/gpu/nvgpu/perf/vfe_equ.c b/drivers/gpu/nvgpu/perf/vfe_equ.c index 3a5b9f45..f8a79a22 100644 --- a/drivers/gpu/nvgpu/perf/vfe_equ.c +++ b/drivers/gpu/nvgpu/perf/vfe_equ.c @@ -11,13 +11,13 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "perf.h" #include "vfe_equ.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e255.h" -#include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" @@ -147,10 +147,7 @@ static u32 devinit_get_vfe_equ_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) - return -EINVAL; - - vfeequs_tbl_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + vfeequs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.perf_token, CONTINUOUS_VIRTUAL_BINNING_TABLE); diff --git a/drivers/gpu/nvgpu/perf/vfe_var.c b/drivers/gpu/nvgpu/perf/vfe_var.c index d1e1d76c..7170f502 100644 --- a/drivers/gpu/nvgpu/perf/vfe_var.c +++ b/drivers/gpu/nvgpu/perf/vfe_var.c @@ -11,13 +11,13 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "perf.h" #include "vfe_var.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" @@ -179,17 +179,14 @@ u32 dev_init_get_vfield_info(struct gk20a *g, u8 *psegmentcount = NULL; u32 status = 0; - if (!g->ops.bios.get_perf_table_ptrs) - return -EINVAL; - - vfieldregtableptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + vfieldregtableptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.virt_token, VP_FIELD_REGISTER); if (vfieldregtableptr == NULL) { status = -EINVAL; goto done; } - vfieldtableptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + vfieldtableptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.virt_token, VP_FIELD_TABLE); if (vfieldtableptr == NULL) { status = -EINVAL; @@ -864,12 +861,7 @@ static u32 devinit_get_vfe_var_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) { - status = -EINVAL; - goto done; - } - - vfevars_tbl_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + vfevars_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.perf_token, CONTINUOUS_VIRTUAL_BINNING_TABLE); if (vfevars_tbl_ptr == NULL) { diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c index 53241734..28fe943e 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c @@ -13,7 +13,6 @@ #include "gk20a/gk20a.h" #include "pwrdev.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c index e831126b..0f87ad26 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrdev.c +++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c @@ -11,9 +11,10 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "pwrdev.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "gm206/bios_gm206.h" @@ -138,10 +139,7 @@ static u32 devinit_get_pwr_device_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) - return -EINVAL; - - pwr_device_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + pwr_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.perf_token, POWER_SENSORS_TABLE); if (pwr_device_table_ptr == NULL) { status = -EINVAL; diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c index ab2460eb..685aa71a 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c +++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c @@ -11,9 +11,10 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "pwrdev.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "gm206/bios_gm206.h" @@ -185,10 +186,7 @@ static u32 devinit_get_pwr_topology_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) - return -EINVAL; - - pwr_topology_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + pwr_topology_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.perf_token, POWER_TOPOLOGY_TABLE); if (pwr_topology_table_ptr == NULL) { status = -EINVAL; diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c index d19f9a1c..4c007337 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c @@ -11,9 +11,10 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "pwrpolicy.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "gm206/bios_gm206.h" @@ -521,10 +522,7 @@ static u32 devinit_get_pwr_policy_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) - return -EINVAL; - - ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.perf_token, POWER_CAPPING_TABLE); if (ptr == NULL) { status = -EINVAL; diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c index 82e809bb..feb8cca8 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/pstate/pstate.c @@ -13,11 +13,12 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "clk/clk.h" #include "perf/perf.h" #include "pmgr/pmgr.h" -#include "include/bios.h" #include "pstate/pstate.h" #include "therm/thrm.h" @@ -342,11 +343,9 @@ static int pstate_sw_setup(struct gk20a *g) goto done; } - if (g->ops.bios.get_perf_table_ptrs) { - hdr = (struct vbios_pstate_header_5x *) - g->ops.bios.get_perf_table_ptrs(g, - g->bios.perf_token, PERFORMANCE_TABLE); - } + hdr = (struct vbios_pstate_header_5x *) + nvgpu_bios_get_perf_table_ptrs(g, + g->bios.perf_token, PERFORMANCE_TABLE); if (!hdr) { gk20a_err(dev_from_gk20a(g), diff --git a/drivers/gpu/nvgpu/therm/thrmchannel.c b/drivers/gpu/nvgpu/therm/thrmchannel.c index f253a196..a09a4599 100644 --- a/drivers/gpu/nvgpu/therm/thrmchannel.c +++ b/drivers/gpu/nvgpu/therm/thrmchannel.c @@ -11,9 +11,10 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "thrmchannel.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include @@ -130,10 +131,7 @@ static u32 devinit_get_therm_channel_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) - return -EINVAL; - - therm_channel_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + therm_channel_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.perf_token, THERMAL_CHANNEL_TABLE); if (therm_channel_table_ptr == NULL) { status = -EINVAL; diff --git a/drivers/gpu/nvgpu/therm/thrmdev.c b/drivers/gpu/nvgpu/therm/thrmdev.c index 3ff199e7..199343e0 100644 --- a/drivers/gpu/nvgpu/therm/thrmdev.c +++ b/drivers/gpu/nvgpu/therm/thrmdev.c @@ -11,9 +11,10 @@ * more details. */ +#include + #include "gk20a/gk20a.h" #include "thrmdev.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include @@ -80,10 +81,7 @@ static u32 devinit_get_therm_device_table(struct gk20a *g, gk20a_dbg_info(""); - if (!g->ops.bios.get_perf_table_ptrs) - return -EINVAL; - - therm_device_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, + therm_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, g->bios.perf_token, THERMAL_DEVICE_TABLE); if (therm_device_table_ptr == NULL) { status = -EINVAL; diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c index a06d3b92..50df55c0 100644 --- a/drivers/gpu/nvgpu/therm/thrmpmu.c +++ b/drivers/gpu/nvgpu/therm/thrmpmu.c @@ -12,7 +12,6 @@ */ #include "gk20a/gk20a.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "thrmpmu.h" diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c index ebc140ef..4807f023 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/volt/volt_dev.c @@ -14,17 +14,17 @@ #include #include "gk20a/gk20a.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" -#include "include/bios.h" #include "volt.h" #include +#include + #define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0 #define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1 @@ -363,14 +363,9 @@ static u32 volt_get_volt_devices_table(struct gk20a *g, u8 entry_idx; u8 *entry_offset; - if (g->ops.bios.get_perf_table_ptrs) { - volt_device_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, - g->bios.perf_token, VOLTAGE_DEVICE_TABLE); - if (volt_device_table_ptr == NULL) { - status = -EINVAL; - goto done; - } - } else { + volt_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, + g->bios.perf_token, VOLTAGE_DEVICE_TABLE); + if (volt_device_table_ptr == NULL) { status = -EINVAL; goto done; } diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c index 488e67a3..f8167000 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.c +++ b/drivers/gpu/nvgpu/volt/volt_pmu.c @@ -12,7 +12,6 @@ */ #include "gk20a/gk20a.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "gm206/bios_gm206.h" @@ -20,7 +19,6 @@ #include "ctrl/ctrlperf.h" #include "gk20a/pmu_gk20a.h" -#include "include/bios.h" #include "volt.h" #include diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c index e943e771..239b908e 100644 --- a/drivers/gpu/nvgpu/volt/volt_policy.c +++ b/drivers/gpu/nvgpu/volt/volt_policy.c @@ -11,16 +11,15 @@ * more details. */ +#include + #include "gk20a/gk20a.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" -#include -#include "include/bios.h" #include "volt.h" static u32 volt_policy_pmu_data_init_super(struct gk20a *g, @@ -170,15 +169,10 @@ static u32 volt_get_volt_policy_table(struct gk20a *g, struct voltage_policy_split_rail split_rail; } policy_type_data; - if (g->ops.bios.get_perf_table_ptrs) { - voltage_policy_table_ptr = - (u8 *)g->ops.bios.get_perf_table_ptrs(g, - g->bios.perf_token, VOLTAGE_POLICY_TABLE); - if (voltage_policy_table_ptr == NULL) { - status = -EINVAL; - goto done; - } - } else { + voltage_policy_table_ptr = + (u8 *)nvgpu_bios_get_perf_table_ptrs(g, + g->bios.perf_token, VOLTAGE_POLICY_TABLE); + if (voltage_policy_table_ptr == NULL) { status = -EINVAL; goto done; } diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c index 6d606228..aaad86a5 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/volt/volt_rail.c @@ -11,16 +11,15 @@ * more details. */ +#include + #include "gk20a/gk20a.h" -#include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" -#include -#include "include/bios.h" #include "volt.h" u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain) @@ -241,14 +240,9 @@ static u32 volt_get_volt_rail_table(struct gk20a *g, struct voltage_rail volt_rail; } rail_type_data; - if (g->ops.bios.get_perf_table_ptrs) { - volt_rail_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, - g->bios.perf_token, VOLTAGE_RAIL_TABLE); - if (volt_rail_table_ptr == NULL) { - status = -EINVAL; - goto done; - } - } else { + volt_rail_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g, + g->bios.perf_token, VOLTAGE_RAIL_TABLE); + if (volt_rail_table_ptr == NULL) { status = -EINVAL; goto done; } -- cgit v1.2.2