From 51b5ec852096c0eeb1eaca48ae132d7bf9ac7a9d Mon Sep 17 00:00:00 2001
From: seshendra Gadagottu <sgadagottu@nvidia.com>
Date: Mon, 22 Aug 2016 13:20:05 -0700
Subject: gpu: nvgpu: gv11b: hw header update

Updated hw headers to CL#37001916. Some of
important changes include new door bell user
mode mechanism and new runlist structure.

Bug 1735765

Change-Id: Icf01156dd3e7d94466f553ffc53267e4043e1188
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1205888
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
---
 drivers/gpu/nvgpu/gv11b/gr_gv11b.c          |  63 ++-
 drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h      |  24 +
 drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h       |  12 -
 drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h     |  20 +-
 drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h     |  12 +-
 drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h       | 830 ++++++----------------------
 drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h      |   8 -
 drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h    |  42 +-
 drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h     |  16 +-
 drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h     |  12 +-
 drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h      |   8 +-
 drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h      | 128 ++++-
 drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h    | 356 ------------
 drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h      |   2 +-
 drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h |  89 +++
 15 files changed, 465 insertions(+), 1157 deletions(-)
 create mode 100644 drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 9d0b4ade..088ec040 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -72,16 +72,16 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
 	gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr);
 
 	/* Check for LRF ECC errors. */
-        lrf_ecc_status = gk20a_readl(g,
-			gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset);
-	if ( (lrf_ecc_status &
+	lrf_ecc_status = gk20a_readl(g,
+		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset);
+	if ((lrf_ecc_status &
 		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) ||
 		(lrf_ecc_status &
 		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) ||
 		(lrf_ecc_status &
 		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) ||
 		(lrf_ecc_status &
-		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f()) ) {
+		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f())) {
 
 		gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
 			"Single bit error detected in SM LRF!");
@@ -93,14 +93,14 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
 			gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset,
 			0);
 	}
-	if ( (lrf_ecc_status &
+	if ((lrf_ecc_status &
 		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) ||
 		(lrf_ecc_status &
 		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) ||
 		(lrf_ecc_status &
 		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) ||
 		(lrf_ecc_status &
-		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f()) ) {
+		gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f())) {
 
 		gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
 			"Double bit error detected in SM LRF!");
@@ -109,14 +109,13 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
 			gk20a_readl(g,
 				gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset);
 		gk20a_writel(g,
-			gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset,
-			0);
+			gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, 0);
 	}
 	gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset,
 			lrf_ecc_status);
 
 	/* Check for SHM ECC errors. */
-        shm_ecc_status = gk20a_readl(g,
+	shm_ecc_status = gk20a_readl(g,
 			gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset);
 	if ((shm_ecc_status &
 		gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) ||
@@ -125,7 +124,7 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
 		(shm_ecc_status &
 		gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) ||
 		(shm_ecc_status &
-		gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) {
+		gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f())) {
 		u32 ecc_stats_reg_val;
 
 		gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
@@ -144,10 +143,10 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
 			gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset,
 			ecc_stats_reg_val);
 	}
-	if ( (shm_ecc_status &
+	if ((shm_ecc_status &
 		gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) ||
 		(shm_ecc_status &
-		gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) {
+		gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f())) {
 		u32 ecc_stats_reg_val;
 
 		gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
@@ -1133,8 +1132,8 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
 		gk20a_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r()));
 	gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n",
 		gk20a_readl(g, gr_cwd_fs_r()));
-	gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n",
-		gk20a_readl(g, gr_fe_tpc_fs_r()));
+	gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS(0): 0x%x\n",
+		gk20a_readl(g, gr_fe_tpc_fs_r(0)));
 	gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n",
 		gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0)));
 	gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n",
@@ -1184,7 +1183,7 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
 
 static bool gr_activity_empty_or_preempted(u32 val)
 {
-	while(val) {
+	while (val) {
 		u32 v = val & 7;
 		if (v != gr_activity_4_gpc0_empty_v() &&
 		    v != gr_activity_4_gpc0_preempted_v())
@@ -1542,16 +1541,16 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
 			gpc, tpc, global_esr);
 
 	if (cilp_enabled && sm_debugger_attached) {
-		if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f())
-			gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
-					gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f());
+		if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f())
+			gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset,
+					gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f());
 
-		if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f())
-			gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
-					gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f());
+		if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f())
+			gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset,
+					gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f());
 
-		global_mask = gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() |
-			gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f();
+		global_mask = gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f() |
+			gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f();
 
 		if (warp_esr != 0 || (global_esr & global_mask) != 0) {
 			*ignore_debugger = true;
@@ -1575,7 +1574,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
 			}
 
 			/* reset the HWW errors after locking down */
-			global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset);
+			global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset);
 			gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy);
 			gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
 					"CILP: HWWs cleared for gpc %d tpc %d\n",
@@ -1588,15 +1587,15 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
 				return ret;
 			}
 
-			dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset);
-			if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) {
+			dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset);
+			if (dbgr_control0 & gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f()) {
 				gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
 						"CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n",
 						gpc, tpc);
 				dbgr_control0 = set_field(dbgr_control0,
-						gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(),
-						gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f());
-				gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0);
+						gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(),
+						gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f());
+				gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset, dbgr_control0);
 			}
 
 			gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
@@ -1703,10 +1702,10 @@ clean_up:
 
 static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr)
 {
-	if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m()))
+	if (!(hww_warp_esr & gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m()))
 		hww_warp_esr = set_field(hww_warp_esr,
-			gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(),
-			gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f());
+			gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(),
+			gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f());
 
 	return hww_warp_esr;
 }
diff --git a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h
index c06a106a..66571ae7 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h
@@ -50,6 +50,30 @@
 #ifndef _hw_bus_gv11b_h_
 #define _hw_bus_gv11b_h_
 
+static inline u32 bus_bar0_window_r(void)
+{
+	return 0x00001700;
+}
+static inline u32 bus_bar0_window_base_f(u32 v)
+{
+	return (v & 0xffffff) << 0;
+}
+static inline u32 bus_bar0_window_target_vid_mem_f(void)
+{
+	return 0x0;
+}
+static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
+{
+	return 0x2000000;
+}
+static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
+{
+	return 0x3000000;
+}
+static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
+{
+	return 0x00000010;
+}
 static inline u32 bus_bar1_block_r(void)
 {
 	return 0x00001704;
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h
index 900054aa..9e4bab8b 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h
@@ -174,18 +174,6 @@ static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
 {
 	return 0x10;
 }
-static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
-{
-	return 0x18;
-}
-static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
-{
-	return 0x20;
-}
-static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
-{
-	return 0x20;
-}
 static inline u32 fb_mmu_invalidate_sys_membar_s(void)
 {
 	return 1;
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
index 9c0f2483..8af66362 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
@@ -104,7 +104,7 @@ static inline u32 fifo_eng_runlist_base_r(u32 i)
 }
 static inline u32 fifo_eng_runlist_base__size_1_v(void)
 {
-	return 0x00000001;
+	return 0x00000002;
 }
 static inline u32 fifo_eng_runlist_r(u32 i)
 {
@@ -112,7 +112,7 @@ static inline u32 fifo_eng_runlist_r(u32 i)
 }
 static inline u32 fifo_eng_runlist__size_1_v(void)
 {
-	return 0x00000001;
+	return 0x00000002;
 }
 static inline u32 fifo_eng_runlist_length_f(u32 v)
 {
@@ -268,7 +268,7 @@ static inline u32 fifo_intr_mmu_fault_id_r(void)
 }
 static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
 {
-	return 0x00000000;
+	return 0x00000040;
 }
 static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
 {
@@ -332,7 +332,7 @@ static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
 }
 static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
 {
-	return 0x00000001;
+	return 0x00000003;
 }
 static inline u32 fifo_intr_runlist_r(void)
 {
@@ -412,7 +412,7 @@ static inline u32 fifo_engine_status_r(u32 i)
 }
 static inline u32 fifo_engine_status__size_1_v(void)
 {
-	return 0x00000002;
+	return 0x00000004;
 }
 static inline u32 fifo_engine_status_id_v(u32 r)
 {
@@ -500,7 +500,7 @@ static inline u32 fifo_pbdma_status_r(u32 i)
 }
 static inline u32 fifo_pbdma_status__size_1_v(void)
 {
-	return 0x00000001;
+	return 0x00000003;
 }
 static inline u32 fifo_pbdma_status_id_v(u32 r)
 {
@@ -600,11 +600,11 @@ static inline u32 fifo_replay_fault_buffer_size_r(void)
 }
 static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
 {
-	return (v & 0x1ff) << 0;
+	return (v & 0x3ff) << 0;
 }
 static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
 {
-	return 0x000000c0;
+	return 0x00000140;
 }
 static inline u32 fifo_replay_fault_buffer_get_r(void)
 {
@@ -612,7 +612,7 @@ static inline u32 fifo_replay_fault_buffer_get_r(void)
 }
 static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
 {
-	return (v & 0x1ff) << 0;
+	return (v & 0x3ff) << 0;
 }
 static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
 {
@@ -624,7 +624,7 @@ static inline u32 fifo_replay_fault_buffer_put_r(void)
 }
 static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
 {
-	return (v & 0x1ff) << 0;
+	return (v & 0x3ff) << 0;
 }
 static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h
index 955626a6..8c324225 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h
@@ -242,6 +242,14 @@ static inline u32 gmmu_new_pte_address_sys_w(void)
 {
 	return 0;
 }
+static inline u32 gmmu_new_pte_address_vid_f(u32 v)
+{
+	return (v & 0xffffff) << 8;
+}
+static inline u32 gmmu_new_pte_address_vid_w(void)
+{
+	return 0;
+}
 static inline u32 gmmu_new_pte_vol_w(void)
 {
 	return 0;
@@ -1110,7 +1118,7 @@ static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
 {
 	return 0x000000de;
 }
-static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
+static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void)
 {
 	return 0x000000cc;
 }
@@ -1174,7 +1182,7 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
 {
 	return 0x000000ec;
 }
-static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
+static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void)
 {
 	return 0x000000cd;
 }
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
index a37ce6e7..6cfa33ea 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
@@ -372,11 +372,11 @@ static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
 {
-	return 0x005046a4;
+	return 0x0050433c;
 }
 static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
 {
-	return 0x00419ea4;
+	return 0x00419b3c;
 }
 static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
 {
@@ -468,7 +468,7 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
 {
-	return 0x005046b8;
+	return 0x00504358;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
 {
@@ -504,7 +504,7 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
 {
-	return 0x005044a0;
+	return 0x0050436c;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
 {
@@ -532,15 +532,15 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pe
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
 {
-	return 0x005046bc;
+	return 0x0050435c;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
 {
-	return 0x005046c0;
+	return 0x00504360;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
 {
-	return 0x005044a4;
+	return 0x00504370;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
 {
@@ -696,7 +696,7 @@ static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
 }
 static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
 {
-	return 0x7fffffff;
+	return 0x1800;
 }
 static inline u32 gr_fe_object_table_r(u32 i)
 {
@@ -706,9 +706,9 @@ static inline u32 gr_fe_object_table_nvclass_v(u32 r)
 {
 	return (r >> 0) & 0xffff;
 }
-static inline u32 gr_fe_tpc_fs_r(void)
+static inline u32 gr_fe_tpc_fs_r(u32 i)
 {
-	return 0x004041c4;
+	return 0x0040a200 + i*4;
 }
 static inline u32 gr_pri_mme_shadow_raw_index_r(void)
 {
@@ -1530,29 +1530,9 @@ static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
 {
 	return 0x00502420;
 }
-static inline u32 gr_rstr2d_gpc_map0_r(void)
+static inline u32 gr_rstr2d_gpc_map_r(u32 i)
 {
-	return 0x0040780c;
-}
-static inline u32 gr_rstr2d_gpc_map1_r(void)
-{
-	return 0x00407810;
-}
-static inline u32 gr_rstr2d_gpc_map2_r(void)
-{
-	return 0x00407814;
-}
-static inline u32 gr_rstr2d_gpc_map3_r(void)
-{
-	return 0x00407818;
-}
-static inline u32 gr_rstr2d_gpc_map4_r(void)
-{
-	return 0x0040781c;
-}
-static inline u32 gr_rstr2d_gpc_map5_r(void)
-{
-	return 0x00407820;
+	return 0x0040780c + i*4;
 }
 static inline u32 gr_rstr2d_map_table_cfg_r(void)
 {
@@ -1656,7 +1636,7 @@ static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
 }
 static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
 {
-	return 0x000001c0;
+	return 0x00000380;
 }
 static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
 {
@@ -1668,7 +1648,7 @@ static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
 }
 static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
 {
-	return 0x00000182;
+	return 0x00000302;
 }
 static inline u32 gr_pd_dist_skip_table_r(u32 i)
 {
@@ -2052,7 +2032,7 @@ static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
 }
 static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
 {
-	return 0x00000018;
+	return 0x00000030;
 }
 static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
 {
@@ -2352,19 +2332,19 @@ static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
 }
 static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
 {
-	return 0x00504698;
+	return 0x00504608;
 }
-static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
+static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v)
 {
 	return (v & 0xffff) << 0;
 }
-static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
+static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r)
 {
 	return (r >> 0) & 0xffff;
 }
 static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
 {
-	return 0x0050469c;
+	return 0x00504330;
 }
 static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
 {
@@ -2404,11 +2384,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
 {
-	return 0x00030000;
+	return 0x00001000;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
 {
-	return 0x00030a00;
+	return 0x00001900;
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
 {
@@ -2452,11 +2432,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
 }
 static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
 {
-	return 0x00030000;
+	return 0x00001000;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
 {
-	return 0x00419b00;
+	return 0x00419e00;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
 {
@@ -2464,7 +2444,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
 {
-	return 0x00419b04;
+	return 0x00419e04;
 }
 static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
 {
@@ -2708,11 +2688,11 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
 {
-	return 0x00000018;
+	return 0x00000030;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
 {
-	return 0x18;
+	return 0x30;
 }
 static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
 {
@@ -2748,7 +2728,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
 {
-	return 0x00500ee4;
+	return 0x005001dc;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
 {
@@ -2756,7 +2736,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
 {
-	return 0x00000250;
+	return 0x00000170;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
 {
@@ -2764,7 +2744,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
 {
-	return 0x00500ee0;
+	return 0x005001d8;
 }
 static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
 {
@@ -2776,7 +2756,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
 }
 static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
 {
-	return 0x00418eec;
+	return 0x004181e4;
 }
 static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
 {
@@ -2870,173 +2850,33 @@ static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
 {
 	return 0x80000000;
 }
-static inline u32 gr_crstr_gpc_map0_r(void)
-{
-	return 0x00418b08;
-}
-static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
-{
-	return (v & 0x7) << 0;
-}
-static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
-{
-	return (v & 0x7) << 5;
-}
-static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
-{
-	return (v & 0x7) << 10;
-}
-static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
-{
-	return (v & 0x7) << 15;
-}
-static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
-{
-	return (v & 0x7) << 20;
-}
-static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
-{
-	return (v & 0x7) << 25;
-}
-static inline u32 gr_crstr_gpc_map1_r(void)
-{
-	return 0x00418b0c;
-}
-static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
-{
-	return (v & 0x7) << 0;
-}
-static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
-{
-	return (v & 0x7) << 5;
-}
-static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
-{
-	return (v & 0x7) << 10;
-}
-static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
-{
-	return (v & 0x7) << 15;
-}
-static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
-{
-	return (v & 0x7) << 20;
-}
-static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
-{
-	return (v & 0x7) << 25;
-}
-static inline u32 gr_crstr_gpc_map2_r(void)
-{
-	return 0x00418b10;
-}
-static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
-{
-	return (v & 0x7) << 0;
-}
-static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
-{
-	return (v & 0x7) << 5;
-}
-static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
-{
-	return (v & 0x7) << 10;
-}
-static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
-{
-	return (v & 0x7) << 15;
-}
-static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
-{
-	return (v & 0x7) << 20;
-}
-static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
-{
-	return (v & 0x7) << 25;
-}
-static inline u32 gr_crstr_gpc_map3_r(void)
-{
-	return 0x00418b14;
-}
-static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
-{
-	return (v & 0x7) << 0;
-}
-static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
-{
-	return (v & 0x7) << 5;
-}
-static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
-{
-	return (v & 0x7) << 10;
-}
-static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
-{
-	return (v & 0x7) << 15;
-}
-static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
-{
-	return (v & 0x7) << 20;
-}
-static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
-{
-	return (v & 0x7) << 25;
-}
-static inline u32 gr_crstr_gpc_map4_r(void)
-{
-	return 0x00418b18;
-}
-static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
-{
-	return (v & 0x7) << 0;
-}
-static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
-{
-	return (v & 0x7) << 5;
-}
-static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
-{
-	return (v & 0x7) << 10;
-}
-static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
+static inline u32 gr_crstr_gpc_map_r(u32 i)
 {
-	return (v & 0x7) << 15;
+	return 0x00418b08 + i*4;
 }
-static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
+static inline u32 gr_crstr_gpc_map_tile0_f(u32 v)
 {
-	return (v & 0x7) << 20;
-}
-static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
-{
-	return (v & 0x7) << 25;
-}
-static inline u32 gr_crstr_gpc_map5_r(void)
-{
-	return 0x00418b1c;
-}
-static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
-{
-	return (v & 0x7) << 0;
+	return (v & 0x1f) << 0;
 }
-static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
+static inline u32 gr_crstr_gpc_map_tile1_f(u32 v)
 {
-	return (v & 0x7) << 5;
+	return (v & 0x1f) << 5;
 }
-static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
+static inline u32 gr_crstr_gpc_map_tile2_f(u32 v)
 {
-	return (v & 0x7) << 10;
+	return (v & 0x1f) << 10;
 }
-static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
+static inline u32 gr_crstr_gpc_map_tile3_f(u32 v)
 {
-	return (v & 0x7) << 15;
+	return (v & 0x1f) << 15;
 }
-static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
+static inline u32 gr_crstr_gpc_map_tile4_f(u32 v)
 {
-	return (v & 0x7) << 20;
+	return (v & 0x1f) << 20;
 }
-static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
+static inline u32 gr_crstr_gpc_map_tile5_f(u32 v)
 {
-	return (v & 0x7) << 25;
+	return (v & 0x1f) << 25;
 }
 static inline u32 gr_crstr_map_table_cfg_r(void)
 {
@@ -3050,159 +2890,39 @@ static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
 {
 	return (v & 0xff) << 8;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
-{
-	return 0x00418980;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
-{
-	return (v & 0x7) << 0;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
-{
-	return (v & 0x7) << 4;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
-{
-	return (v & 0x7) << 8;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
-{
-	return (v & 0x7) << 12;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
-{
-	return (v & 0x7) << 16;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
-{
-	return (v & 0x7) << 20;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
-{
-	return (v & 0x7) << 24;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
-{
-	return (v & 0x7) << 28;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
-{
-	return 0x00418984;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
-{
-	return (v & 0x7) << 0;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
-{
-	return (v & 0x7) << 4;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
-{
-	return (v & 0x7) << 8;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
-{
-	return (v & 0x7) << 12;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
-{
-	return (v & 0x7) << 16;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
-{
-	return (v & 0x7) << 20;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
-{
-	return (v & 0x7) << 24;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
-{
-	return (v & 0x7) << 28;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
-{
-	return 0x00418988;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
-{
-	return (v & 0x7) << 0;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
-{
-	return (v & 0x7) << 4;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
-{
-	return (v & 0x7) << 8;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
-{
-	return (v & 0x7) << 12;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
-{
-	return (v & 0x7) << 16;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
-{
-	return (v & 0x7) << 20;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
-{
-	return (v & 0x7) << 24;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
-{
-	return 3;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
-{
-	return (v & 0x7) << 28;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
-{
-	return 0x7 << 28;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
-{
-	return (r >> 28) & 0x7;
-}
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i)
 {
-	return 0x0041898c;
+	return 0x00418980 + i*4;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v)
 {
 	return (v & 0x7) << 0;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v)
 {
 	return (v & 0x7) << 4;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v)
 {
 	return (v & 0x7) << 8;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v)
 {
 	return (v & 0x7) << 12;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v)
 {
 	return (v & 0x7) << 16;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v)
 {
 	return (v & 0x7) << 20;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v)
 {
 	return (v & 0x7) << 24;
 }
-static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v)
 {
 	return (v & 0x7) << 28;
 }
@@ -3210,14 +2930,6 @@ static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
 {
 	return 0x00418c6c;
 }
-static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
-{
-	return 0x0;
-}
-static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
-{
-	return 0x1;
-}
 static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
 {
 	return 0x00419004;
@@ -3286,135 +2998,87 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
 {
 	return 0x10000000;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_r(void)
 {
-	return 0x00419e44;
+	return 0x00419f28;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_error_report_f(void)
 {
 	return 0x2;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void)
 {
 	return 0x4;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
-{
-	return 0x8;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void)
 {
 	return 0x10;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
 {
 	return 0x20;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void)
 {
 	return 0x40;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
-{
-	return 0x80;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
 {
 	return 0x100;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
 {
 	return 0x200;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
-{
-	return 0x400;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
 {
 	return 0x800;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
-{
-	return 0x1000;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void)
 {
 	return 0x2000;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void)
 {
 	return 0x4000;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
 {
 	return 0x8000;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
 {
 	return 0x10000;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
-{
-	return 0x20000;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
 {
 	return 0x40000;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void)
 {
 	return 0x800000;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void)
 {
 	return 0x400000;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
-{
-	return 0x80000;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
-{
-	return 0x100000;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
-{
-	return 0x00419e4c;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_r(void)
 {
-	return 0x1;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
-{
-	return 0x2;
+	return 0x00419f2c;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
 {
 	return 0x4;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
-{
-	return 0x8;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_int_report_f(void)
 {
 	return 0x10;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void)
-{
-	return 0x20000000;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void)
-{
-	return 0x40000000;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void)
 {
 	return 0x20;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void)
 {
 	return 0x40;
 }
@@ -3482,190 +3146,118 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
 {
 	return 0x00000001;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void)
 {
-	return 0x00504610;
+	return 0x00504704;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void)
 {
 	return 0x1 << 0;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r)
 {
 	return (r >> 0) & 0x1;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void)
 {
 	return 0x00000001;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void)
 {
 	return 0x00000000;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void)
 {
 	return 0x80000000;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void)
 {
 	return 0x0;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void)
 {
 	return 0x8;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void)
 {
 	return 0x0;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void)
 {
 	return 0x40000000;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
-{
-	return 0x1 << 1;
-}
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
+static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void)
 {
-	return (r >> 1) & 0x1;
-}
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
-{
-	return 0x0;
-}
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
-{
-	return 0x1 << 2;
-}
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
-{
-	return (r >> 2) & 0x1;
-}
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
-{
-	return 0x0;
-}
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
-{
-	return 0x00000000;
-}
-static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
-{
-	return 0x00000000;
-}
-static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
-{
-	return 0x00504614;
+	return 0x00504708;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void)
 {
-	return 0x00504624;
+	return 0x00504710;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void)
 {
-	return 0x00504634;
+	return 0x00504718;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_bpt_pause_mask_r(void)
 {
-	return 0x00419e24;
+	return 0x00419f10;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void)
 {
-	return 0x0050460c;
+	return 0x00504700;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r)
 {
 	return (r >> 0) & 0x1;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r)
 {
 	return (r >> 4) & 0x1;
 }
-static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void)
 {
 	return 0x00000001;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_r(void)
 {
-	return 0x00419e50;
+	return 0x00419f34;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_int_pending_f(void)
 {
 	return 0x10;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(void)
 {
 	return 0x20;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_single_step_complete_pending_f(void)
 {
 	return 0x40;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
-{
-	return 0x1;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
-{
-	return 0x2;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f(void)
 {
 	return 0x4;
 }
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
-{
-	return 0x8;
-}
-static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void)
 {
-	return 0x80000000;
-}
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
-{
-	return 0x00504650;
+	return 0x00504734;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void)
 {
 	return 0x10;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void)
-{
-	return 0x20000000;
-}
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void)
-{
-	return 0x40000000;
-}
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void)
 {
 	return 0x20;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void)
 {
 	return 0x40;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
-{
-	return 0x1;
-}
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
-{
-	return 0x2;
-}
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void)
 {
 	return 0x4;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
-{
-	return 0x8;
-}
-static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
-{
-	return 0x80000000;
-}
 static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
 {
 	return 0x00504224;
@@ -3682,45 +3274,45 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
 {
 	return 0x100;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void)
 {
-	return 0x00504648;
+	return 0x00504730;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r)
 {
 	return (r >> 0) & 0xffff;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void)
 {
 	return 0x00000000;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void)
 {
 	return 0x0;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void)
 {
-	return 0x1 << 24;
+	return 0xff << 16;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void)
 {
-	return 0x7 << 25;
+	return 0xf << 24;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void)
 {
 	return 0x0;
 }
-static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void)
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void)
 {
-	return 0x00504654;
+	return 0x00504738;
 }
 static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
 {
-	return 0x00504770;
+	return 0x005043a0;
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
 {
-	return 0x00419f70;
+	return 0x00419ba0;
 }
 static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
 {
@@ -3732,11 +3324,11 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
 }
 static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
 {
-	return 0x0050477c;
+	return 0x005043b0;
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
 {
-	return 0x00419f7c;
+	return 0x00419bb0;
 }
 static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
 {
@@ -3754,29 +3346,9 @@ static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
 {
 	return 0x4;
 }
-static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
+static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i)
 {
-	return 0x0041bf00;
-}
-static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
-{
-	return 0x0041bf04;
-}
-static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
-{
-	return 0x0041bf08;
-}
-static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
-{
-	return 0x0041bf0c;
-}
-static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
-{
-	return 0x0041bf10;
-}
-static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
-{
-	return 0x0041bf14;
+	return 0x0041bf00 + i*4;
 }
 static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
 {
@@ -3798,10 +3370,6 @@ static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
 {
 	return (v & 0x7) << 21;
 }
-static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
-{
-	return (v & 0x1f) << 24;
-}
 static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
 {
 	return 0x0041bfd4;
@@ -3810,33 +3378,25 @@ static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
 {
 	return (v & 0xffffff) << 0;
 }
-static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
-{
-	return 0x0041bfe4;
-}
-static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i)
 {
-	return (v & 0x1f) << 0;
+	return 0x0041bfb0 + i*4;
 }
-static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v)
 {
-	return (v & 0x1f) << 5;
-}
-static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
-{
-	return (v & 0x1f) << 10;
+	return (v & 0xff) << 0;
 }
-static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v)
 {
-	return (v & 0x1f) << 15;
+	return (v & 0xff) << 8;
 }
-static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v)
 {
-	return (v & 0x1f) << 20;
+	return (v & 0xff) << 16;
 }
-static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v)
 {
-	return (v & 0x1f) << 25;
+	return (v & 0xff) << 24;
 }
 static inline u32 gr_bes_zrop_settings_r(void)
 {
@@ -3884,107 +3444,75 @@ static inline u32 gr_zcull_subregion_qty_v(void)
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
 {
-	return 0x00504604;
+	return 0x00504308;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
 {
-	return 0x00504608;
+	return 0x0050430c;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
 {
-	return 0x0050465c;
+	return 0x00504318;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
 {
-	return 0x00504660;
+	return 0x00504320;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
 {
-	return 0x00504664;
+	return 0x00504324;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
 {
-	return 0x00504668;
+	return 0x00504328;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
 {
-	return 0x0050466c;
+	return 0x0050432c;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
 {
-	return 0x00504658;
+	return 0x0050431c;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
 {
-	return 0x00504730;
+	return 0x00504378;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
 {
-	return 0x00504734;
+	return 0x0050437c;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
 {
-	return 0x00504738;
+	return 0x00504380;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
 {
-	return 0x0050473c;
+	return 0x00504384;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
 {
-	return 0x00504740;
+	return 0x00504388;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
 {
-	return 0x00504744;
+	return 0x0050438c;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
 {
-	return 0x00504748;
+	return 0x00504390;
 }
 static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
 {
-	return 0x0050474c;
-}
-static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
-{
-	return 0x00504678;
+	return 0x00504394;
 }
-static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
+static inline u32 gr_pri_gpc0_tpc0_sm0_dsm_perf_counter_status_s1_r(void)
 {
-	return 0x00504694;
-}
-static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
-{
-	return 0x005046f0;
-}
-static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
-{
-	return 0x00504700;
-}
-static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
-{
-	return 0x005046f4;
-}
-static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
-{
-	return 0x00504704;
-}
-static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
-{
-	return 0x005046f8;
-}
-static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
-{
-	return 0x00504708;
-}
-static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
-{
-	return 0x005046fc;
+	return 0x00504744;
 }
-static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
+static inline u32 gr_pri_gpc0_tpc0_sm0_dsm_perf_counter_status1_r(void)
 {
-	return 0x0050470c;
+	return 0x00504750;
 }
 static inline u32 gr_fe_pwr_mode_r(void)
 {
@@ -4082,55 +3610,55 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
 {
 	return 0x004188ac;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_r(void)
 {
-	return 0x00419e10;
+	return 0x00419f04;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_f(u32 v)
 {
 	return (v & 0x1) << 0;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_on_v(void)
 {
 	return 0x00000001;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_m(void)
 {
 	return 0x1 << 31;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_v(u32 r)
 {
 	return (r >> 31) & 0x1;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_enable_f(void)
 {
 	return 0x80000000;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_disable_f(void)
 {
 	return 0x0;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(void)
 {
 	return 0x1 << 3;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f(void)
 {
 	return 0x8;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f(void)
 {
 	return 0x0;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_m(void)
 {
 	return 0x1 << 30;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_v(u32 r)
 {
 	return (r >> 30) & 0x1;
 }
-static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
+static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_task_f(void)
 {
 	return 0x40000000;
 }
@@ -4148,7 +3676,7 @@ static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
 {
-	return 0x00419c84;
+	return 0x00419bd8;
 }
 static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
 {
@@ -4164,7 +3692,7 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_ma
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
 {
-	return 0x00419f78;
+	return 0x00419ba4;
 }
 static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
 {
@@ -4180,10 +3708,10 @@ static inline u32 gr_gpcs_tc_debug0_r(void)
 }
 static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
 {
-	return (v & 0xff) << 0;
+	return (v & 0x1ff) << 0;
 }
 static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
 {
-	return 0xff << 0;
+	return 0x1ff << 0;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h
index 2dbd759f..4c10852e 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h
@@ -570,12 +570,4 @@ static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
 {
 	return (r >> 16) & 0x1f;
 }
-static inline u32 ltc_ltca_g_axi_pctrl_r(void)
-{
-	return 0x00160000;
-}
-static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v)
-{
-	return (v & 0xff) << 2;
-}
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
index b3aaa7e6..259d366d 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
@@ -72,7 +72,7 @@ static inline u32 pbdma_gp_base_r(u32 i)
 }
 static inline u32 pbdma_gp_base__size_1_v(void)
 {
-	return 0x00000001;
+	return 0x00000003;
 }
 static inline u32 pbdma_gp_base_offset_f(u32 v)
 {
@@ -470,10 +470,6 @@ static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
 {
 	return 0x80000;
 }
-static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
-{
-	return 0x100000;
-}
 static inline u32 pbdma_intr_0_method_pending_f(void)
 {
 	return 0x200000;
@@ -510,10 +506,6 @@ static inline u32 pbdma_intr_0_signature_pending_f(void)
 {
 	return 0x80000000;
 }
-static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void)
-{
-	return 0x10000000;
-}
 static inline u32 pbdma_intr_1_r(u32 i)
 {
 	return 0x00040148 + i*8192;
@@ -566,38 +558,6 @@ static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v)
 {
 	return (v & 0x7fff) << 0;
 }
-static inline u32 pbdma_syncpointa_r(u32 i)
-{
-	return 0x000400a4 + i*8192;
-}
-static inline u32 pbdma_syncpointa_payload_v(u32 r)
-{
-	return (r >> 0) & 0xffffffff;
-}
-static inline u32 pbdma_syncpointb_r(u32 i)
-{
-	return 0x000400a8 + i*8192;
-}
-static inline u32 pbdma_syncpointb_op_v(u32 r)
-{
-	return (r >> 0) & 0x1;
-}
-static inline u32 pbdma_syncpointb_op_wait_v(void)
-{
-	return 0x00000000;
-}
-static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
-{
-	return (r >> 4) & 0x1;
-}
-static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
-{
-	return 0x00000001;
-}
-static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
-{
-	return (r >> 8) & 0xfff;
-}
 static inline u32 pbdma_runlist_timeslice_r(u32 i)
 {
 	return 0x000400f8 + i*8192;
diff --git a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h
index 4d11fef4..836c014b 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h
@@ -52,7 +52,7 @@
 
 static inline u32 perf_pmasys_control_r(void)
 {
-	return 0x001b4000;
+	return 0x0024a000;
 }
 static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
 {
@@ -84,7 +84,7 @@ static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
 }
 static inline u32 perf_pmasys_mem_block_r(void)
 {
-	return 0x001b4070;
+	return 0x0024a070;
 }
 static inline u32 perf_pmasys_mem_block_base_f(u32 v)
 {
@@ -148,7 +148,7 @@ static inline u32 perf_pmasys_mem_block_valid_false_f(void)
 }
 static inline u32 perf_pmasys_outbase_r(void)
 {
-	return 0x001b4074;
+	return 0x0024a074;
 }
 static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
 {
@@ -156,7 +156,7 @@ static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
 }
 static inline u32 perf_pmasys_outbaseupper_r(void)
 {
-	return 0x001b4078;
+	return 0x0024a078;
 }
 static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
 {
@@ -164,7 +164,7 @@ static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
 }
 static inline u32 perf_pmasys_outsize_r(void)
 {
-	return 0x001b407c;
+	return 0x0024a07c;
 }
 static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
 {
@@ -172,7 +172,7 @@ static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
 }
 static inline u32 perf_pmasys_mem_bytes_r(void)
 {
-	return 0x001b4084;
+	return 0x0024a084;
 }
 static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
 {
@@ -180,7 +180,7 @@ static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
 }
 static inline u32 perf_pmasys_mem_bump_r(void)
 {
-	return 0x001b4088;
+	return 0x0024a088;
 }
 static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
 {
@@ -188,7 +188,7 @@ static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
 }
 static inline u32 perf_pmasys_enginestatus_r(void)
 {
-	return 0x001b40a4;
+	return 0x0024a0a4;
 }
 static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h
index e08c6854..3477c03e 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h
@@ -108,23 +108,23 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void)
 }
 static inline u32 proj_host_num_engines_v(void)
 {
-	return 0x00000002;
+	return 0x00000004;
 }
 static inline u32 proj_host_num_pbdma_v(void)
 {
-	return 0x00000001;
+	return 0x00000003;
 }
 static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
 {
-	return 0x00000002;
+	return 0x00000004;
 }
 static inline u32 proj_scal_litter_num_fbps_v(void)
 {
-	return 0x00000001;
+	return 0x00000002;
 }
 static inline u32 proj_scal_litter_num_fbpas_v(void)
 {
-	return 0x00000001;
+	return 0x00000004;
 }
 static inline u32 proj_scal_litter_num_gpcs_v(void)
 {
@@ -132,7 +132,7 @@ static inline u32 proj_scal_litter_num_gpcs_v(void)
 }
 static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
 {
-	return 0x00000001;
+	return 0x00000002;
 }
 static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h
index 27ea4246..965f8663 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h
@@ -608,11 +608,11 @@ static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
 }
 static inline u32 pwr_pmu_queue_head_r(u32 i)
 {
-	return 0x0010a4a0 + i*4;
+	return 0x0010a800 + i*4;
 }
 static inline u32 pwr_pmu_queue_head__size_1_v(void)
 {
-	return 0x00000004;
+	return 0x00000008;
 }
 static inline u32 pwr_pmu_queue_head_address_f(u32 v)
 {
@@ -624,11 +624,11 @@ static inline u32 pwr_pmu_queue_head_address_v(u32 r)
 }
 static inline u32 pwr_pmu_queue_tail_r(u32 i)
 {
-	return 0x0010a4b0 + i*4;
+	return 0x0010a820 + i*4;
 }
 static inline u32 pwr_pmu_queue_tail__size_1_v(void)
 {
-	return 0x00000004;
+	return 0x00000008;
 }
 static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
index 6ccbc266..c6f51acb 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
@@ -148,7 +148,7 @@ static inline u32 ram_in_page_dir_base_lo_w(void)
 }
 static inline u32 ram_in_page_dir_base_hi_f(u32 v)
 {
-	return (v & 0xff) << 0;
+	return (v & 0xffffffff) << 0;
 }
 static inline u32 ram_in_page_dir_base_hi_w(void)
 {
@@ -354,14 +354,6 @@ static inline u32 ram_fc_allowed_syncpoints_w(void)
 {
 	return 58;
 }
-static inline u32 ram_fc_syncpointa_w(void)
-{
-	return 41;
-}
-static inline u32 ram_fc_syncpointb_w(void)
-{
-	return 42;
-}
 static inline u32 ram_fc_target_w(void)
 {
 	return 43;
@@ -443,6 +435,74 @@ static inline u32 ram_userd_gp_top_level_get_hi_w(void)
 	return 23;
 }
 static inline u32 ram_rl_entry_size_v(void)
+{
+	return 0x00000010;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+	return (v & 0x1) << 0;
+}
+static inline u32 ram_rl_entry_type_channel_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ram_rl_entry_type_tsg_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+	return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v)
+{
+	return (v & 0x1) << 1;
+}
+static inline u32 ram_rl_entry_chan_inst_target_f(u32 v)
+{
+	return (v & 0x3) << 4;
+}
+static inline u32 ram_rl_entry_chan_inst_target_target_sys_mem_ncoh_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 ram_rl_entry_chan_userd_target_f(u32 v)
+{
+	return (v & 0x3) << 6;
+}
+static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_nvlink_coh_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_coh_v(void)
+{
+	return 0x00000002;
+}
+static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_ncoh_v(void)
+{
+	return 0x00000003;
+}
+static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v)
+{
+	return (v & 0xffffff) << 8;
+}
+static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_inst_ptr_align_shift_v(void)
+{
+	return 0x0000000c;
+}
+static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_ptr_align_shift_v(void)
+{
+	return 0x00000008;
+}
+static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_align_shift_v(void)
 {
 	return 0x00000008;
 }
@@ -450,40 +510,56 @@ static inline u32 ram_rl_entry_chid_f(u32 v)
 {
 	return (v & 0xfff) << 0;
 }
-static inline u32 ram_rl_entry_id_f(u32 v)
+static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v)
 {
-	return (v & 0xfff) << 0;
+	return (v & 0xfffff) << 12;
 }
-static inline u32 ram_rl_entry_type_f(u32 v)
+static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v)
 {
-	return (v & 0x1) << 13;
+	return (v & 0xffffffff) << 0;
 }
-static inline u32 ram_rl_entry_type_chid_f(void)
+static inline u32 ram_rl_entry_tsg_vmid_f(u32 v)
 {
-	return 0x0;
+	return (v & 0xff) << 4;
 }
-static inline u32 ram_rl_entry_type_tsg_f(void)
+static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v)
 {
-	return 0x2000;
+	return (v & 0xf) << 16;
 }
-static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+static inline u32 ram_rl_entry_tsg_timeslice_scale_entry_tsg_timeslice_scale_3_v(void)
 {
-	return (v & 0xf) << 14;
+	return 0x00000003;
 }
-static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v)
 {
-	return 0xc000;
+	return (v & 0xff) << 24;
 }
-static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_128_v(void)
 {
-	return (v & 0xff) << 18;
+	return 0x00000080;
 }
-static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_disable_v(void)
 {
-	return 0x2000000;
+	return 0x00000000;
 }
 static inline u32 ram_rl_entry_tsg_length_f(u32 v)
 {
-	return (v & 0x3f) << 26;
+	return (v & 0xff) << 0;
+}
+static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_init_v(void)
+{
+	return 0x00000000;
+}
+static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_min_v(void)
+{
+	return 0x00000001;
+}
+static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_max_v(void)
+{
+	return 0x00000080;
+}
+static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v)
+{
+	return (v & 0xfff) << 0;
 }
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h
index 2c464d2c..a3cfcf91 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h
@@ -50,360 +50,4 @@
 #ifndef _hw_therm_gv11b_h_
 #define _hw_therm_gv11b_h_
 
-static inline u32 therm_use_a_r(void)
-{
-	return 0x00020798;
-}
-static inline u32 therm_use_a_ext_therm_0_enable_f(void)
-{
-	return 0x1;
-}
-static inline u32 therm_use_a_ext_therm_1_enable_f(void)
-{
-	return 0x2;
-}
-static inline u32 therm_use_a_ext_therm_2_enable_f(void)
-{
-	return 0x4;
-}
-static inline u32 therm_evt_ext_therm_0_r(void)
-{
-	return 0x00020700;
-}
-static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
-{
-	return (v & 0x3f) << 24;
-}
-static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
-{
-	return 0x00000001;
-}
-static inline u32 therm_evt_ext_therm_0_mode_f(u32 v)
-{
-	return (v & 0x3) << 30;
-}
-static inline u32 therm_evt_ext_therm_0_mode_normal_v(void)
-{
-	return 0x00000000;
-}
-static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void)
-{
-	return 0x00000001;
-}
-static inline u32 therm_evt_ext_therm_0_mode_forced_v(void)
-{
-	return 0x00000002;
-}
-static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void)
-{
-	return 0x00000003;
-}
-static inline u32 therm_evt_ext_therm_1_r(void)
-{
-	return 0x00020704;
-}
-static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
-{
-	return (v & 0x3f) << 24;
-}
-static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
-{
-	return 0x00000002;
-}
-static inline u32 therm_evt_ext_therm_1_mode_f(u32 v)
-{
-	return (v & 0x3) << 30;
-}
-static inline u32 therm_evt_ext_therm_1_mode_normal_v(void)
-{
-	return 0x00000000;
-}
-static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void)
-{
-	return 0x00000001;
-}
-static inline u32 therm_evt_ext_therm_1_mode_forced_v(void)
-{
-	return 0x00000002;
-}
-static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void)
-{
-	return 0x00000003;
-}
-static inline u32 therm_evt_ext_therm_2_r(void)
-{
-	return 0x00020708;
-}
-static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
-{
-	return (v & 0x3f) << 24;
-}
-static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
-{
-	return 0x00000003;
-}
-static inline u32 therm_evt_ext_therm_2_mode_f(u32 v)
-{
-	return (v & 0x3) << 30;
-}
-static inline u32 therm_evt_ext_therm_2_mode_normal_v(void)
-{
-	return 0x00000000;
-}
-static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void)
-{
-	return 0x00000001;
-}
-static inline u32 therm_evt_ext_therm_2_mode_forced_v(void)
-{
-	return 0x00000002;
-}
-static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void)
-{
-	return 0x00000003;
-}
-static inline u32 therm_weight_1_r(void)
-{
-	return 0x00020024;
-}
-static inline u32 therm_config1_r(void)
-{
-	return 0x00020050;
-}
-static inline u32 therm_config2_r(void)
-{
-	return 0x00020130;
-}
-static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
-{
-	return (v & 0x1) << 24;
-}
-static inline u32 therm_config2_grad_enable_f(u32 v)
-{
-	return (v & 0x1) << 31;
-}
-static inline u32 therm_gate_ctrl_r(u32 i)
-{
-	return 0x00020200 + i*4;
-}
-static inline u32 therm_gate_ctrl_eng_clk_m(void)
-{
-	return 0x3 << 0;
-}
-static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
-{
-	return 0x0;
-}
-static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
-{
-	return 0x1;
-}
-static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
-{
-	return 0x2;
-}
-static inline u32 therm_gate_ctrl_blk_clk_m(void)
-{
-	return 0x3 << 2;
-}
-static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
-{
-	return 0x0;
-}
-static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
-{
-	return 0x4;
-}
-static inline u32 therm_gate_ctrl_eng_pwr_m(void)
-{
-	return 0x3 << 4;
-}
-static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
-{
-	return 0x10;
-}
-static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
-{
-	return 0x00000002;
-}
-static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
-{
-	return 0x20;
-}
-static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
-{
-	return (v & 0x1f) << 8;
-}
-static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
-{
-	return 0x1f << 8;
-}
-static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
-{
-	return (v & 0x7) << 13;
-}
-static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
-{
-	return 0x7 << 13;
-}
-static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
-{
-	return (v & 0xf) << 16;
-}
-static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
-{
-	return 0xf << 16;
-}
-static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
-{
-	return (v & 0xf) << 20;
-}
-static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
-{
-	return 0xf << 20;
-}
-static inline u32 therm_fecs_idle_filter_r(void)
-{
-	return 0x00020288;
-}
-static inline u32 therm_fecs_idle_filter_value_m(void)
-{
-	return 0xffffffff << 0;
-}
-static inline u32 therm_hubmmu_idle_filter_r(void)
-{
-	return 0x0002028c;
-}
-static inline u32 therm_hubmmu_idle_filter_value_m(void)
-{
-	return 0xffffffff << 0;
-}
-static inline u32 therm_clk_slowdown_r(u32 i)
-{
-	return 0x00020160 + i*4;
-}
-static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
-{
-	return (v & 0x3f) << 16;
-}
-static inline u32 therm_clk_slowdown_idle_factor_m(void)
-{
-	return 0x3f << 16;
-}
-static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
-{
-	return (r >> 16) & 0x3f;
-}
-static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
-{
-	return 0x0;
-}
-static inline u32 therm_grad_stepping_table_r(u32 i)
-{
-	return 0x000202c8 + i*4;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
-{
-	return (v & 0x3f) << 0;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
-{
-	return 0x3f << 0;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
-{
-	return 0x1;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
-{
-	return 0x2;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
-{
-	return 0x6;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
-{
-	return 0xe;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
-{
-	return (v & 0x3f) << 6;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
-{
-	return 0x3f << 6;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
-{
-	return (v & 0x3f) << 12;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
-{
-	return 0x3f << 12;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
-{
-	return (v & 0x3f) << 18;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
-{
-	return 0x3f << 18;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
-{
-	return (v & 0x3f) << 24;
-}
-static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
-{
-	return 0x3f << 24;
-}
-static inline u32 therm_grad_stepping0_r(void)
-{
-	return 0x000202c0;
-}
-static inline u32 therm_grad_stepping0_feature_s(void)
-{
-	return 1;
-}
-static inline u32 therm_grad_stepping0_feature_f(u32 v)
-{
-	return (v & 0x1) << 0;
-}
-static inline u32 therm_grad_stepping0_feature_m(void)
-{
-	return 0x1 << 0;
-}
-static inline u32 therm_grad_stepping0_feature_v(u32 r)
-{
-	return (r >> 0) & 0x1;
-}
-static inline u32 therm_grad_stepping0_feature_enable_f(void)
-{
-	return 0x1;
-}
-static inline u32 therm_grad_stepping1_r(void)
-{
-	return 0x000202c4;
-}
-static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
-{
-	return (v & 0x1ffff) << 0;
-}
-static inline u32 therm_clk_timing_r(u32 i)
-{
-	return 0x000203c0 + i*4;
-}
-static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
-{
-	return (v & 0x1) << 16;
-}
-static inline u32 therm_clk_timing_grad_slowdown_m(void)
-{
-	return 0x1 << 16;
-}
-static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
-{
-	return 0x10000;
-}
 #endif
diff --git a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h
index cb65cad8..2e2ff6ba 100644
--- a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h
@@ -208,7 +208,7 @@ static inline u32 top_device_info_data_pri_base_align_v(void)
 }
 static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
 {
-	return (r >> 3) & 0x1f;
+	return (r >> 3) & 0x7f;
 }
 static inline u32 top_device_info_data_fault_id_v(u32 r)
 {
diff --git a/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h
new file mode 100644
index 00000000..8bcf163f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_usermode_gv11b_h_
+#define _hw_usermode_gv11b_h_
+
+static inline u32 usermode_cfg0_r(void)
+{
+	return 0x00810000;
+}
+static inline u32 usermode_cfg0_usermode_class_id_f(u32 v)
+{
+	return (v & 0xffff) << 0;
+}
+static inline u32 usermode_cfg0_usermode_class_id_value_v(void)
+{
+	return 0x0000c361;
+}
+static inline u32 usermode_time_0_r(void)
+{
+	return 0x00810080;
+}
+static inline u32 usermode_time_0_nsec_f(u32 v)
+{
+	return (v & 0x7ffffff) << 5;
+}
+static inline u32 usermode_time_1_r(void)
+{
+	return 0x00810084;
+}
+static inline u32 usermode_time_1_nsec_f(u32 v)
+{
+	return (v & 0x1fffffff) << 0;
+}
+static inline u32 usermode_notify_channel_pending_r(void)
+{
+	return 0x00810090;
+}
+static inline u32 usermode_notify_channel_pending_id_f(u32 v)
+{
+	return (v & 0xffffffff) << 0;
+}
+#endif
-- 
cgit v1.2.2