From 4f67a794ddbb9e5c1ce66461fabdf3f27708945a Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Thu, 30 Nov 2017 01:08:52 -0800 Subject: gpu: nvgpu: vgpu: add io coherency support Modify command message parameter to support io coherency. Jira EVLR-2025 Change-Id: I38b21c72d85f559555c4d97dab73d0f715ecc655 Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1614388 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c | 5 ++++- drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c | 1 + include/linux/tegra_vgpu.h | 5 ++++- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c index 8c5a6d27..b857ea95 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c @@ -165,7 +165,10 @@ u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, p->pgsz_idx = pgsz_idx; p->iova = 0; p->kind = kind_v; - p->cacheable = (flags & NVGPU_VM_MAP_CACHEABLE) ? 1 : 0; + if (flags & NVGPU_VM_MAP_CACHEABLE) + p->flags = TEGRA_VGPU_MAP_CACHEABLE; + if (flags & NVGPU_VM_MAP_IO_COHERENT) + p->flags |= TEGRA_VGPU_MAP_IO_COHERENT; p->prot = prot; p->ctag_offset = ctag_offset; p->clear_ctags = clear_ctags; diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c index 9ba1892b..93e26541 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c @@ -35,6 +35,7 @@ int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) } __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); + __nvgpu_set_enabled(g, NVGPU_SUPPORT_IO_COHERENCE, true); return 0; } diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 5c81e8c9..7b5c9e11 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h @@ -160,6 +160,9 @@ struct tegra_vgpu_as_map_params { u32 ctag_offset; }; +#define TEGRA_VGPU_MAP_CACHEABLE (1 << 0) +#define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1) + struct tegra_vgpu_as_map_ex_params { u64 handle; u64 gpu_va; @@ -168,7 +171,7 @@ struct tegra_vgpu_as_map_ex_params { u8 pgsz_idx; u8 iova; u8 kind; - u8 cacheable; + u32 flags; u8 clear_ctags; u8 prot; u32 ctag_offset; -- cgit v1.2.2