From 47c794ab5238482d15448a862dbd63530f261952 Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Thu, 30 Nov 2017 01:11:36 -0800 Subject: gpu: nvgpu: vgpu: add l3 allocation support Modify rpc command parameter to support l3 cache allocation. Jira EVLR-1752 Change-Id: I1be00e04ee01c0763f46c0d0da6a112316cc7e1d Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1616566 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c | 6 +++++- include/linux/tegra_vgpu.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c index b857ea95..d343da03 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c @@ -1,7 +1,7 @@ /* * Virtualized GPU Memory Management * - * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -169,6 +169,10 @@ u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, p->flags = TEGRA_VGPU_MAP_CACHEABLE; if (flags & NVGPU_VM_MAP_IO_COHERENT) p->flags |= TEGRA_VGPU_MAP_IO_COHERENT; +#ifdef CONFIG_TEGRA_19x_GPU + if (flags & NVGPU_VM_MAP_L3_ALLOC) + p->flags |= TEGRA_VGPU_MAP_L3_ALLOC; +#endif p->prot = prot; p->ctag_offset = ctag_offset; p->clear_ctags = clear_ctags; diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 105870dc..9980f4bc 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h @@ -163,6 +163,7 @@ struct tegra_vgpu_as_map_params { #define TEGRA_VGPU_MAP_CACHEABLE (1 << 0) #define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1) +#define TEGRA_VGPU_MAP_L3_ALLOC (1 << 2) struct tegra_vgpu_as_map_ex_params { u64 handle; -- cgit v1.2.2