From 434b1c588b9c8d61ac413b0c9ae402b483deb68b Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 28 Feb 2017 16:17:04 -0800 Subject: gpu: nvgpu: gv11b: handle l2 related changes Implemented gv11b specific l2 state init and Configured ltc_ltcs_ltss_cbc_num_active_ltcs_r with following info: - cbc_num_active_ltcs is read only for gv11b, so did not write any data to that field. - enforced serilized access to l2 from sysmem and peermem. - nvlink connected peer trafic sent through l2 JIRA GV11B-71 Change-Id: I63d9ee3f0a6da62e672a34e207f1f5214b6ed1b4 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1312831 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 38 ++++++++++++++++++++++ .../nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h | 22 ++++++++++++- 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 85ff33d2..70919f24 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -20,6 +20,8 @@ #include "ltc_gv11b.h" #include +#include +#include /* * Sets the ZBC stencil for the passed index. @@ -39,8 +41,44 @@ static void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g, gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); } +static void gv11b_ltc_init_fs_state(struct gk20a *g) +{ + u32 ltc_intr; + u32 reg; + + gk20a_dbg_info("initialize gv11b l2"); + + g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r()); + g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); + gk20a_dbg_info("%u ltcs out of %u", g->ltc_count, g->max_ltc_count); + + reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r()); + reg |= ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(true) + | ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(true); + gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), reg); + + gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(), + gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) | + ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m()); + + /* Disable LTC interrupts */ + reg = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); + reg &= ~ltc_ltcs_ltss_intr_en_evicted_cb_m(); + reg &= ~ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(); + gk20a_writel(g, ltc_ltcs_ltss_intr_r(), reg); + + /* Enable ECC interrupts */ + ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); + ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | + ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); + gk20a_writel(g, ltc_ltcs_ltss_intr_r(), + ltc_intr); +} + + void gv11b_init_ltc(struct gpu_ops *gops) { gp10b_init_ltc(gops); gops->ltc.set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry; + gops->ltc.init_fs_state = gv11b_ltc_init_fs_state; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h index 6968c699..45d3df07 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -174,6 +174,26 @@ static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) { return 0x0017e27c; } +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) +{ + return (r >> 24) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) +{ + return (r >> 25) & 0x1; +} static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) { return 0x0017e000; -- cgit v1.2.2