From 3735dba6f83e8de21eb2db620402d0ea9fd28835 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 23 May 2016 18:35:34 -0700 Subject: gpu: nvgpu: vgpu: add general event support Events like bpt int/pause will help cuda work properly. Bug 200173403 VFND-1568 Change-Id: I29e534969028bf08aedd81c99f5a536779f431d1 Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1159621 (cherry picked from commit a266e53c514639e15ed166e2c8ce5a55efc48eda) Reviewed-on: http://git-master/r/1152154 Reviewed-by: Aingara Paramakuru GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/vgpu.c | 34 ++++++++++++++++++++++++++++++++++ include/linux/tegra_vgpu.h | 10 +++++++++- 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index aa4ece5f..0d5dd27b 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c @@ -23,6 +23,8 @@ #include "gk20a/hal_gk20a.h" #include "gk20a/hw_mc_gk20a.h" #include "gk20a/ctxsw_trace_gk20a.h" +#include "gk20a/tsg_gk20a.h" +#include "gk20a/channel_gk20a.h" #include "gm20b/hal_gm20b.h" #ifdef CONFIG_ARCH_TEGRA_18x_SOC @@ -97,6 +99,32 @@ int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value) return 0; } +static void vgpu_handle_general_event(struct gk20a *g, + struct tegra_vgpu_general_event_info *info) +{ + if (info->id >= g->fifo.num_channels || + info->event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX) { + gk20a_err(g->dev, "invalid general event"); + return; + } + + if (info->is_tsg) { + struct tsg_gk20a *tsg = &g->fifo.tsg[info->id]; + + gk20a_tsg_event_id_post_event(tsg, info->event_id); + } else { + struct channel_gk20a *ch = &g->fifo.channel[info->id]; + + if (!gk20a_channel_get(ch)) { + gk20a_err(g->dev, "invalid channel %d for event %d", + (int)info->id, (int)info->event_id); + return; + } + gk20a_channel_event_id_post_event(ch, info->event_id); + gk20a_channel_put(ch); + } +} + static int vgpu_intr_thread(void *dev_id) { struct gk20a *g = dev_id; @@ -127,6 +155,12 @@ static int vgpu_intr_thread(void *dev_id) continue; } + if (msg->event == TEGRA_VGPU_EVENT_CHANNEL) { + vgpu_handle_general_event(g, &msg->info.general_event); + tegra_gr_comm_release(handle); + continue; + } + if (msg->unit == TEGRA_VGPU_INTR_GR) vgpu_gr_isr(g, &msg->info.gr_intr); else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR) diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index e6e03459..9a31ff40 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h @@ -483,6 +483,12 @@ struct tegra_vgpu_fecs_trace_event_info { u32 type; }; +struct tegra_vgpu_general_event_info { + u32 event_id; + u32 is_tsg; + u32 id; /* channel id or tsg id */ +}; + enum { TEGRA_VGPU_INTR_GR = 0, @@ -496,7 +502,8 @@ enum { enum { TEGRA_VGPU_EVENT_INTR = 0, TEGRA_VGPU_EVENT_ABORT, - TEGRA_VGPU_EVENT_FECS_TRACE + TEGRA_VGPU_EVENT_FECS_TRACE, + TEGRA_VGPU_EVENT_CHANNEL, }; struct tegra_vgpu_intr_msg { @@ -509,6 +516,7 @@ struct tegra_vgpu_intr_msg { struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr; struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; struct tegra_vgpu_fecs_trace_event_info fecs_trace; + struct tegra_vgpu_general_event_info general_event; char padding[32]; } info; }; -- cgit v1.2.2