From 351f519c2e1a2424a9a09c7a6b0f5c075198b3f0 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 5 Jan 2018 08:10:44 -0800 Subject: gpu: nvgpu: Add HAL for dumping ctxsw statistics Add HAL for dumping ctxsw statistics. The statistics are dependent on the architecture, and the function that calls this operation needs to be moved to gk20a. Bug 1842197 Change-Id: I285c74b8ddc8c7854c85b3fef4cbfc582098919e Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1632681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 ++ drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 9 +++++---- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 2 ++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 5 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 4f05ba8f..070b26b6 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -439,6 +439,8 @@ struct gpu_ops { void (*ecc_init_scrub_reg)(struct gk20a *g); u32 (*get_gpcs_swdx_dss_zbc_c_format_reg)(struct gk20a *g); u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g); + void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm, + struct gr_ctx_desc *gr_ctx); } gr; struct { void (*init_hw)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 68d18aa1..ca2bc52b 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1115,8 +1115,8 @@ fail_free_gk20a_ctx: return err; } -static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, - struct gr_ctx_desc *gr_ctx) +void gr_gp10b_dump_ctxsw_stats(struct gk20a *g, struct vm_gk20a *vm, + struct gr_ctx_desc *gr_ctx) { struct nvgpu_mem *mem = &gr_ctx->mem; @@ -1175,8 +1175,9 @@ void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, if (!gr_ctx) return; - if (g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close) - dump_ctx_switch_stats(g, vm, gr_ctx); + if (g->ops.gr.dump_ctxsw_stats && + g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close) + g->ops.gr.dump_ctxsw_stats(g, vm, gr_ctx); nvgpu_dma_unmap_free(vm, &gr_ctx->pagepool_ctxsw_buffer); nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer); diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 1d39a38b..64a076ef 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -108,6 +108,8 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, struct nvgpu_mem *mem); int gr_gp10b_dump_gr_status_regs(struct gk20a *g, struct gk20a_debug_output *o); +void gr_gp10b_dump_ctxsw_stats(struct gk20a *g, struct vm_gk20a *vm, + struct gr_ctx_desc *gr_ctx); int gr_gp10b_wait_empty(struct gk20a *g, unsigned long duration_ms, u32 expect_delay); void gr_gp10b_commit_global_attrib_cb(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index cfba7d65..7ca9e313 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -340,6 +340,7 @@ static const struct gpu_ops gp10b_ops = { gr_gp10b_init_gfxp_wfi_timeout_count, .get_max_gfxp_wfi_timeout_count = gr_gp10b_get_max_gfxp_wfi_timeout_count, + .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, }, .fb = { .reset = fb_gk20a_reset, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f19832b9..7c22448d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -397,6 +397,7 @@ static const struct gpu_ops gv11b_ops = { .get_max_gfxp_wfi_timeout_count = gr_gv11b_get_max_gfxp_wfi_timeout_count, .ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg, + .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, }, .fb = { .reset = gv11b_fb_reset, -- cgit v1.2.2