From 2114869a4084809be18a489dc44d1b8f28e66598 Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Wed, 8 Nov 2017 15:26:23 +0530 Subject: gpu: nvgpu: Update clk_fll interface as per chips_a Two new members added to fll struct and code modified to support GV100 VBIOS NAFLL tables Add g->ops for getting vbios clk domains JIRA NVGPUGV100-39 Change-Id: Iaabea893d55d44a272e2bce2b1d525b122cd36f5 Signed-off-by: Tejal Kudav Reviewed-on: https://git-master.nvidia.com/r/1594289 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar Tested-by: Mahantesh Kumbar Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/clk/clk_fll.c | 85 ++++++++++++++++------- drivers/gpu/nvgpu/clk/clk_fll.h | 7 +- drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 4 ++ drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | 7 +- drivers/gpu/nvgpu/gk20a/gk20a.h | 3 + drivers/gpu/nvgpu/include/nvgpu/bios.h | 3 + drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | 2 + 7 files changed, 82 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index 2f05448f..e85168e3 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ #include "gk20a/gk20a.h" #include "clk.h" #include "clk_fll.h" +#include "clk_domain.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "ctrl/ctrlclk.h" @@ -277,19 +278,35 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, fll_id = fll_desc_table_entry.fll_device_id; - pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, - (u8)fll_desc_table_entry.vin_idx_logic); - if (pvin_dev == NULL) - return -EINVAL; - - pvin_dev->flls_shared_mask |= BIT(fll_id); - - pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, - (u8)fll_desc_table_entry.vin_idx_sram); - if (pvin_dev == NULL) + if ( (u8)fll_desc_table_entry.vin_idx_logic != CTRL_CLK_VIN_ID_UNDEFINED) { + pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, + (u8)fll_desc_table_entry.vin_idx_logic); + if (pvin_dev == NULL) + return -EINVAL; + else + pvin_dev->flls_shared_mask |= BIT(fll_id); + } else { + /* Return if Logic ADC device index is invalid*/ + nvgpu_err(g, "Invalid Logic ADC specified for Nafll ID"); return -EINVAL; + } - pvin_dev->flls_shared_mask |= BIT(fll_id); + fll_dev_data.lut_device.vselect_mode = + (u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params, + NV_FLL_DESC_LUT_PARAMS_VSELECT); + + if ( (u8)fll_desc_table_entry.vin_idx_sram != CTRL_CLK_VIN_ID_UNDEFINED) { + pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, + (u8)fll_desc_table_entry.vin_idx_sram); + if (pvin_dev == NULL) + return -EINVAL; + else + pvin_dev->flls_shared_mask |= BIT(fll_id); + } else { + /* Make sure VSELECT mode is set correctly to _LOGIC*/ + if (fll_dev_data.lut_device.vselect_mode != CTRL_CLK_FLL_LUT_VSELECT_LOGIC) + return -EINVAL; + } fll_dev_data.super.type = (u8)fll_desc_table_entry.fll_device_type; @@ -305,24 +322,17 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, vbios_domain = (u32)(fll_desc_table_entry.clk_domain & NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK); - if (vbios_domain == 0) - fll_dev_data.clk_domain = CTRL_CLK_DOMAIN_GPC2CLK; - else if (vbios_domain == 1) - fll_dev_data.clk_domain = CTRL_CLK_DOMAIN_XBAR2CLK; - else if (vbios_domain == 3) - fll_dev_data.clk_domain = CTRL_CLK_DOMAIN_SYS2CLK; - else - continue; + fll_dev_data.clk_domain = + g->ops.pmu_ver.clk.get_vbios_clk_domain(vbios_domain); fll_dev_data.rail_idx_for_lut = 0; - fll_dev_data.vin_idx_logic = (u8)fll_desc_table_entry.vin_idx_logic; fll_dev_data.vin_idx_sram = (u8)fll_desc_table_entry.vin_idx_sram; - fll_dev_data.lut_device.vselect_mode = - (u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params, - NV_FLL_DESC_LUT_PARAMS_VSELECT); + fll_dev_data.b_skip_pldiv_below_dvco_min = + (bool)BIOS_GET_FIELD(fll_desc_table_entry.fll_params, + NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN); fll_dev_data.lut_device.hysteresis_threshold = (u8)BIOS_GET_FIELD(fll_desc_table_entry.lut_params, NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD); @@ -336,7 +346,6 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, status = boardobjgrp_objinsert(&pfllobjs->super.super, (struct boardobj *)pfll_dev, index); - fll_tbl_entry_ptr += fll_desc_table_header.entry_size; } @@ -345,6 +354,28 @@ done: return status; } +u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain) +{ + if (vbios_domain == 0) + return CTRL_CLK_DOMAIN_GPCCLK; + else if (vbios_domain == 1) + return CTRL_CLK_DOMAIN_XBARCLK; + else if (vbios_domain == 3) + return CTRL_CLK_DOMAIN_SYSCLK; + return 0; +} + +u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain) +{ + if (vbios_domain == 0) + return CTRL_CLK_DOMAIN_GPC2CLK; + else if (vbios_domain == 1) + return CTRL_CLK_DOMAIN_XBAR2CLK; + else if (vbios_domain == 3) + return CTRL_CLK_DOMAIN_SYS2CLK; + return 0; +} + static u32 lutbroadcastslaveregister(struct gk20a *g, struct avfsfllobjs *pfllobjs, struct fll_device *pfll, @@ -387,6 +418,8 @@ static struct fll_device *construct_fll_device(struct gk20a *g, board_obj_fll_ptr->min_freq_vfe_idx = pfll_dev->min_freq_vfe_idx; board_obj_fll_ptr->freq_ctrl_idx = pfll_dev->freq_ctrl_idx; + board_obj_fll_ptr->b_skip_pldiv_below_dvco_min = + pfll_dev->b_skip_pldiv_below_dvco_min; memcpy(&board_obj_fll_ptr->lut_device, &pfll_dev->lut_device, sizeof(struct nv_pmu_clk_lut_device_desc)); memcpy(&board_obj_fll_ptr->regime_desc, &pfll_dev->regime_desc, @@ -427,7 +460,7 @@ static u32 fll_device_init_pmudata_super(struct gk20a *g, perf_pmu_data->min_freq_vfe_idx = pfll_dev->min_freq_vfe_idx; perf_pmu_data->freq_ctrl_idx = pfll_dev->freq_ctrl_idx; - + perf_pmu_data->b_skip_pldiv_below_dvco_min = pfll_dev->b_skip_pldiv_below_dvco_min; memcpy(&perf_pmu_data->lut_device, &pfll_dev->lut_device, sizeof(struct nv_pmu_clk_lut_device_desc)); memcpy(&perf_pmu_data->regime_desc, &pfll_dev->regime_desc, diff --git a/drivers/gpu/nvgpu/clk/clk_fll.h b/drivers/gpu/nvgpu/clk/clk_fll.h index 481ca707..79ecf5e1 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.h +++ b/drivers/gpu/nvgpu/clk/clk_fll.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -61,10 +61,15 @@ struct fll_device { u8 min_freq_vfe_idx; u8 freq_ctrl_idx; u8 target_regime_id_override; + bool b_skip_pldiv_below_dvco_min; + bool b_dvco_1x; struct boardobjgrpmask_e32 lut_prog_broadcast_slave_mask; fll_lut_broadcast_slave_register *lut_broadcast_slave_register; }; +u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain); +u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain); + #define CLK_FLL_LUT_VF_NUM_ENTRIES(pclk) \ (pclk->avfs_fllobjs.lut_num_entries) diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index ea5b21ab..cac5079e 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c @@ -1305,6 +1305,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) nvgpu_volt_rail_get_voltage_gv10x; g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu = nvgpu_volt_send_load_cmd_to_pmu_gv10x; + g->ops.pmu_ver.clk.get_vbios_clk_domain = + nvgpu_clk_get_vbios_clk_domain_gv10x; } else { g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = get_pmu_init_msg_pmu_queue_params_v4; @@ -1470,6 +1472,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) nvgpu_volt_rail_get_voltage_gp10x; g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu = nvgpu_volt_send_load_cmd_to_pmu_gp10x; + g->ops.pmu_ver.clk.get_vbios_clk_domain = + nvgpu_clk_get_vbios_clk_domain_gp10x; break; case APP_VERSION_GM20B: g->ops.pmu_ver.pg_cmd_eng_buf_load_size = diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h index cfc6538a..59a542c8 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -79,7 +79,7 @@ BIT(CTRL_CLK_FLL_ID_GPC4) | \ BIT(CTRL_CLK_FLL_ID_GPC5)) /*! - * Mask of all FLL IDs supported by RM + * Mask of all FLL IDs supported by Nvgpu driver */ #define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \ BIT(CTRL_CLK_FLL_ID_LTC) | \ @@ -96,4 +96,7 @@ #define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001) #define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002) +#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000) +#define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001) +#define CTRL_CLK_FLL_LUT_VSELECT_SRAM (0x00000002) #endif diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index e3b37747..2d1eb388 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -788,6 +788,9 @@ struct gpu_ops { u8 volt_domain, u32 *pvoltage_uv); u32 (*volt_send_load_cmd_to_pmu)(struct gk20a *g); } volt; + struct { + u32 (*get_vbios_clk_domain)(u32 vbios_domain); + }clk; } pmu_ver; struct { int (*get_netlist_name)(struct gk20a *g, int index, char *name); diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 86e009a3..191f0dbd 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h @@ -110,6 +110,9 @@ struct fll_descriptor_entry_10 { #define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F #define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 +#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_MASK 0x20 +#define NV_FLL_DESC_FLL_PARAMS_SKIP_PLDIV_BELOW_DVCO_MIN_SHIFT 5 + #define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 #define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h index 81a1d72e..616aca5c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h @@ -230,6 +230,8 @@ struct nv_pmu_clk_clk_fll_device_boardobj_set { struct nv_pmu_clk_regime_desc regime_desc; u8 min_freq_vfe_idx; u8 freq_ctrl_idx; + bool b_skip_pldiv_below_dvco_min; + bool b_dvco_1x; struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask; }; -- cgit v1.2.2