From 1dfcf1833ba3e8fa58d0ad6ecb189db32c6b986f Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Thu, 8 Jun 2017 11:21:52 +0530 Subject: gpu: nvgpu: Update PMU firmware version. This patch also updates PMU cmdline args as required by updated firmware. GPUT19x-30 Change-Id: I44214007046081a44acc7284eb2854d0548a8da8 Signed-off-by: Deepak Goyal Reviewed-on: http://git-master/r/1498188 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 7 ++++++- drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/pmu.h | 1 + drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | 11 +++++++++++ 4 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index f296b57c..4e416f67 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -205,6 +205,11 @@ static u32 pmu_cmdline_size_v5(struct nvgpu_pmu *pmu) return sizeof(struct pmu_cmdline_args_v5); } +static u32 pmu_cmdline_size_v6(struct nvgpu_pmu *pmu) +{ + return sizeof(struct pmu_cmdline_args_v6); +} + static void set_pmu_cmdline_args_cpufreq_v5(struct nvgpu_pmu *pmu, u32 freq) { pmu->args_v5.cpu_freq_hz = 204000000; @@ -1586,7 +1591,7 @@ int gk20a_init_pmu(struct nvgpu_pmu *pmu) g->ops.pmu_ver.cmd_id_zbc_table_update = 16; g->ops.pmu_ver.is_pmu_zbc_save_supported = false; g->ops.pmu_ver.get_pmu_cmdline_args_size = - pmu_cmdline_size_v5; + pmu_cmdline_size_v6; g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = set_pmu_cmdline_args_cpufreq_v5; g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode = diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 3941d90f..24bc5822 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h @@ -30,7 +30,7 @@ struct nvgpu_firmware; #define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) -#define APP_VERSION_NC_3 21688026 +#define APP_VERSION_NC_3 22204331 #define APP_VERSION_NC_2 20429989 #define APP_VERSION_NC_1 20313802 #define APP_VERSION_NC_0 20360931 diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 0fcc5710..687e00ae 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -314,6 +314,7 @@ struct nvgpu_pmu { struct pmu_cmdline_args_v3 args_v3; struct pmu_cmdline_args_v4 args_v4; struct pmu_cmdline_args_v5 args_v5; + struct pmu_cmdline_args_v6 args_v6; }; unsigned long perfmon_events_cnt; bool perfmon_sampling_enabled; diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h index 6df92c1d..a8897034 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h @@ -77,6 +77,17 @@ struct pmu_cmdline_args_v5 { u32 dummy; }; +struct pmu_cmdline_args_v6 { + u32 cpu_freq_hz; + struct flcn_mem_desc_v0 trace_buf; + u8 secure_mode; + u8 raise_priv_sec; + struct flcn_mem_desc_v0 gc6_ctx; + struct flcn_mem_desc_v0 gc6_bsod_ctx; + struct flcn_mem_desc_v0 init_data_dma_info; + u32 dummy; +}; + /* GPU ID */ #define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2 #define PMU_SHA1_GID_SIGNATURE_SIZE 4 -- cgit v1.2.2