From 15ec5722be8f483f6d9c1cd0bfd61a7e2bcbfca2 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 25 Apr 2018 03:08:49 -0700 Subject: gpu: nvgpu: add HAL to handle nonstall interrupts Add new HAL gops.mc.isr_nonstall() to handle nonstall interrupts We already handle nonstall interrupts in nvgpu_intr_nonstall() But this API is completely in linux specific code Separate out os-independent code to handle nonstall interrupts in new API mc_gk20a_isr_nonstall() and set it to HAL gops.mc.isr_nonstall() for all existing chips Call this HAL from nvgpu_intr_nonstall() Jira NVGPUT-8 Change-Id: Iec6a56db03158a72a256f7eee8989a0a8a42ae2f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1706589 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/intr.c | 35 +++--------------------- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 39 +++++++++++++++++++++++++++ drivers/gpu/nvgpu/gk20a/mc_gk20a.h | 1 + drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 + drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 + drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 + 11 files changed, 52 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/nvgpu/common/linux/intr.c b/drivers/gpu/nvgpu/common/linux/intr.c index 6b4b2dc9..05dd3f2a 100644 --- a/drivers/gpu/nvgpu/common/linux/intr.c +++ b/drivers/gpu/nvgpu/common/linux/intr.c @@ -69,11 +69,8 @@ irqreturn_t nvgpu_intr_thread_stall(struct gk20a *g) irqreturn_t nvgpu_intr_nonstall(struct gk20a *g) { - u32 mc_intr_1; + u32 non_stall_intr_val; u32 hw_irq_count; - u32 engine_id_idx; - u32 active_engine_id = 0; - u32 engine_enum = ENGINE_INVAL_GK20A; int ops_old, ops_new, ops = 0; struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); @@ -81,37 +78,13 @@ irqreturn_t nvgpu_intr_nonstall(struct gk20a *g) return IRQ_NONE; /* not from gpu when sharing irq with others */ - mc_intr_1 = g->ops.mc.intr_nonstall(g); - if (unlikely(!mc_intr_1)) + non_stall_intr_val = g->ops.mc.intr_nonstall(g); + if (unlikely(!non_stall_intr_val)) return IRQ_NONE; g->ops.mc.intr_nonstall_pause(g); - if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1)) - ops |= gk20a_fifo_nonstall_isr(g); - - for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; - engine_id_idx++) { - struct fifo_engine_info_gk20a *engine_info; - - active_engine_id = g->fifo.active_engines_list[engine_id_idx]; - engine_info = &g->fifo.engine_info[active_engine_id]; - - if (mc_intr_1 & engine_info->intr_mask) { - engine_enum = engine_info->engine_enum; - /* GR Engine */ - if (engine_enum == ENGINE_GR_GK20A) - ops |= gk20a_gr_nonstall_isr(g); - - /* CE Engine */ - if (((engine_enum == ENGINE_GRCE_GK20A) || - (engine_enum == ENGINE_ASYNC_CE_GK20A)) && - g->ops.ce2.isr_nonstall) - ops |= g->ops.ce2.isr_nonstall(g, - engine_info->inst_id, - engine_info->pri_base); - } - } + ops = g->ops.mc.isr_nonstall(g); if (ops) { do { ops_old = atomic_read(&l->nonstall_ops); diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 03cfe285..bf2e0dbb 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -1066,6 +1066,7 @@ struct gpu_ops { u32 (*intr_nonstall)(struct gk20a *g); void (*intr_nonstall_pause)(struct gk20a *g); void (*intr_nonstall_resume)(struct gk20a *g); + int (*isr_nonstall)(struct gk20a *g); void (*enable)(struct gk20a *g, u32 units); void (*disable)(struct gk20a *g, u32 units); void (*reset)(struct gk20a *g, u32 units); diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index e6d81a87..7fed410e 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c @@ -74,6 +74,45 @@ void mc_gk20a_isr_stall(struct gk20a *g) g->ops.bus.isr(g); } +int mc_gk20a_isr_nonstall(struct gk20a *g) +{ + int ops = 0; + u32 mc_intr_1; + u32 engine_id_idx; + u32 active_engine_id = 0; + u32 engine_enum = ENGINE_INVAL_GK20A; + + mc_intr_1 = g->ops.mc.intr_nonstall(g); + + if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1)) + ops |= gk20a_fifo_nonstall_isr(g); + + for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; + engine_id_idx++) { + struct fifo_engine_info_gk20a *engine_info; + + active_engine_id = g->fifo.active_engines_list[engine_id_idx]; + engine_info = &g->fifo.engine_info[active_engine_id]; + + if (mc_intr_1 & engine_info->intr_mask) { + engine_enum = engine_info->engine_enum; + /* GR Engine */ + if (engine_enum == ENGINE_GR_GK20A) + ops |= gk20a_gr_nonstall_isr(g); + + /* CE Engine */ + if (((engine_enum == ENGINE_GRCE_GK20A) || + (engine_enum == ENGINE_ASYNC_CE_GK20A)) && + g->ops.ce2.isr_nonstall) + ops |= g->ops.ce2.isr_nonstall(g, + engine_info->inst_id, + engine_info->pri_base); + } + } + + return ops; +} + void mc_gk20a_intr_enable(struct gk20a *g) { u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h index 870a1d3f..1ce308b8 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h @@ -32,6 +32,7 @@ u32 mc_gk20a_intr_stall(struct gk20a *g); void mc_gk20a_intr_stall_pause(struct gk20a *g); void mc_gk20a_intr_stall_resume(struct gk20a *g); u32 mc_gk20a_intr_nonstall(struct gk20a *g); +int mc_gk20a_isr_nonstall(struct gk20a *g); void mc_gk20a_intr_nonstall_pause(struct gk20a *g); void mc_gk20a_intr_nonstall_resume(struct gk20a *g); void gk20a_mc_enable(struct gk20a *g, u32 units); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 328c1c38..26b3f61a 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -573,6 +573,7 @@ static const struct gpu_ops gm20b_ops = { .intr_nonstall = mc_gk20a_intr_nonstall, .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause, .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume, + .isr_nonstall = mc_gk20a_isr_nonstall, .enable = gk20a_mc_enable, .disable = gk20a_mc_disable, .reset = gk20a_mc_reset, diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 03e3bd07..82cc36aa 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -688,6 +688,7 @@ static const struct gpu_ops gp106_ops = { .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .isr_nonstall = mc_gk20a_isr_nonstall, .enable = gk20a_mc_enable, .disable = gk20a_mc_disable, .reset = gk20a_mc_reset, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index f0c6b410..79eeb25a 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -621,6 +621,7 @@ static const struct gpu_ops gp10b_ops = { .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .isr_nonstall = mc_gk20a_isr_nonstall, .enable = gk20a_mc_enable, .disable = gk20a_mc_disable, .reset = gk20a_mc_reset, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 838dbf87..40f16ed1 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -745,6 +745,7 @@ static const struct gpu_ops gv100_ops = { .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .isr_nonstall = mc_gk20a_isr_nonstall, .enable = gk20a_mc_enable, .disable = gk20a_mc_disable, .reset = gk20a_mc_reset, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 76820d2e..c62dee26 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -684,6 +684,7 @@ static const struct gpu_ops gv11b_ops = { .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .isr_nonstall = mc_gk20a_isr_nonstall, .enable = gk20a_mc_enable, .disable = gk20a_mc_disable, .reset = gk20a_mc_reset, diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 78b8d012..6b593359 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -494,6 +494,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .isr_nonstall = mc_gk20a_isr_nonstall, .enable = gk20a_mc_enable, .disable = gk20a_mc_disable, .reset = gk20a_mc_reset, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index deb5f37f..1b78a4c9 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -541,6 +541,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .intr_nonstall = mc_gp10b_intr_nonstall, .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .isr_nonstall = mc_gk20a_isr_nonstall, .enable = gk20a_mc_enable, .disable = gk20a_mc_disable, .reset = gk20a_mc_reset, -- cgit v1.2.2