From 13bebeced17c206995bd17c573d094968cc0fbca Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 20 Apr 2017 14:08:26 -0700 Subject: gpu: nvgpu: Use retry timer for short delays CPU timer is inaccurate for short delays, and can produce false timeouts. Bug 1903521 Change-Id: I688b5a59489b62cbd59e418d641fd188ecd3b7e0 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1467002 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 18 ++++++++++++------ drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 9 +++++---- drivers/gpu/nvgpu/gm206/bios_gm206.c | 22 +++++++++++++++------- 3 files changed, 32 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f47d3b12..57cd266d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -1596,8 +1596,10 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, if (!g->is_fmodel) { struct nvgpu_timeout timeout; - nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, - NVGPU_TIMER_CPU_TIMER); + nvgpu_timeout_init(g, &timeout, + FE_PWR_MODE_TIMEOUT_MAX / + FE_PWR_MODE_TIMEOUT_DEFAULT, + NVGPU_TIMER_RETRY_TIMER); gk20a_writel(g, gr_fe_pwr_mode_r(), gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_force_on_f()); do { @@ -1639,8 +1641,10 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, if (!g->is_fmodel) { struct nvgpu_timeout timeout; - nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, - NVGPU_TIMER_CPU_TIMER); + nvgpu_timeout_init(g, &timeout, + FE_PWR_MODE_TIMEOUT_MAX / + FE_PWR_MODE_TIMEOUT_DEFAULT, + NVGPU_TIMER_RETRY_TIMER); gk20a_writel(g, gr_fe_pwr_mode_r(), gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_auto_f()); @@ -4998,8 +5002,10 @@ static int gr_gk20a_wait_mem_scrubbing(struct gk20a *g) gk20a_dbg_fn(""); - nvgpu_timeout_init(g, &timeout, CTXSW_MEM_SCRUBBING_TIMEOUT_MAX / 1000, - NVGPU_TIMER_CPU_TIMER); + nvgpu_timeout_init(g, &timeout, + CTXSW_MEM_SCRUBBING_TIMEOUT_MAX / + CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT, + NVGPU_TIMER_RETRY_TIMER); do { fecs_scrubbing = gk20a_readl(g, gr_fecs_dmactl_r()) & (gr_fecs_dmactl_imem_scrubbing_m() | diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 257d9f7c..229d5b4f 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -41,7 +41,7 @@ #define GK20A_PMU_UCODE_IMAGE "gpmu_ucode.bin" -#define PMU_MEM_SCRUBBING_TIMEOUT_MAX 2000 +#define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 #define gk20a_dbg_pmu(fmt, arg...) \ @@ -2315,7 +2315,7 @@ int pmu_idle(struct pmu_gk20a *pmu) struct nvgpu_timeout timeout; u32 idle_stat; - nvgpu_timeout_init(g, &timeout, 2000, NVGPU_TIMER_CPU_TIMER); + nvgpu_timeout_init(g, &timeout, 2000, NVGPU_TIMER_RETRY_TIMER); /* wait for pmu idle */ do { @@ -2418,8 +2418,9 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) g->blcg_enabled); nvgpu_timeout_init(g, &timeout, - PMU_MEM_SCRUBBING_TIMEOUT_MAX / 1000, - NVGPU_TIMER_CPU_TIMER); + PMU_MEM_SCRUBBING_TIMEOUT_MAX / + PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT, + NVGPU_TIMER_RETRY_TIMER); do { u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & (pwr_falcon_dmactl_dmem_scrubbing_m() | diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c index f460a053..6db37d72 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.c +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c @@ -105,8 +105,10 @@ static int gm206_bios_devinit(struct gk20a *g) gk20a_dbg_fn(""); g->ops.pmu.reset(g); - nvgpu_timeout_init(g, &timeout, PMU_BOOT_TIMEOUT_MAX / 1000, - NVGPU_TIMER_CPU_TIMER); + nvgpu_timeout_init(g, &timeout, + PMU_BOOT_TIMEOUT_MAX / + PMU_BOOT_TIMEOUT_DEFAULT, + NVGPU_TIMER_RETRY_TIMER); do { u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & (pwr_falcon_dmactl_dmem_scrubbing_m() | @@ -152,8 +154,10 @@ static int gm206_bios_devinit(struct gk20a *g) gk20a_writel(g, pwr_falcon_cpuctl_r(), pwr_falcon_cpuctl_startcpu_f(1)); - nvgpu_timeout_init(g, &timeout, PMU_BOOT_TIMEOUT_MAX / 1000, - NVGPU_TIMER_CPU_TIMER); + nvgpu_timeout_init(g, &timeout, + PMU_BOOT_TIMEOUT_MAX / + PMU_BOOT_TIMEOUT_DEFAULT, + NVGPU_TIMER_RETRY_TIMER); do { devinit_completed = pwr_falcon_cpuctl_halt_intr_v( gk20a_readl(g, pwr_falcon_cpuctl_r())) && @@ -183,8 +187,10 @@ static int gm206_bios_preos(struct gk20a *g) gk20a_dbg_fn(""); g->ops.pmu.reset(g); - nvgpu_timeout_init(g, &timeout, PMU_BOOT_TIMEOUT_MAX / 1000, - NVGPU_TIMER_CPU_TIMER); + nvgpu_timeout_init(g, &timeout, + PMU_BOOT_TIMEOUT_MAX / + PMU_BOOT_TIMEOUT_DEFAULT, + NVGPU_TIMER_RETRY_TIMER); do { u32 w = gk20a_readl(g, pwr_falcon_dmactl_r()) & (pwr_falcon_dmactl_dmem_scrubbing_m() | @@ -222,7 +228,9 @@ static int gm206_bios_preos(struct gk20a *g) gk20a_writel(g, pwr_falcon_cpuctl_r(), pwr_falcon_cpuctl_startcpu_f(1)); - nvgpu_timeout_init(g, &timeout, PMU_BOOT_TIMEOUT_MAX / 1000, + nvgpu_timeout_init(g, &timeout, + PMU_BOOT_TIMEOUT_MAX / + PMU_BOOT_TIMEOUT_DEFAULT, NVGPU_TIMER_CPU_TIMER); do { val = pwr_falcon_cpuctl_halt_intr_v( -- cgit v1.2.2