From 11009e0e69a497780ddb918fab89da62089510ce Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 20 Jun 2017 15:31:46 -0700 Subject: gpu: nvgpu: gv11b: sm register changes gv11b has multiple SMs and SM register addresses have changed as compared to legacy chips. JIRA GPUT19X-75 Change-Id: I2319f4c78f3efda3430bab1f5ecf1a068e57a1ca Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1506013 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 10 +- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 318 +++++++++++---------- 2 files changed, 170 insertions(+), 158 deletions(-) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 41892746..59865a0f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1658,8 +1658,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f()); - global_mask = gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f() | - gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(); + global_mask = gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f() | + gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(); if (warp_esr != 0 || (global_esr & global_mask) != 0) { *ignore_debugger = true; @@ -1697,13 +1697,13 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, } dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); - if (dbgr_control0 & gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f()) { + if (dbgr_control0 & gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f()) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", gpc, tpc); dbgr_control0 = set_field(dbgr_control0, - gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(), - gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f()); + gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(), + gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f()); gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset, dbgr_control0); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 75a64be5..daa4c08a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -174,6 +174,10 @@ static inline u32 gr_exception_ds_m(void) { return 0x1 << 4; } +static inline u32 gr_exception_sked_m(void) +{ + return 0x1 << 8; +} static inline u32 gr_exception1_r(void) { return 0x00400118; @@ -966,14 +970,82 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void) { return 0x80000000; } -static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) -{ - return 0x00419ea8; -} static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) { return 0x00419eac; } +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) +{ + return 0x0050472c; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) +{ + return 0x00419eb4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) +{ + return 0x00504734; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) +{ + return 0x1 << 6; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) +{ + return 0x100; +} static inline u32 gr_fe_go_idle_timeout_r(void) { return 0x00404154; @@ -2422,6 +2494,22 @@ static inline u32 gr_sked_hww_esr_reset_active_f(void) { return 0x40000000; } +static inline u32 gr_sked_hww_esr_en_r(void) +{ + return 0x00407024; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) +{ + return 0x1 << 25; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) +{ + return 0x2000000; +} static inline u32 gr_cwd_fs_r(void) { return 0x00405b00; @@ -3302,90 +3390,74 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { return 0x10000000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_r(void) +static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) { - return 0x00419f28; + return 0x00419ea8; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) +{ + return 0x00504728; +} +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) { return 0x2; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) { return 0x4; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) { return 0x10; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) { return 0x20; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) { return 0x40; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) { return 0x100; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) { return 0x200; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) { return 0x800; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) { return 0x2000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) { return 0x4000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) { return 0x8000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) { return 0x10000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) { return 0x40000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) { return 0x800000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) +static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) { return 0x400000; } -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_r(void) -{ - return 0x00419f2c; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40; -} static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) { return 0x00419d0c; @@ -3562,10 +3634,22 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) +{ + return 0x1; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) { return 0x00000000; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) +{ + return 0x1 << 31; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; @@ -3574,6 +3658,10 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) +{ + return 0x1 << 3; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) { return 0x8; @@ -3590,17 +3678,37 @@ static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) { return 0x00504708; } +static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) +{ + return 0x0050470c; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) { return 0x00504710; } +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00504714; +} static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) { return 0x00504718; } -static inline u32 gr_gpcs_tpcs_sm0_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) +{ + return 0x0050471c; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_r(void) { - return 0x00419f10; + return 0x00419e90; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) +{ + return 0x00419e94; +} +static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) +{ + return 0x00419e80; } static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) { @@ -3618,46 +3726,6 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) { return 0x00000001; } -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_r(void) -{ - return 0x00419f34; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) -{ - return 0x00504734; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4; -} static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) { return 0x00504730; @@ -3686,6 +3754,18 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) +{ + return 0x0050460c; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) +{ + return (r >> 1) & 0x1; +} static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) { return 0x00504738; @@ -3958,57 +4038,9 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) { return 0x004188ac; } -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_r(void) +static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) { - return 0x00419f04; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(void) -{ - return 0x1 << 3; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000; + return 0x00419e84; } static inline u32 gr_fe_gfxp_wfi_timeout_r(void) { @@ -4666,24 +4698,4 @@ static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) { return (r >> 16) & 0xffff; } -static inline u32 gr_sked_hww_esr_en_r(void) -{ - return 0x00407024; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) -{ - return 0x1 << 25; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) -{ - return 0x2000000; -} -static inline u32 gr_exception_sked_m(void) -{ - return 0x1 << 8; -} #endif -- cgit v1.2.2