From 0e0767672ae7e66d0ec249b8847f36c685fe995e Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Tue, 8 Aug 2017 15:45:33 -0700 Subject: gpu: nvgpu: vgpu: get engines info from RM server - get engines info from constants - remove according HAL from gp10b vgpu Jira VFND-3797 Change-Id: If010e59c358ab0519cb0d8d6211c0bcc20fc3723 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1536179 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 45 +++++++++++++++++--------- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c | 28 ---------------- include/linux/tegra_vgpu.h | 18 +++++++++++ 3 files changed, 48 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 3f03e25a..252b4e43 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c @@ -163,27 +163,42 @@ static int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, static int vgpu_fifo_init_engine_info(struct fifo_gk20a *f) { - struct fifo_engine_info_gk20a *gr_info; - struct fifo_engine_info_gk20a *ce_info; - const u32 gr_sw_id = ENGINE_GR_GK20A; - const u32 ce_sw_id = ENGINE_GRCE_GK20A; + struct vgpu_priv_data *priv = vgpu_get_priv_data(f->g); + struct tegra_vgpu_engines_info *engines = &priv->constants.engines_info; + u32 i; gk20a_dbg_fn(""); - f->num_engines = 2; + if (engines->num_engines > TEGRA_VGPU_MAX_ENGINES) { + nvgpu_err(f->g, "num_engines %d larger than max %d", + engines->num_engines, TEGRA_VGPU_MAX_ENGINES); + return -EINVAL; + } + + f->num_engines = engines->num_engines; + for (i = 0; i < f->num_engines; i++) { + struct fifo_engine_info_gk20a *info = + &f->engine_info[engines->info[i].engine_id]; - gr_info = &f->engine_info[0]; + if (engines->info[i].engine_id >= f->max_engines) { + nvgpu_err(f->g, "engine id %d larger than max %d", + engines->info[i].engine_id, + f->max_engines); + return -EINVAL; + } - /* FIXME: retrieve this from server */ - gr_info->runlist_id = 0; - gr_info->engine_enum = gr_sw_id; - f->active_engines_list[0] = 0; + info->intr_mask = engines->info[i].intr_mask; + info->reset_mask = engines->info[i].reset_mask; + info->runlist_id = engines->info[i].runlist_id; + info->pbdma_id = engines->info[i].pbdma_id; + info->inst_id = engines->info[i].inst_id; + info->pri_base = engines->info[i].pri_base; + info->engine_enum = engines->info[i].engine_enum; + info->fault_id = engines->info[i].fault_id; + f->active_engines_list[i] = engines->info[i].engine_id; + } - ce_info = &f->engine_info[1]; - ce_info->runlist_id = 0; - ce_info->inst_id = 2; - ce_info->engine_enum = ce_sw_id; - f->active_engines_list[1] = 1; + gk20a_dbg_fn("done"); return 0; } diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c index 23d945fb..52e90f33 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c @@ -13,36 +13,8 @@ #include "vgpu_fifo_gp10b.h" -static int vgpu_gp10b_fifo_init_engine_info(struct fifo_gk20a *f) -{ - struct fifo_engine_info_gk20a *gr_info; - struct fifo_engine_info_gk20a *ce_info; - const u32 gr_sw_id = ENGINE_GR_GK20A; - const u32 ce_sw_id = ENGINE_GRCE_GK20A; - - gk20a_dbg_fn(""); - - f->num_engines = 2; - - gr_info = &f->engine_info[0]; - - /* FIXME: retrieve this from server */ - gr_info->runlist_id = 0; - gr_info->engine_enum = gr_sw_id; - f->active_engines_list[0] = 0; - - ce_info = &f->engine_info[1]; - ce_info->runlist_id = 0; - ce_info->inst_id = 0; - ce_info->engine_enum = ce_sw_id; - f->active_engines_list[1] = 1; - - return 0; -} - void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops) { /* syncpoint protection not supported yet */ - gops->fifo.init_engine_info = vgpu_gp10b_fifo_init_engine_info; gops->fifo.resetup_ramfc = NULL; } diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 3f73d357..1c486f5c 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h @@ -422,6 +422,23 @@ struct tegra_vgpu_gpu_clk_rate_params { u32 rate; /* in kHz */ }; +/* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ +#define TEGRA_VGPU_MAX_ENGINES 4 +struct tegra_vgpu_engines_info { + u32 num_engines; + struct engineinfo { + u32 engine_id; + u32 intr_mask; + u32 reset_mask; + u32 runlist_id; + u32 pbdma_id; + u32 inst_id; + u32 pri_base; + u32 engine_enum; + u32 fault_id; + } info[TEGRA_VGPU_MAX_ENGINES]; +}; + #define TEGRA_VGPU_MAX_GPC_COUNT 16 #define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16 @@ -459,6 +476,7 @@ struct tegra_vgpu_constants_params { u32 default_timeslice_us; u32 preempt_ctx_size; u32 channel_base; + struct tegra_vgpu_engines_info engines_info; }; struct tegra_vgpu_channel_cyclestats_snapshot_params { -- cgit v1.2.2