From 0dd02e634ddc2f3e048b39048d2299d24401fdf8 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 13 Jul 2017 00:40:31 +0100 Subject: gpu: nvgpu: Add su_rd_coalesce register field Add the surface rd coalesce field in the register that controls read coalescing. Bug 200314091 Change-Id: I185ad7e6ef64ecae9369e26d22a7381611ddc693 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1518305 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h | 8 ++++++++ drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h index b6f0d047..fa6e8c5f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h @@ -2266,6 +2266,14 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) { return 0x1 << 2; } +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) +{ + return 0x1 << 4; +} static inline u32 gr_gpccs_falcon_addr_r(void) { return 0x0041a0ac; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h index a71f2c2b..fe902cbb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h @@ -2546,6 +2546,14 @@ static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) { return 0x1 << 2; } +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) +{ + return 0x1 << 4; +} static inline u32 gr_gpccs_falcon_addr_r(void) { return 0x0041a0ac; -- cgit v1.2.2