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* gpu: nvgpu: flags to query specific clk domainsThomas Fleury2016-12-07
| | | | | | | | | | | | | | | | | | Added NVGPU_GPU_CLK_FLAG_SPECIFIC_DOMAINS to indicate that a request (get clock info/range) applies only to domains specified in clock entries. If flag is not set, request returns all clock domains. Jira DNVGPU-125 Change-Id: I11bffbdf491ebffa7f47bd327037b0b8cfcbde31 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1227998 (cherry picked from commit 7613dd30e120a82d342da402b4e0b070512dddad) Reviewed-on: http://git-master/r/1243108 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ioctls for clock controlsThomas Fleury2016-12-07
| | | | | | | | | | | | | | | | | | Add ioctls for clock range and VF points query. Add ioctls to set target mhz, and get actual mhz. Jira DNVGPU-125 Change-Id: I7639789bb15eabd8c98adc468201dba3a6e19ade Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1223473 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> (cherry picked from commit 5e635ae34221c99a739321bcfc1418db56c1051d) Reviewed-on: http://git-master/r/1243107 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: API to access fb memoryDeepak Nibade2016-11-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add IOCTL API NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY to read/write fb/vidmem memory Interface will accept dmabuf_fd of the buffer in vidmem, offset into the buffer to access, temporary buffer to copy data across API, size of read/write and command indicating either read or write operation API will first parse all the inputs, and then call gk20a_vidbuf_access_memory() to complete fb access gk20a_vidbuf_access_memory() will then just use gk20a_mem_rd_n() or gk20a_mem_wr_n() depending on the command issued Bug 1804714 Jira DNVGPU-192 Change-Id: Iba3c42410abe12c2884d3b603fa33d27782e4c56 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1255556 (cherry picked from commit 2c49a8a79d93fc526adbf6f808484fa9a3fa2498) Reviewed-on: http://git-master/r/1260471 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Fix signed comparison bugsTerje Bergstrom2016-11-17
| | | | | | | | | | | | Fix small problems related to signed versus unsigned comparisons throughout the driver. Bump up the warning level to prevent such problems from occuring in future. Change-Id: I8ff5efb419f664e8a2aedadd6515ae4d18502ae0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1252068 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "Revert "gpu: nvgpu: vgpu: alloc hwpm ctxt buf on client""Peter Daifuku2016-11-14
| | | | | | | | | | | | | | | | | This reverts commit 5f1c2bc27fb9dd66ed046b0590afc365be5011bf. Added back now that matching RM server has been updated: In hypervisor mode, all GPU VA allocations must be done by client; fix this for the allocation of the hwpm ctxt buffer Bug 200231611 Change-Id: Ie5ce2c2562401b1f00821231d37608e3fc30d4a4 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1252138 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove IOCTL FREE_OBJ_CTXTerje Bergstrom2016-11-11
| | | | | | | | | | | | | We have never used the IOCTL FREE_OBJ_CTX. Using it leads to context being only partially available, and can lead to use-after-free. Bug 1834225 Change-Id: I9d2b632ab79760f8186d02e0f35861b3a6aae649 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1250004 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gk20a: Fix FBP/L2 masks, add GET_FBP_L2_MASKSSami Kiminki2016-11-11
| | | | | | | | | | | | | | | | | | | | Fix FBP and ROP_L2 enable masks for Maxwell+. Deprecate rop_l2_en_mask in GPU characteristics by adding _DEPRECATED postfix. The array is too small to hold ROP_L2 enable masks for desktop GPUs. Add NVGPU_GPU_IOCTL_GET_FBP_L2_MASKS to expose the ROP_L2 masks for userspace. Bug 200136909 Bug 200241845 Change-Id: I5ad5a5c09f3962ebb631b8d6e7a2f9df02f75ac7 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/1245294 (cherry picked from commit 0823b33e59defec341ea7919dae4e5f73a36d256) Reviewed-on: http://git-master/r/1249883 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: vgpu: alloc hwpm ctxt buf on client"Sivaram Nair2016-11-04
| | | | | | | | | | This reverts commit 57821e215756b3df7acc9c0eb5017e39f141d381. Change-Id: Ic4801115064ccbcd1435298a61871921d056b8ea Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/1247825 Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com> Tested-by: Rakesh Babu Bodla <rbodla@nvidia.com>
* gpu: nvgpu: vgpu: alloc hwpm ctxt buf on clientPeter Daifuku2016-11-03
| | | | | | | | | | | | | | | | | | In hypervisor mode, all GPU VA allocations must be done by client; fix this for the allocation of the hwpm ctxt buffer Bug 200231611 Change-Id: I0270b1298308383a969a47d0a859ed53c20594ef Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1240913 (cherry picked from commit 49314d42b13e27dc2f8c1e569a8c3e750173148d) Reviewed-on: http://git-master/r/1245867 (cherry picked from commit d0b10e84d90d0fd61eca8be0f9e879d9cec71d3e) Reviewed-on: http://git-master/r/1246700 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* include: nvgpu: change alloc_gpfifo ioctl #Sachit Kadle2016-10-27
| | | | | | | | | | | | | | | This moves the newly added ioctl, NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX, to the end of the ioctl list. This ensures that nvrm_gpu can correctly determine whether the kernel has this IOCTL. Bug 1795076 Change-Id: Ic42d88142809e71b5d7a4328388338c937252b8b Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1242442 GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: make deferred clean-up conditionalSachit Kadle2016-10-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change makes the invocation of the deferred job clean-up mechanism conditional. For submissions that require job tracking, deferred clean-up is only required if any of the following conditions are met: 1) Channel's deterministic flag is not set 2) Rail-gating is enabled 3) Channel WDT is enabled 4) Buffer refcounting is enabled 5) Dependency on Sync Framework In case deferred clean-up is not needed, we clean-up a single job tracking resource in the submit path. For deterministic channels, we do not allow deferred clean-up to occur and fail any submits that require it. Bug 1795076 Change-Id: I4021dffe8a71aa58f12db6b58518d3f4021f3313 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1220920 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> (cherry picked from commit b09f7589d5ad3c496e7350f1ed583a4fe2db574a) Reviewed-on: http://git-master/r/1223941 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: update channel max_arg_sizeSachit Kadle2016-10-20
| | | | | | | | | | | | | | | Increase channel ioctl max arg size to support ALLOC_GPFIFO_EX ioctl. Bug 1795076 Change-Id: Ifb8e7c564333f4c6dd244d7d85acfee4e029b41b Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1218048 (cherry picked from commit 75c52887a0350433e7334681009f5c7cac3fb6a9) Reviewed-on: http://git-master/r/1223936 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add deterministic submit flagSachit Kadle2016-10-20
| | | | | | | | | | | | | | | | | | | | | This change adds a new ioctl flag, NVGPU_SUBMIT_GPFIFO_FLAGS_DETERMINISTIC, which indicates that a gpfifo submission must exhibit deterministic behavior within the kernel. For submissions that require job tracking and also set this flag, we require the channel to have previously pre-allocated job tracking resources. Bug 1795076 Change-Id: I0496a2513c6c683fcda161b32db9e7ee6712d45c Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1210527 (cherry picked from commit 0a36a0ce3a6cbe398931993e742fc928f7b2c0aa) Reviewed-on: http://git-master/r/1223935 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for pre-allocated resourcesSachit Kadle2016-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | Add support for pre-allocation of job tracking resources w/ new (extended) ioctl. Goal is to avoid dynamic memory allocation in the submit path. This patch does the following: 1) Intoduces a new ioctl, NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX, which enables pre-allocation of tracking resources per job: a) 2x priv_cmd_entry b) 2x gk20a_fence 2) Implements circular ring buffer for job tracking to avoid lock contention between producer (submitter) and consumer (clean-up) Bug 1795076 Change-Id: I6b52e5c575871107ff380f9a5790f440a6969347 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1203300 (cherry picked from commit 9fd270c22b860935dffe244753dabd87454bef39) Reviewed-on: http://git-master/r/1223934 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add ioctl for querying memory stateKonsta Holtta2016-10-14
| | | | | | | | | | | | | | | | | | | Add NVGPU_GPU_IOCTL_GET_MEMORY_STATE to read the amount of free device-local video memory, if applicable. Some reserved fields are added to support different types of queries in the future (e.g. context-local free amount). Bug 1787771 Bug 200233138 Change-Id: Id5ffd02ad4d6ed3a6dc196541938573c27b340ac Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1223762 (cherry picked from commit 96221d96c7972c6387944603e974f7639d6dbe70) Reviewed-on: http://git-master/r/1235980 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Retrieve VBIOS version from dGPUTerje Bergstrom2016-10-12
| | | | | | | | | | | | | | Retrieve VBIOS version from biosdata VBIOS structure. Bug 1811880 Change-Id: I24f4114ce7c8925bde4b195888da62454707b8e6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1218062 (cherry picked from commit fb23e9522bc268fcf0d71cc7f2ae9a0bc6cfda23) Reviewed-on: http://git-master/r/1234089 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Post GR_SEMAPHORE_WRITE_AWAKEN eventNikhil Mahale2016-09-22
| | | | | | | | | | | | | | Post GR_SEMAPHORE_WRITE_AWAKEN event on semaphore write awken interrupt for channel. BUG 200223530 Change-Id: I19eb61578d1c562be84e20ecaff9fb3bc9ace516 Signed-off-by: Nikhil Mahale <nmahale@nvidia.com> Reviewed-on: http://git-master/r/1193726 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Expose PCI device id infoSami Kiminki2016-09-21
| | | | | | | | | | | | | | Expose PCI device id info for PCI devices. Bug 1643487 Change-Id: Ib0e3295b33c2343d99553a5c48e3f67d419d207b Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/1214946 (cherry picked from commit a6e23a315a094f1df1f7db8e4307a10d06f28411) Reviewed-on: http://git-master/r/1216336 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move gpfifo submit wait to userspaceAingara Paramakuru2016-09-15
| | | | | | | | | | | | | | | | | Instead of blocking for gpfifo space in the nvgpu driver, return -EAGAIN and allow userspace to decide the blocking policy. Bug 1795076 Change-Id: Ie091caa92aad3f68bc01a3456ad948e76883bc50 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/1202591 (cherry picked from commit 8056f422c6a34a4239fc4993c40c2e517c932714) Reviewed-on: http://git-master/r/1203800 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: cyclestat snapshot supportPeter Daifuku2016-09-08
| | | | | | | | | | | | | Add support for cyclestats snapshots in the virtual case Bug 1700143 JIRA EVLR-278 Change-Id: I376a8804d57324f43eb16452d857a3b7bb0ecc90 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1211547 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: get constants of gpc_tpc_count/mask arraysRichard Zhao2016-08-15
| | | | | | | | | | | | It'll cover multi-gpcs. JIRA VFND-2103 Change-Id: Ie82bdaad360294696c5a679d694f6f0e2364ca2e Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1194631 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add getting gr constantsRichard Zhao2016-08-15
| | | | | | | | | | | | | | | | | | | | move below attributes to constants: TEGRA_VGPU_ATTRIB_GPC_COUNT TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT TEGRA_VGPU_ATTRIB_NUM_FBPS TEGRA_VGPU_ATTRIB_FBP_EN_MASK TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC JIRA VFND-2103 Change-Id: Ic2ac14a0f8a1cf19a996bcef20bef0003d3b9a3b Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1194630 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add getting sm version constantsRichard Zhao2016-08-15
| | | | | | | | | | | | | | move below attributes to constants: TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH JIRA VFND-2103 Change-Id: I5d6aa8f4a49e65307989ef02d223c3ee31fcdeed Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1190481 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add getting ltc constantsRichard Zhao2016-08-15
| | | | | | | | | | | | | | | | | | | move below attributes to constants: TEGRA_VGPU_ATTRIB_COMPTAG_LINES TEGRA_VGPU_ATTRIB_L2_SIZE TEGRA_VGPU_ATTRIB_CACHELINE_SIZE TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE TEGRA_VGPU_ATTRIB_SLICES_PER_LTC TEGRA_VGPU_ATTRIB_LTC_COUNT JIRA VFND-2103 Change-Id: Iecf9717ee553a16ffe8de445be5bfe5a99c3a094 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1190480 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add getting constants golden img size and zcull ctx sizeRichard Zhao2016-08-15
| | | | | | | | | | JIRA VFND-2103 Change-Id: I180324b36a1c6b39300b92a2cff6448d7665679b Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1190479 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add cmd to get RM server constantsRichard Zhao2016-08-15
| | | | | | | | | | | | | | | | Moving getting constant attributes into one cmd which will be called only once. This patch adds basic infrastructure and gpu arch info, max_freq and num_channels support. JIRA VFND-2103 Change-Id: I100599b49f29c99966f9e90ea381b1f3c09177a3 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1189832 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: remove deprecated gr_ctx alloc/free cmdRichard Zhao2016-07-26
| | | | | | | | | | JIRA VFND-2080 Change-Id: Ied4c1af9377a6d18c20814190b679ad98450513e Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1183738 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: add vidmem allocation ioctlKonsta Holtta2016-07-21
| | | | | | | | | | | | | | | | | | Add NVGPU_GPU_IOCTL_ALLOC_VIDMEM to the ctrl fd for letting userspace allocate on-board GPU memory (aka vidmem). The allocations are returned as dmabuf fds. Also, report the amount of local video memory in the gpu characteristics. Jira DNVGPU-19 Jira DNVGPU-38 Change-Id: I28e361d31bb630b96d06bb1c86d022d91c7592bc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1181152 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add ref counting for GPU sched ctrlThomas Fleury2016-07-19
| | | | | | | | | | | | | | | Jira VFND-1968 Change-Id: Id84c5732e312e44db3d412df5c21e429227dd7fa Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1171286 (cherry picked from commit 13a3a4355914635ed175708affef17dc8ef0b133) Reviewed-on: http://git-master/r/1177824 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add sched control APIThomas Fleury2016-07-19
| | | | | | | | | | | | | | | | | | | | | | | Added a dedicated device node to allow an app manager to control TSG scheduling parameters: - Get list of TSGs - Get list of recent TSGs - Get list of TSGs per pid - Get TSG current scheduling parameters - Set TSG timeslice - Set TSG runlist interleave Jira VFND-1586 Change-Id: I014c9d1534bce0eaea6c25ad114cf0cff317af79 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1160384 (cherry picked from commit 75ca739517cc7f7f76714b5f6a1a57c39b8cb38e) Reviewed-on: http://git-master/r/1167021 Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: remove BIT macros from header fileThomas Fleury2016-07-18
| | | | | | | | | | | | | | Jira EVLR-472 Change-Id: Ica90888a1dfd17ae1ea2c2a359805288cd648b76 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1172095 (cherry picked from commit 43d639f89154b8d7639da1c13546f0d2d1b4e101) Reviewed-on: http://git-master/r/1177822 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add pm qos supportRichard Zhao2016-07-14
| | | | | | | | | | | | | | | | | Send cmd to RM server to change clk rate when PM_QOS_GPU_FREQ_BOUNDS max changes. Bug 200206160 Change-Id: I7f19e5f711426517baf8e7f934bf41972012644b Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1172792 (cherry picked from commit 973c258fd85449c3862df2498362e358fd3682c9) Reviewed-on: http://git-master/r/1180892 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: vgpu: dbg_set_powergate supportPeter Daifuku2016-07-06
| | | | | | | | | | | | | | | | | | Add support for dbg_set_powergate when virtualized Jira VFND-1905 Change-Id: I0d81c8863b3eda4ae4fee42e5a95d2fc9d78b174 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1162048 (cherry picked from commit 0dfc55f390a10e21ae13e14dd2f16e89a3bddfa7) Reviewed-on: http://git-master/r/1167182 (cherry picked from commit 4e34a1844558d93da5ad208532ec28aeda228f95) Reviewed-on: http://git-master/r/1174701 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: explicitly set values for big enumsRichard Zhao2016-06-22
| | | | | | | | | | | | | | | It helps when a few people add ivc cmds at same time. It can also decouple the changes when integrating to other branches. JIRA VFND-1903 Change-Id: I1d9b6cc0443b230dd7da4a0c1b445af2acb0487c Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1162741 (cherry picked from commit b40c06fd0ec92cba932497892a9242b702b5d3d7) Reviewed-on: http://git-master/r/1167286 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add read ptimer supportRichard Zhao2016-06-16
| | | | | | | | | | | | | Bug 1395833 Change-Id: Id0d427b6a1ddaecfeec33c61a6161679cf596c92 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1159588 (cherry picked from commit d33aa89420990626fb377c56ed5517a00f717c2a) Reviewed-on: http://git-master/r/1158897 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add uapi support for non-graphics enginesLakshmanan M2016-06-13
| | | | | | | | | | | | | | | | | | | Extend the existing NVGPU_GPU_IOCTL_OPEN_CHANNEL interface to allow opening channels for other than the primary (i.e., the graphics) runlists. This is required to push work to dGPU engines that have their own runlists, such as the asynchronous copy engines and the multimedia engines. Minor change - Added active_engines_list allocation and assignment for fifo_vgpu back end. JIRA DNVGPU-25 Change-Id: I3ed377e2c9a2b4dd72e8256463510a62c64e7a8f Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1161541 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add uapi support for NVGPU_GPU_IOCTL_GET_ENGINE_INFOLakshmanan M2016-06-10
| | | | | | | | | | | | | | | | Implement NVGPU_GPU_IOCTL_GET_ENGINE_INFO for retrieving the list of supported engines and their corresponding run list id:s. JIRA DNVGPU-25 Change-Id: I8703388660190f7dcb509c0676f283ca4b820b6f Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1160939 Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add general event supportRichard Zhao2016-06-09
| | | | | | | | | | | | | | | | Events like bpt int/pause will help cuda work properly. Bug 200173403 VFND-1568 Change-Id: I29e534969028bf08aedd81c99f5a536779f431d1 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1159621 (cherry picked from commit a266e53c514639e15ed166e2c8ce5a55efc48eda) Reviewed-on: http://git-master/r/1152154 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add channel enable supportRichard Zhao2016-06-09
| | | | | | | | | | | | | | Bug 200173403 VFND-1568 Change-Id: I3636a77bbbbd719e961dce5ca7ca7bdd5aa33881 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1159620 (cherry picked from commit b22fb6518da15a09c3e298213af5e60b8e6907a2) Reviewed-on: http://git-master/r/1155403 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add channel force resetSachit Kadle2016-06-09
| | | | | | | | | | | | | | | | Add forced channel reset support for vgpu Bug 200187507 JIRA EVLR-337 Change-Id: I48e3e2b430f3a4ae94244225232902a8c037cb07 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1154781 (cherry picked from commit abd6688801fe76c822d6f67f554c18705d9f23d6) Reviewed-on: http://git-master/r/1161259 GVS: Gerrit_Virtual_Submit Tested-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add support for max_freqPeter Daifuku2016-06-06
| | | | | | | | | | | | | | | | | | Add vgpu support for max_freq characteristic Bug 200182714 JIRASW VFND-1570 Change-Id: Ibeddfbba1bf0529d6f576cefcb82978dbae315d1 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1149216 (cherry picked from commit 8e8b5979e87268401d5b0fc658a73589710a2e09) Reviewed-on: http://git-master/r/1155416 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use correct config for t19xSeshendra Gadagottu2016-06-03
| | | | | | | | | | | | | | | Use TEGRA_19x_GPU config instead of ARCH_TEGRA_19x_SOC for t19x functionality. This config will defined only when gpu repository for t19x is available. Bug 1757988 Change-Id: I53421f31cbed49a2fb24085c150599c78b8158c0 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1158183 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: vgpu: add tsg set interleave supportRichard Zhao2016-05-31
| | | | | | | | | | | | | | | | added a new cmd to support setting tsg interleave level. Bug 1702773 VFND-1492 Change-Id: Idd9b9c59180b156293ddfc4e2b879d0ea6908388 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1145024 (cherry picked from commit 0929ff1089fbc331b07e17073a46fda4086ae785) Reviewed-on: http://git-master/r/1150706 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add tsg set timeslice supportRichard Zhao2016-05-31
| | | | | | | | | | | | | | Bug 1702773 JIRA VFND-1496 Change-Id: Ice570df78d974fa59f2a932caf0e6249b13493a1 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144929 (cherry picked from commit 8b6ec996f3773e497a040a8fe4148e01e8dc35fa) Reviewed-on: http://git-master/r/1150705 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add tsg support for vgpuRichard Zhao2016-05-31
| | | | | | | | | | | | | | | | | | - make tsg_gk20a.c call HAL for enable/disable channels - add preempt_tsg HAL callbacks - add tsg bind/unbind channel HAL callbacks - add according tsg callbacks for vgpu Bug 1702773 JIRA VFND-1003 Change-Id: I2cba74b3ebd3920ef09219a168e6433d9574dbe8 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144932 (cherry picked from commit c3787de7d38651d46969348f5acae2ba86b31ec7) Reviewed-on: http://git-master/r/1126942 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: manage gr_ctx as independent resourceRichard Zhao2016-05-31
| | | | | | | | | | | | | | | gr_ctx will managed as independent resource in RM server and vgpu can get a gr_ctx handle. Bug 1702773 Change-Id: I87251af61711f0d7997ce90df8a3de196a9b481a Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144931 (cherry picked from commit 2efbd143adaf60570121f1c212dc6b6f3d5a1661) Reviewed-on: http://git-master/r/1150704 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add notifier for pbcrc mismatchDeepak Nibade2016-05-31
| | | | | | | | | | | | | | | | | | Add below notifier for pbcrc mismatch NVGPU_CHANNEL_PBDMA_PUSHBUFFER_CRC_MISMATCH And use this notifier value when we have pbdma pbcrc interrupt pending Bug 200179981 Change-Id: I289351e990afb0a4e002902881b99023530f6443 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1156210 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add support for gm204 and gm206Terje Bergstrom2016-05-23
| | | | | | | | | | | Add support for chips gm204 and gm206. Adds also support for reading VBIOS and booting devinit and pre-os images on PMU. Change-Id: I4824b44245611e5379ace62793cc37158048f432 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120467 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: fix engine reset in FECS traceThomas Fleury2016-05-21
| | | | | | | | | | | | | | | | | | | In virtualization case, VM server is the only one allowed to write to ctxsw ring buffer. It will also generate an event in case of engine reset. Only generate a tracepoint on Guest OS side. EVLR-314 Change-Id: I2cb09780a9b41237fe196ef1f3515923f36a24a4 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1130743 (cherry picked from commit 4bbf9538e2a3375eb86b2feea6c605c3eec2ca40) Reviewed-on: http://git-master/r/1133614 (cherry picked from commit 2076d944db41b37143c27795b3cffd88e99e0b00) Reviewed-on: http://git-master/r/1150046 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add ctxsw channel reset eventThomas Fleury2016-05-21
| | | | | | | | | | | | | | | | | | Generate a ctxsw channel reset when engine needs to be reset. This event is generated by the driver, while other events are generated by FECS. JIRA ELVR-314 Change-Id: I7791cf3e538782464c37c442c871acb177484566 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1129029 (cherry picked from commit 114038a1a5d9e8941bc53f3e95115b01dd1f8c6e) Reviewed-on: http://git-master/r/1134379 (cherry picked from commit 15fa2a7b48a0937dfd449ca0c4ed5ad3a863d6bf) Reviewed-on: http://git-master/r/1123916 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 02:13:15 -0500