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* gpu: nvgpu: Don't use -lpthread for QNXAlex Waterman2018-05-24
| | | | | | | | | | | | | | | | | The QNX compiler seems to automatically link against this library and as such the extra -lpthread is not necessary. Instead it causes a link failure since the pthread library is not present. JIRA NVGPU-525 Change-Id: Id5a6fcdffb067ed961665a3ee44a9d44301b725b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722157 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove __uXX typedefsAlex Waterman2018-05-24
| | | | | | | | | | | | | | | | | Integrity already typedefs these and complains if you override them even with the same underlying type. Since we only use these in the regops_gk20a.h header file (outside of the Linux specific code, that is) this patch just changes the __uXX to uXX. With that we can delete the now unnecessary __uXX defs. JIRA NVGPU-525 Change-Id: I01dd2723b68db2170449342f73c711ee5a589adb Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721186 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add posix condition in sim.hAlex Waterman2018-05-24
| | | | | | | | | | | | | | | Without this the default fall back includes are the rmos headers which are obviously not present for the POSUX build. Change-Id: Iaf7d459e09c62dd57c5b33e21934e40f5780840a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1727427 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use proper include path for clockgating headerAlex Waterman2018-05-24
| | | | | | | | | | | | | | | | | | Instead of referencing the header from $NVGPU/drivers/gpu/nvgpu/common reference it from $NVGPU/drivers/gpu/nvgpu. This makes the POSIX compilation happy since we don't do a -Idrivers/gpu/nvgpu/common. Not sure exactly why the regular kernbel build does this but it probably should not. Change-Id: I00aee373b651e3b7710669fa04c5b75fc1c814d9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1727426 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix oob access in submit profiling dumpKonsta Holtta2018-05-24
| | | | | | | | | | | | | | | | The number of samples has to be at least the number of percentile ranges (here 20) for the reporting to work as expected and also to not cause negative indices in reading the sorted profile data. If there are not enough samples, just report all zeroes. Change-Id: Ie893859d95074f5ceabf6abe873941873668861d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721892 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to enable/disable hub interruptsDeepak Nibade2018-05-24
| | | | | | | | | | | | | | | | | | Add below two new HALs gops.fb.enable_hub_intr() to enable hub interrupts gops.fb.disable_hub_intr() to disable hub interrupts Set existing APIs gv11b_fb_enable/disable_hub_intr() to these HALs Call the HALs everywhere instead of calling the APIs directly Jira NVGPUT-44 Change-Id: Id299c6d228733ed365a71be6b180186776cc1306 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725977 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: export hub intr handling APIsDeepak Nibade2018-05-24
| | | | | | | | | | | | | | | | | | | | | | | | Export below APIs in fb_gv11b.h gv11b_fb_handle_dropped_mmu_fault() gv11b_fb_handle_other_fault_notify() gv11b_fb_handle_mmu_nonreplay_replay_fault() gv11b_fb_handle_nonreplay_fault_overflow() gv11b_fb_handle_replay_fault_overflow() gv11b_handle_l2tlb_ecc_isr() gv11b_handle_hubtlb_ecc_isr() gv11b_handle_fillunit_ecc_isr() Jira NVGPUT-44 Change-Id: Ib50e3f3c2f698d486ffe718ebf4a651ccfe8cd93 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725976 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Regenerated the gating_reglist.c files for various chips after fixing the script for MISRA C-2012 violations Rule 15.5: Multiple points of exit detected Rule 15.6: "if" body without compound statement Rule 10.3: Implicit conversions of 64bit to 32bit int Rule 7.2: Const must be declared with "U" Rule 5.7: Tags with name xxx already declared Add preprocessor conditional gaurds in gating_reglist header files JIRA NVGPU-671 JIRA NVGPU-656 JIRA NVGPU-688 JIRA NVGPU-686 JIRA NVGPU-644 Change-Id: Ie5a688cb8c39f072d2a15d86fb0ee0f2039a2cf1 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724444 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Delete unused static variableAlex Waterman2018-05-24
| | | | | | | | | | | | | | | | This variable is never used. So remove it. JIRA NVGPU-525 Change-Id: I7ace77ffe1c2da58d8d9cee3bbbcf8361886bddf Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724094 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cast unsigned arith to signed for abs()Alex Waterman2018-05-24
| | | | | | | | | | | | | | | | | | | | | | | | | Before passing in an unsigned value to abs() cast the result of the subtraction to signed. In Linux this happens automatically but on non-Linux platforms abs() does not necessarily do this. clang flags this case as a pointless operation: abs(x) obviously must equal x for any unsigned x. This change should hopefully preserve the Linux behavior but avoid the compiler warning from clang. JIRA NVGPU-525 Change-Id: I71320964c0922f1e4890c8b25d801f17e54ed3c0 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724093 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove broken force_pramin featureKonsta Holtta2018-05-24
| | | | | | | | | | | | | | The forced PRAMIN reads and writes for sysmem buffers haven't worked in a while since the PRAMIN access code was refactored to work with vidmem-only sgt allocs. This feature was only ever meant for testing and debugging PRAMIN access and early dGPU support, but that is stable enough now so just delete the broken feature instead of fixing it. Change-Id: Ib31dae4550f3b6fea3c426a2e4ad126864bf85d2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1723725 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_current_time_ns in submit profilingKonsta Holtta2018-05-24
| | | | | | | | | | | | | Replace Linux-specific and dubious sched_clock() with common nvgpu_current_time_ns(). sched_clock() used also nanoseconds. Jira NVGPU-708 Change-Id: I70f992fe42cc9c3ffed374fdebd582867475e84f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1723202 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add nvgpu_current_time_ns()Konsta Holtta2018-05-24
| | | | | | | | | | | | | | | | | | | | Add an abstraction over a monotonic system clock in nanosecond units. Use ktime_get() for the Linux implementation, similarly to nvgpu_current_time_ms(). Jira NVGPU-708 Change-Id: I3165c20abf2652f1a1fa04e66c04cd34a8fe6dcc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1723201 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: populate gpu rev based on soc checkseshendra Gadagottu2018-05-24
| | | | | | | | | | | | | | | | | | Populate gpu rev as 0xa2 for gv11b with t194 A02 soc. Bug 2053668 Change-Id: I22a2bc7026162e34e9a605dfda3d83fa989b5248 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1713096 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Wei Sun <wsun@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: chip revision check for invalidatesseshendra Gadagottu2018-05-24
| | | | | | | | | | | | | | | Only for T194 A01 version following invalidates are disabled: -CBM alpha and beta invalidations for L2 -SCC pagepool invalidates -SWDX spill buffer invalidates Bug 2053668 Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680500 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu types.h in clock gating sourceSourab Gupta2018-05-22
| | | | | | | | | | | | | | | | Use the nvgpu/types.h instead of linux/types.h in the clock gating sources Jira VQRM-3700 Change-Id: Ib399cc4367c77f0d08454aa7639bb619367f673b Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726782 Reviewed-by: Shashank Singh <shashsingh@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add GPU Fmax@Vmin access through BPMPAlex Frid2018-05-22
| | | | | | | | | | | | | | On Tegra platforms that have clock management under BPMP, and do not support Tegra DVFS, GPU driver cannot access Fmax@Vmin (get interface always returns "0"). Added such access through BPMP DVFS shim driver. Bug 2045903 Change-Id: I0222f2e2917cda15d18ea3296dd1fe53b2ea6b45 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722431 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: Added QNX specific include in sim.hAntony Clince Alex2018-05-21
| | | | | | | | | | | | | | | | | | | | Added QNX specific include in the common sim.h Forward declared "platform_device". JIRA VQRM-3836 Change-Id: I6e965ccc41df2445b36111d88e9cebf9866dd877 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725686 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-21
| | | | | | | | | | | | | | | | As part of the MISRA fixes, moving all the gating_reglist files to common/clock_gating dir, the new directory structure suggested to follow. Removed unused gating_reglist files for gk20a JIRA NVGPU-646 Change-Id: I388855befcf991ee68eeffed10fe9ac456210649 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722330 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: init gr->ch_tlb_lockRichard Zhao2018-05-21
| | | | | | | | | | | | | | | | | | The bug was exposed when enable CONFIG_DEBUG_SPINLOCK. Jira VFND-4943 Change-Id: I01720f93fe6de9b85987d490df852c8d1c8fb1c2 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1703656 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: call nvgpu_init_ltc_supportRichard Zhao2018-05-20
| | | | | | | | | | | | | | | vgpu needs to call nvgpu_init_ltc_support to floor sweep and set ltc_count. And set gops.ltc.set_enabled to null as guest is not allowed to change ltc settings. Jira VQRM-2345 Change-Id: I83517d631aa947db4a0a4c312f0cecda9ba03973 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1703626 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: do not init idle filtersSeema Khowala2018-05-18
| | | | | | | | | | | | | | | | | | | | | gv100 cannot use idle filter values defined for gp106 since values are different. Also gv100 cannot use gv11b idle filter values since prod values are different between gv100 and gv11b. Finally since PROD values match with POR INIT values, there is no need to init idle filters for gv100. Bug 2115080 Change-Id: I9e7cfbde364d993ae04d80af14650739f32345cc Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724060 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: release runlist_lock before issuing recoverySeema Khowala2018-05-18
| | | | | | | | | | | | | Release runlist_lock before issuing runlist update timeout recovery. Bug 2115080 Change-Id: I22cd0dd8ab6828412fcc98f587e4a5cdce907651 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722308 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add timeouts_disabled_refcount for enabling timeoutSeema Khowala2018-05-18
| | | | | | | | | | | | | | | | -timeouts will be enabled only when timeouts_disabled_refcount will reach 0 -timeouts_enabled debugfs will change from u32 type to file type to avoid race enabling/disabling timeout from debugfs and ioctl -unify setting timeouts_enabled from debugfs and ioctl Bug 1982434 Change-Id: I54bab778f1ae533872146dfb8d80deafd2a685c7 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1588690 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | | | Code related to MC module is updated for handling MISRA violations Rule 10.1: Operands shalln't be an inappropriate essential type. Rule 10.3: Value of expression shalln't be assigned to an object with a narrow essential type. Rule 10.4: Both operands in an operator shall have the same essential type. Rule 14.4: Controlling if statement shall have essentially Boolean type. Rule 15.6: Enclose if() sequences with braces. JIRA NVGPU-646 JIRA NVGPU-659 JIRA NVGPU-671 Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1720926 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: drop force_need_sync_fence in submit pathKonsta Holtta2018-05-18
| | | | | | | | | | | | | | | | For CDE work a sync fence is always requested, but kernel does not need it and submit flags from userspace will be passed to the submit function in cde path so a sync fence will get created if necessary. To reduce some complexity, remove the explicit boolean in favor of just NVGPU_SUBMIT_FLAGS_SYNC_FENCE. Jira NVGPU-705 Change-Id: I8aac85288513ed7cc640acd021d892cee86f41d8 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1721785 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs for devinit and preos bios operationsDeepak Nibade2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | Add below new HALs for bios operations gops.bios.devinit() gops.bios.preos() gops.bios.verify_devinit() Export existing APIs gp106_bios_devinit() and gp106_bios_preos() and set them to above HALs on gp106 and gv100 And call new HALs from gp106_bios_init() if supported instead of directly calling APIs Jira NVGPUT-48 Change-Id: Ic89f1c86cf6e3e0785b3663fe733b201d6f2f773 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1708382 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle clk arb event posting in OS specific codeSourab Gupta2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mechanism of posting events to userspace is OS specific. In linux this works through poll fd, wherein we can make use of nvgpu_cond variables to poll and trigger the corresponding wait_queue. The post event functionality on QNX doesn't work on poll though. It uses iofunc_notify_trigger to post the events to the calling process. As such QNX can't work with nvgpu_cond's. To overcome this issue, it is proposed to create OS specific interface function for posting clk arb events. Linux can call nvgpu_cond based implementation, which makes sense since these are already initialized and poll'ed in Linux specific code only. QNX can implement this interface to call iofunc_notify_* functions, as per its need. Jira VQRM-3741 Change-Id: I7d9f71dae2ae7f6a09cd56662003fd1b7e50324c Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709656 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove usage of xchg in clk arb codeSourab Gupta2018-05-18
| | | | | | | | | | | | | | | | | | With the removal of rcu locks and using spinlocks in place, the usage of xchg for atomic pointer swap is unneccesary. A few places already have barriers in place before changing the pointer values, so a simple pointer assignment would do. Jira VQRM-3741 Change-Id: I03296202b273b5175f166ab3e094c0e4de910eb8 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709655 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use os agnostic api for retrieving timestampSourab Gupta2018-05-18
| | | | | | | | | | | | | | | | | currently clk arbiter is using the Linux specific sched_clock() api for retrieving current timestamp. Instead use the OS agnostic nvgpu_hr_timestamp(). Jira VQRM-3741 Change-Id: I315ca16327b30db06c39046af1eb05249d1a97ca Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709654 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add conversion function for clk domainSourab Gupta2018-05-18
| | | | | | | | | | | | | | | Add a conversion function for NVGPU_GPU_CLK_DOMAIN_* defines present in uapi header. This enables movement of related code to the OS agnostic clk_arb.c Jira VQRM-3741 Change-Id: I922d1cfb91d6a5dda644cf418f2f3815d975fcfd Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709653 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add macro for clk arb debug logsSourab Gupta2018-05-18
| | | | | | | | | | | | | | | Introduce a macro for clk arbiter debug logs. Jira VQRM-3741 Change-Id: I9f4ebf5f979e84b6383dc8755eb34c0ffa3d0f43 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709652 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move clk_arb.c to common codeSourab Gupta2018-05-18
| | | | | | | | | | | | | | | | Now that clk_arb.c is free of Linux'isms, move it to the clk/ directory. Jira VQRM-741 Change-Id: I53298c76f834322aa586781cdfd2e6031f4826a1 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709651 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update gv100 nvlink TLC buffer configTejal Kudav2018-05-18
| | | | | | | | | | | | | | | | | | TLC buffer sizes and credit init values do not match with the values recommended by IAS for dGPU-Xavier configuration. These buffer configuration values affect the latency over link. JIRA NVLINK-158 Change-Id: I7822747cb0ae5a5efdd2d57e2104d0cb30bf9352 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1686601 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLISTDavid Li2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | Add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST ioctl to reschedule runlist, and optionally check host and FECS status to preempt pending load of context not belonging to the calling channel on GR engine during context switch. This should be called immediately after a submit to decrease worst case submit to start latency for high interleave channel. There is less than 0.002% chance that the ioctl blocks up to couple miliseconds due to race condition of FECS status changing while being read. For GV11B it will always preempt pending load of unwanted context since there is no chance that ioctl blocks due to race condition. Also fix bug with host reschedule for multiple runlists which needs to write both runlist registers. Bug 1987640 Bug 1924808 Change-Id: I0b7e2f91bd18b0b20928e5a3311b9426b1bf1848 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1549050 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix gp106/clk_gp106.c compile errorsAlex Waterman2018-05-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following compiler errors: /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c: In function 'gp106_init_clk_support': /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:109:3: error: unknown field 'cntr' specified in initializer cc1: warnings being treated as errors /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:109:3: error: missing braces around initializer /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:109:3: error: (near initialization for '(anonymous).<anonymous>') /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:110:3: error: unknown field 'cntr' specified in initializer /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:112:3: error: unknown field 'cntr' specified in initializer /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:115:2: error: initialized field with side-effects overwritten /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:115:2: error: (near initialization for '(anonymous).scale') /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:122:3: error: unknown field 'cntr' specified in initializer /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gp106/clk_gp106.c:122:3: error: missing braces around initializer Not sure why this shows up for the L4T userspace compiler but not in any other compilers. JIRA NVGPU-525 Change-Id: I0609c1d9ad20232053768258103debadd6d9206f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1720924 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Translate as_alloc flagsAlex Waterman2018-05-17
| | | | | | | | | | | | | | | | | | | Translate the as_alloc flags so that the common/as.c code no longer needs to include <uapi/linux/nvgpu.h>. This was an oversight from prior MM unification efforts which was caught by the userspace POSIX build on QNX. JIRA NVGPU-525 Change-Id: I6af6cb9904c2ae9edeb8dbb970846c31b56822bf Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1720918 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update PMU firmware versionDeepak Goyal2018-05-17
| | | | | | | | | | | | | | | | | Removed PMU breakpoints if there is failure during GR save/restore during ELPG entry/exit. Bug 2108544 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Change-Id: I08c342f5f79b7484d31e2437ede1881c4dceb6d0 Reviewed-on: https://git-master.nvidia.com/r/1719659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make sure there an nvlink.h header for POSIXAlex Waterman2018-05-17
| | | | | | | | | | | | | | | | | | | This header doesn't have anything in it yet but the header is now present. A change recently went in that only checked for __KERNEL__ before falling back to including the QNX header. This caused the POSIX build in GVS to attempt to include the QNX header. The QNX src is not synced in userspace dev-kernel tests builds resulting in a missing header. JIRA NVGPU-525 Change-Id: I60f29ad69cbed38b6ea47f95ca504dab51fa01e7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1714083 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update POSIX BIT() macro to ULLAlex Waterman2018-05-17
| | | | | | | | | | | | | | | | | | | | | | | | For most of the builds we have in GVS userspace is 64 bits. But it seems like at least some L4T userspace builds are either not 32 bits or have an UL that only covers 32 bits. This is seen in GVS: /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gv11b/mm_gv11b.c: In function 'gv11b_gpu_phys_addr': /dvs/git/dirty/git-master_modular/kernel/nvgpu/drivers/gpu/nvgpu/gv11b/mm_gv11b.c:273:3: error: left shift count >= width of type make[2]: *** [/dvs/git/dirty/git-master_modular/tmake/artifacts/CommonRules.tmk:318: mm_gv11b.o] Error 1 This patch simply bumps the UL to ULL in BIT() to make sure that we always have at least 64 bits available for the BIT() macro. JIRA NVGPU-525 Change-Id: I67de4338afc5bee4f1fa16faee6116e0e7dbf108 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1718564 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: runlist_lock released before preempt timeout recoverySeema Khowala2018-05-17
| | | | | | | | | | | | | | | | | Release runlist_lock and then initiate recovery if preempt timed out. Also do not issue preempt if ch, tsg or runlist id is invalid. tsgid could be invalid for below call trace gk20a_prepare_poweroff->gk20a_channel_suspend-> *_fifo_preempt_channel->*_fifo_preempt_tsg Bug 2065990 Bug 2043838 Change-Id: Ia1e3c134f06743e1258254a4a6f7256831706185 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1662656 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10b: fix priv error for blcg regSeema Khowala2018-05-17
| | | | | | | | | | | | | Bug 2112073 Change-Id: I4cf97d3e10e2e8d56ab97479d094c47ef842c662 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1710636 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: use new MINION ucode formatAdeel Raza2018-05-16
| | | | | | | | | | | | | | | | Migrate to the new NVLINK MINION ucode format. The new format strips out an unnecessary ACR header from the ucode image. Moving to the new format will allow MINION ucode generation scripts to be unified. Bug 2113404 Change-Id: I9a72d6c3fa5edd50a4ec5eb835d157672931f994 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709986 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: implement new host semaphore methods for VoltaDeepak Nibade2018-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Semaphore methods currently being used in Volta are deprecated for future chips And on Volta we support both old and new methods So replace old methods by new methods on Volta itself so that new methods get tested on silicon Implement below HALs for Volta with new semaphore methods gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer Also use new methods in these APIs gv11b_fifo_add_syncpt_wait_cmd() gv11b_fifo_add_syncpt_incr_cmd() And change corresponding APIs to reflect correct size of command buffer gv11b_fifo_get_syncpt_wait_cmd_size() gv11b_fifo_get_syncpt_incr_cmd_size() Jira NVGPUT-16 Change-Id: Ia3a37cd0560ddb54761dfea9bd28c4384cd8a11c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704518 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to insert semaphore commandsDeepak Nibade2018-05-16
| | | | | | | | | | | | | | | | | | | | | Add below new HALs gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer Separate out new API gk20a_fifo_add_sema_cmd() to implement semaphore acquire/ release sequence and set it to gops.fifo.add_sema_cmd() Add gk20a_fifo_get_sema_wait_cmd_size() and gk20a_fifo_get_sema_incr_cmd_size() to return respective command buffer sizes Jira NVGPUT-16 Change-Id: Ia81a50921a6a56ebc237f2f90b137268aaa2d749 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704490 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: load mem_unlockSeema Khowala2018-05-16
| | | | | | | | | | | | | | | | | mem unlock bin should be written to install traps even if VPR isn’t actually supported Bug 2093809 Change-Id: I4024c66ff72a079c3f20f3b8ab356fba7ce05d4e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709765 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix build errors on qnx for thermRichard Zhao2018-05-15
| | | | | | | | | | | | | | | | | | | - include therm header file in source file - remove unreferenced function JIRA VQRM-2343 Change-Id: Ibfeaf1e431631fa2b9a8e8f1bf044c17edc018c5 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1706201 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Tested-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106 pmu f/w version updateMahantesh Kumbar2018-05-14
| | | | | | | | | | | | | | | | | | | - gp106 f/w version update for ucode https://git-master.nvidia.com/r/#/c/1708195/ - APP_VERSION_GP10X 24008084 to 24069912 - nvgpu driver cl's for current changes https://git-master.nvidia.com/r/#/c/1694546/ https://git-master.nvidia.com/r/#/c/1700746/ p4 CL# 24076634 Change-Id: If15663983a8753a256e47451938be1cf0102fadb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1708199 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: Add dummy variables to accomodate PS3.5 structureVaikundanathan S2018-05-14
| | | | | | | | | | | | Change-Id: I437f2aba6a63de87033721fa9a29c565cf8f4256 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694546 Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vf inject changesVaikundanathan S2018-05-14
| | | | | | | | | | | | | | | | | | | | - Added vf change inject support for gv10x - Updated clk_pmu_vf_inject() to fill required data for pascal or volta vf change inject support - Added new ctrl clk interface for gv10x clk domain list - Added pmu interface for gv10x clk domain list & vf change inject request - Modified clk cmd, msg & RPC id's to match with chips_a_23609936 branch Bug 200399373 Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700746 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-23 18:18:05 -0400