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* gpu: nvgpu: kmem debug bitrot updateAlex Waterman2017-10-10
| | | | | | | | | | | | | | | | | Fix bitrot that was incurred when large amounts of the debugfs stuff was moved the Linux struct. Since the debugfs debugging is largely hidden under a config for the kmem code the necessary changes for the kmem debugging were missed until now. Change-Id: I105549ce39343e503212e302f39ede36c6ea5194 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1575564 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: report GR_SEMAPHORE_TIMEOUT on PBDMA sema timeoutKonsta Holtta2017-10-10
| | | | | | | | | | | | | | | | | | As with GR's semaphore acquires that timeout, report NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT to userspace in the error notifier also when a semaphore acquire timeout interrupt is received from PBDMA. This timeout is used when the kernel watchdog timer is enabled. Bug 1782480 Change-Id: I1ceb8632548c5e89febb2b80a5850116a2d4b670 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1574293 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: Declare gk20a_user_*init() in ioctl.hTerje Bergstrom2017-10-10
| | | | | | | | | | | | | | The functions are gk20a_user_init() and gk20a_user_deinit() are defined in ioctl.c. Move declaration of the functions to new header file ioctl.h. JIRA NVGPU-259 Change-Id: If348b51e9032083f252a7c7717ed7bc153dbba52 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1569696 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move gk20a->busy_lock to os_linuxTerje Bergstrom2017-10-10
| | | | | | | | | | | | | gk20a->busy_lock is a Linux specific rw_semaphore used only by Linux code. Move it to os_linux. JIRA NVGPU-259 Change-Id: I220a8a080a5050732683b875d3c1d0539ba0f40e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1569695 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: clean up channel open/release declaresDeepak Nibade2017-10-10
| | | | | | | | | | | | | | | | | | | Below APIs are already declared in ioctl_channel.h, and hence remove duplicate declaration from channel_gk20a.h gk20a_channel_open() gk20a_channel_ioctl() gk20a_channel_release() And move declaration of gk20a_channel_open_ioctl() from channel_gk20a.h to ioctl_channel.h Jira NVGPU-259 Change-Id: I46702ca481e41a19f92f4fe0169f95e31360abe0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1573106 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for pre-os FWDavid Nieto2017-10-10
| | | | | | | | | | | | | | | | | | | Pre-os firmware takes care, among others, of the control of FAN till the driver takes over its control. On some GPUs not enabling this FW can lead tp physical board damage, hence it is needed to run this firmware. JIRA: NVGPUGV100-9 Change-Id: I18d54cfd5eb64ecec79c5dae67ac8d5bb1facf36 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1549035 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add null check for perfbuffer enable and disable dbg opsSeema Khowala2017-10-10
| | | | | | | | | | | | This is needed to disable/enable features on new chips Bug 200352825 Change-Id: I02eb58e6fdd554ed20866fe8a8553a667541f512 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1574481 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: vgpu: set tsg_verify_channel_status to NULLPeter Daifuku2017-10-10
| | | | | | | | | | | | | | | | | | | | | vgpu inherits the HAL from the native implementation. But currently, the tsg_veriy_channel_status entry point is not supported on vgpu, so make sure to NULL it. Bug 200327095 Change-Id: Ic3604c6ed9bb7a2cddaed8426ce8d291a4adff1a Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1573331 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com>
* gpu: nvgpu: Move PRAMIN functions to nvgpu_memTerje Bergstrom2017-10-10
| | | | | | | | | | | | | | PRAMIN batch access functions are only used by nvgpu_mem. The way the functions are written is Linux specific, so move the implementation from common PRAMIN code. JIRA NVGPU-259 Change-Id: I6e2aba08c98568c651a86fe8ca7f9f5220d67348 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1569697 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Split VIDMEM support from mm_gk20a.cAlex Waterman2017-10-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Split VIDMEM support into its own code files organized as such: common/mm/vidmem.c - Base vidmem support common/linux/vidmem.c - Linux specific user-space interaction include/nvgpu/vidmem.h - Vidmem API definitions Also use the config to enable/disable VIDMEM support in the makefile and remove as many CONFIG_GK20A_VIDMEM preprocessor checks as possible from the source code. And lastly update a while-loop that iterated over an SGT to use the new for_each construct for iterating over SGTs. Currently this organization is not perfectly adhered to. More patches will fix that. JIRA NVGPU-30 JIRA NVGPU-138 Change-Id: Ic0f4d2cf38b65849c7dc350a69b175421477069c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1540705 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add nvgpu/errno.hAlex Waterman2017-10-10
| | | | | | | | | | | | | | | | Add an <nvgpu/errno.h> header file to explicitly include the -E* error messages. Useful for header files with static inlines that return error messages. In actual C code normally enough Linux/QNX headers bleed in to get the error messages but header files with sparse includes do not have this luxury. Change-Id: I4833c7a6003578b9792bbf6b14cce3bd0adfec22 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1573307 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix double iteration in gmmu updateKonsta Holtta2017-10-10
| | | | | | | | | | | | | | | | | | | | __nvgpu_gmmu_do_update_page_table() uses nvgpu_sgt_for_each_sgl to loop through the entries of a buffer to be mapped, so when continue is used, the sgl entry must not be reassigned again like it was before with a pure while-and-update loop. Delete a reassignment to fix a case where sgl = sgl->next could happen twice. Bug 2002279 Bug 2001466 Change-Id: I47c8b853d4b35304740cd4e8a840df02fcd23054 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1575279 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Timo Alho <talho@nvidia.com>
* gpu: nvgpu: falcon: Qualify unsigned HW constantsMahantesh Kumbar2017-10-04
| | | | | | | | | | | | | | | -Falcon HW header re-generate for gk20a, gm20b, gp10b & gp106. -Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions Change-Id: Ifdaac2c697ee7ba8be627e059bf18024a67bbd27 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1570775 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: change logging enum namesShashank Singh2017-10-04
| | | | | | | | | | | | | | | | | Add nvgpu prefix to logging enums. In debug mode QNX, Integrity have already a hashdef DEBUG and it is conflicting with logging enum DEBUG Change-Id: I882e566302842f8b79daf11d5f0850dec222cfea Signed-off-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1570193 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: kill TSG if channel has NEXT set while closingDeepak Nibade2017-10-04
| | | | | | | | | | | | | | | | | | | | | | | | | Currently if channel has NEXT bit set while closing the channel we just print an error and continue channel unbind sequence from TSG But since channel with NEXT set is active killing it can potentially corrupt the TSG context and cause unpredictable errors on remaining channels/TSG Hence fix this by killing whole TSG context if channel being closed has NEXT bit set if gk20a_fifo_tsg_unbind_channel() API returns error, kill the TSG otherwise continue with channel unbind sequence Bug 200327095 Change-Id: I2abf1a3db8ba6f105b6ca86e78006c7b2a7726cc Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1568566 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: verify channel status while closing per-platformDeepak Nibade2017-10-04
| | | | | | | | | | | | | | | | We right now call gk20a_fifo_tsg_unbind_channel_verify_status() to verify channel status while unbinding a channel from TSG while closing Add support to do this verification per-platform and keep this disabled for vgpu platforms Bug 200327095 Change-Id: I19fab41c74d10d528d22bd9b3982a4ed73c3b4ca Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1572368 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Combine VIDMEM and SYSMEM map pathsAlex Waterman2017-10-04
| | | | | | | | | | | | | | | | | | | | | | | | Combine the VIDMEM and SYSMEM GMMU mapping paths into one single function. With the proper nvgpu_sgt abstraction in place the high level mapping code can treat these two types of maps identically. The benefits of this are immediate: a change to the mapping code will have much more testing coverage - the same code runs on both vidmem and sysmem. This also makes it easier to make changes to mapping code since the changes will be testable no matter what type of mem is being mapped. JIRA NVGPU-68 Change-Id: I308eda03d426966ba8e1d4892c99cf97b45c5993 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566706 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add for_each construct for nvgpu_sgtsAlex Waterman2017-10-04
| | | | | | | | | | | | | Add a macro to iterate across nvgpu_sgts. This makes it easier on developers who may accidentally forget to move to the next SGL. JIRA NVGPU-243 Change-Id: I90154a5d23f0014cb79bbcd5b6e8d8dbda303820 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566627 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: skip clk gating prog for sim/emu.Deepak Goyal2017-10-04
| | | | | | | | | | | | | | | For Simualtion/Emulation platforms,clock gating should be skipped as it is not supported. Added new flags "can_"X"lcg" to check platform capability before doing SLCG,BLCG and ELCG. Bug 200314250 Change-Id: I4124d444a77a4c06df8c1d82c6038bfd457f3db0 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566049 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename ops.mm.get_physical_addr_bitsAlex Waterman2017-10-04
| | | | | | | | | | | | | | | | Rename get_physical_addr_bits and related functions to something that more clearly conveys what they are doing. The basic idea of these functions is to translate from a physical GPU address to a IOMMU GPU address. To do that a particular bit (that varies from chip to chip) is added to the physical address. JIRA NVGPU-68 Change-Id: I536cc595c4397aad69a24f740bc74db03f52bc0a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1542966 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add common vaddr translate functionAlex Waterman2017-10-04
| | | | | | | | | | | | | | | | | | | | | | | | Add a function to do address translation for IOMMU capable GPUs. When an iGPU is behind and IOMMU it can pick whether to use that IOMMU for translation by adding a bit to physical addresses. This function takes care of that. However, this required an abstracted nvgpu_iommuable() API to check whether a GPU is behind an IOMMU. This patch adds that API for Linux. JIRA NVGPU-68 Change-Id: I489d14475167c019c294407372395df78c8b5feb Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1542965 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Remove sg_phys() from GMMU codeAlex Waterman2017-10-04
| | | | | | | | | | | | | | | | | | Remove the last sg_phys() call from the GMMU code and replace it with a generic nvgpu_mem API. This new API, nvgpu_mem_get_phys_addr(), returns the physical address of an nvgpu_mem struct. Also, implement this new API in the Linux specific nvgpu_mem code since it requires access to the underlying SGT/SGL. JIRA NVGPU-68 Change-Id: Idf88701a2a8515464c658c26e0de493c82ff850d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1542964 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Return -EINVAL for bad l2 flush argsAlex Waterman2017-10-04
| | | | | | | | | | | | | | When the L2 flush IOCTL gets no l2 flush and no fb flush we now return -EINVAL. This can sometimes happen if the user tries to just invalidate. Currently we do not support L2 invalidates only. Bug 1661242 Change-Id: I87f3259bfbd736b5f4222cfe7b3cfa4a6475389e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1227125 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove GR falcons bootstrap support using VAMahantesh Kumbar2017-10-03
| | | | | | | | | | | | | | | | | | | | - GR falcons bootstrap can be done using physical or virtual address by setting flag usevamask in PMU interface PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS command - With this change always setting to physical address support & removed virtual address support along with code removal. - Removed Linux specific code used to get info regarding WPR VA. JIRA NVGPU-128 Change-Id: Id58f3ddc4418d61126f2a4eacb50713d278c10a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1572468 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Fix license of nvgpu_mem and pmu_debugTerje Bergstrom2017-10-03
| | | | | | | | | | | | | | | nvgpu_mem and pmu_debug should be MIT licensed. Change the license boilerplate. JIRA NVGPU-218 Change-Id: I7750368674faa4c4e8bf071e136b80fd53d9a0c4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1568779 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: gp106: Qualify unsigned HW constantsTerje Bergstrom2017-09-27
| | | | | | | | | | | | Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions. Change-Id: I4221521e00442b044ff70007b7971f44cc3c4f67 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567986 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: gp10b: Qualify unsigned HW constantsTerje Bergstrom2017-09-27
| | | | | | | | | | | | Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions. Change-Id: I33d46bb103d083316266eb1d325ca9f1525bf047 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567985 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: gm20b: Qualify unsigned HW constantsTerje Bergstrom2017-09-27
| | | | | | | | | | | | Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions. Change-Id: Ic50345252c6d7ccb7e9059120b6cc751cdc28362 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567984 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: gk20a: Qualify unsigned HW constantsTerje Bergstrom2017-09-27
| | | | | | | | | | | | Re-generate hardware headers so that all unsigned constants are qualified with postfix U. This removes the need for compiler to do implicit signed->unsigned conversions. Change-Id: I6f23cb6be4000300388bf17a04103d01571fc250 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567983 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: fix coverity, Recursion in included headersMahantesh Kumbar2017-09-27
| | | | | | | | | | | | | | | | - Fix recursion in included header, gk20a.h -> perf.h -> pstate.h -> gk20a.h - Removed "gk20a.h" from pstate.h but need to forward declare "struct gk20a" as referenced in header file. bug 200291879 Change-Id: I124c1c5cf4adcbd485de0800a73e0dc7f11fa92e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566037 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: nvgpu_pmu_disable_elpg() status checkMahantesh Kumbar2017-09-27
| | | | | | | | | | | | | | | | | | | | | - Added status check for nvgpu_pmu_disable_elpg() return value & prints error information upon failure. - Below CID's are due to missing status check of function nvgpu_pmu_disable_elpg() return value, so this CL helps to fix it 2624546 2624547 2624548 Bug 200291879 Change-Id: I263fc6bc9e2667af478bfd7160fe205167556f99 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1565998 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Selectively disable/enable CFCTejal Kudav2017-09-27
| | | | | | | | | | | | | | | | | | clk_pmu_freq_controller_load used the default mask and affected all the clock frequency controllers (CFC) which had their bits set in the mask. We wish to enable/disable the CFCs in isolation through debugfs. So we add a parameter(bit_idx) to the function which will help affect only one CFC at a time JIRA DNVGPU-207 DEPENDS ON: <http://git-master/r/1563302> Change-Id: I233f52158b4a987bcc058a425380983dbe53fac8 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1563303 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gpu: Add debugfs nodes for CFC controlTejal Kudav2017-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | Develop a file heirarchy to hold clock frequency controller(CFC) related debugfs nodes. /gpu_root -> /clk_freq_ctlr -> sys -> ltc -> xbar -> gpc Reading the file should tell if the particular CFC is enabled(1) or disabled(0). Write 0 to the file to disable the CFC and 1 to enable the CFC. We can write 0 to all the files to disable all CFCs. JIRA DNVGPU-207 DEPENDS ON: <http://git-master/r/1563303> Change-Id: I845a4aab8b1195b24fe2377a697c1de0cfe9ecfd Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1563302 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Re-generate hardware headersTerje Bergstrom2017-09-26
| | | | | | | | | | | | JIRA NVGPU-218 Change-Id: Ib00a921150612d59454d0ed76233e7e39a63d6ce Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1563850 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix handling of EGPC_ETPC_SM addressesseshendra Gadagottu2017-09-26
| | | | | | | | | | | | | | | | | | | | | | Added new defines for following litter values: GPU_LIT_SMPC_PRI_BASE GPU_LIT_SMPC_PRI_SHARED_BASE GPU_LIT_SMPC_PRI_UNIQUE_BASE9 GPU_LIT_SMPC_PRI_STRIDE Calculate offsets for ctx operations considering sm per tpc. Following functions are modified for this: gr_gk20a_get_ctx_buffer_offsets gr_gk20a_get_pm_ctx_buffer_offsets __gr_gk20a_exec_ctx_ops Bug 200337994 Change-Id: I3a4ca470a4107d3078b708f38601762626ce1bf1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1539069 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add forward declaration of nvgpu_sgtSourab Gupta2017-09-26
| | | | | | | | | | | | | | The patch adds a forward declaration of nvgpu_sgt in nvgpu_mem.h header file to be referred inside struct nvgpu_sgt_ops. This is to prevent compilation issue while including this header elsewhere without explicit forward declaration. Change-Id: I5cfe5c723e961813425be5301d9bb770bb10c896 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567713 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use u64 instead of dma_addr_tSourab Gupta2017-09-26
| | | | | | | | | | | | | The patch modifies a common dma api (nvgpu_dma_alloc_flags_vid_at) to use u64 argument (which is OS agnostic) instead of dma_addr_t as the argument type which is Linux specific. Change-Id: I74a694b08364b4d9e2826ffaf4620b113604d1cf Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567709 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: include rmos headers in common headersSourab Gupta2017-09-26
| | | | | | | | | | | The patch includes rmos atomic.h and barrier.h headers in nvgpu common header files Change-Id: Ia20c9694de0753a2397ab75c98e661f3b155965a Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567697 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Change license for common files to MITTerje Bergstrom2017-09-26
| | | | | | | | | | | | Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I1474065f4b552112786974a16cdf076c5179540e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1565880 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: cpu access for ctxheaderseshendra Gadagottu2017-09-25
| | | | | | | | | | | | | | | | | | | | | | | | Before updating ctxheader in gr_gk20a_ctx_patch_smpc() add cpu access with nvgpu_mem_begin. After updating ctxheader, close cpu access with nvgpu_mem_end. Reviewed usage of ctxheader in other places and its cpu access is taken care correctly. Bug 200333285 Change-Id: I88ab0b040f95240673a4be55bcfe880a1440655b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1564764 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pg init task hogging cpuDavid Nieto2017-09-25
| | | | | | | | | | | | | | | | | | | | | | | The Pg init task hogs the kernel by having a wait condition with no timeout waiting for pg state change, but ps state may not post a change in a long time depending on runtime conditions, so we get soft-crashes warning spews in the kernel We solve this by making the condition wait interruptible bug 200346134 Change-Id: I8a3349031acc5065b767dc22eec6e5df113d3ad7 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566545 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: PMU debug reorgMahantesh Kumbar2017-09-25
| | | | | | | | | | | | | | | | | | | | | - Moved PMU debug related code to pmu_debug.c Print pmu trace buffer Moved PMU controller/engine status dump debug code Moved ELPG stats dump code - Removed PMU falcon controller status dump code & used nvgpu_flcn_dump_stats() method, - Method to print ELPG stats. - PMU HAL to print PMU engine & ELPG debug info upon error NVGPU JIRA-96 Change-Id: Iaa3d983f1d3b78a1b051beb6c109d3da8f8c90bc Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1516640 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Falcon IMEM/DMEM dump supportMahantesh Kumbar2017-09-25
| | | | | | | | | | | | | | | | | | | - Added falcon interface/HAL for IMEM-copy-from to read data from IMEM from given location with requested size -Added falcon interface to print data of IMEM/DMEM from given location with requested size using falcon HAL. JIRA NVGPU-105 Change-Id: I84cf7b5769b84a2baee2c7e65027539598ec1295 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514536 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: falcon status dump supportMahantesh Kumbar2017-09-25
| | | | | | | | | | | | | | | | | | | - Added support to dump flacon controller status - Method to print recent PC history to know call trace - Method to dump IMBLK info - Updated falcon hw header files to include registers of PC trace & IMBLK JIRA NVGPU-105 Change-Id: Id4aaafd87113d47e552afb21b87f8b087d36004e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1515371 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Change HW header licenses to MITTerje Bergstrom2017-09-22
| | | | | | | | | | | | Change the license of all HW headers to MIT license. JIRA NVGPU-218 Change-Id: I49a22502159384575ac9e0f901f10c4bdffbbf96 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1563849 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: defer channel worker initializationDavid Nieto2017-09-22
| | | | | | | | | | | | | | | | | | | | | | | | kthread_run can fail if SIGKILL is triggered on an application during driver load. On this change we defer the channel worker init to the enqueue to avoid this condition during driver power on which would cause the driver state to be corrupted leaving subsequent attempts to load the driver unsuccesful. By moving this code to a later time, it is now needed to protect the task structure with a mutex. JIRA: EVLR-956 Bug 1816515 Change-Id: I3a159de2d1f03e70b2a3969730a927532ede2d6e Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1462490 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1460689 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow bind to be interruptedDavid Nieto2017-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change solves two problems: (*) the possibility of a crash due to interrupting the gpu initialization following a bind (*) a IOVA memory leak that could prevent the GPU from binding after about 200 bind/unbind cycles A detailed list of fixes: - chek that arbiter is initialized before freeing it. - do not re-enable interrupts when MSI is enabled on unbind. - free the semaphore sea on unbind. - ensure we dont double load the vbios. - check return value of nvgpu_mutex_init for semaphores. - add corresponding nvgpu_mutex_destroy calls. bug 1816516 Change-Id: Ia8af73019e0e1183998855d55bb3eea09672a8b7 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1465302 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: David Jarrett <djarrett@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1563019 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: prevent crash during unbindDavid Nieto2017-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change solves crashes during bind that were introduced in the driver during the OS unification refactoring due to lack of coverage of the remove() function. The fixes during remove are: (1) Prevent NULL dereference on GPUs with secure boot (2) Prevent NULL dereferences when fecs_trace is not enabled (3) Added PRAMIN blocker during driver removal if HW is no longer accesible (4) Prevent double free of debugfs nodes as they are handled on the debugfs_remove_recursive() call (5) quiesce() can now be called without checking is HW accesible flag is set (6) added function to free irq so no IRQ association is left on the driver after it is removed (7) prevent NULL dereference on nvgpu_thread_stop() if the thread is already stopped JIRA: EVLR-1739 Change-Id: I787d38f202d5267a6b34815f23e1bc88110e8455 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1563005 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: fix indentationSreejith V2017-09-22
| | | | | | | | | | | | | | | | | Fix gcc 6.4 toolchain comppilation error due to misleading indentation. Bug 200348663 Change-Id: I06858bc5e0a96a0c23228ac9333102080ccb2da2 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1564717 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Nirav Patel <nipatel@nvidia.com>
* gpu: nvgpu: SGL passthrough implementationSunny He2017-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | The basic nvgpu_mem_sgl implementation provides support for OS specific scatter-gather list implementations by simply copying them node by node. This is inefficient, taking extra time and memory. This patch implements an nvgpu_mem_sgt struct to act as a header which is inserted at the front of any scatter- gather list implementation. This labels every struct with a set of ops which can be used to interact with the attached scatter gather list. Since nvgpu common code only has to interact with these function pointers, any sgl implementation can be used. Initialization only requires the allocation of a single struct, removing the need to copy or iterate through the sgl being converted. Jira NVGPU-186 Change-Id: I2994f804a4a4cc141b702e987e9081d8560ba2e8 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1541426 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 14:56:29 -0500