| Commit message (Collapse) | Author | Age |
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PMU ucode is updated to include LDIV slowdown factor in gr_init_param command.
- Defined a new version gr_init_param_v2.
- Updated the PMU FW version code.
- Set the LDIV slowdown factor to 0x1e by default.
- Added sysfs entry to program ldiv_slowdown factor at runtime.
Bug 200391931
Change-Id: Ic66049588c3b20e934faff3f29283f66c30303e4
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1674208
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set_user_nice is no longer needed to improve the efficiency of
gk20a_finalize_poweron and can be removed as suggested by Terje.
Change-Id: I303bbee266b4624bb775ea793f843dbfc8f88c5d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1692609
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Get host1x node reference from c1_rp device tree node, and
enable syncpoints shim in case of nvlink.
JIRA EVLR-2441
JIRA EVLR-2585
Change-Id: Idbf1edf656557f2ed2d3bd27393c2f4d5d1ad75a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1663360
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Add new HAL gops.mc.isr_nonstall() to handle nonstall interrupts
We already handle nonstall interrupts in nvgpu_intr_nonstall()
But this API is completely in linux specific code
Separate out os-independent code to handle nonstall interrupts in new API
mc_gk20a_isr_nonstall() and set it to HAL gops.mc.isr_nonstall() for all
existing chips
Call this HAL from nvgpu_intr_nonstall()
Jira NVGPUT-8
Change-Id: Iec6a56db03158a72a256f7eee8989a0a8a42ae2f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1706589
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Implement a worker thread to replace the workqueue based
handling for clk arbiter update callbacks.
The work items scheduled with the thread are of two types,
update_vf_table and arb_update. Previously, there were two
workqueues for handling these two work struct's separately.
Now the single worker thread would process these two events.
If a work item of a particular type is scheduled to be run
on the worker, another instance of same type won't be
scheduled, which mirrors the linux workqueue behavior.
This also removes dependency on linux workqueues/work struct
and makes code portable to be used by QNX also.
Jira VQRM-3741
Change-Id: Ic27ce718c62c7d7c3f8820fbd1db386a159e28f2
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1706032
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clk arbiter code uses linux kernel specific 'list' handling.
Use 'nvgpu_list' data structure and constructs instead.
Also, remove other linux includes from clk_arb.c, while at it.
Jira VQRM-3741
Change-Id: I89bf73a62537447dc23726a43e1f6ad96589ae34
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1705962
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RCU's are available only in (linux) kernel. Though they are
able to achieve lockless access in some specific scenarios,
they are heavily dependent on the kernel for their functionality.
E.g. synchronize_rcu(), which depends on the kernel in order to
delimit read side critical sections.
As such it is very difficult to implement constructs analogous
to RCUs in userspace code. As a result the code which depends on
RCU's for synchronization is not portable between OS'es,
especially if one of them is in userspace, viz. QNX.
Also, if the code is not in performance critical path, we can do
with non-RCU constructs.
For clk arbiter code here, RCU's are replaced by the traditional
spinlocks, so that the code could be used by QNX down the line.
Jira VQRM-3741
Change-Id: I178e5958788c8fd998303a6a94d8f2f328201508
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1705535
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In order to enable the movement of clk arbitrator to common
code, we need to remove the linux specific POLL* defines
and instead use NVGPU defines. Add a conversion function
for the same.
Also remove debugfs include, while at it.
Jira VQRM-3741
Change-Id: I3c367625f9fa5fb8480d01bdaf6233df8cc2c722
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704885
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In order to enable the movement of clk arbitrator to common
code, we need to remove the NVGPU_GPU_EVENT_* defines (which
are present in uapi) and instead use the common code defines.
Add a conversion function for the same.
With this the uapi header is no longer required to be included
inside clk_arb.c
Jira VQRM-3741
Change-Id: If01614b01733876046f98b97e70285c52bc33e45
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699241
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Clk arbiter uses the legacy gk20a_dbg_fn logging APIs.
Use nvgpu logging instead, while also defining a new
log mask for clk arbiter.
Jira VQRM-3741
Change-Id: I86feb4fa434b404705cc3fba1e854180d4df508d
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
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Add support for compiling nvgpu in a POSIX compliant userspace.
This code adds all of the necessary abstraction interfaces (mostly
stubbed) to enabled extremely limited and basic functionality in
nvgpu.
The goal of this code is to facilitate unit testing of the nvgpu
common core. By doing this in userspace it is much easier to write
tests that rely on very particular states within nvgpu since a user
can very precisely control the state of nvgpu.
JIRA NVGPU-525
Change-Id: I30e95016df14997d951075777e0585f912dc5960
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1683914
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Mostly just including necessary includes to make sure that
global function declarations actually match their implementations.
Also work around pointer munging warning:
/build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c: In function 'nvgpu_pmu_process_init_msg':
/build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c:348:4: error: dereferencing type-punned pointer will break strict-aliasing rules [-Werror=strict-aliasing]
(*(u32 *)gid_data.signature == PMU_SHA1_GID_SIGNATURE);
Work around this warning by simply moving the type punning.
This code is certainly dangerous - it assumes the endianness
of the header data is the same as the machine this code is
running on. Apparently it works, though, so this ignores
the warning.
JIRA NVGPU-525
Change-Id: Id704bae7805440bebfad51c8c8365e6d2b7a39eb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1692454
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- gp106 f/w version update for ucode
https://git-master.nvidia.com/r/1702217
- APP_VERSION_GP10X 23913597 to 24008084
- nvgpu clk_vin interface as per chips_a_23609936 CL
https://git-master.nvidia.com/r/#/c/1687591/
p4 CL # 24069912
Bug 200399373
Change-Id: If16566aaf42dfc2460d426f18927eab08309dfcf
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702218
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
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clk_vin data structures updated as new calibration type (v20) is added.
GP106 header does not have vin calibration type.
Assuming V10 if calibration type is not V20.
Add fuse calibration for V20 type.
Bug 200399373
Change-Id: I9449de1ecb0d0873f3bc16f46660f93fab5b9eac
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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mmu fault information for client and gpc differ
on various chip. Add separate table for each chip
based on that change and add hal functions to access
those descriptors.
bug 2050564
Change-Id: If15a4757762569d60d4ce1a6a47b8c9a93c11cb0
Signed-off-by: Vinod G <vinodg@nvidia.com>
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Set rpc buffer to 0xFF instead of 0x0 to handle fucntions with rpc id 0
Change-Id: Ife692d9fd19008e225975e41bb13e53522283a54
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702133
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Add Nvdclk domain as a valid vbios domain for GV100
Change-Id: Ib65d880b26c279018bbf7d2faa304084f9ce4b1a
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
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- Made change to pass correct VOLT RPC param to get
voltage request.
- Change VOLT_SET_VOLTAGE request to blocking call
to make sure, set voltage request completes in
PMU & ACK's
- Created rail count define for pascal & volta then
made changes to use define as needed.
Change-Id: I2662fadbe32b82585711f2568c4f800162899206
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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Added sw method for NVC397_SET_SHADER_CUT_COLLECTOR
to enable/disable SHADER_CUT_COLLECTOR_STATE.
Added support for this sw method in gv11b and gv100.
Bug 2108381
Change-Id: Ief2c2bf5d9c99779dad3b1243041c5efe56287d3
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
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Add below rc_types to be passed to gk20a_fifo_recover
MMU_FAULT
PBDMA_FAULT
GR_FAULT
PREEMPT_TIMEOUT
CTXSW_TIMEOUT
RUNLIST_UPDATE_TIMEOUT
FORCE_RESET
SCHED_ERR
This is nice to have to know what triggered recovery.
Bug 2065990
Change-Id: I202268c5f237be2180b438e8ba027fce684967b6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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Rename mutex to runlist_lock in fifo_runlist_info_gk20a
struct. This is good to have for code readability.
Bug 2065990
Bug 2043838
Change-Id: I716685e3fad538458181d2a9fe592410401862b9
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Currently gv100 is using very large timeout for polling
eng preempt done. This will prevent eng preempt polling
loop from timing out. Also before eng preempt loop times
out, there could be channel timeout getting kicked in.
Avoid this by using gr_idle_timeout defined by driver.
Change-Id: Icff5ae37f95f58f3195b9d630bdae42c08ced9a6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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The return value from NVGPU_COND_WAIT_INTERRUPTIBLE in
channel poll worker is wrongly compared with 0 and the
boolean result is assigned to ret value used subsequently.
Instead, the direct return value from
NVGPU_COND_WAIT_INTERRUPTIBLE should be used.
This bug seems remnant of the following patch which moved
the handling from 'wait_event_timeout' to 'NVGPU_COND_WAIT'.
commit 301965fb77b3dc97445957712b82ce430eaa17e3
gpu: nvgpu: Use nvgpu_cond in channel worker
Change-Id: Id48e197756a6855b35a9ee0dc26d014b62ed3860
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1705976
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Necessary in order for QNX to avoid setting __NVGPU_POSIX__ globally.
Change-Id: I020609c28766951269371358bae71b0fb4de7803
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1703386
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fecs_ctxsw_mailbox_size varies per chip. Use hal to
get the size. Also dump fecs_ctxsw_status_1 to help
debug
Bug 2093809
Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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Bug 2102373
Change-Id: I13a5faa18cf26233eb04ac08d2b8755aeb56ae4b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1696890
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- total DMA memory allocation is currently tracked by adding page aligned
size of nvgpu_mem
- The sequence is roughly as follows:
- total dma memory used += mem->aligned_size
- mem->aligned_size = PAGE_ALIGN(size)
- In above sequence, nvgpu_mem structure is initially zero when it is added
to total dma memory used after which it is assigned page aligned value
- This patch fixes total dma memory usage tracking.
Change-Id: Ibb879c8d38ae9077c3d198d9bb008a72e9208b4d
Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1685312
Reviewed-by: Automatic_Commit_Validation_User
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Add new HAL gops.fifo.ring_channel_doorbell() to update channel doorbell
register and to trigger a runlist scan
Set existing API gv11b_ring_channel_doorbell() to this HAL for all volta chips
Jira NVGPUT-18
Change-Id: I9d5e84cf5aa7b763363d84befe169efda00a0932
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1702114
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sim pointer is not init for non simulation
platforms.
Change-Id: Ia30e66efbb009293b4e1151c2f1e4ac5d08c3d78
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1701681
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Clk arbiter code contains two significant portions -
the one which interacts with userspace and is OS specific,
and the other which does the heavylifting work which can
be moved to the common OS agnostic code.
Split the code into two files in prep towards refactoring
the clk arbiter.
Jira VQRM-3741
Change-Id: I47e2c5b18d86949d02d6963c69c2e2ad161626f7
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
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ETIME does not exist on integrity.
Jira VQRM-2344
Change-Id: I4c9642c5ccf6d5d7ada456716589461b27b72c99
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699843
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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as_share is more os specific and not yet used on other OSes.
Jira VQRM-2344
Change-Id: Ie2ed007125400484352fbab602c37a198e8a64ae
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699842
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The code uses ioremap, readl_relaxed/writel_relaxed, which only exists
on linux. So move them to linux folder.
Also fix build errors on qnx.
Jira VQRM-2344
Change-Id: Ide1176d0bf954a804187aa842a6bbfdecbdb0286
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698973
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max_comptag_lines will be used by RM server to calculate how many lines
each guest can get.
Jira VQRM-2345
Change-Id: If52208d79617f2f894e48d3a4daec186fda862f1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1695082
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- gp106 f/w version update for ucode
https://git-master.nvidia.com/r/#/c/1693596/
- APP_VERSION_GP10X 23732390 to 23913597
Change-Id: Id3ae28325fda8a66b833245113e7010c76ed2750
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1693616
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- Update PMU interface for vf_point
Change-Id: I1c457026938025266a9325a93985d81fae3b9fa5
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1684286
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Changes made:
1. Fuse value can now be signed or unsigned. A new boolean added to check
if the value is signed or not.
2. Masks added for dependent variable and equations
3. Restructing some data structures as per r384
JIRA NVGPUGV100-39
Change-Id: I7d9d1a55e26a06686f6253dedeb55925a32fd0ad
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1597761
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Only for gv11b A01 version following invalidates are disabled:
-CBM alpha and beta invalidations for L2
-SCC pagepool invalidates
-SWDX spill buffer invalidates
Bug 2053668
Change-Id: I027f923b63b24bbbc054a7d9a377d757994a07ad
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700981
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Add below two new HALs
gops.fifo.runlist_hw_submit() to submit a new runlist to hardware
gops.fifo.runlist_wait_pending() to wait until runlist write is successful
Set existing API gk20a_fifo_runlist_wait_pending() to
gops.fifo.runlist_wait_pending HAL
Add new API gk20a_fifo_runlist_hw_submit() which submits the runlist to h/w
and set it to gops.fifo.runlist_hw_submit HAL
Jira NVGPUT-20
Change-Id: Ic23f7d947e30883aca0b536de818e79e14733195
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700548
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Need to include bug.h and dbg_gpu_gv11b.h to fix compilation issue
at QNX. These changes are required as part of debug session
unification.
Jira VQRM-2363
Change-Id: I543dab8be16ef6eb321c31f2f262e4dbdeb7dd6a
Signed-off-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699079
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Allow a potential IOMMU'ed GMMU mapping for all SYSMEM buffers
inlcuding coherent sysmem. Typically this won't actually happen
since IO coherent mappings will also often be accessed over
NVLINK which is physically addressed.
Also update the comments surrounding this code to take into
account the new NVLINK nuances. Since NVLINK buffers are
directly mapped even when the IOMMU is enabled this is very
deserving of a comment explaining what's going on.
Lastly add some simple functions for checking if an nvgpu_mem
(or a particular aperture field) is a sysmem aperture. Currently
this includes SYSMEM and SYSMEM_COH.
JIRA EVLR-2333
Change-Id: I992d3c25d433778eaad9eef338aa5aa42afe597e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665185
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Cache the rate used in clk_set_rate().
Return that cached rate on clk_get_rate(), don't read from hardware.
This cached rate is used to avoid duplicate requests to clk_set_rate().
Motivation is to support multiple governors for gpu clk.
Reading clock from hardware is unreliable in multi-governor situation.
Relying on hardware clock value could mislead the kernel gpu governor
in its scaling calculations.
Bug 2051688
Change-Id: I43fc056eea6f69fe0889c45640fcb892b658071c
Signed-off-by: Arun Kannan <akannan@nvidia.com>
(cherry picked from commit 7f819a9ba707e6e905168b00b0f3bf6348e86188)
Reviewed-on: https://git-master.nvidia.com/r/1662759
Reviewed-on: https://git-master.nvidia.com/r/1668919
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Previously all nvlink recovery modes were being grouped under 1 enum.
Create an enum for each recovery mode, so the link can go into specific
recovery modes.
Bug 2090322
Change-Id: I5c2aea758f77b0286e3538424684ddceca98a873
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698799
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If the power gating mode is not disabled before hwpm
context switch mode register write, return error.
Bug 200379815
Bug 2053656
Bug 2092996
Change-Id: I656f5c38616a4250830779d2bca5e207ff28f3a9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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Fetch ROP_L2 enable masks in addition to other parameters
when guest sends command to query constants.
Bug 200401223
Change-Id: Ie386f24caaf7acd1155fc3f2a5e8c1f27016970a
Signed-off-by: Aparna Das <aparnad@nvidia.com>
(cherry picked from commit a08bb08fb9fff40138d26e5e9bfa21267ca6b6af)
Reviewed-on: https://git-master.nvidia.com/r/1694911
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This patch deals with cleanups meant to make things simpler for the
upcoming os abstraction patches for the sync framework. This patch
causes some substantial changes which are listed out as follows.
1) sync_timeline is moved out of gk20a_fence into struct
nvgpu_channel_linux. New function pointers are created to facilitate os
independent methods for enabling/disabling timeline and are now named
as os_fence_framework. These function pointers are located in the struct
os_channel under struct gk20a.
2) construction of the channel_sync require nvgpu_finalize_poweron_linux()
to be invoked before invocations to nvgpu_init_mm_ce_context(). Hence,
these methods are now moved away from gk20a_finalize_poweron() and
invoked after nvgpu_finalize_poweron_linux().
3) sync_fence creation is now delinked from fence construction and move
to the channel_sync_gk20a's channel_incr methods. These sync_fences are
mainly associated with post_fences.
4) In case userspace requires the sync_fences to be constructed, we
try to obtain an fd before the gk20a_channel_submit_gpfifo() instead of
trying to do that later. This is used to avoid potential after effects
of duplicate work submission due to failure to obtain an unused fd.
JIRA NVGPU-66
Change-Id: I42a3e4e2e692a113b1b36d2b48ab107ae4444dfa
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
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Implement support for dGPU fmodel. The message protocol is slightly
different and accessed via BAR0 aperture.
JIRA NVGPUT-41
Change-Id: Ide3c52a751530f520854965c1eba19fa8339a315
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Export below APIs from fifo_gv11b.h
gv11b_fifo_init_ramfc_eng_method_buffer()
gv11b_userd_writeback_config()
Also move #define PBDMA_SUBDEVICE_ID to header file
Jira NVGPUT-19
Change-Id: I5e3abf02acfe014e39550f236d60d8991a75b4ef
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699315
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Add new HAL gops.bus.set_ppriv_timeout_settings() to set platform specific
ppriv timeouts
Set this HAL for all supported GPUs for now
Jira NVGPUT-35
Change-Id: I88b438a7bf381d0216e0947a16cd267461d0e8d7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699314
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H/W field NV_PPBDMA_PB_HEADER_PRIV is obsolete in Volta and has no effect
Hence remove use of pb_header_priv_user() from channel_gv11b_setup_ramfc()
Jira NVGPUT-31
Change-Id: I0bb08c5d5a26218bb057e19983044dac5238142f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1699313
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