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* gpu: nvgpu: update_smpc_ctxsw_mode changes for t19xSeema Khowala2017-07-19
| | | | | | | | | | | | Support t19x ctx header changes Bug 200313979 Change-Id: Ide5c5f9f3227bd6aba530e736896006fb72d4d19 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1508549 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add perf gr ops to support t19xSeema Khowala2017-07-19
| | | | | | | | | | | | | Add init_ovr_sm_dsm_perf & get_ovr_perf_regs gr ops JIRA GPUT19X-49 Bug 200311674 Change-Id: If02dd9dc0e2e0eb1f68fdbaa86a37c6768eddcef Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1497403 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add esc read for PPC_COUNTSeema Khowala2017-07-19
| | | | | | | | | | | | | | | | | | Add esc read for GRCTX_REG_LIST_PPC_COUNT else gr_gk20a_determine_ppc_configuration function would return -EINVAL if num_pes_per_gpc i.e. GPU_LIT_NUM_PES_PER_GPC is > 1 JIRA GPUT19X-49 Bug 200311674 Change-Id: Iee7ee9ba14fcc7dca07c4c1dc20f8e7d018ed820 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522443 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add ctxsw etpc regsSeema Khowala2017-07-19
| | | | | | | | | | | | | | Add etpc ctxsw regs for t19x Bug 200311674 Change-Id: I2d5076cb4df8040613c20d28518325ad7c6a9145 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1520140 GVS: Gerrit_Virtual_Submit Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com> Reviewed-by: Tushar Kashalikar <tkashalikar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu : nvgpu: secure boot code unification.Deepak Goyal2017-07-18
| | | | | | | | | | | | | | This exposes all secure boot functions that can be re-used by other chips. This is the first patch in this series. Other pacthes will also follow. JIRA NVGPU-60 Change-Id: I523637bbf601166f8a01ddf29a913e193d3fdc7a Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514567 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check return value of sm exception handlerDeepak Nibade2017-07-18
| | | | | | | | | | | | | | | | | | | | | | | In gr_gp10b_handle_sm_exception(), we do not check return value of gr_gk20a_handle_sm_exception() In case SM debug mode is disabled, gr_gk20a_handle_sm_exception() returns an error. But due to uncaught error we return success from gr_gp10b_handle_sm_exception() which results in not triggering the recovery routine and fails the tests Fix this by checking return value of gr_gk20a_handle_sm_exception() We then parse ECC errors and then finally return error value back to caller Bug 200325081 Change-Id: I0c328a75494b9ca6a070f04c1f984e2653ffd90e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1521563 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Ashutosh Jain <ashutoshj@nvidia.com>
* gpu: nvgu: Support SET_BES_CROP_DEBUG3 sw methodLauri Peltonen2017-07-14
| | | | | | | | | | | | | | | The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is used by the user space driver to disable enough ROP optimizations to maintain ZBC state of target tiles. Bug 1942454 Change-Id: Id4e4d9d06c6c66080d06b6d4694546fe5cba8436 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1516202 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gpu: Remove unnecessary hw header includesSunny He2017-07-14
| | | | | | | | | | | | | | | Remove some unnecessary hardware register header includes. Jira NVGPU-118 Change-Id: Ie05ca78bbab49c6fcc05eaa5a9a5890a0943cd8f Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1520148 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg debug HAL initializationSunny He2017-07-13
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the debug and dbg_session_ops sub-modules of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Id51feeccbea91f884a6057efc680566a7d5d0b6d Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514822 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Move gops.mc's non-fp membersSunny He2017-07-13
| | | | | | | | | | | | | | | | | | Move non-function pointer members out of the mc substruct of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. gops.mc.intr_mask_restore is now mc_intr_mask_restore Jira NVGPU-74 Change-Id: Iddf5e761012086e993c375d59e1bbdfb1e64db0c Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509602 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg mc HAL initializationSunny He2017-07-13
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I26d74c14661a193af7e8d90dd672b73010e5f841 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509601 GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg falcon HAL initializationSunny He2017-07-13
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the falcon sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ib1aaaa248b079bb591ccfada3382b689452de0e9 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514012 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add get/set PTE routinesAlex Waterman2017-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | Add new routines for accessing and modifying PTEs in situ. They are: __nvgpu_pte_words() __nvgpu_get_pte() __nvgpu_set_pte() All the details of modifying a page table entry are handled within. Note, however, that these routines will not build page tables. If a PTE does not exist then said PTE will not be created. Instead -EINVAL will be returned. But, keep in mind, a PTE marked as invalid still exists. So this API can be used to mark an invalid PTE valid. JIRA NVGPU-30 Change-Id: Ic8615f209a0c4eb6fa64af9abadcfb3b2c11ee73 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1510447 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: fix tpc exception enablementSeema Khowala2017-07-10
| | | | | | | | | | | | | | Use read modify write to enable sm exception. This is to avoid disabling alredy enabled interrupts e.g. tex etc. JIRA GPUT19X-69 Change-Id: I94f75f9a37310a8271193b4996e9b4b2ba29e4ae Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1515914 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add gr ops for mpc exception handlingSeema Khowala2017-07-10
| | | | | | | | | | | | | Required for t19x JIRA GPUT19X-69 Change-Id: I96d1ee2ae1bf310ce572cb4dc7773818a42a25a0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1515913 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add ops and var for t19x mmu faultSeema Khowala2017-07-08
| | | | | | | | | | | | | Add new ops and fields required for t19x mmu fault JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I29694c15ff9a4150bb1737adac6b58ccba76bea4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1492640 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move dev field from gk20a to nvgpu_os_linuxTerje Bergstrom2017-07-07
| | | | | | | | | | | | | Move field "struct device *dev" from struct gk20a to struct nvgpu_os_linux. The field is valid only for Linux. JIRA NVGPU-38 Change-Id: I09286aa3a9c5a2406e5a27c1fbf21b2c515b4dd4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1514162 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use correct units for bios waitKonsta Holtta2017-07-07
| | | | | | | | | | | | | nvgpu_flcn_wait_for_halt() takes a timeout value in milliseconds, so pass it the millisecond value instead of number of iterations to sleep if one iteration took a specific amount of time, a bug left over from refactoring. Change-Id: Ifddea16522c14c52d765f1c1bfaa69d1f7dfd011 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1514396 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use u32 for timeout API durationKonsta Holtta2017-07-07
| | | | | | | | | | | | | | | | A negative value in the timeout duration does not have any special uses, so change the duration type to u32 (from just int). Delete some unnecessary typecasts to int. Also change MAX_SCHEDULE_TIMEOUT to ULONG_MAX in default gr idle timeout because the value is in milliseconds instead of scheduling units and to drop unnecessary Linux dependency. Change-Id: I5cf6febd4f1cb00c46fe159603436a9ac3b003ac Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1512565 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reorg cde HAL initializationSunny He2017-07-07
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the cde sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I9343ce4985eb941a2610f5f11e8f01269ab68481 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1511673 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorg xve HAL initializationSunny He2017-07-07
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the xve sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ieb9afc230199c341d2df1e9f75792a136a2a6067 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1510470 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Cleanup GMMU debug printingAlex Waterman2017-07-07
| | | | | | | | | | | | | | | | | | | | | | | Ensure that all debug prints are consistent from chip to chip and function to function. The following maps letters in the debug print to their meaning: C Mapping is cachable v Mapping is volatile S Mapping is sparse P Mapping is private (VPR/WPR) c Mapping is coherent V Mapping is valid JIRA NVGPU-30 Change-Id: Ia890af88677c3e6d3fdd8c4fe266158c35b8afcd Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1514903 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Tested-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add t19x GMMU attributesAlex Waterman2017-07-07
| | | | | | | | | | | | | | | | Add t19x specific flags into the GMMU attributes struct. Jira GPUT19X-10 Bug 200279508 Change-Id: Ib45b83705fa1ca4ff6d14da0a2f132050e7d2cd5 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1514876 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Tested-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: support platform specific physical address translationDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | On some GPUs certain physical address bits have special meaning. This patch adds support for setting those bits based on the GMMU attributes struct. Jira GPUT19X-10 Bug 200279508 Change-Id: I32b8a028be7fd62af06a60c393a8c9251de0ef3c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1512600 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: use coherent aperture for coherent buffersDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | | | Use sysmem_coherent aperture if the buffer mappings are requested to be IO coherent. Use sysmem_noncoherent aperture otherwise. This is implemented by adding a new coherent field to the GMMU attrs struct. Jira GPUT19X-17 Bug 1651331 Bug 200283998 Change-Id: I5cfb71b5913d4db50ebf10331b19f5a4216456bf Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1514438 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: remove coherence support from gp10bDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | | | | | | | We do not support coherence for gp10b, hence clean up related code Remove API gp10b_mm_phys_addr_translate() and use physical address instead Also, since now gp10b_mm_iova_addr() becomes equivalent to gk20a_mm_iova_addr(), remove gp10b_mm_iova_addr() altogether We first set gk20a_mm_iova_addr() to get_iova_addr() pointer anyways so we continue using gk20a version of the API Jira GPUT19X-17 Bug 1651331 Bug 200283998 Change-Id: Ic1ca198fcde7ddbcd23516bff8a2e65c9eae32b1 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1512598 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Implement PD packingAlex Waterman2017-07-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases page directories require less than a full page of memory. For example, on Pascal, the final PD level for large pages is only 256 bytes; thus 16 PDs can fit in a single page. To allocate an entire page for each of these 256 B PDs is extremely wasteful. This patch aims to alleviate the wasted DMA memory from having small PDs in a full page by packing multiple small PDs into a single page. The packing is implemented as a slab allocator - each page is a slab and from each page multiple PD instances can be allocated. Several modifications to the nvgpu_gmmu_pd struct also needed to be made to support this. The nvgpu_mem is now a pointer and there's an explicit offset into the nvgpu_mem struct so that each nvgpu_gmmu_pd knows what portion of the memory it's using. The nvgpu_pde_phys_addr() function and the pd_write() functions also require some changes since the PD no longer is always situated at the start of the nvgpu_mem. Initialization and cleanup of the page tables for each VM was slightly modified to work through the new pd_cache implementation. Some PDs (i.e the PDB), despite not being a full page, still require a full page for alignment purposes (HW requirements). Thus a direct allocation method for PDs is still provided. This is also used when a PD that could in principle be cached is greater than a page in size. Lastly a new debug flag was added for the pd_cache code. JIRA NVGPU-30 Change-Id: I64c8037fc356783c1ef203cc143c4d71bbd5d77c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1506610 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gmmu programming rewriteAlex Waterman2017-07-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the high level mapping logic. Instead of iterating over the GPU VA iterate over the scatter-gather table chunks. As a result each GMMU page table update call is simplified dramatically. This also modifies the chip level code to no longer require an SGL as an argument. Each call to the chip level code will be guaranteed to be contiguous so it only has to worry about making a mapping from virt -> phys. This removes the dependency on Linux that the chip code currently has. With this patch the core GMMU code still uses the Linux SGL but the logic is highly transferable to a different, nvgpu specific, scatter gather list format in the near future. The last major update is to push most of the page table attribute arguments to a struct. That struct is passed on through the various mapping levels. This makes the funtions calls more simple and easier to follow. JIRA NVGPU-30 Change-Id: Ibb6b11755f99818fe642622ca0bd4cbed054f602 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1484104 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add handle_tpc_sm_ecc_exception gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | Needed to handle t19x sm ecc errors per tpc JIRA GPUT19X-75 JIRA GPUT19X-109 Change-Id: I921615dd5f551f34cdf55c1b085b16f562f16eb0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514044 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add clear_sm_hww gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | Required for multiple SM support and t19x SM register address changes JIRA GPUT19X-75 Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514043 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add sm lock_down gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | Add lock_down_sm and wait_for_sm_lock_down gr ops Required to support multiple SM and t19x SM register address changes JIRA GPUT19X-75 Change-Id: I529babde51d9b2143fe3740a4f67c582b7eb404b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514042 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add get_sm_no_lock_down_hww_global_esr_mask gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | This is required to take care of t19x changes to support multiple SM JIRA GPUT19X-75 Change-Id: Ifd2cb28ae442462fef1d2c4439baa817f00c2c9e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514041 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add gr ops get_sm_hww_global_esrSeema Khowala2017-07-06
| | | | | | | | | | | | | | Required for multiple SM support and t19x sm register address changes JIRA GPUT19X-75 Change-Id: I437095cb8f8d2ba31b85594a7609532991441a37 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514040 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorg misc HAL initializationSunny He2017-07-06
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the lone function pointers of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I30d379bf52709c8382c9d7aa87f1672ca0f89c6f Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1510386 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmu: check before initializing perfmonDeepak Goyal2017-07-06
| | | | | | | | | | | We should check if perfmon is enabled before sending perfmon init command. This is needed for debug purposes. Change-Id: Ia95a590a76074c469b5d87a5820cd5b2e50d13be Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master/r/1510036 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix null ptr in gm20b_tegra_postscale()Peter Boonstoppel2017-07-06
| | | | | | | | | | | | | | | If devfreq governor is called from a timer during boot it is possible that gm20b_tegra_postscale() gets called before we have called gk20a_tegra_scale_init(). This change adds an explicit null ptr check to prevent any null ptr dereference. Bug 1954269 Change-Id: I4ebb6c702175b99af2862169f76623e24256b1ed Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: https://git-master/r/1514262 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: falcon bootstrap supportMahantesh Kumbar2017-07-06
| | | | | | | | | | | | | | | | - Added falcon interface/HAL to bootstrap falcon by taking boot vector as parameter - Replaced falcon bootstrap code in multiple files with nvgpu_flcn_bootstrap() method JIRA NVGPU-102 Change-Id: I4324824c50c6196d8b7ecf981f815ec778da2fd9 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1513643 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add support for t19x tsg/channelseshendra Gadagottu2017-07-05
| | | | | | | | | | | | | | Required modifications to add t19x channel specific info and handle t19x tsg requests. Bug 1842197 Change-Id: I0f8bcce20edea8f2f9a01e5bf5a9e4181af54875 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1511144 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: falcon copy to IMEM supportMahantesh Kumbar2017-07-05
| | | | | | | | | | | | | | | | - Added falcon interface/HAL copy to IMEM method - Deleted copy to IMEM code & then replaced with nvgpu_flcn_copy_to_imem() in multiple files - Code cleanup JIRA NVGPU-117 Change-Id: Ic47197ef7dc449e5bf1f418ac02598500c96da21 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1513273 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix race condition during poweronskadamati2017-07-05
| | | | | | | | | | | | | | | | | | When two or more apps ran simultaneously First app context sets power_on flag & starts init Other app context check the power_on flag and try to use GPU without init completed Which makes aother apps to assert Added mutex to synchronize poweron access Bug 200297265 Change-Id: Ie138f7f43bb0dd3304ed91ae3649a6a4947bee91 Signed-off-by: skadamati <skadamati@nvidia.com> Reviewed-on: https://git-master/r/1511436 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add get_sm_hww_warp_esr gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | | mask_hww_warp_esr gr ops is removed and replaced with get_sm_hww_warp_esr gr ops JIRA GPUT19X-75 Change-Id: I8c7194ca1b0e4fe740a6f8998a02fba846234e9e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512218 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add resume_all_sms gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: I844b5cf02a75ba397891a1100d917875e5a3e181 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512217 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add resume_single_sm gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512216 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add suspend_all_sms gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Icdae3b6ed67a3d3deeb17f29528184b2d7a70af5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512215 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add suspend_single_sm gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: Id104f611736535874cdaa5a2f768f692d799c2c5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512214 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add sm_debugger_attached gr opsSeema Khowala2017-07-05
| | | | | | | | | | | | | This is required to support t19x sm register address changes JIRA GPUT19X-75 Change-Id: I7f961147e0e6464a71e240487f7bc964b0544e5d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1512213 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: replace gk20a_dbg_* with nvgpu_dbg_*Mahantesh Kumbar2017-07-05
| | | | | | | | | | | | | | -replace gk20a_dbg_* statements with nvgpu_dbg_* for PMU in drivers/gpu/nvgpu/common/pmu folder JIRA NVGPU-93 Change-Id: Id616d1f5cb5ce4007bc9543f05e57e4631cdd691 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1512925 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: rename gk20a_pmu_cmd_post()Mahantesh Kumbar2017-07-05
| | | | | | | | | | | | | | | - rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post() - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1512904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Falcon controller halt interrupt status clearMahantesh Kumbar2017-07-04
| | | | | | | | | | | | | | | | | | | | | - Added nvgpu_flcn_clear_halt_intr_status() to Wait for halt interrupt status clear by clear_halt_interrupt_status() HAL within timeout - Added gk20a_flcn_clear_halt_interrupt_status() to clear falcon controller halt interrupt status - Replaced flacon halt interrupt clear with nvgpu_flcn_clear_halt_intr_status() method NVGPU JIRA-99 Change-Id: I762a3c01cd1d02028eb6aaa9898a50be94376619 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1511333 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Falcon controller wait for haltMahantesh Kumbar2017-07-04
| | | | | | | | | | | | | | | | | | | - Added nvgpu_flcn_wait_for_halt() interface to wait for falcon halt, which block till falcon halt or timeout expire for selected falcon controller - Replaced falcon wait for halt code with method nvgpu_flcn_wait_for_halt() NVGPU JIRA-99 Change-Id: Ie1809dc29ff65bddc7ef2859a9ee9b4f0003b127 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1510201 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 01:12:01 -0500