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* gpu: nvgpu: Add SMMU bit only if SMMU enabledTerje Bergstrom2015-04-04
| | | | | | | | | | If SMMU is disabled, we should not add the SMMU bit to addresses. Change-Id: I6dd82e18b63474fb487d21f421ef06467551595b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/673250 Reviewed-by: Adeel Raza <araza@nvidia.com> Tested-by: Adeel Raza <araza@nvidia.com>
* gpu: nvgpu: Update gk20a and gm20b headersSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | | | | Update gk20a and gm20b headers with bar2 register block registers. Also updated gm20b ctxsw headers with latest tool output. Bug 1587825 Change-Id: I9d1c459e03051278e7e79806803aaf71655f0dc5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/672124 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not panic if PMU/regops not supportedTerje Bergstrom2015-04-04
| | | | | | | | | | | Fix panics when using regops when PMU is disabled, or when whitelists have not been defined. Bug 1592505 Change-Id: I316c98147c54be7b1114ad23049ce3a634d4805e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/671841
* gpu: nvgpu: Make locally used function staticTerje Bergstrom2015-04-04
| | | | | | | | | | Make gr_gm20b_alloc_gr_ctx static. It is used only in the same file. Bug 200067946 Change-Id: I484ff84ebe9a356f251db5a14ca0e60db64578bf Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/673267
* gpu: nvgpu: make larger address space workAlex Waterman2015-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement several fixes for allowing the GVA address space to grow to larger than 32GB and increase the address space to 128GB. o Implement dynamic allocation of PDE backing pages. The memory to store the PDE entries was hard coded to 1 page. Now the number of pages necessary is computed dynamically based on the size of the address space and the size of large pages. o Fix an arithmetic problem in the gm20b sparse texture code that caused large address spaces to be truncated when sparse PDEs/PTEs were being filled in. This caused a kernel panic when freeing the address space since a lot of the backing PTE memory was not allocated. o Change the address space split for large and small pages. Small pages now occupy the bottom 16GB of the address space. Large pages are used for the rest of the address space. Now, with a 128GB address space, there are 112GB of large page GVA available. This patch exists to allow large (16GB) sparse textures to be allocated without running into lack of memory issues and kernel panics. Bug 1574267 Change-Id: I7c59ee54bd573dfc53b58c346156df37a85dfc22 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/671204 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: enable ce2 interruptsSam Payne2015-04-04
| | | | | | | | | | | | | | enables non-blocking interrupts in ce2 all other ce2 interrupts are cleared and not handled. bug 200036089 Change-Id: I9f47b06c677c72ac523019e6a3f70fedd07830a2 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/671783 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: update clock gating listsSeshendra Gadagottu2015-04-04
| | | | | | | | | | | Bug 1584688 Change-Id: I9c0f3dcd3287ec8ced3520847b44a6a6a4c55cec Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/658550 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix struct file memleak in alloc_asKonsta Holtta2015-04-04
| | | | | | | | | | | | | Free also newly allocated struct file in error conditions with fput, and pair it by not trying to release the resulting null as_share on release. Bug 1597056 Change-Id: Ifad5c3a829b2c459ed6a738ecdc1ac2ac7e1678a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/671527 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: correct channel open sequenceSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | | | Corrected sequence to bind and enable channel only afer channel gpfifo alloction done. Bug 1591647 Change-Id: I539458d1b666c0403cca1abcf8271b9c8c09f52c Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/671208 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: Set lockboost size for computeTerje Bergstrom2015-04-04
| | | | | | | | | | | For compute channel on gk20a, set lockboost size to zero. Bug 1573856 Change-Id: I369cebf72241e4017e7d380c82caff6014e42984 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/594843 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gm20b: Enable CTA preemptionTerje Bergstrom2015-04-04
| | | | | | | | | | | | CTA preemption needs to be enabled by setting a value in context. Set it for gm20b. Bug 200063473 Bug 1517461 Change-Id: I080cd71b348d08f834fd23ebbe7443dba79224db Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/661299
* gpu: nvgpu: unify instance block creationKonsta Holtta2015-04-04
| | | | | | | | | | | Reduce copypaste code in instance block allocation and deletion with functions purposed for that. Change-Id: I2c8ae6a317ac89e2c857dde4296cb4316b8aaafe Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/668698 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Pre-Population of zbc entriessujeet baranwal2015-04-04
| | | | | | | | | | | | | | | | | | | | The default zbc entries were never populated in zbc HW table because the conditional flag "gr->sw_ready" was always set thus avoided the zbc default loading function call. Now zbc default loading would happen only during boot time in sw structure.Hw zbc regs would be loaded from that structure every time a railgate exit happens. Bug 1580210 Change-Id: Ie3e40738cbc84cf724c3f3871f15b17a5c84025a Signed-off-by: Sujeet Baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/662306 Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Tested-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: check gpfifo size against requestSam Payne2015-04-04
| | | | | | | | | | | | | | | | | if a request is submitted larger than the allocated fifo, an error is returned immediately rather than waiting for timeout while enough space becomes available in the fifo (timeout will not trigger in this case) bug 1563401 Change-Id: I264dee2673dc8722034881f9e7db7bb137a8c0c8 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/665113 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move debug dump to HALAingara Paramakuru2015-04-04
| | | | | | | | | | | | Move the debug dump to HAL and add a stub for vgpu. Bug 1595164 Change-Id: Ifdcdd8a8caca7a41919dad075fee1c87032f53b0 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/662722 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: fix comptag alloc failureAingara Paramakuru2015-04-04
| | | | | | | | | | | | | setup_buffer_kind_and_compression() expects vm->big_page_size to be set, which was not done for the vgpu case. Bug 200064162 Change-Id: I15af3600fda0161aad2185ec7a12b560044cc171 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/662721 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use u32 for priv_cmd_queue get/put/sizeJanne Hellsten2015-04-04
| | | | | | | | | | | | | | | | Switch to a larger integer type for priv_cmd_queue get/put/size fields. The previous 16-bit int type overflowed on >= 2048 gpfifo buffer sizes. This triggered a div-by-zero kernel panic. Bug 1592391 Signed-off-by: Janne Hellsten <jhellsten@nvidia.com> Change-Id: Ibffcbbd145f39fdb4a63d05b1dcb42bb4b101795 Reviewed-on: http://git-master/r/667103 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: protect channel abort with submit lockKonsta Holtta2015-04-04
| | | | | | | | | | | | Bug 200065789 Change-Id: I59eb93c7929a77cd4de4be40fd7902cd05e536c7 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/665655 (cherry-picked from commit 4ee1893926557b01d7058a0a4c1c23e4476d7668) Reviewed-on: http://git-master/r/668850 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: fix list_add_tail in dmabuf stateKonsta Holtta2015-04-04
| | | | | | | | | | | | | | | | | Fix a memory leak: add the newly created state to the dmabuf priv's state list, instead of the other way around. Bug 1594784 Bug 200064154 Change-Id: I939746a254bb8bf4d06de7fcecba06c191da665f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/668758 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: nvgpu: cde: ignore spurious context releasesKonsta Holtta2015-04-04
| | | | | | | | | | | | | | | | Gpu channels may get spurious updates from at least nonstalling semaphore wait interrupts. Protect data structure sanity by ignoring releases on already released (= not in use) cde contexts. Bug 200062826 Change-Id: I5940a7557e902bcfcff1a7e8e4593472d9ac306c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/666235 (cherry picked from commit 47dc2f41eb8054b099b6eb9a4a7d82c97295d415) Reviewed-on: http://git-master/r/666657 GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
* gpu: gk20a: Removing erroneous increment statementIshan Mittal2015-03-20
| | | | | | | | | | | | | This must have occurred while rebasing dev-kernel-3.10 over kernel 3.18. This change corrects the mistake. Change-Id: I11fbc11105a032198828e8bc31da5ab92af0ffdb Signed-off-by: Ishan Mittal <imittal@nvidia.com> Reviewed-on: http://git-master/r/720240 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Fix/HACK for v3.18Dan Willemsen2015-03-18
| | | | Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
* host/gpu: Upgrade to new fence-based sync implementationDan Willemsen2015-03-18
| | | | Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
* gpu: remove devm_request_and_ioremapDan Willemsen2015-03-18
| | | | Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
* gpu: nvgpu: add error prints for do_idle() failureDeepak Nibade2015-03-18
| | | | | | | | | | | | | | Add error prints in gk20a_do_idle() to narrow down the failure point Bug 200064302 Change-Id: Iffe1151bdc200a79b88e273b3b01523f8e46d130 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/664446 (cherry picked from commit bf1cd9b5551d27cb5cc468795cd147376f48e482) Reviewed-on: http://git-master/r/666218 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: update regops whitelistMatt Craighead2015-03-18
| | | | | | | | | | | | | | Remove an undesired register from the regops whitelist on both gk20a and gm20b. Bug 1589732 Change-Id: I7747fafd3c2c32a9c5ce6388be73c7f61e509f0a Signed-off-by: Matt Craighead <mcraighead@nvidia.com> Reviewed-on: http://git-master/r/663373 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Send aligned addresses to allocatorSupriya2015-03-18
| | | | | | | | | | | | | | | | | | Bug 1587090 Bug 200050711 PMU dmem start address is unaligned. Allocator allocates aligned length amount of memory But address alloced is nto checked to be aligned, but free checks for alignment of addresses before free. For dmem case, frees never actually happened. This fix ensures addresses are aligned. Change-Id: I8b95f89940aa4d23355c3788dc95afb5c8867373 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/663140 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove gk20a sparse texture & PTE freeingTerje Bergstrom2015-03-18
| | | | | | | | | | | | Remove support for gk20a sparse textures. We're using implementation from user space, so gk20a code is never invoked. Also removes ref_cnt for PTEs, so we never free PTEs when unmapping pages, but only at VM delete time. Change-Id: I04d7d43d9bff23ee46fd0570ad189faece35dd14 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/663294
* nvgpu: gm20b: Ensure ACR boot failure is returnedSupriya2015-03-18
| | | | | | | | | | | | | | | | | | Bug 200059877 ACR boot failure is returned in falcon mailbox 0 return EAGAIN in case of ACR boot failure Change-Id: I683984402137bb42dd69f2d667191d5986144c17 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/660529 (cherry picked from commit 404c98b704bec5c707bd0c9b03364c8c6d546cbf) Reviewed-on: http://git-master/r/662476 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Mitch Luban <mluban@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Added GPMU app version for T18xMahantesh Kumbar2015-03-18
| | | | | | | | | | | | Added app version which allows to load & boot T18x GPMU. Bug 200064127 Change-Id: Iebcfcb984bfbdcd3fb55cf2155c5e75831d5ad95 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/663141 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Allow enabling/disabling MC interruptMahantesh Kumbar2015-03-18
| | | | | | | | | | | | Added method to enable/disable MC interrupt by unit Bug 200064127 Change-Id: I89e794d5b69a2a93642e2df437d6744bf595f021 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/661211 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cde: allow duplicate finish signalsKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | | Channel update callback for a channel that has no more cde jobs signals that a cde context is free. Spurious channel updates may still happen from at least nonstalling semaphore wait interrupts. Instead of scary WARNs, use only gk20a_dbg_info() for info prints in these harmless situations, and double check that only the first update starts a deleter work for temporary contexts. Change-Id: I68de8f35e2c366206c6efac3ee97025239e8bba2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> (cherry-picked from commit f56a941b4962c5479291cae48e2abca6067e3f13) Reviewed-on: http://git-master/r/660849 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: update regops whitelistMatt Craighead2015-03-18
| | | | | | | | | | | | | | Remove an undesired register from the regops whitelist on both gk20a and gm20b. Bug 1589712 Change-Id: I76e8ff1f4b68d6d5ce2c11adc08d984df7883e5e Signed-off-by: Matt Craighead <mcraighead@nvidia.com> Reviewed-on: http://git-master/r/663371 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: update regops whitelistSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | Update regops whitelist ranges with latest script output. Bug 1500195 Change-Id: I2c61bf068cf81e07f64cbe8a496db7c784a44d8d Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/607603 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Per-chip context creationTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Add HAL for context creation, and expose functions that T18x context creation needs. Bug 1517461 Bug 1521790 Bug 200063473 Change-Id: I63d1c52594e851570b677184a4585d402125a86d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660237
* gpu: nvgpu: Generic mem_desc & allocationTerje Bergstrom2015-03-18
| | | | | | | | | | | | Make mem_desc a generic container for buffers. Add functions for allocating and mapping buffers to an address space which store their data in mem_desc. Change-Id: I031643442c6fd41f5e7222fe9b7bfcaf9b784db5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660908 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: Simplify pagepool size queryTerje Bergstrom2015-03-18
| | | | | | | | | | | Make pagepool size query into a function instead of storing the value during boot time in a structure. This simplifies the structure and users of pagepool size do not need to worry about whether it has already been set. Change-Id: Iba16e840cdf9b6c39449730237aa7d8fdff47848 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660907
* nvgpu: gm20b: remove write to RO registerMatt Craighead2015-03-18
| | | | | | | | | | | | This register has no writeable fields. Change-Id: I86c132e866c7502a3d0e3a1b8b9942522051992b Signed-off-by: Matt Craighead <mcraighead@nvidia.com> Reviewed-on: http://git-master/r/660956 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: fix sparse warningsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | Fix below sparse warnings : kernel/drivers/gpu/nvgpu/gm20b/mm_gm20b.c:283:5: warning: symbol 'gm20b_mm_get_big_page_sizes' was not declared. Should it be static? kernel/drivers/gpu/nvgpu/gm20b/clk_gm20b.c:1055:12: warning: symbol 'gm20b_clk_get' was not declared. Should it be static? Bug 200032218 Change-Id: Id199b4b1853b3c933c91509fd550c7b5538cff29 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/660133 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* Revert "gpu: nvgpu: Enable syncpt reclaim only on gm20b"Timo Alho2015-03-18
| | | | | | | | | | This reverts commit 8eefb93c21934b101d7f423c38d9ea384a45fad6. Bug 1585422 Change-Id: I217e0ffe6c230ee3c63d9aec1c48ce9c41770468 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/659426
* gpu: nvgpu: Submit coverity fixesTerje Bergstrom2015-03-18
| | | | | | | | | | Clear ioctl buffer and fix double free, and error case memory leak. Bug 200059216 Change-Id: I21cc2b0f6a7e8fca09f72caf4c54d570b13f400b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/655347
* gpu: nvgpu: fix coverity issue in pmu loggingVijayakumar2015-03-18
| | | | | | | | | | | | | | | bug 200059216 use boolean to return status of hex search in the string Change-Id: Ifa53edccf54b9741b369f3a1ab5c79b6aad6cf86 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/656749 Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: debugger interface fixesAingara Paramakuru2015-03-18
| | | | | | | | | | | | | | | | | To run CUDA apps, the following minimal changes have been made: - power-gating is disabled for vgpu - regop rd/wr returns -ENOSYS Tools (debugger/profiler) support is known to not work and not needed at this time. Bug 200043227 Change-Id: I923caad78450e72d310fb9290cf2849ed5460ad5 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/592878 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Enable syncpt reclaim only on gm20bTerje Bergstrom2015-03-18
| | | | | | | | | | | | | gm20b has more channels than sync points. We use aggressive reclaim of sync points to offset that. Disable aggressive reclaim for gk20a because it is not needed there. Bug 1583849 Change-Id: I2a74b0504150a54cb8a97016effe20c5d905ac95 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/657095 Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu:nvgpu:gm20b: update pg sequencer dataVijayakumar2015-03-18
| | | | | | | | | | | | | | bug 1553301 sequencer data picked up from p4sw #19041893 Change-Id: I3d05972201572e3db31d1b46e93c03dda3e58d54 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/657023 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cde: remove unused obj_idsKonsta Holtta2015-03-18
| | | | | | | | | | | | | obj_id from gk20a_alloc_obj_ctx is not used and calling free_obj_ctx is effectively a no-op, since the corresponding channel is also freed. Bug 200059216 Change-Id: Icbe2cf5dc21d50cb007bf73829705451ada106ac Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/655368 Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add gk20a_scale_exit()Konsta Holtta2015-03-18
| | | | | | | | | | | | When removing the module, remove the device from devfreq and free resources allocated when scaling is initialized. Bug 1476801 Change-Id: I7bb0f8112a5bf7e5ce2fc56cf8af7059d910002c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/594444 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove platform device on exitKonsta Holtta2015-03-18
| | | | | | | | | | | | | Add ->remove() for undoing the ->probe() and ->late_probe() in gk20a_platform devices, and call it when gk20a is removed. Bug 1476801 Change-Id: Ic9b29c0a7ea4a4cae7b5a0f66774bd799eb28434 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/594443 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Export gm20b kind functionsTerje Bergstrom2015-03-18
| | | | | | | | | Bug 1567274 Change-Id: I21dadc0e473f174e7ae876b934dcd938bc956453 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/607007 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: cde: fix off-by-1 in buf allocationKonsta Holtta2015-03-18
| | | | | | | | | | Bug 200046882 Change-Id: I515e972f84cb7e1b17eef42ade6a4eaf0f8d71f8 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/559332 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:54:22 -0500