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* gpu: nvgpu: gv11b: Enable perfmon.Deepak Goyal2018-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | t19x PMU ucode uses RPC mechanism for PERFMON commands. - Declared "pmu_init_perfmon", "pmu_perfmon_start_sampling", "pmu_perfmon_stop_sampling" and "pmu_perfmon_get_samples" in pmu ops to differenciate for chips using RPC & legacy cmd/msg mechanism. - Defined and used PERFMON RPC commands for t19x - INIT - START - STOP - QUERY - Adds RPC handler for PERFMON RPC commands. - For guerying GPU utilization/load, we need to send PERFMON_QUERY RPC command for gv11b. - Enables perfmon for gv11b. Bug 2039013 Change-Id: Ic32326f81d48f11bc772afb8fee2dee6e427a699 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1614114 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: RPC interface supportMahantesh Kumbar2018-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Created nv_pmu_rpc_cmd & nv_pmu_rpc_msg struct, & added member rpc under pmu_cmd & pmu_msg - Created RPC header interface - Created RPC desc struct & added as member to pmu payload - Defined PMU_RPC_EXECUTE() to convert different RPC request to make generic RPC call. - nvgpu_pmu_rpc_execute() function to execute RPC request by creating required RPC payload & send request to PMU to execute. - nvgpu_pmu_rpc_execute() function as default callback handler for RPC if caller not provided callback - Modified nvgpu_pmu_rpc_execute() function to include check of RPC payload parameter. - Modified nvgpu_pmu_cmd_post() function to handle RPC payload request. JIRA GPUT19X-137 Change-Id: Iac140eb6b98d6bae06a089e71c96f15068fe7e7b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1613266 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add cleanup in gk20a_probe()Alex Waterman2018-01-18
| | | | | | | | | | | | | | | Add cleanup to the gk20a_probe() function since it will often fail due to probe deferal. These "failures" cause this function to be called multiple times and potentially allocate many resources over and over again, leaking the old allocations. Bug 200369627 Change-Id: Ic0bba0ae6542485135d9cb7393086e4460cd271d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640628 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: railgate platform only if it is not railgatedseshendra Gadagottu2018-01-18
| | | | | | | | | | | | | | | | | Avoid railgating platform, if it is already in railgated state. This is right thing to do and it also avoids ref counting issues related to fuse clock disable. Bug 200381275 Change-Id: Id745f9b878be129bf9b0cc972fadcfc102c8ddc2 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640548 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ramin_big_page_size default val is set to 64kbSeema Khowala2018-01-18
| | | | | | | | | | | | | | | | | | | | | | | | -MMU_CTRL_USE_PDB_BIG_PAGE_SIZE is set to TRUE and hence RAMIN_BIG_PAGE_SIZE should be set to 64KB i.e. val 1. By default this is set to 128KB i.e. val 0. -This change will also fix an issue where perfbuffer_enable and nvgpu_init_hwpm function pass 0 as big page size while initializing inst_block and due to which ramin_big_page_size does not get updated to 64KB and remains set to unsupported 128KB value. -Volta supports 64KB for big pages. Selecting 128KB for big pages results in an UNBOUND_INSTANCE fault. Bug 200327596 Change-Id: Ie304e4e5ff7bedaead27e9380d64c59013dd64ca Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639540 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv1xx: remove scg_type from channel infoseshendra Gadagottu2018-01-18
| | | | | | | | | | | | | scg_type for graphics_compute0 and compute1 is deprecated for gv1xx. Remove it from setting in the channel info. Bug 1842197 Change-Id: I37354adcd82bb0ab648e0f04d47de796b79f91cd Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640440 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: bypass_smmu debugfs changed to read onlySeema Khowala2018-01-18
| | | | | | | | | | | bypass_smmu is set based on whether device_is_iommuable or not during probe. It cannot be changed during runtime. Change-Id: I69fd29c87ea3873652a4eb95764f52dc40abf483 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640381 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: print ctxsw timeout info statusSeema Khowala2018-01-18
| | | | | | | | | | | | | | | | | | For ctxsw timeout failures, fifo_intr_ctxsw_timeout_info_status was not output as error print. Add it to help debugging ctxsw timeout failures Bug 2039371 Bug 2044497 Change-Id: I79d964fcda47847fdea6e8b59b68787c02e28379 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639509 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unexport gk20a_ce_create/delete_contextRichard Zhao2018-01-17
| | | | | | | | | | | | | | | | | No external referencing of them. Jira VFND-4713 Change-Id: If053bbdbb37e9bd4789bfd7cccb1aef035fbf317 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639674 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make graphics context property of TSGTerje Bergstrom2018-01-17
| | | | | | | | | | | | | | | | | | | | Move graphics context ownership to TSG instead of channel. Combine channel_ctx_gk20a and gr_ctx_desc to one structure, because the split between them was arbitrary. Move context header to be property of channel. Bug 1842197 Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639532 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: clean-up clock gating register listseshendra Gadagottu2018-01-12
| | | | | | | | | | | | | | | | | | | | | | | | | Following fb iso register is not valid for gv11b but hw headers has it. So, removing it manually from gating register list: 0x00100D1C Following sm blcg register not hooked up correctly in gv11b. So, removing it manually from gating register list: 0x00419c84 Once hw headers are updated, gating register tool will automatically remove them from kernel code. Bug 2042775 Change-Id: I4839b857656220566e53b66d3aead676893aaa59 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1636787 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: update whitelist regsSeema Khowala2018-01-12
| | | | | | | | | | | | | | | List generated for p4 sw cl 23385063 Bug 200375131 Change-Id: I9f58d7d1ab2659a86353a368c7e1e2284e5b760c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1634954 Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add l3 allocation supportAparna Das2018-01-12
| | | | | | | | | | | | | Modify rpc command parameter to support l3 cache allocation. Jira EVLR-1752 Change-Id: I1be00e04ee01c0763f46c0d0da6a112316cc7e1d Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616566 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: move t19x specific code to general codeRichard Zhao2018-01-12
| | | | | | | | | | | | | | - remove vgpu_t19x.h and tegra_vgpu_t19x.h - merge t19x specific ivc commands to the big enum - move TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT to constants Jira EVLR-2293 Change-Id: I34344bffa03bb69e1282b1f19382e3199f9ba105 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1636128 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Combine gk20a and gp10b free_gr_ctxTerje Bergstrom2018-01-12
| | | | | | | | | | | | | | gp10b version of free_gr_ctx was created to keep gp10b source code changes out from the mainline. gp10b was merged back to mainline a while ago, so this separation is no longer needed. Merge the two variants. Change-Id: I954b3b677e98e4248f95641ea22e0def4e583c66 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635127 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: Delete gm20b supportTerje Bergstrom2018-01-12
| | | | | | | | | | | | Delete gm20b vgpu support. It has not been supported for a long time and keeping it up-to-date is extra work. Change-Id: I3c06d29a79cb83d53a25d2242247b4eeabeab310 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635126 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add HAL for dumping ctxsw statisticsTerje Bergstrom2018-01-12
| | | | | | | | | | | | | | | | | Add HAL for dumping ctxsw statistics. The statistics are dependent on the architecture, and the function that calls this operation needs to be moved to gk20a. Bug 1842197 Change-Id: I285c74b8ddc8c7854c85b3fef4cbfc582098919e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1632681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle SM reported MMU_NACK exceptionDeepak Nibade2018-01-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upon receiving MMU_FAULT error, MMU will forward MMU_NACK to SM If MMU_NACK is masked out, SM will simply release the semaphores And if semaphores are released before MMU fault is handled, user space could see that operation as successful incorrectly Fix this by handling SM reported MMU_NACK exception Enable MMU_NACK reporting in gv11b_gr_set_hww_esr_report_mask In MMU_NACK handling path, we just set the error notifier and clear the interrupt so that the User Space sees the error as soon as semaphores are released by SM And MMU_FAULT handling path will take care of triggering RC recovery anyways Also add necessary h/w accessors for mmu_nack Bug 2040594 Jira NVGPU-473 Change-Id: Ic925c2d3f3069016c57d177713066c29ab39dc3d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631708 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: perf: fix coverity issueVijayakumar2018-01-12
| | | | | | | | | | | | | | | | remove recurring header file include coverity defect id: 2682953 bug 200291879 Change-Id: Iae53377ff1609c138a0c75a4cbf04afa3a533100 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1636579 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: runlist info mutex not needed for runlist_stateSeema Khowala2018-01-11
| | | | | | | | | | | | | | | | runlist_info mutex for the runlist being enabled or disabled in fifo_sched_disable_r is not needed to be acquired Bug 2043838 Change-Id: Ia9839ab7effbe7daf353c3a54f25a2b4914af5e8 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1630345 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: disable fifo_intr_0_runlist_eventSeema Khowala2018-01-11
| | | | | | | | | | | | | | | | | | | | | | runlist event interrupt is not needed to be enabled as s/w polls for preemption completion for preempts issued in RUNLIST_PREEMPT. Even though it is not enabled, intr will get set in fifo_intr_0 status register whenever RUNLIST_PRREMPT is successfully completed. Since intr is disabled, fifo intr will not be triggered but it will be handled during handling of other fifo interrupts whenever fifo intr is triggered. Bug 2039371 Change-Id: I0817c2b6e9f3f14958ca7c738392bc67875be5d5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1630283 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: get virtual SMs mappingThomas Fleury2018-01-10
| | | | | | | | | | | | | | | On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in vgpu constants to properly dimension the virtual SM to TPC/GPC mapping in virtualization case. Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping. Bug 2039676 Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631203 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: protect linux include with configDeepak Nibade2018-01-10
| | | | | | | | | | | | | | | | In fence_gk20a.c protect <linux/file.h> and <linux/fs.h> includes with config CONFIG_SYNC since they are only needed with this config enabled Jira NVGPU-487 Change-Id: I6c26aa0fbb4ee284129109c625a0e324d5caf235 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635471 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use chip specific zbc_c/z format regseshendra Gadagottu2018-01-10
| | | | | | | | | | | | | | Use chip specific gpcs_swdx_dss_zbc_c_format_reg and gpcs_swdx_dss_zbc_z_format_reg. These registers are different for gv11b/gv100 from gp10b/gp106. Change-Id: I9e209c878a11edc986ba4304ff60fcccbb5087aa Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635091 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fix for gfx preemptionseshendra Gadagottu2018-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Used chip specific attrib_cb_gfxp_default_size and attrib_cb_gfxp_size buffer sizes during committing global callback buffer when gfx preemption is requested. These sizes are different for gv11b from gp10b. For gp10b used smaller buffer sizes than specified value in hw manuals as per sw requirement. Also used gv11b specific preemption related functions: gr_gv11b_set_ctxsw_preemption_mode gr_gv11b_update_ctxsw_preemption_mode This is required because preemption related buffer sizes are different for gv11b from gp10b. More optimization will be done as part of NVGPU-484. Another issue fixed is: gpu va for preemption buffers still needs to be 8 bit aligned, even though 49 bits available now. This done because of legacy implementation of fecs ucode. Bug 1976694 Change-Id: I2dc923340d34d0dc5fe45419200d0cf4f53cdb23 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635027 GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: skip comptag re-initializationDeepak Nibade2018-01-10
| | | | | | | | | | | | | | | | | | | | | In case we need to re-initialize GR after floorsweeping TPC, gp10b_ltc_init_comptags() will try to allocate comptag memory again Skip this during re-initialization since it is unnecessary to re-allocate all those buffers Comptag buffer size is 33MB and reallocating causes huge memory leak anyways Bug 2031635 Change-Id: I935f96eb133283d6f935589c0e581e0997e980e2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1634737 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Free enabled flags on driver unloadAlex Waterman2018-01-10
| | | | | | | | | | | | Make sure the enabled flags are freed before the driver unloads. Bug 200369180 Change-Id: Ibac9ee61ca99bdfda03d76e393c7cd6cb6cc299a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1632752 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Suppress nvlink credits init msgTerje Bergstrom2018-01-09
| | | | | | | | | | | | | | Suppress message indicating nvlink credits initialization. Change-Id: I8cd9c64c10412cea783b3d3eeb271a3e1c68d29f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1632780 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: correct function arguments to fix QNX compilationSourab Gupta2018-01-09
| | | | | | | | | | | | | | | The patch changes the function argument from 'int' to 'unsigned int' to fix the QNX compilation failures. Change-Id: Iaee7850d8310bea693996ac618b95252ca5d1b35 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626397 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: gv11b: fix for gfx preemption"Alex Waterman2018-01-09
| | | | | | | | | | | | | | | | | | This reverts commit caf168e33ec12ff6f0ed90fd4aa7654c09eaa553. Might be causing an intermittency in quill-c03 graphics submit. Super weird since the only change that seems like it could affect it is the header file update but that seems rather safe. Bug 2044830 Change-Id: I14809d4945744193b9c2d7729ae8a516eb3e0b21 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1634349 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com>
* gpu: nvgpu: gv11b PMU ucode F/W version updateMahantesh Kumbar2018-01-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - F/W version update for gv11b PMU ucode of CL https://git-master.nvidia.com/r/#/c/1628288/ Current CL has PMU F/W version for ucode bin of P4 CL# 23378914 P4 CL# & its changes. - 23378914 - Don't post "PMU_PG_EVENT_IDLE_SNAP" event in method pgConvertPgInterrupts_GP10X() - 23355380 - Remove debug code included by mistake in P4 change list #23354716 - 23354716 - Made change to point CONVERT_PG_INTERRUPTS of gv11b to _GP10x - pgConvertPgInterrupts_GP10X() - Removed PMU halt upon FIFO preempt timeout in _fifoPreemptRunlist_GP10X() Bug 2039371 Bug 200377983 Change-Id: I8ce7cb926203b329308944235a06933768ed2a5f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1628380 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allocate from coherent poolDavid Nieto2018-01-08
| | | | | | | | | | | | | | | | | | | | Maps memory coherently on devices that are connected to a coherent bus. (1) Add code to be able to get the platform device node. (2) Create a new flag to mark if the device is connected to a coherent bus (3) Map memory coherently on coherent devices. bug 2040331 Change-Id: Ide83a9261acdbbc6e9fef4fc5f38d6f9d0e5ab5b Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1633985 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: init ch_wdt_timeout_msSeema Khowala2018-01-08
| | | | | | | | | | | | | This is needed for watchdog to work. Change-Id: Ic1e197e5f6701fafd8b614cd43bb610bdc8518ae Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1632230 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fix for gfx preemptionseshendra Gadagottu2018-01-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Used chip specific attrib_cb_gfxp_default_size and attrib_cb_gfxp_size buffer sizes during committing global callback buffer when gfx preemption is requested. These sizes are different for gv11b from gp10b. Also used gv11b specific preemption related functions: gr_gv11b_set_ctxsw_preemption_mode gr_gv11b_update_ctxsw_preemption_mode This is required because preemption related buffer sizes are different for gv11b from gp10b. More optimization will be done as part of NVGPU-484. Another issue fixed is: gpu va for preemption buffers still needs to be 8 bit aligned, even though 49 bits available now. This done because of legacy implementation of fecs ucode. Bug 1976694 Change-Id: I284e29e0815d205c150998b07d0757b5089d3267 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1630520 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Tested-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: include nvgpu types.h explicitly in fence.hSourab Gupta2018-01-08
| | | | | | | | | | | | | QNX needs defines for u32 data type, which is retrieved from nvgpu/types.h. We need to explicity include this for fence.h Change-Id: I0768042b8b10db550a1e321a0c3c1d86d981f9b0 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626401 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace pr_err with nvgpu_errSourab Gupta2018-01-08
| | | | | | | | | | | | | Replace the linux specific pr_err with nvgpu_err function Change-Id: I856a3030c62009b078a8cdfc0050b541a66e6eaa Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626400 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: make gv11b fifo function staticSourab Gupta2018-01-08
| | | | | | | | | | | | The patch makes 'gv11b_fifo_get_eng_method_buffer_size' function as static since it is being used only in this file. Otherwise, QNX throws compilation error. Change-Id: I96feaad8e77d11eabc78843d7dc29f749b55edab Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626399 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: replace usleep_range with nvgpu_usleep_rangeSourab Gupta2018-01-08
| | | | | | | | | | | The patch replaces the linux specific usleep_range usage with nvgpu_usleep_range OS agnostic function, in fifo_gv11b.c Change-Id: I8ada3ffc1b70caa571cbabe5c3973f37e819538b Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626398 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove dma-buf.h include in channelSourab Gupta2018-01-08
| | | | | | | | | | | | | | The patch removes the dma-buf.h include from channel_gk20a.c, now that there are no references to dma_buf present here. Change-Id: I079c3c3763e7ac4f91e43a4bc54a23ec8d5a23fa Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1626396 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* DNI: gpu: nvgpu: Increase GV100 ctxsw timeoutsDavid Nieto2018-01-05
| | | | | | | | | | | | | | | During bringup and before nvlink is up GV100 on the DDPX platform operates with a very, very slow sysmem link. In order to get sysmem test to pass it is neccesary to significantly increase most timeouts by an order the magnitude. Bug 2040544 Change-Id: I26858afde4ae80c70f86b47cfff674b6b00b5bf8 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627417 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix L2 ROP maskDavid Nieto2018-01-05
| | | | | | | | | | | | | | | | | L2 mask was assuming FS units contain valid information, but they do not. The new code checks if the L2 is FS before reading the L2/ROP mask Bug 2040328 Change-Id: Id07cc630e65cfc71ab8084a3700d884b6cd3430f Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627327 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: no hv support for write_sm_error_statePeter Daifuku2018-01-04
| | | | | | | | | | | | | | | | | There is no current need for a virtualized version of nvgpu_dbg_gpu_ioctl_write_single_sm_error_state, so return -ENOSYS when virtual. Bug 200331110 Change-Id: I223a6298eb4c891859f1c8252049f9a83d84ccb5 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631270 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Do not disable ELPG when committing buffersTerje Bergstrom2018-01-04
| | | | | | | | | | | | | Committing buffer addresses only writes to the memory. There's no need to disable ELPG for the duration, so drop the ELPG protection. Change-Id: I8d8d08506387197e4737e0311df4a20085496056 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631149 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gk20a specific optimizationTerje Bergstrom2018-01-04
| | | | | | | | | | | Remove compute optimization specific to gk20a. We do not support gk20a anymore. Change-Id: Ibd548eee8d891a667f28a451d586fcfaac7f026a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631144 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix erroneous gk20a_put() callDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | | | | | | With a recent rework we moved gk20a_get() call to nvgpu_ioctl_tsg_open(), but corresponding gk20a_put() call remained in gk20a_tsg_release() So if a TSG is opened and released from within kernel with APIs gk20a_tsg_open()/gk20a_tsg_release() we mistakenly drop extra refcount through gk20a_put() Fix this by moving gk20a_put() call to nvgpu_ioctl_tsg_release() which balances gk20a_get() call in nvgpu_ioctl_tsg_open() Bug 200374011 Change-Id: Id0cec0426e6231309dc530ab5c934dacaba9f8da Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1630969 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: return error code in failure casesDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | | In gk20a_ce_create_context(), if gk20a_tsg_open() or gk20a_open_new_channel() fails, we bail out from the function without setting the error code This could mislead the caller and report incorrect success Fix this by setting error code explicitly in failure cases Bug 200374011 Change-Id: Idf6cba4a57740107bada698295745352f7b5d5ac Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631506 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix TSG leak from CE codeDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | | | | | In gk20a_ce_delete_gpu_context(), we unbind the channel from TSG and close the channel. But we do not drop the TSG refcount leaking the TSG reference Fix this by explicitly dropping TSG refcount Also, do not explicitly unbind the channel from TSG gk20a_channel_close() will internally unbind the channel from TSG Bug 200374011 Change-Id: Ie4aa32f1d0bff4231f41aa2b33743cdc63e967c7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1629972 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: return error if TSG allocation failsDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | In gk20a_cde_load(), if TSG allocation fails we bail out the function without setting the error code and caller of this functions assumes CDE load is successful Fix this by setting explicit error code if TSG allocation fails Bug 200374011 Change-Id: I6e7bcb325fb0062605fa2f696da4abdeb34e241a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627117 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix TSG leak from CDE codeDeepak Nibade2018-01-04
| | | | | | | | | | | | | | | | | | | | | | | | In gk20a_cde_remove_ctx(), we unbind the channel from TSG and close the channel. But we do not drop the TSG refcount leaking the TSG reference After allocating sufficient contexts, we see TSG creation fails as below nvgpu: 17000000.gp10b: gk20a_cde_load:1286 [ERR] cde: could not create TSG Fix this by explicitly dropping TSG refcount Also, do not explicitly unbind the channel from TSG gk20a_channel_close() will internally unbind the channel from TSG Bug 200374011 Change-Id: If6d75b20d5e03d710c0597d7a320d1157206a2a5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1627116 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add golden_img_loaded flag to gr ctx descSourab Gupta2018-01-04
| | | | | | | | | | | | | | | The patch adds the boolean flag 'golden_img_loaded' to gr ctx desc. This is needed for refactoring the ctx initialization. Change-Id: I6d6df273e764a4cd06d062d59427dd33f4669778 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1617174 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-24 02:14:48 -0400