| Commit message (Collapse) | Author | Age |
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This method is called when setting up gr
hardware. It is meant to adjust preemption
parameters.
Bug 1593548
Jira VFND-1894
Change-Id: I0f5aa3212bec3058a0493366bed6fe2a365c9542
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1162625
(cherry picked from commit c2e6d12570af28b3aae087401d7f670df40d40bd)
Reviewed-on: http://git-master/r/1166987
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix coverity issues in debugfs related to null check
before accessing data member.
Fix coverity issues in sysfs related to error code
over-write and unintilized error code.
coverity ids: 20087564, 20087460, 20087461
Bug 200192125
Change-Id: If82288fca18464dca7093ce10f0beb1272489609
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1171943
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Define specific QoS notifier for common clk framework
and protect it with CONFIG_COMMON_CLK
This new API will first get min/max requirements from
pm_qos and set min/max freq values in devfreq
A call to update_devfreq() will then ensure that
new estimated frequency is clipped appropriately
between min and max values
This also ensures that frequency is set along with
all the book-keeping
Add below platform specific notifier callback and use it
with pm_qos_add_notifier()
int (*qos_notify)()
If qos_notify is set, then only register the callback
We currently support only one qos_id which is treated
as notifier for min frequency
Remove dependency on qos_id, and use appropriate QoS
APIs like pm_qos_read_min/max_bound()
Store devfreq's min/max frequency in struct gk20a
for reference
Bug 1772462
Change-Id: I63d6d17451d19c9d376b67df7db775b38929287d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1161161
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gk20a_tsg_bind_channel_fd(), API gk20a_get_channel_from_file()
already handles converting a channel fd to channel
Hence explicit fget(ch_fd) is not required and is unused
Coverity id : 32386
Bug 200192125
Change-Id: I28674cebf088240b8b15129a22f6743c856ed88f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1171713
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Properly check that flush method exists. Before
this change, it was inconditionnaly called from
poll function by accident.
Bug 1778951
Change-Id: Ibb8a5b7448bc4b7c475d60439e5b5bd1af9a12bf
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1168144
(cherry picked from commit 178967b91f2632e5b84ce6d11e24f2a8f49c52ea)
Reviewed-on: http://git-master/r/1170549
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add CE engine to vgpu engine list. CE engine is defined differently
for different GPUs, so we also add HAL for initializing the engine
info.
Bug 1780185
Change-Id: I5ae265551feac08d0c4d45402dd3277514e62b2d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1169720
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Tested-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lakshmanan M <lm@nvidia.com>
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When an allocator is created with a base of 0 the first allocated
block could well be 0. This appears to be an error since gk20a_balloc()
normally returns 0 for error cases.
This patch removes one block from the allocatable resources when base
is set to 0 so that code using gk20a_balloc() does not get tricked
into thinking valid allocations are OOM cases.
Change-Id: I641642d3f790c4c7860d0d1381f4db6f4f72e709
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1169764
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Compute a reasonable maximum order for buddy allocators that are
created with a max_order of 0. Previously the max_order was just
left as 0.
Change-Id: I5c2f878fcd390610a4c02ac65189138ec7db30c8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1169763
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added interface for privileged channel allocation to excute
the privileged method (ex. CE phys mode transfer).
JIRA DNVGPU-53
Change-Id: I07f9181720b14345cf5890919c2818dfcf505d86
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1169315
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit 6bbc169d33ae601b5947c1e54806b9f9bfa6054e.
channel_suspend() might cause new interrupts to trigger,
and if irqs are already disabled, then these interrupts will
not get served
Hence revert this patch, and move disable_irq() to
original place
Bug 200207867
Change-Id: I45617a1a0aa9a1f805dd937a34ebb572a61c05c0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1169380
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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following compilation error are reported with CONFIG_DEBUG_FS=n:
pci.c:246:7: error: 'struct mm_gk20a' has no member named 'ltc_enabled'
pci.c:247:7: error: 'struct mm_gk20a' has no member named 'ltc_enabled_debug'
possible compilation error(reported sometime):
gk20a_allocator.c:1163:13: error: 'gk20a_alloc_debugfs_init' defined
but not used
fixed by adding '#ifdef CONFIG_DEBUG_FS' for debug only code.
following variables from gk20a.c are not initialized from
CONFIG_DEBUG_FS=n path, it will cause kernel oops when booting:
gk20a->mm.bypass_smmu = platform->bypass_smmu;
gk20a->mm.disable_bigpage = platform->disable_bigpage;
gk20a->mm.has_physical_mode = true;
fix it by move them out from '#ifdef CONFIG_DEBUG_FS' section.
Bug 1778001
Change-Id: Ic2da36b3f500882748ee46a5150903244b697761
Signed-off-by: David Pu <dpu@nvidia.com>
Reviewed-on: http://git-master/r/1167358
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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ltc.init_fs_state was not called for vgpu, because
vgpu has its own poweron function. fixed it.
Bug 1778448
Change-Id: I023625c3e2efc86e72e9dcd04195c5d0b3d0eada
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1165969
(cherry picked from commit 3304b459593e92650cb772301e9c5745abb6c371)
Reviewed-on: http://git-master/r/1169050
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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CUDA needs it disabled.
Bug 1775453
Change-Id: Ic6d5050f9fda259337668e2a245c05e27d65e047
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1162765
(cherry picked from commit 44b48d84e75ced2fd9eecebbe94a0289c527c0c2)
Reviewed-on: http://git-master/r/1169049
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Cancel channel watchdog timeout during channel suspend
This should help fix race conditions when watchdog is triggered
during shutdown
Bug 200209309
Change-Id: I6cf740d854c27985217a1a76afa822e3126d4153
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1168613
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This patch_context map/unmap pair has become a mere wrapper for the more
general gk20a_mem_{begin,end}(). To be consistent about mappings,
require that each patch_write is surrounded by an explicit begin/end
pair, instead of relying on possible inefficient per-write map/unmap.
Remove also the cpu_va check from .._write_end() since the buffers may
be exist in vidmem without a cpu mapping.
JIRA DNVGPU-24
Change-Id: Ia05d52d3d712f2d63730eedc078845fde3e217c1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1157298
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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-update get_netlist_name ops declaration to support
to load GPU FW based on GPU-ARCH
-"GAxxx" string used to get size for "gm204/" or
"gm206/" which will added to NETIMAGE path like
"gm204/NETC_img.bin"
Change-Id: I5bfa13df014533a885c4328d3c767e51c29f9255
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1166783
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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1) Keep the __user tag in the type of the user gpfifo when copying,
2) use NULL instead of 0 for initializing user_gpfifo pointer.
Bug 200067946
Change-Id: I631b4bca44ded0900204134338fa1d62d0017df0
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1168441
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use gk20a_mem_*() accessors for gpfifo memory in work submission instead
of direct cpu accesses in order to support other apertures than sysmem.
The gpfifo memory is still allocated from sysmem for dgpus too.
Split the copying of priv_cmds and the main gpfifo to be submitted in
gk20a_submit_channel_gpfifo() into separate functions.
JIRA DNVGPU-21
Change-Id: If271ca8e7e34235f00d31855dbccf77c0008e10b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1145923
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit edd080b05ab118307c7c7b01426ea1e7c1cc9be7.
Re-enable the watchdog since power management races
are now resolved
Bug 200198908
Change-Id: I74b97e564583aaedd858bc968adcfcaa275ea739
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1165746
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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vgpu has not implemented batch map buffer yet, so report it in gpu
characteristics.
Bug 200201431
Change-Id: Ia9bfd71735889706242f0c06a1c44c5ed318ab6d
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1157467
(cherry picked from commit c6999995f9a48f645d6ffb6b7361d29cf641e5e3)
Reviewed-on: http://git-master/r/1156636
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use the general video memory allocator for reserving wpr space for acr
ucode blob instead of crafting a mem_desc manually.
Jira DNVGPU-16
Change-Id: Ie1b1e4b76b9678a33f4ef10ddcbf85259bfab5fd
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1165643
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1395833
Change-Id: Id0d427b6a1ddaecfeec33c61a6161679cf596c92
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1159588
(cherry picked from commit d33aa89420990626fb377c56ed5517a00f717c2a)
Reviewed-on: http://git-master/r/1158897
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move all places that read ptimer to use the callback.
It's for add vgpu implementation of read ptimer.
Bug 1395833
Change-Id: Ia339f2f08d75ca4969a443fffc9a61cff1d3d2b7
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1159587
(cherry picked from commit a01f804684f875c9cffc31eb2c1038f2f29ec66f)
Reviewed-on: http://git-master/r/1158449
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Allow nvgpu to identify sync_pts that were made by nvgpu so that
the underlying data structures can be accessed. This is important
for the semaphore fast-path that allows nvgpu to skip doing a
long CPU wait on a sync_fence.
Bug 1732449
JIRA DNVGPU-12
Change-Id: Iea43de21d2d7a4e75db6b6dbf24efb78ce64d619
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1162688
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Replace an accidental non-breaking space character with a normal space,
fixing the "ignoring unsupported character" build warning.
Change-Id: Ib3faca8489f083bb0027a8cfea82b256221b4e43
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1165134
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-34
Change-Id: Ib9618bdd928a02917b40e6f9619265bf27aa6879
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1162632
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add in-nvgpu APIs for allocating and freeing mem_descs in video memory.
Changes for gmmu tables etc. will be added in upcoming changes.
Video memory is allocated via nvmap by initially registering the
aperture size to it and binding it to a struct device, and then going
via the usual dma alloc. This API allows also fixed-address allocations,
meant for reserving special memory areas at boot.
The aperture registration is skipped completely if vidmem isn't found
for the particular device.
gk20a_gmmu_alloc_attr() still uses sysmem, and the unmap/free paths
select internally the correct path by the mem_desc's aperture.
Video memory allocation is off by default, and can be turned on with
CONFIG_GK20A_VIDMEM.
JIRA DNVGPU-16
Change-Id: I77eae5ea90cbed6f4b5db0da86c5f70ddf2a34f9
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1157216
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use snprintf instead of sprintf to avoid
any buffer overflows.
Bug 200192125
Change-Id: I6df43c6d6ee62677f5fd4d4e99f16be77c9e101e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1164312
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Rename alloc_fence() to gk20a_alloc_fence() and allow this function
to be called by the channel_sync_gk20a.c code.
Bug 1732449
JIRA DNVGPU-12
Change-Id: Ic17131db2c8545832a2e8caacbd092cf970af4d1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1162687
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Export gk20a_free_priv_cmdbuf() so that the channel_sync_gk20a.c code
can call this function. This is necessary for error paths in the
semaphore wait/incr functions.
Bug 1732449
JIRA DNVGPU-12
Change-Id: Id2ea13e5553d50475ee1bbf94781e18590321fdf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1162686
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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When debug dump is called from an interrupt thread, we do not want
to call gk20a_busy() because it causes race in case rail gating is
being engaged at the same time. It has to be called from all debugfs
paths.
Bug 200198908
Bug 1770522
Change-Id: I7eda7d029b0a59cce0320ecc1b750dc2f4d7ccf0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1163440
GVS: Gerrit_Virtual_Submit
Tested-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 200198908
Change-Id: I4dfb3517f5467f8b5449e65290453ba1c828243d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1163439
Tested-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Do not register device for debug dump to nvhost. This can cause races
if nvhost calls debug dump spew at the same time when GPU is being
powered off.
Bug 200198908
Bug 1770522
Change-Id: Ia7e57437d647041e82dd4c61ffd08fb1cbe1f32f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1163441
GVS: Gerrit_Virtual_Submit
Tested-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Do not spew an error when choosing the default runlist for engine. That is
normal behavior.
Change-Id: Ide786712f3f74bf59aee48de98c2186db1d97378
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1163511
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Tested-by: Lakshmanan M <lm@nvidia.com>
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In some of the conditionally compiled code in the nvgpu driver there
are places where the code looks like:
#ifdef LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0)
some-loop {
#else
a-diff-loop {
#endif
/* Some code... */
}
This leaves unbalanced curley braces: two open braces for one close
brace. This messes up some editors syntax highlighting and auto-
indentation features.
This patch puts in the extra brace. It's not necessary for compiling
code but it makes some editors much happier.
Change-Id: Ida28bc001cc840fe52a43982db934d49c07cc7d3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1153668
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Extend the existing NVGPU_GPU_IOCTL_OPEN_CHANNEL interface to allow
opening channels for other than the primary (i.e., the graphics)
runlists. This is required to push work to dGPU engines that have
their own runlists, such as the asynchronous copy engines and the
multimedia engines.
Minor change - Added active_engines_list allocation
and assignment for fifo_vgpu back end.
JIRA DNVGPU-25
Change-Id: I3ed377e2c9a2b4dd72e8256463510a62c64e7a8f
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1161541
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Instead of going via gk20a_mem_{wr,rd}32() on each iteration, do direct
memcpy/memset with sysmem, and minimize the enter/exit overhead with
vidmem.
JIRA DNVGPU-23
Change-Id: I5437e35f8393a746777a40636c1e9b5d93ced1f6
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1159524
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: I3f1645ed7a465c93b0a0a6f885ef77bea0066ed0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1160372
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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If PMU version is not supported, gk20a_pmu_init returns an error
code. Check the error code and fail poweron if gk20a_pmu_init
fails.
Change-Id: Ia1d6a6fcbcc5a144d2e5bc88734df778e887fa53
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1160371
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Rework how the messages in the channel timeout handler to be a little
bit more verbose and more clear about what is happening.
Bug 1732449
JIRA DNVGPU-12
Change-Id: Ifc018d99c647b3036caa8ad453e5e3dfc4151396
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1153669
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Remove the gp_get and gp_put pointers from the priv_cmdbuf code. These
pointers appear to track the position of th the priv_cmdbuf in the gp_fifo.
However, these pointers are not used for anything nor are they needed for
anything in the future. This code appears to be a relic left over from the
past.
Change-Id: Ibed1a6d51fa0cac12c5e0429760e8e2f611fc899
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1161859
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement NVGPU_GPU_IOCTL_GET_ENGINE_INFO for retrieving the
list of supported engines and their corresponding run list id:s.
JIRA DNVGPU-25
Change-Id: I8703388660190f7dcb509c0676f283ca4b820b6f
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1160939
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fixed the following sparse warnings:
- warning: symbol 'gm206_ce_isr' was not declared.
Should it be static?
- warning: symbol ''gm206_ce_nonstall_isr' was not declared.
Should it be static?
Bug 200088648
Change-Id: I30f66ba4225d5544d6110bc4a70235234ad4001d
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1161604
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gk20a_event_id_poll(), we always set the mask value
and return it. This causes poll() from UMD to be always
successful irrespective of event is really generated or not
Fix this by adding a flag event_posted for each event
Set this flag while posting the event
In gk20a_event_id_poll(), set the mask value only if
this flag is set. If flag is set, set mask and clear the flag
Bug 200089620
Change-Id: If14236547c611fe4bfa1410ff5b69c9fa02d43bb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1160253
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- ACR interface update to support
next GPU chip ACR boot
- Udpate falcon ID
JIRA DNVGPU-34
Change-Id: Ic9e5e1f9bd965dbb65b4feaadcf63e457b49263b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1161695
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- update PMU interface/code to support
latest version of secure boot FW
- Add PMU FW version for next GPU support
- can_elpg check in pmu_setup_hw helps
to fix queue error
JIRA DNVGPU-34
Change-Id: Iecf47fbc5b71cbf0f4bcdfeafad5c635cb6bff82
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1161107
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Events like bpt int/pause will help cuda work properly.
Bug 200173403
VFND-1568
Change-Id: I29e534969028bf08aedd81c99f5a536779f431d1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1159621
(cherry picked from commit a266e53c514639e15ed166e2c8ce5a55efc48eda)
Reviewed-on: http://git-master/r/1152154
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 200173403
VFND-1568
Change-Id: I3636a77bbbbd719e961dce5ca7ca7bdd5aa33881
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1159620
(cherry picked from commit b22fb6518da15a09c3e298213af5e60b8e6907a2)
Reviewed-on: http://git-master/r/1155403
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add forced channel reset support for vgpu
Bug 200187507
JIRA EVLR-337
Change-Id: I48e3e2b430f3a4ae94244225232902a8c037cb07
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1154781
(cherry picked from commit abd6688801fe76c822d6f67f554c18705d9f23d6)
Reviewed-on: http://git-master/r/1161259
GVS: Gerrit_Virtual_Submit
Tested-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit 2219f38727ffa17291e15c1898bd3e65f43d09fd. It leaves
GPU in on state for some tests that require powering down GPU.
Change-Id: I79d44fed729e98692021c57bbeff6a0ef2e8c983
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1161846
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