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* gpu: nvgpu: suspend context support for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | Add API gr_gp10b_suspend_contexts() to support context suspend on gp10b sequence to suspend: - disable ctxsw - loop through list of channels - if channel is ctx resident, suspend all SMs - if CILP channel, set CILP preempt pending = true - resume all SMs - otherwise, disable channel/TSG - enable ctxsw - if CILP preempt is pending, wait for it to complete Bug 200156699 Change-Id: Id9609077c283f99f420ad21c636b29f74b8eff6b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1120334 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Wait for BAR1 bindTerje Bergstrom2016-12-27
| | | | | | | | | | | Wait for BAR1 bind to complete before continuing. The register to wait exists Maxwell onwards. Change-Id: Icf03ae66aeb265808c4ba8da24ba4e1ebb91564e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1123939 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Use sysmem aperture for SoC memoryTerje Bergstrom2016-12-27
| | | | | | | | | | | | | In Tegra GPU, SoC memory has to be accessed as vidmem. In discrete GPU, it has to be accessed as sysmem. Change-Id: Id26588df17b4921533804f72bc8c0ac3892ae154 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1122591 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: gp10b: Add litter values HALTerje Bergstrom2016-12-27
| | | | | | | | | | | Move per-chip constants to be returned by a chip specific function. Implement get_litter_value() for each chip. Change-Id: I8bda9bf99b2cc6aba0fb88a69cc374e0a6abab6b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1121384 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: register to nvhost for debug dumpDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | Register debug dump callback gk20a_debug_dump_device() to nvhost using nvhost_register_dump_device() Unregister the callback in gp10b_tegra_remove() Bug 200188753 Change-Id: I9161cfdf969208bd8b6160742bf89e327aa2a6b4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1126792 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: return from scale_init() if no profileDeepak Nibade2016-12-27
| | | | | | | | | | | | In gp10b_tegra_scale_init(), return immediately if CONFIG_GK20A_DEVFREQ is disabled and profile is NULL Change-Id: I08e15afdc72bef62a4fb43f30b74cebf8a4b0d68 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1125444 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: pass bool pointer to debugfs_create_bool()Deepak Nibade2016-12-27
| | | | | | | | | | | Port the change 621a5f7ad9cd1ce7933f1d302067cbd58354173c from kernel.org to the nvgpu driver Change-Id: I3a8aa873e1f0b601bfe89f836c400113e50b638e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1125443 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gp10b: Support GPUs with no physical modeTerje Bergstrom2016-12-27
| | | | | | | | | | | | Support GPUs which cannot choose between SMMU and physical addressing. Change-Id: Ic097fccb313d98fcea918a705eefb5cd619138f1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1122590 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Use device instead of platform_deviceTerje Bergstrom2016-12-27
| | | | | | | | | Use struct device instead of struct platform_device wherever possible. This allows adding other bus types later. Change-Id: I90623c020919ca8e2e5b31d53914c324d2dc6af9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120464
* gpu: nvgpu: Add fbpa number and stridePeter Daifuku2016-12-27
| | | | | | | | | | | | | Add fbpa number and stride, used in hwpm context switch code Bug 1648200 Change-Id: I44570c072b1266d7ec2fc5dfb7fa73000ac01831 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1120451 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: disable force_reset_in_do_idleSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Since gpu rail gating is enabled, force_reset in idle can be disabled. Bug 200183798 Change-Id: I04ed04b66e3059459ec32cbffbfdb6756b009200 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1120147 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Sync with register generatorTerje Bergstrom2016-12-27
| | | | | | | | | Use re-generated register definitions. This synchronizes kernel with the register generator. Change-Id: I5ad34ad0b92327091758a2d10581a1b4170fa919 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120811
* gpu: nvgpu: post CILP_PREEMPTION_STARTED/COMPLETE eventsDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | Remove posting of events using old channel event API i.e. gk20a_channel_post_event() Also, update gk20a_channel_semaphore_wakeup() to post events when called from ce2_nonblockpipe_isr() Bug 200089620 Change-Id: I677cdab11183a649663ff9272a527c63b9994430 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1112275 (cherry picked from commit 4840efda393cd5928f1a8463db8b52cc586860bc) Reviewed-on: http://git-master/r/1120289 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Determine ECC-enabled units for GP10BSami Kiminki2016-12-27
| | | | | | | | | | | | | | | | Determine ECC-enabled units for GP10B by reading fuses/registers. Bug 1637486 Change-Id: I6431709e3c405d6156dd96438df14d4054b48644 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/780992 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120463 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move t18x code to kernel-nvgpu-t18xAlex Van Brunt2016-12-27
| | | | | | | | | | | | | | Part of moving the nvgpu driver out of the common kernel is moving the T18x part of the nvgpu driver out of kernel-t18x. So, update the Makefile to replect this change. bug 200187033 Change-Id: I61288943ee210840e483b3e3e14758d4a47a0a2f Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com> Reviewed-on: http://git-master/r/1119965 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: add emc clock requestSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Use Bandwidth manager API to request required emc clock. Bug 1673672 Change-Id: I909213d2a69a45939247fd079b1c57ce93be6e0e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/843777 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvpgu: setup fecs_trace hal operationsThomas Fleury2016-12-27
| | | | | | | | | | bug 1648908 Change-Id: I630f74f09e0a4143f5028c88634b9793ec86b279 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1022730 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add function to access ptimer timeArul Sekar2016-12-27
| | | | | | | | | | | | | | | bug 1648908 Change-Id: I32211b13489b21eba25f7473a18b9d1a303d2642 Signed-off-by: Arul Sekar <aruls@nvidia.com> Reviewed-on: http://git-master/r/1029733 Reviewed-by: Arun Gona <agona@nvidia.com> Tested-by: Arun Gona <agona@nvidia.com> Reviewed-on: http://git-master/r/1111716 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Update regops whitelistTerje Bergstrom2016-12-27
| | | | | | | | | | | | Update regops whitelist with two new registers. Bug 1734151 Change-Id: Id09bdfb1733620bb75d4558299c5e9c7f66bb00b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1029772 GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com>
* gpu: nvgpu: gp10b: update prod setiingsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Add/update following prod settings: blcg ce slcg ce2 Change-Id: I10a62d980479ad23efd7033d29e269c4aac08834 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1030986 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Allow importing makefile via includeTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Refactor makefiles so that there is one makefile, and that file can be included in the main nvgpu build. Bug 1476801 Change-Id: I23ac451d695fc64064de2300e83b9d9487c52743 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1028353 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: t18x: update blcg prod settingsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Update prod settings to disable stall blcg. Bug 1729471 Change-Id: I1123bf47159fc9dbb1223aebcacf37361b90743f Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1026611 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: only create ECC stats onceAdeel Raza2016-12-27
| | | | | | | | | | | | | | The ECC sysfs stat creation function is called on GR init. GR can get initialized multiple times but we only need to create the ECC stats once. Therefore, add a check to avoid creating duplicate stat sysfs nodes. Change-Id: Ifb338e57643f2f15492df137d2a7521e0c990cf2 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/1021660 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: make local symbol staticAmit Sharma2016-12-27
| | | | | | | | | | | | | | | | Fixed the following sparse warning by making local symbol static: - platform_gp10b_tegra.c:365: warning: symbol 'ecc_hash_table' was not declared. Should it be static? Bug 200088648 Change-Id: Iea1a682c3ee0609730366d44fab91849cd59c9ad Signed-off-by: Amit Sharma <amisharma@nvidia.com> Reviewed-on: http://git-master/r/1022410 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: t18x: update slcg prod settingsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Update prod settings to disable slcg pbdma related domains. Bug 1703083 Change-Id: I9f9192da69d07c5cea5bc7d79a031e5d2428b685 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1022219 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "Revert "gpu: nvgpu: gp10b: enable gpu rail gating""Seshendra Gadagottu2016-12-27
| | | | | | | | | | | This reverts commit 7c1f6f0b2998c354f315b431e00f3c8f861cb190. Bug 200176691 Change-Id: Ia546513ec5c61999f6eb4d56ccd7e45ae072167c Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1020813 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ECC overrideSupriya2016-12-27
| | | | | | | | | | | | | | | | -sysfs functions to call into LS PMU and modify ECC overide register Bug 1699676 Change-Id: Iaf6cc3a86160b806e52ab168577caad42b2c5d22 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/921252 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: gp10b: enable gpu rail gating"Prashant Gaikwad2016-12-27
| | | | | | | | | | | | | | | | | | This reverts commit 71b59d75fc49e2159830026bce387ef4d829faa8 since it causes suspend_sanity to fail on quill platform. On system resume, we see the following error dump from GPU gk20a 17000000.gp10b: gk20a_channel_timeout_handler: Job on channel 501 timed out gk20a 17000000.gp10b: gk20a_fifo_set_ctx_mmu_error_ch: channel 501 generated a mmu fault gk20a 17000000.gp10b: gk20a_set_error_notifier: error notifier set to 31 for ch 501 gk20a 17000000.gp10b: gk20a_channel_timeout_handler: Job on channel 509 timed out Change-Id: I61bc3b0745fe136675ab79b13f54e9126602f51c Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-on: http://git-master/r/1017967 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gp10b: enable gpu rail gatingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | Bug 1698618 Change-Id: Iabfd726891165d7879376ab96445b7b81b907153 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/841856 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Enable adaptive ELPGMahantesh Kumbar2016-12-27
| | | | | | | | | | | | ELPG is enabled on TOT. Bug 200144583 Change-Id: Icbdcb5f575a4ca37becf47b098fbd6a1f89feec7 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1013845 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add ECC stats sysfs nodesAdeel Raza2016-12-27
| | | | | | | | | | | Add sysfs nodes for querying ECC single/double bit error counts. Bug 1699676 Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935363 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pass channel pointer to handle sm exceptionDeepak Nibade2016-12-27
| | | | | | | | | | | | | Pass faulting channel pointer to gr_gk20a_handle_sm_exception() instead of NULL Bug 200156699 Change-Id: I909327e2a000bea8bc91cfd0820a759960664b46 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1011289 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: fix sparse warningDeepak Nibade2016-12-27
| | | | | | | | | | | | | | fix below sparse warning : drivers/gpu/nvgpu/gp10b/gr_gp10b.c:1364:5: warning: symbol 'gr_gp10b_pre_process_sm_exception' was not declared. Should it be static? Bug 200088648 Change-Id: Ie55ffc12eb653b10358001e2aef8766562fd0df9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1009938 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: vgpu: fix sparse warningsRichard Zhao2016-12-27
| | | | | | | | | | | Bug 200088648 Change-Id: I61be7b4787e9bc9bac310a8739977f43c38a67ee Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1000174 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: post events on all channels of TSGDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | While posting CILP preemption complete event to user space, raise the event to all channels of TSG (if channel is part of TSG) This is a WAR until we have proper sync mechanism with user space to raise CILP events Bug 200156699 Change-Id: Ieedc866498a8c5464cf65962257a803b37da6826 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1001696 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add CILP support for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CILP support for gp10b by defining below function pointers (with detailed explanation) pre_process_sm_exception() - for CILP enabled channels, get the mask of errors - if we need to broadcast the stop_trigger, suspend all SMs - otherwise suspend only current SM - clear hww_global_esr values in h/w - gr_gp10b_set_cilp_preempt_pending() - get ctx_id - using sideband method, program FECS to generate interrupt on next ctxsw - disable and preempt the channel/TSG - set cilp_preempt_pending = true - clear single step mode - resume current SM handle_fecs_error() - we get ctxsw_intr1 upon next ctxsw - clear this interrupt - get handle of channel on which we first triggered SM exception - gr_gp10b_clear_cilp_preempt_pending() - set cilp_preempt_pending = false - send events to channel and debug session fd Bug 200156699 Change-Id: Ia765db47e68fb968fada6409609af505c079df53 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/925897 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: mask hww_warp_esr for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | Add API gp10b_mask_hww_warp_esr() to mask hww_warp_esr appropriately on gp10b Bug 200156699 Change-Id: I451b5e949bd4e6d286e5d0c7cd7616e6cfaf3ea9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/927129 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add ECC supportAdeel Raza2016-12-27
| | | | | | | | | | | | | Add ECC exception handling support for SM, TEX, and LTC. Bug 1635727 Bug 1637486 Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935362 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: clean-up pmu init operationsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Removed unwanted initlization of function pointer. Bug 200157852 Change-Id: I3b44ccce366f1b72c3ff769a7b9ab350bb2c0066 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/843218 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: enable power gatingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Enable engine level power gating(elpg) Bug 200144583 Change-Id: I66f3be841625c2c9e07cafbf19af8f1dbdbfd390 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/818637 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add delay cycles before engine gatingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | For copy engine, add 16 clock cycle delay before engine clock gating. Bug 1717152 Change-Id: Ife92299c052f44000bc0d900f0129a2eab13f3b5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/998408 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: enable gradual slowdownSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Enable gradual slowdown for gp10b and also correct thermal slowdown factors with extended mode. Bug 1719974 Change-Id: I31a5d7df71c98135273a980c49b70bc76fac0b40 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/933279 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: bitmap allocator for comptagsKonsta Holtta2016-12-27
| | | | | | | | | | | | | Restore comptags to be bitmap-allocated, like they were before we had the buddy allocator. Bug 200145635 Change-Id: I681493871096f437014b7eca1182fefbaf7f6a74 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/839240 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: enable semaphore acquire timeout for gp10bRichard Zhao2016-12-27
| | | | | | | | | | | | | | | | | It'll detect dead semaphore acquire. The worst case is when ACQUIRE_SWITCH is disabled, semaphore acquire will poll and consume full gpu timeslicees. The timeout value is set to half of channel WDT. Bug 1636800 Change-Id: Idbd4bfa52981e8a849b62a168e3a6828330112f5 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/928830 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Refresh regops whitelistTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Context & global whitelists are same, so delete second copy. Update the list. Bug 200164983 Change-Id: I440ce04316120b8128baeabc002c55436cf41d5b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/931178 GVS: Gerrit_Virtual_Submit Reviewed-by: Sandarbh Jain <sanjain@nvidia.com> Tested-by: Sandarbh Jain <sanjain@nvidia.com>
* gpu: nvgpu: vgpu: update interface to free GR ctxAingara Paramakuru2016-12-27
| | | | | | | | | | | | | | | | The server only releases ownership of the ctxsw buffer mappings after the GR ctx has been released. Update the sequence to account for this. JIRA VFND-1117 Bug 1708163 Change-Id: I3aed015805b4ca51433e7d37ad32de2f8353999f Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/922817 Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: fix setting gr_pd_ab_dist_cfg1_r()David Li2016-12-27
| | | | | | | | | | | | | gr_*__set_alpha_circular_buffer_size() left max_batches field of gr_pd_ab_dist_cfg1_r as 0 which results in too many alpha beta transitions and poor performance when tessellation or geometry shaders are used Change-Id: Ic3673f45b60674b3527641a6fdda0cedc6861db5 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: http://git-master/r/840079 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: fix set_circular_buffer_sizeDavid Li2016-12-27
| | | | | | | | | | | | | | | It didn't set gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r causing a GPU MMU fault when used. Bug 200141640 Bug 200141981 Bug 200141640 Change-Id: I8b9f71e480553ead2827ff1f1dde2ba2e6efe697 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: http://git-master/r/807694 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Recreate HW headersTerje Bergstrom2016-12-27
| | | | | | | | | | | Add gradual slowdown registers, and fix names for L2 flush registers. Change-Id: If085c4febef494ae299d2147ca5201cd373bee0b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/839369 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: gp10b: Add tile caching registersTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Add tile caching registers to access map. Bug 1692373 Change-Id: Ic95fce02c564fa8d5556543a744c9828b542fb1f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/812352 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 19:59:23 -0400