| Commit message (Collapse) | Author | Age |
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Remove a variable which is assigned to but never used.
Add proper include (<nvgpu/log2.h>) for ilog2().
JIRA NVGPU-525
Change-Id: I42f3fddad9c294dc64343082e1dbd44b19120089
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673816
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gv100 does not have new fifo ctxsw timeout
interrupt that is present on gv11b. Use non gv11b
sched error and ctxsw timeout handlers.
Bug 2069807
Change-Id: I9dc2b8d9212145d7a1b0fef656aa20d2f073ea13
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1668401
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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RM server will notify clients with TEGRA_VGPU_EVENT_SET_ERROR_NOTIFIER
whenever .set_error_notifier is called. Clients will set error notifier
accordingly.
Jira VQRM-3058
Change-Id: I2f435335867cce5dfd7fddb718ac6a1ff7cd66ae
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1679711
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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RM server uses the command to notify clients to abort and clean up a
channel. Clients will set has_timedout at the same time.
Jira VQRM-3058
Change-Id: Iebd28ccdae52dd789ee93d65c4e816b83df8d891
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1679710
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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RM Server will implement callback for semaphore wakeup and broadcast
event TEGRA_VGPU_EVENT_SEMAPHORE_WAKEUP. The patch adds handling of the
event in vgpu code.
Jira VQRM-3058
Change-Id: Ife38eff8252f5b4036e6df71f1c64c99cb58c1b5
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676240
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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bar1/userd setup is different for RM server. created common function
gk20a_init_fifo_setup_sw_common.
Jira VQRM-3058
Change-Id: I655b54e21ed5f15dcb8e7b01bd9cd129b35ae7a3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665691
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RM Server overrides it for handling stall interrupts.
Jira VQRM-3058
Change-Id: I8b14f073e952d19c808cb693958626b8d8aee8ca
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1679709
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RM Server acts differently for channel suspend/resume.
Jira VQRM-3058
Change-Id: If41e3099164654db448d1157fd7f51dd00c5e201
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1679707
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RM Server acts differently for ctxsw timeout check. It won't check
GP_GET or accumulated timeouts, but notify guest and go to recovery.
Jira VQRM-3058
Change-Id: I428aea34dc517311eb7e73feb556145e916309fb
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1679706
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Channel abort clean up is only needed by native and vgpu driver but not
RM server. RM server expects guest will clean up itself. RM server
should not set the callback.
Jira VQRM-3058
Change-Id: I11b49b6f2d51c871e31de16955d487dca82609cb
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1679705
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The patch declares globally few channel/fifo HAL functions
required for QNX code compilation (as they are being referred
elsewhere in QNX code). This is required as a part of
bringing in the nvgpu Channel/FIFO HAL into QNX.
Jira VQRM-3058
Change-Id: Ia176535b64de981d2f7ddb20f62015a0da74fd2a
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1662411
GVS: Gerrit_Virtual_Submit
Tested-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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-Dump timeout save0 and save1 even if they could
be unreliable when fecs_tgt in set in save0 . This
is good to have for debug purposes.
-Add priv_ring hal for decode_error_code
-Decode fecs error code for supported error types
Bug 1998067
Change-Id: I60cb6902d099df4a7df45fa624e44d9e0d46360f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1683014
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Using tpc_count instead of gpc_tpc_count indexed by gpc, will result
in pbus error with decode error or client floorswept error codes.
tpc_count represents total number of tpc while gpc_tpc_count[gpc]
represents number of tpc in the indexed gpc.
Bug 1998067
Change-Id: I9adfb98a6c3e209cbb02a8cd5090f6b6adc1ec4b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1682469
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Current code does not compute priv error register offsets
properly. This leads to invalid decoding of priv errors, and
can also trigger additional priv errors.
- add GPU_LIT_GPC_PRIV_STRIDE define
- return proj_gpc_priv_stride for GPU_LIT_GPC_PRIV_STRIDE in hals
- use GPU_LIT_GPC_PRIV_STRIDE instead of GPU_LIT_GPC_STRIDE in
g->ops.priv_ring.isr() to compute priv error register offsets.
Bug 2093058
Change-Id: Ia7c36ccba0441126784bb0e00452f2cf1196ef71
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1682118
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Re-generate headers for proj_gpc_priv_stride accessor.
This is needed to compute priv error register offsets.
Bug 2093058
Change-Id: Ied4e2b072f650940757c44e261b416d388e8924c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1682117
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Instead of looping all jobs and releasing their semaphores separately,
do just one semaphore release. All the jobs are using the same sema
index, and the final, maximum value of it is known.
Move also this resetting into ch->sync->set_min_eq_max() to be
consistent with syncpoints.
Change-Id: I03601aae67db0a65750c8df6b43387c042d383bd
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1680362
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Semaphores don't need to be released from CPU anymore, so clarify the
code by deleting nvgpu_semaphore_release() and refactoring
__nvgpu_semaphore_release() to nvgpu_semaphore_reset() that only
"fast-forwards" the semaphore to a later value.
While doing this, the meaning of nvgpu_semaphore_incr() changes, so
rename it to nvgpu_semaphore_prepare(). Now it's only used to prepare an
nvgpu_semaphore for a value that the HW will increment the sema to.
Also change the BUG_ON that guards sema double-inits into just WARN_ON.
Change-Id: I6f6df368ec5436cc97a229697742b6a4115dca51
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1680361
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This is to fix *SM_ICACHE_ECC* priv errors for sm suspend
resume test. gv100 has significantly less ECC protected
SRAMs. gv11b ECC hals will not work for gv100.
Bug 1998067
Change-Id: I437a7981ed1832c2070185f3ad8f802c7454e8c9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1681270
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Sandarbh Jain <sanjain@nvidia.com>
Tested-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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nvgpu_mem_begin() needs to have it's return code checked to
make sure that it did not fail.
Coverity defect id: 2883904
Bug 200291879
Change-Id: Ic845a73439a905997a1f871708b1f847f5b93293
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1681249
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Similarly to css_hw_(enable|disable)_snapshot the HWPM
state should be reset on perfbuf_enable and perfbuf_disable
to avoid leaking snapshot data into a freshly mapped buffer.
Bug 1960846
Change-Id: I94826b209ef4b8cb6ad44d3b8667745270c6a7e1
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676009
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Error path is not implemented in nvgpu_pci_probe(), and that could lead to
memory leaks if any of the step in nvgpu_pci_probe() fails
Fix this by implementing error path and freeing all allocated buffers
Bug 200291879
Coverify defect id : 2845621
Change-Id: Iee1abb041089e47a517a6698f0a4067c9c4fa289
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1681028
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Instead of ignoring a wait when a raw syncpoint prefence has an invalid
id, reject the submit with -EINVAL just like with syncpoints in syncfds.
Change-Id: I9b5c417bd1c7cd081c79659d088ac2c915de8c0e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1680281
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Accept submits on deterministic channels even when the prefence is a
syncfd, but only if it has just one fence inside.
Because NVGPU_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE is shared between pre- and
postfences, a postfence (SUBMIT_GPFIFO_FLAGS_FENCE_GET) is not allowed
at the same time though.
The sync framework is problematic for deterministic channels due to
certain allocations that are not controlled by nvgpu. However, that only
applies for postfences, yet we've disallowed FLAGS_SYNC_FENCE for
deterministic channels even when a postfence is not needed.
Bug 200390539
Change-Id: I099bbadc11cc2f093fb2c585f3bd909143238d57
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1680271
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nvgpu_semaphore_pool_alloc() returns an ERR_PTR instead of NULL which
the caller checks on failure. Common code should not use ERR_PTRs
though, so modify nvgpu_semaphore_pool_alloc() to return error code
separately and fix nvgpu_init_sema_pool() to consider this.
Jira NVGPU-513
Change-Id: I435c0d2794d226774ed4c6b3bcbdde1e741854d8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673458
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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MAX/threshold value of user managed syncpoint is not tracked by nvgpu
So if channel is reset by nvgpu there could be waiters still waiting on some
user syncpoint fence
Fix this by setting a large safe value to user managed syncpoint when aborting
the channel and when closing the channel
We right now increment the current value by 0x10000 which should be sufficient
to release any pending waiter
Bug 200326065
Jira NVGPU-179
Change-Id: Ie6432369bb4c21bd922c14b8d5a74c1477116f0b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1678768
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Add support for 20G speed by updating initPLL command and
update the default link speed set during nvlink init to 20G.
Bug 200398181
Change-Id: I22cde32842d140b34481aaec2b1561ffbd44e2d8
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1678444
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Cleanup superfluous traces in nvgpu_clk_set_info.
Jira DNVGPU-210
Jira DNVGPU-211
Change-Id: I78249d7a2a11e205c808695ea76293bff8892efc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627357
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GV100 ucode is changed so that it expects LIST_nv_perf_pma_ctx_reg list in
ctxsw buffer to be 256 byte aligned but same change is not applied to other
chip ucodes
ADD new HAL (*add_ctxsw_reg_perf_pma) to configure PMA register list and
define a common HAL gr_gk20a_add_ctxsw_reg_perf_pma() for all other
chips except GV100
Define a separate HAL for GV100 gr_gv100_add_ctxsw_reg_perf_pma() and fix
the required alignment in this function
Bug 1998067
Change-Id: Ie172fe90e2cdbac2509f2ece953cd8552e66fc56
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676655
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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For LIST_nv_pm_fbpa_ctx_regs, we right now call
add_ctxsw_buffer_map_entries_subunits() to add registers corresponding
to all the FBPAs
But while configuring total number of registers, we do not consider
floorswept FBPAs and that causes misalignment in subsequent lists for GV100
Fix this by reading disabled/floorswept FBPAs from fuse and consider only those
FBPAs which are active for GV100
Add new HAL (*add_ctxsw_reg_pm_fbpa) to support this setting and define a
common HAL gr_gk20a_add_ctxsw_reg_pm_fbpa() for all chips except GV100
Define GV100 specific gr_gv100_add_ctxsw_reg_pm_fbpa() with above mentioned
implementation to consider floorsweeping
Bug 1998067
Change-Id: Id560551bb0b8142791c117b6d27864566c90b489
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676654
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Switching GPU clock in/out of bypass concurrently with h/w thermal
throttling may result in unpredictable/unstable clock output from GPU
linear divider. Hence, made sure thermal throttling is disabled before
bypass entry, and enabled after bypass exit.
Bug 1893467
Change-Id: Ia919c599eeb0115e11a34370aea3982aa935db2f
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1677022
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The pre_fence member in channel_gk20a_job is no longer used for
anything. Delete it. Only the post fence needs to be tracked.
Jira NVGPU-527
Jira NVGPU-528
Bug 200390539
Change-Id: Ia1a556728dabf9a8e305ed76020ac1aa0b4d6b88
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676735
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Req : Some boardobjgrp don't need getstatus support, so
boardobjgrp pmu cmd not constructed for those boardobjgrp.
Don't request memory alloc if boardobjgrp pmu cmd
not constructed & should exit cleanly without allocating memory.
Fix: Don't request memory alloc if boardobjgrp pmu cmd
not constructed by checking "sturct boardobjgrp_pmu_cmd"
member "fbsize" value.
Change-Id: I610d6812ec1d1bcf7ea38645236601b3e5672650
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1674191
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When generating the aperture field for the PDE being programmed
we must use the next PD not the current PD. This is important for
cases on the dGPU where VIDMEM runs out.
In such cases the page table may reside in both VIDMEM and SYSMEM.
Thus, if a PDE points to a PDE in a different type of memory
(VIDMEM -> SYSMEM or SYSMEM -> VIDMEM) then the aperture will not
be programmed correctly if the code uses the current PD for
picking the next PD aperture.
Bug 2082475
Change-Id: Ic1a8d1e2c2237712039dc298b97095d3bbc6c844
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676831
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The fence parameter that gets output from gk20a_channel_sync's wait()
and wait_fd() APIs is no longer used for anything. Delete it.
Jira NVGPU-527
Jira NVGPU-528
Bug 200390539
Change-Id: I659504062dc6aee83a0a0d9f5625372b4ae8c0e2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676734
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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gp10b_get_pde0_pgsz computes pgsz depending on aperture and
address, but it was not handling sysmem coherent case.
Bug 2082475
Change-Id: I095acb05e3f917518368b879f5839f8e9dbcd8ea
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676255
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Delete the proxy waiter for non-semaphore-backed syncfds in sema wait
path to simplify code, to remove dependencies to the sync framework (and
thus Linux) and to support upcoming refactorings. This feature has never
been used for actually foreign fences.
Jira NVGPU-43
Jira NVGPU-66
Change-Id: I2b539aefd2d096a7bf5f40e61d48de7a9b3dccae
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665119
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syncpoint"
This reverts commit fb40f2a80739985abac273bc493e07341aa003af.
aggressive_sync_destroy_thresh was inadvertently set for gv11b vGPU, and that is
now being removed
hence restore original check
Bug 200397265
Bug 200326065
Change-Id: If56e1c462adb2db7d9186fbb6038169aa7ea33dc
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676556
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aggressive_sync_destroy_thresh was inadvertently set for gv11b on vGPU, and that
caused issues while allocating user managed syncpoint
remove that threshold as it is no longer needed
Bug 200397265
Bug 200326065
Change-Id: I63dfdcae1fd7b99068d07807c84775b9a9f9f95d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676555
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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When __NVGPU_POSIX__ is defined do no use ioremap(). This operation
probably doesn't make much sense. Currently we have no plans to run
the driver in userspace against a real GPU, hence programming the
nvlink credits registers is simply not necessary.
Also fix an unused variable by returing it as an error.
JIRA NVGPU-525
Change-Id: Ic94d332551f6e25c1836331bf92188e7651546cb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673815
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A RPFB debug function was still using pr_info() instead of
nvgpu_info() so make that conversion.
JIRA NVGPU-525
Change-Id: Ib157dfd2f743374215bc16230c7f422601133d2f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673814
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Cleanup a macro in clk_gm20b.c to not use pr_info() - instead
use nvgpu_info(). Also add necessary includes.
JIRA NVGPU-525
Change-Id: I2dcaf41c1e31131acf63b24b33b5a24795128024
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673813
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This variable is only ever used under the CONFIG_SYNC config so
make sure that we only define/assign to it when CONFIG_SYNC is
enabled.
JIRA NVGPU-525
Change-Id: I27160adbd6a46f58e21f24ab19d37966ded5e7de
Signed-off-by: Alex Waterman <alexw@nvidia.com>
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get_cycles is a linux specific API used in common code. This API
is being used, it seems, as a method to generate time stamps. So
add an API to generate 'high resolution' time stamps. This API
returns an opaque time stamp: that is not something one may use
directly as a time since in the Linux implementation we just use
this cycle counter.
Other implementations will, of course, be free to implement as a
real time stamp.
JIRA NVGPU-525
Change-Id: I237aac9bd6c795d000459025bdb4fce92e8aaa3d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1673811
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It'll allow the function to use fixed mapping.
Jira VQRM-2982
Change-Id: I98159c5b199ce1854b1b40704392237cadb71ef2
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1660225
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The pre-fence wait for semaphores in the submit path has supported a
fast path for fences that have only one underlying semaphore. The fast
path just inserts the wait on this sema to the pushbuffer directly. For
other fences, the path has been using a CPU wait indirection, signaling
another semaphore when we get the CPU-side callback.
Instead of only supporting prefences with one sema, unroll all the
individual semaphores and insert waits for each to a pushbuffer, like
we've already been doing with syncpoints. Now all sema-backed syncs get
the fast path. This simplifies the logic and makes it more explicit that
only foreign fences need the CPU wait.
There is no need to hold references to the sync fence or the semas
inside: this submitted job only needs the global read-only sema mapping
that is guaranteed to stay alive while the VM of this channel stays
alive, and the job does not outlive this channel.
Jira NVGPU-43
Jira NVGPU-66
Jira NVGPU-513
Change-Id: I7cfbb510001d998a864aed8d6afd1582b9adb80d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1636345
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VGPU has set aggressive_sync_destroy_thresh even for GV11B, and that breaks
allocation of user managed syncpoint on VGPU
Remove this check for now until some solution is finalized
Bug 200397265
Bug 200326065
Change-Id: Idd765cfdd40b9055d9e083d59c85c84d8b213ee9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1675678
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Async probe of vgpu driver results in a race condition where GICD registers
are being programmed incorrectly because of the race.
Remove ASYNC_PROBE for vgpu driver as a WAR to prevent it. This change
would be reverted after GICD register programming is serialized
bug 200385192
Change-Id: I7279152867470ece93c5efbd72ac24db28878024
Signed-off-by: Nagaraj P N <nagarajp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1674898
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- Updating gp10x PMU f/w version for ucode
git cl : https://git-master.nvidia.com/r/#/c/1674816/
P4 CL# : 23732390
Change-Id: I4426f7fc96b52f342ac885199e7dd3e413af4a8e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1674857
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- Added support for single rail multi step volt policy & below
are the list of define & struct added/updated to support same.
CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04,
NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04,
Updated struct vbios_voltage_policy_table_1x_entry,
struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set, this holds
members which help to config single rail multi step like delay
between switch step, ramp up & ramp down step size in uv.
- Added case to support SINGLE_RAIL_MULTI_STEP in
volt_volt_policy_construct() based on boardobj type.
- Added case to support SINGLE_RAIL_MULTI_STEP in
volt_get_volt_policy_table() to read data from VBIOS
table vbios_voltage_policy_table_1x_entry & extract to
voltage_policy_single_rail_multi_step.
- Added methods to forward single rail multi step data to
PMU using below methods by assigning data read from
VBIOS voltage_policy_single_rail_multi_step to
nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set
interface.
volt_construct_volt_policy_single_rail_multi_step()
volt_policy_pmu_data_init_sr_multi_step()
volt_policy_pmu_data_init_single_rail()
construct_volt_policy_single_rail()
Change-Id: I17bc8c320777191611365ee63274c38ffe5ecbf7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1660687
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- Created volt ops under pmu_ver to support volt_set_voltage,
volt_get_voltage & volt_send_load_cmd_to_pmu.
- Renamed volt load, set_voltage & get_voltage gp10x method names.
- Added new volt load, set_voltage & get_voltage methods for gv10x
using RPC & added code to handle ack in pmu_rpc_handler() along
with struct rail_list changes.
- Updated volt ops of gp106 & gv100 to point to respective methods.
- Added member volt_dev_idx_ipc_vmin & volt_scale_exp_pwr_equ_idx to
"struct nv_pmu_volt_volt_rail_boardobj_set" & "struct voltage_rail"
made changes to update members as needed.
- Added member volt_scale_exp_pwr_equ_idx to
"struct vbios_voltage_rail_table_1x_entry" to read
value from VBIOS table & update rail boardobj set interface.
- Defines for volt RPC "NV_PMU_RPC_ID_VOLT_*"
- Define struct's volt load, set_voltage & get_voltage to execute
volt RPC.
Change-Id: I4a41adcf7536468beaa8a73f551b1d608aabd161
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1659728
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