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* gpu: nvgpu: Move MC HAL to commonTerje Bergstrom2018-09-13
| | | | | | | | | | | | | | | | | | | | | | | Move implementation of MC HAL to common/mc. Also bump gk20a implementation to gm20b. gk20a_mc_boot_0 was used via a HAL, but we have only one possible implementation. It also has to be anyway called directly to detect which HALs to assign, so make it a true common function. mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c so move it there. JIRA NVGPU-954 Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813519 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: railgate returns early if no platform implementationRichard Zhao2018-09-13
| | | | | | | | | | | | | | | | | | | | | If platform didn't set railgate/unrailgate callbacks, it means it does not support railgate. It avoids vgpu calling tegra_fuse_clock_disable/enable. Bug 200436689 Jira EVLR-2983 Change-Id: I759dc23145429a59f40cec6e9c1de9536dcf43c4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1821663 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gsp accessors for GV100Deepak Nibade2018-09-12
| | | | | | | | | | | | | Change-Id: I0b0992e2eda98209ed3d7277a69a7fcf1d01f083 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1816025 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add sources for nvgpu-next in tmakeAlex Waterman2018-09-12
| | | | | | | | | | | | | | | | | | | | Update the tmake build to build nvcgpu-next as well. See https://git-master.nvidia.com/r/1814622 For the necessary changes to make this compile. JIRA NVGPU-1104 Change-Id: Id44e20de78c1ebdb0247a1c3da79273380aba9fb Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1814623 Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (pd_cache.c)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. Fixes for all the pd_cache functions that use '__' prefixes. This was trivial: the '__' prefix was simply deleted. JIRA NVGPU-1029 Change-Id: Ia91dabe3ef97fb17a2a85105935fb3a72d7c2c5e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813643 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (nvgpu_mem.c, mm.c)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. Handle the 21.2 fixes for nvgpu_mem.c and mm.c; this deletes the '__' prefixes and slightly renames the __nvgpu_aperture_mask() function since there's a coherent version and a general version. Change-Id: Iee871ad90db3f2622f9099bd9992eb994e0fbf34 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813623 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (buddy_allocator.c)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. Fixes for the buddy allocator. These are all pretty trivial; mostly the '__' prefix is simply deleted since the functions are all static. The one exception is the list accessors were also renamed slightly to include a 'do' component to show more clearly that the other list accessors are convenience functions. JIRA NVGPU-1029 Change-Id: Ia39cdde9a81e740537fc9b4d70d87eadc12f8d4d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813601 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (public allocator APIs)Alex Waterman2018-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. This fixes places in the public allocator APIs. This consists of the various init routines which are used to create an allocator and the debug macro used within the allocator code. The buddy allocator was handled by collapsing the internal '__' prepended version with the non-prefixed version. The only required change was in the page_allocator code which now had to pass in a NULL vm pointer (since the VM is not needed for managing VIDMEM). JIRA NVGPU-1029 Change-Id: I484a144e61789bf594c525c1ca307b96d120830f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813578 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move gk20a.h to include/nvgpu/gk20a.hddutta2018-09-12
| | | | | | | | | | | | | | | | | | | Move the contents of the gk20a/gk20a.h to <nvgpu/gk20a.h>. In order to enable a smooth transition, include <nvgpu/gk20a.h> in the current file (i.e. gk20a/gk20a.h). Jira NVGPU-597 Change-Id: I998da0e7688a5827e2974e88ab8ad6849083aa4a Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813140 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: skip waiting for runlist preempt to complete in RCAparna Das2018-09-12
| | | | | | | | | | | | | | | | Since RC is triggered due to fatal interrupt always skip waiting for runlist preemption to complete in RC path. Also poll PBDMA status to verify TSG is no longer on the PDBMA before doing engine reset. Bug 2322245 Change-Id: I3cce3a2c50b527a407ad967b6b9ac964c42f6df9 Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1806317 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 15.6 violationssmadhavan2018-09-12
| | | | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces by introducing the braces. JIRA NVGPU-671 Change-Id: I8046a09fa7ffc74c3d737ba57132a0a9ae2ff195 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797699 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: deny any request less than engine timeout"Emad Mir2018-09-10
| | | | | | | | | | | | This reverts commit 4f01d6a9b9a54cf6042db157de0d40965077f6a2. Change-Id: I604acef2a1f322a521df3ceb39e7df5d249a5716 Reviewed-on: https://git-master.nvidia.com/r/1818387 Reviewed-by: Emad Mir <emir@nvidia.com> Tested-by: Emad Mir <emir@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix vsm mapping used by gv11b_gr_set_sm_debug_modeAnup Mahindre2018-09-10
| | | | | | | | | | | | | | Mapping used by gv11b_gr_set_sm_debug_mode is inconsistent with mapping exposed via gk20a_ctrl_vsm_mapping as it doesn't consider non pes aware GPC/TPC to SM mapping. Bug 200448172 Change-Id: Id8a7208a779e577377464f632b819bc0cb228e92 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1816191 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: warn if cde map failsKonsta Holtta2018-09-10
| | | | | | | | | | | | | This shouldn't happen, but is dangerous enough to warrant its own warning if it does. A message might help debug a rare corruption bug. Bug 2038362 Change-Id: I7915760fc31e7acaa0148a10f9acae303d53ea95 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1815863 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix some MISRA 10.3 violationsPhilip Elcan2018-09-10
| | | | | | | | | | | | | | | | Fix MISRA 10.3 violations in mclk_gp106.c. Cleanup cases where values were being assigned to narrower types. Changes in mclk_gp106.c required updates to other files to resolve errors and prevent introducing new violations. JIRA NVGPU-647 Change-Id: Ifdb03ad41d9dbf05dbcf79494ae8565fff6ee083 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809366 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move programming of debug page to FBTerje Bergstrom2018-09-10
| | | | | | | | | | | | | | | Debug page was allocated and programmed to HUB MMU in GR code. This introduces a dependency from GR to FB and is anyway the wrong place. Move the code to allocate memory to generic MM code, and the code to program the addresses to FB. Change-Id: Ib6d3c96efde6794cf5e8cd4c908525c85b57c233 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801423 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB size query to FBTerje Bergstrom2018-09-10
| | | | | | | | | | | | | Vidmem size query was in mm_xxx.c. It involves reading a register from FB, so move the query to FB HAL. JIRA NVGPU-1063 Change-Id: I30dfd2c4fdcdd6c841f85aaab7431d52473759bd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801425 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu:ps35: Clock domain changesVaikundanathan S2018-09-10
| | | | | | | | | | | | | | | | 1. PMU interface changes 2. Split PS3.0 and PS3.5 into two dev init functions. 3. Split construct and pmu_data_init to two funcitons. 4. Fixing GV100 impact on PS3.5 changes Change-Id: I46ba80325d4a249918edbe4cf868ddf47c778aa1 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1777739 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: deny any request less than engine timeoutPreetham Chandru R2018-09-10
| | | | | | | | | | | | Bug 2343124 JIRA NVGPU-1065 Change-Id: I43a436673117af8ac2490d075cea07532f01af0b Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1818164 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: include: MISRA Rule 21.2 header guard fixessmadhavan2018-09-10
| | | | | | | | | | | | | | | | | | | | | | MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in the include directory by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H'. JIRA NVGPU-1028 Change-Id: I14e3558c80511314e32ef79c2b609a9fd9cf0a44 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813123 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add Top as a unitTejal Kudav2018-09-10
| | | | | | | | | | | | | | | | | | | | | NVHSCLK registers used by NVLINK IP are part of dev_top hardware headers. This patch adds "Top" as a separate unit and exposes HALs to access dev_top registers. The top unit contains top-level configuration information and any extra registers or features that do not fit into another block's feature set. JIRA NVGPU-1053 JIRA NVGPU-966 Change-Id: Id9a43d4a1c5397959897a242ea97a39a1b95f916 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803632 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Return gr_ctx_resident from NVGPU_DBG_GPU_IOCTL_REG_OPSAnup Mahindre2018-09-09
| | | | | | | | | | | | | | | | | | NVGPU_DBG_GPU_IOCTL_REG_OPS currently doesn't return if the ctx was resident in engine or not. Regops are broken down into batches of 128 and each batch is executed together. Since there only 32 bits were available in IOCTL args, returning is ctx was resident isn't possible for all batches. Hence return if the ctx was resident for the first batch. Bug 200445575 Change-Id: Iff950be25893de0afadd523d4ea04842a8ddf2af Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812975 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move fecs trace debugfs to linuxNitin Kumbhar2018-09-09
| | | | | | | | | | | | | | | | | | Add fecs trace debugfs initialization as an os op. The debugfs nodes are set up for gpu versions which call gk20a_fecs_trace_init(). JIRA NVGPU-602 Change-Id: I606ec31acbf04f633500be4c342db32f3f537794 Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812449 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: add chip specific init functionMubushir Rahman2018-09-09
| | | | | | | | | | | | | | | | | | | - Add gv11b specific init function - This init function will set a chip specific value for emc3d_ratio and then call the gp10b init function Bug 200438743 Change-Id: If6128c2156e4b65086827615909ed17cce1d9224 Signed-off-by: Mubushir Rahman <mubushirr@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808673 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Ilan Aelion <iaelion@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix several issues with the buddy allocatorAlex Waterman2018-09-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issues are: 1. Non-fixed allocs must take into account explicit PTE size requests. Previously the PTE size was determines from the allocation size which was incorect. To do this, the PTE size is now plumbed through all GPU VA allocations. This is what the new alloc_pte() op does. 2. Fix buddy PTE size assignment. This changes a '<=' into a '<' in the buddy allocation logic. Effectively this is now leaving the PTE size for buddy blocks equal to the PDE block size as 'ANY'. This prevents a buddy block of PDE size which has yet to be allocated from having a specific PDE size. Without this its possible to do a fixed alloc that fails unexpectedly due to mismatching PDE sizes. Consider two PDE block sized fixed allocs that are contained in one buddy twice the size of a PDE block. Let's call these fixed allocs S and B (small and big). Let's assume that two fixed allocs are done, each targeting S and B, in that order. With the current logic the first alloc, when we create the two buddies S and B, causes both S and B to have a PTE size of SMALL. Now when the second alloc happens we attempt to find a buddy B with a PTE size of either BIG or ANY. But we cannot becasue B already has size SMALL. This casues us to appear like we have a conflicting fixed alloc despite this not being the case. 3. Misc cleanups & bug fixes: - Clean up some MISRA issues - Delete an extraneous unlock that could have caused a deadlock. Bug 200105199 Change-Id: Ib5447ec6705a5a289ac0cf3d5e90c79b5d67582d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1768582 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: changing page_idx from int to u64Sai Nikhil2018-09-07
| | | | | | | | | | | | | | | | | | | | | page_idx is an element of the struct nvgpu_semaphore_pool, defined in include/nvgpu/semaphore.h file. page_idx can not be negative so changing it from int to u64 and its related changes in various files. This also fixes MISRA 10.4 violations in these files. Jira NVGPU-992 Change-Id: Ie9696dab7da9e139bc31563783b422c84144f18b Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801632 Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: cleanup return types for MISRA 10.3Philip Elcan2018-09-07
| | | | | | | | | | | | | | | This is a big cleanup of return types across a number of modules in the nvgpu driver. Many functions were returning u32 but using negative return codes. This is a MISRA 10.3 violation by assigning signed values to a u32. JIRA NVGPU-647 Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810743 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix nvgpu_readl MISRA 17.7 violationsNicolas Benech2018-09-07
| | | | | | | | | | | | | | | | | MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for calls to nvgpu_readl. JIRA NVGPU-677 Change-Id: I432197cca67a10281dfe407aa9ce2dd8120030f0 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807528 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gpu_powered_on sysfsThomas Fleury2018-09-07
| | | | | | | | | | | | | | | | | Add sysfs to indicate if GPU has ever been powered on. This allows an application to avoid booting dGPU, when there is no need for it. For instance the fan controller can check this value, and refrain from booting the GPU, only to check the temperature. This will save power, and also avoid locking some registers which currently prevent from using VBIOS update tool. Bug 200408936 Change-Id: I6344001e91e9eee8762ff8b227ca6698d8c6786f Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1802098 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gk20a: MISRA Rule 21.2 header guard fixessmadhavan2018-09-06
| | | | | | | | | | | | | | | | | | | MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations caused by include guards by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H' JIRA NVGPU-1028 Change-Id: I478be317d067a75cdc8cb7fe9577a66d06318a11 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813068 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix nvgpu_sim_esc_readl MISRA 17.7 violationsNicolas Benech2018-09-06
| | | | | | | | | | | | | | | | | | MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for calls to nvgpu_sim_esc_readl by changing its return to void and printing an error message instead. JIRA NVGPU-677 Change-Id: I949bea253dafc316c7dfbf870eb1225b6fc5b9c3 Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812887 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add return code to fb.tlb_invalidateNicolas Benech2018-09-06
| | | | | | | | | | | As part of MISRA 17.7 fixes for a different GPU, the tlb_invalidate needs to return an error code. Change-Id: I3b8b9f112708c17457855dd1fb151168791bc6bf Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810106 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gm20b: MISRA Rule 21.2 header gurad fixessmadhavan2018-09-06
| | | | | | | | | | | | | | | | | | | MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations caused by include guards by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H' JIRA NVGPU-1028 Change-Id: Ic60b2de8bb705f189134483fff1e2dff8ea96a12 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808186 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add ltc HAL get_cbc_base_divisorDeepak Nibade2018-09-06
| | | | | | | | | | | | | | | | Add gops.ltc.get_cbc_base_divisor() HAL to get CBC base divisor value Bug 2180284 Jira NVGPUT-12 Change-Id: Ifec5e050723a71c2fa735652cb5063f80aaecf60 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805469 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add compbit backing size to gr_gk20aDeepak Nibade2018-09-06
| | | | | | | | | | | | | | | | | | Add compbit_backing_size variable to struct gr_gk20a to hold compbit backing size And copy this value in respective init_comptags() HAL Bug 2180284 Jira NVGPUT-12 Change-Id: I3c1bea3a6b7ed39a1e901357e6e062dbf45b747b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776028 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support allocating CBC in vidmemDeepak Nibade2018-09-06
| | | | | | | | | | | | | | | | Update nvgpu_ltc_alloc_cbc() API to accept a flag for vidmem allocation and allocate CBC memory into vidmem if flag is set Bug 2180284 Jira NVGPUT-12 Change-Id: Ia6b9bb670c9fab6b5787de15526fcc753d702a73 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805468 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: make bootstrap allocations contiguousDeepak Nibade2018-09-06
| | | | | | | | | | | | | | | | | | | | | | | | We use bootstrap vidmem allocator for all the vidmem allocations that happen boot time And we need to program physical address for all the potential vidmem buffers that we program into h/w and are needed during boot So force the allocator to allocate contigous memory We otherwise see a warning dump when we program physical address of memory which is allocated in multiple pages Bug 2180284 Jira NVGPUT-12 Change-Id: Ib9c2d42ea463bc424c2cb4da8ffd8ebae436e0f6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805467 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: increase bootstrap vidmem carveout to 256MDeepak Nibade2018-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We right now have a bootstrap carveout in vidmem of size 16M and having base address at {total_vidmem_size - 256M} So this design divides rest of the vidmem into two chunks And the size of bootstrap carveout is also small and insufficient for vidmem allocations during boot Hence increase the bootstrap vidmem carevout to 256M and move it to the end of entire vidmem Rename the carevout name for wpr_co to bootstrap_co as it is more appropriate Also update __nvgpu_vidmem_do_clear_all() to clear only one chunk of vidmem instead of two Bug 2180284 Jira NVGPUT-12 Change-Id: I9c8d62bcd705c7112385df3d4f714e0190b48e17 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805466 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix crash with uninitialized comptag allocatorDeepak Nibade2018-09-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If gk20a_comptaglines_alloc() is called with an uninitialized comptag allocator we right now see a kernel panic like this [ 445.097931] [<ffffff8008fdd650>] __mutex_lock_slowpath+0xe0/0x188 [ 445.104275] [<ffffff8008fdd748>] mutex_lock+0x50/0x68 [ 445.109773] [<ffffff80012ef340>] gk20a_comptaglines_alloc+0x30/0x98 [nvgpu] [ 445.117169] [<ffffff80012e0fdc>] gk20a_alloc_or_get_comptags+0xe4/0x140 [nvgpu] [ 445.124910] [<ffffff80012ee1cc>] nvgpu_vm_map+0x414/0x7b8 [nvgpu] [ 445.131433] [<ffffff80012dd754>] nvgpu_vm_map_linux+0x114/0x1e8 [nvgpu] [ 445.138475] [<ffffff80012dd978>] nvgpu_vm_map_buffer+0x150/0x238 [nvgpu] [ 445.145605] [<ffffff80012d2834>] gk20a_as_dev_ioctl+0x30c/0xa78 [nvgpu] [ 445.152473] [<ffffff8008262154>] do_vfs_ioctl+0xc4/0x8f8 Fix this by checking explicitly that comptag allocator is initialized in gk20a_comptaglines_alloc() and gk20a_comptaglines_free() Bug 2171567 Change-Id: Iaac6d77e40a8aaa01f2bacbe0cb54ec447100075 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805170 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gk20a: gr: Fix MISRA 15.6 violationsSrirangan2018-09-06
| | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces by introducing the braces. JIRA NVGPU-671 Change-Id: Ie4bd8bffdafe6321e35394558dc9559f9c2d05c2 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797689 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add BIT8() and BIT16() macrosAmulya2018-09-06
| | | | | | | | | | | | | | | Added BIT8() and BIT16() macros to bit-shift u8 and u16 respectively. Change-Id: I5ca43165b0dcf3702a49bc5f5b120ad7a63b39a8 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813039 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unused regops HALsDeepak Nibade2018-09-05
| | | | | | | | | | | | | | | | | | | | Below regops HALs are not being called from anywhere, so remove them gops.regops.get_runcontrol_whitelist_ranges() gops.regops.get_runcontrol_whitelist_ranges_count() gops.regops.get_qctl_whitelist_ranges() gops.regops.get_qctl_whitelist_ranges_count() HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it was originally only needed for gk20a which is not unsupported So remove this HAL and its call too Jira NVGPU-620 Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813106 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 21.2 violations (page_allocator.c)Alex Waterman2018-09-05
| | | | | | | | | | | | | | | | | | | | | | | MISRA 21.2 states that we may not use reserved identifiers; since all identifiers beginning with '_' are reserved by libc, the usage of '__' as a prefix is disallowed. This change fixes uses of '__' prepended to static functions defined in page_allocator.c. Since these funcitons were static and had no naming conflicts the '__' was simply removed. For free_pages() this also needed to have a nvgpu specific prefix since free_pages() conflicts with a Linux kernel function name. JIRA NVGPU-1029 Change-Id: I8b96e55244bd2de166f7dcc64d2b30427757ea8f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812826 Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: volt: Fix MISRA 15.6 violationsSrirangan2018-09-05
| | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces by introducing the braces. JIRA NVGPU-671 Change-Id: I938f49b2d1d042dc96573e1a579fe82909a679ab Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812421 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move usermode buffer alloc to os_channelKonsta Holtta2018-09-05
| | | | | | | | | | | | | | Allocation of usermode submit buffers is not chip specific but is operating system specific; the API belongs to the os_channel layer, not in the fifo ops HAL. Bug 200145225 Change-Id: I90adb47103ab4b2e888c3db191d78ceda35e777d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812287 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move channel header to commonKonsta Holtta2018-09-05
| | | | | | | | | | | | | channel_gk20a is clear from chip specifics and from most dependencies, so move it under the common directory. Jira NVGPU-967 Change-Id: I41f2160b96d4ec84064288ecc22bb360e82352df Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810578 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: common: MISRA 10.1 boolean fixesAmulya2018-09-05
| | | | | | | | | | | | | Fix violations where a variable of type non-boolean is used as a boolean in gpu/nvgpu/common. JIRA NVGPU-646 Change-Id: I91baa5cf1d38081161336bde5fbc06661b741273 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807133 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix mutex MISRA 17.7 violationsNicolas Benech2018-09-05
| | | | | | | | | | | | | | | | | | MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. This patch contains fix for calls to nvgpu_mutex_init and improves related error handling. JIRA NVGPU-677 Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805598 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move common DMA code to common/mmAlex Waterman2018-09-05
| | | | | | | | | | | | | | | | | | | | | | | | | This migrates the common DMA code (os agnostic) to the common directory. This new unit will be the common DMA allocator that lets users allocate SYSMEM, VIDMEM, or either. Other units will be responsible for actually handling the mechanics of allocating VIDMEM or SYSMEM. Also update the names of the DMA related files so that tmake doesn't complain about duplicate C file names. To do this call the common DMA file dma.c and prepend the OS to the other DMA files. So now we have: common/mm/dma.c os/posix/posix-dma.c os/linux/linux-dma.c JIRA NVGPU-990 Change-Id: I22d2d41803ad89be7d9c28f87864ce4fedf10836 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1799807 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: clk: Fix MISRA 15.6 violationsSrirangan2018-09-05
| | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces by introducing the braces. JIRA NVGPU-671 Change-Id: I228f04adea809e1dd4e6826bf1a04f051a533102 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796831 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 12:58:44 -0400