| Commit message (Collapse) | Author | Age |
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It was initialized at .init_comptags, but we may also need them without
comptags.
Jira NVGPUT-63
Change-Id: Ie818c3ecf890fc84323b9662a32d666a6d2b3936
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756373
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- Added suspend/resume power management callbacks for vGPU
- Added suspend/resume commands for communication between vGPU and
RM server
- Added suspend/resume message parameters for IVC messages between
vGPU and RM server
JIRA EVLR-2305
JIRA EVLR-2306
Change-Id: I83a314b4e125a53117d16c5ea72dbc5d8ef96ef7
Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1735153
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gk20a_submit_prepare_syncs can fall to error handling paths without an
allocated wait command buffer. In that case, just don't try to free the
null wait_cmd; the user never requested one.
Change-Id: Ice9041c0efa9bb14cde917e7ea82f4a7b6bf537c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756829
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In K4.14, dma_buf_ops members are renamed from kmap_atomic to map_atomic
and kmap to map. So put the kernel version check to fix the build error
for k4.14.
Bug 200414723
Bug 200421495
Change-Id: Ic959960a43d2247f9cd4b530f9172a152bcbc08b
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1747013
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With arm64 mapping buffers to CPU is free. Remove the use of
NO_KERNEL_MAPPING.
Change-Id: Ic99ca6b7f8c698e2d3cb1d61a821939798bb237b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1753709
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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In gk20a_submit_channel_gpfifo the gpfifo entries can come from a kernel
buffer or from userspace. To simplify the logic in
gk20a_submit_append_gpfifo, extract out a function that copies the
entries directly from userspace to the gpu memory for performance, and
another function that copies from a kernel buffer to the gpu memory. The
latter is used for kernel submits and when the gpfifo pipe exists which
would mean that the gpfifo memory is in vidmem and is thus not directly
accessible with a kernel virtual pointer.
While this function is being changed a lot, also rename it to start with
nvgpu_ instead of gk20a_.
Additionally, simplify pushbuffer debug tracing by always using the
kernel memory for the prints. Tracing when the gpfifo memory has been
allocated in vidmem is no longer supported; sysmem is almost always used
in practice anyway.
Jira NVGPU-705
Change-Id: Icab843a379a75fb46054dee157a0a54ff9fbba59
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730481
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The biggest remaining Linuxism in the submit path is the
copy_from_user() calls for reading the gpfifo entries to the HW-visible
buffer. Abstract away the copy of one such segment starting at some
offset and keep the wraparound logic and vidmem proxy in the core submit
path.
Jira NVGPU-705
Change-Id: I0c6438045c695e5e3f5da4fbc0c92d2c6e7f32cb
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730480
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gk20a_submit_channel_gpfifo() supports reading the gpfifo entries from
either a kernel buffer or an userspace buffer in an ioctl. Add two
separate entry points: one for the ioctl and another for any other
kernel use. This shortens the function prototypes and simplifies and
clarifies the call sites slightly.
Jira NVGPU-705
Change-Id: If5141a459261a451f78cc50972f4c94d95ba44d1
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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Moved PG refcount checking to a wrapper function, this
function manages the refcount and decides whether to call
dbg_set_powergate function.
Instead of checking the dbg_s->is_pg_disabled variable,
code is checking g->dbg_powergating_disabled_refcount
variable to know if powergate is disabled or not.
Updating hwpm ctxsw mode without disabling powergate
will result in priv errors.
Bug 200410871
Bug 2109765
Change-Id: I33c9022cb04cd39249c78e72584dfe6afb7212d0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1753550
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Add an OS-abstracted API for printing the name of the current process
into a log message and convert the single occurrence of current->comm in
submit path power failure to use it.
Jira NVGPU-705
Change-Id: I1a509dcc5aecc3c89ce4582733888081b3e38f1f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1749833
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Index for global_ctx_buffer #8 and global_ctx_buffer_va #5 are reserved
Hence move FECS_TRACE_BUFFER to 9 and FECS_TRACE_BUFFER_VA to 6
Change-Id: I165842b6a68f67a8b357109988c87d4020c7b1ed
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1751500
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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We don't need to enable l2/fb/hub/xbar from PMC_ENABLE or PMC_ELPG_ENABLE
explicitly from nvgpu
Remove the redundant code which accesses those registers
Jira NVGPUT-51
Change-Id: I423d3bfc2f63460fc168815b5b5104962e3e72ef
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1751445
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Avoid arithmetic on a void pointer by casting the priv cmdbuf pointer to
u32 first, then adding offset.
Jira NVGPU-705
Change-Id: I6734a002bc376f6ff72e5b73b720921bfd63951f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1749899
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Move all Linux source code files to drivers/gpu/nvgpu/os/linux from
drivers/gpu/nvgpu/common/linux. This changes the meaning of common
to be OS independent.
JIRA NVGPU-598
JIRA NVGPU-601
Change-Id: Ib7f2a43d3688bb0d0b7dcc48469a6783fd988ce9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In case of mmu nack error interrupt is received twice through SM
reported mmu nack interrupt and mmu fault in undertermined order.
Recover on the first received interrupt to avoid semaphore release
and skip doing a second recovery.
Also fix NULL pointer dereference in function
gv11b_fifo_reset_pbdma_and_eng_faulted when channel reference is
invalid in teardown path.
Bug 200382235
Change-Id: I361a5725d7b6355ebf02b2870727f647fbd7a37e
Signed-off-by: Aparna Das <aparnad@nvidia.com>
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The watchdog tracks wall clock time. If the GPU's runlist is heavily
congested, other work can last long enough to trigger the watchdog for
trusted kernel channels too.
We don't expect the CDE work to ever get stuck, so disable wdt there.
Bug 200311892
Change-Id: I58c7d23891bc73aaeea0ccfcead567b3c6c13a52
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1493814
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Delete a couple of unused struct pmu_msg locals from clk.c.
Change-Id: Idc7b7e4d18eefb12c4b5c0ebb852f74f721fd0fc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1749927
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Make ecc sysfs hash table per GPU by adding it as
part of nvgpu_os_linux. Using a single hash table
might give incorrect results as GPUs have same filenames
and a filename is used as a key for a lookup.
Add device_attribute as part of struct gk20a_ecc_stat. Using
a single array of pointers of device attribute for an
ecc_stat results in memory leak and incorrect stats if
multiple GPUs are present on the system. This array of pointers
will always hold info for GPU which created sysfs nodes last.
Fix this by making device attribute array per ecc stat per GPU.
Fix ecc stat removal to consider zero sub-units for a given
number of hwunits. The multiplication with zero results
in not removing any sysfs node at all.
Bug 1987855
Change-Id: Ifcacc5623cede8decfe228c02d72786337cd0876
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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To make ecc sysfs related code reusable, move it to
a seprate file. This allows possible optimizations
with localized changes.
There is no change in the code.
Bug 1987855
Change-Id: I69aefb649df628d0c8dad529de6dde07ab4e6009
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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Add remove_gr_sys() op to gpu_ops to reverse steps
done in create_gr_sysfs().
Make gv11b_tegra_remove() specific to gv11b instead
to properly remove sysfs nodes. This also helps in
having gv11b specific remove steps.
Also, update platform remove function of dGPU i.e.
nvgpu_pci_tegra_remove() to remove sysfs nodes. This
adds parity with iGPU platform remove.
Bug 1987855
Change-Id: Ibbaffac5c24346709347f86444a951461894354d
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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FB flush timeout is deprecated in h/w and we use memop timeout instead
which has same bits in the register
Hence remove fb flush timeout accessors and use memop timeout ones
Jira NVGPUT-50
Change-Id: Ia4696275f721f28cbb7e300889c4d70aaf0824ef
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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Add support for PCI device with ID 0x1eba
Add corresponding platform data
Change-Id: I2e5fe25666d4c00a6d4d27f0124fa02639f7aebd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1746579
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- defined platform agnostic wrapper for mempool
mapping and unmapping.
- used platform agnositc wrapper for device
tree parsing.
- modified css_gr_gk20a to include special
handling incase of rm-server
JIRA: VQRM:3699
Change-Id: I08fd26052edfa1edf45a67be57f7d27c38ad106a
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1733576
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- removed inclusion of linux includes.
- replaced with nvgpu/*.h's
- reformated the function signature of
"css_hw_get_pending_snapshot" and
"css_hw_get_overflow_status" be global instead of
static.
- added get_pending_snapshot and get_overflow_status
to ops->css.
JIRA: VQRM-3699
Change-Id: I177904c263e143b414924c2c28ad6fd3cfd00132
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
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Added nvgpu_dt_read_u32_index() for now.
Jira VFND-4870
Change-Id: I3e51c408dfba3864372c515ba5d2c77708a489c8
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All DS ZBC registers are non functional beginning Pascal and only the DSS ZBC
registers are functional
Hence remove access to deprecated ZBC registers
Jira NVGPUT-25
Jira NVGPUT-107
Change-Id: I85ba13d2a9ec47b3fe98df7285f7a310ee69dadb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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gk20a.c and mm_gk20a.c include bus_gk20a.h without needing anything
from it. Drop that dependency.
JIRA NVGPU-737
Change-Id: Ia1ae39248dad854797fb4be75c9ffeef3b191c7b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The following changes moved/renamed/deleted files:
- https://git-master.nvidia.com/r/#/c/1730893/
- https://git-master.nvidia.com/r/#/c/1730890/
These changes did not update Makefile.sources which is used by the
userspace build. That's why the userspace build broke. This change
updates Makefile.sources and fixes the userspace build.
Change-Id: I011101c2f956cd1304d44d54d3e4a1a4cdfb6da9
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1747659
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Add below HALs to setup mmu_fault configuration registers and to read
information registers and set them on Volta
gops.fb.write_mmu_fault_buffer_lo_hi()
gops.fb.write_mmu_fault_buffer_get()
gops.fb.write_mmu_fault_buffer_size()
gops.fb.write_mmu_fault_status()
gops.fb.read_mmu_fault_buffer_get()
gops.fb.read_mmu_fault_buffer_put()
gops.fb.read_mmu_fault_buffer_size()
gops.fb.read_mmu_fault_addr_lo_hi()
gops.fb.read_mmu_fault_inst_lo_hi()
gops.fb.read_mmu_fault_info()
gops.fb.read_mmu_fault_status()
Jira NVGPUT-13
Change-Id: Ia99568ff905ada3c035efb4565613576012f5bef
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1744063
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below HALs were missing in vGPU/gv11b. Add them.
gops.fb.enable_hub_intr() to enable hub interrupts
gops.fb.disable_hub_intr() to disable hub interrupts
Jira NVGPUT-44
Change-Id: I981744b79e9fc0d72e6ab991b09bbbcb3f6bcd44
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1744086
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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A few review comments got lost in the review of moving bus code to
common/bus. This takes care of renaming the header file protection
define, deletes the unnecessary description of the file in header,
and updates copyright years.
Change-Id: Ib7dfe3d8fdf31ff3ea1fbf96fc41f9e454486dd1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1741824
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-gp10x f/w version update for ucode
https://git-master.nvidia.com/r/#/c/1748070/
Change-Id: Ie6f40fc931a24162497ef62778069814fd668c20
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1748071
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Read clk frequency through PMU RPC
Bug 200399373
Change-Id: I9e887dcb1c5b622110eb4c1584f2f34434efd674
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1701276
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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HCE interrupt is not being used in nvgpu platform now,
masking the bit from the interrupt register.
bug 2082123
Change-Id: I1d53584afebe57b9621c8f4ec395cd1dcd6c7611
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1746850
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Print the surface address for which we fail to resolve an iova address
when patcing cde parameters. This appears to happen extremely rarely for
yet unknown reasons.
Bug 2038362
Change-Id: I5ca300ea9b2f8c8867b7b43e37f51a50836129b7
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1748455
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Enable FECS trace support for t194 Linux + HV
EVLR-2309
Change-Id: If22c931a54833eb995710b6e0dcad335e4ffbae6
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1674970
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- On t186, ucode expects physical address to be
programmed for FECS trace buffer.
- On t194, ucode expects GPU VA to be programmed
for FECS trace buffer. This patch adds extra
support to handle this change for linux native.
- Increase the size of FECS trace buffer (as few
entries were getting dropped due to overflow of
FECS trace buffer.)
- This moves FECS trace buffer handling in global
context buffer.
- This adds extra check for updation of mailbox1
register. (Bug 200417403)
EVLR-2077
Change-Id: I7c3324ce9341976a1375e0afe6c53c424a053723
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1536028
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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bios size is currently set to 0x40000, but this could insufficient on
some platforms
Increase it to 0x90000 so that we have buffer of sufficient size to
store bios content
Change-Id: I510d10763b1fc6ba427680e44a55e3604f67e049
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1746578
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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For gv1xx, kernel smid configuration programming is done based
on nonpes aware tpc. For user space to be in sync with hw
populate vsm mapping based on nonpes_aware_tpcs.
Bug 200405202
Change-Id: Id89291ca64c2118915dc6f18f62e17f411d467b0
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1744304
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Starting with Volta, one TPC could have more than 1 SMs. So
.record_sm_error_state needs to have sm number as parameter.
Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r.
Let the function return logical sm_id. RM server will need it to nofify
client.
Jira EVLR-2643
Bug 200405202
Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1742165
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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outstanding replayable mmu fault will prevent SM from lockdown, so
handle the replayable mmu fault while polling lockdown status.
Jira EVLR-2643
Bug 200405202
Change-Id: I811f16ef4394a6cc42a5f37a17e426dd749c5652
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1741997
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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NVGPU_SUPPORT_IO_COHERENCE is already set in gk20a_probe based
on the presence of dma-coherent property of gpu DT so this change
removes the redundant enable in gv11b_init_gpu_characteristics
VQRM-4044
Change-Id: I8c8d8d485f00aec6fae7a6794fecd855ce3a0004
Signed-off-by: Anup Kumar Sah <asah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1741090
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- PMU version update for NEXT GPU
- Added condition to assign correct ops
for NEXT GPU.
P4 CL#: 24313845
Change-Id: Ia6ee5978d450c228b4f298382746e06da56056a5
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1745022
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Export below APIs in gr_gk20a.h header
gk20a_gr_alloc_ctx_buffer()
gk20a_gr_destroy_ctx_buffer()
Jira NVGPUT-27
Change-Id: Ia181a3f464ffbc9abe12963dd709cebee9e7dbc9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1743364
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Increase NR_GLOBAL_CTX_BUF from 8 to 9 and increase NR_GLOBAL_CTX_BUF_VA
from 5 to 6 to accomodate a new global context buffer
Jira NVGPUT-27
Change-Id: I21fe4357f19db7f5647741d9ce932460868a856d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1743363
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add below new HALs to allocate/map/commit global context buffers
gops.gr.alloc_global_ctx_buffers()
gops.gr.map_global_ctx_buffers()
gops.gr.commit_global_ctx_buffers()
Set these HALs for all the supported GPUs
We right now re-use below APIs to set these HALs
gr_gk20a_alloc_global_ctx_buffers()
gr_gk20a_map_global_ctx_buffers()
gr_gk20a_commit_global_ctx_buffers()
Jira NVGPUT-27
Change-Id: I975a54e8d1716af057f982d543787748d35a256e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1743362
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added support to get fecs/gpcss sign file
based on GPU ID for sign verification by ACR
for the NEXT gpu.
Change-Id: I8e12d74ae70c6635049dd1a2248685f1382ad2a2
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1742976
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Unregister nvlink and nvlink device when gpu is
getting removed. Without this next modprobe of
nvgpu results in nvlink registration failure.
Bug 1987855
Change-Id: I785e707d1fa90f45a3ff0e9790f3f02fa15510d4
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1735986
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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ldiv_slowdown_factor sysfs node is added with change
f9e55fba but it didn't update nvgpu_remove_sysfs() to
remove it. This results in EEXIST error for
modprobe-rmmod-modprobe sequence of nvgpu driver.
Bug 1987855
Change-Id: I4360028ba75435f3e144be23f6d9f42a81dcb94b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730538
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Workaround of setting SAFE_CTR_INIT on NVLINK (WAR for Bug 1888034)
is needed only on nvlink 2.0. Add HAL to avoid running the WAR on
future chips.
Bug 2006692
Change-Id: I85fb90ea5ce7b848946f2c362e7a952787cc1261
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1738401
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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