| Commit message (Collapse) | Author | Age |
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- pmu version update to sync with CL-19816709
- GPCCS version update to sync with CL-19816709
Change-Id: Ia60bb538ddba35c973183ca2d4d3a7a0013b4b59
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/779628
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gk20a_busy() is already called on all the paths to
__gk20a_channel_syncpt_incr() i.e. in gk20a_submit_channel_gpfifo()
hence remove the redundant gk20a_busy() call since it causes
deadlock scenario with VPR resize use case
Bug 200128257
Bug 1645760
Bug 200114947
Bug 200124519
Change-Id: I4cd47b7e7cdc92aaeda17256a99f2ba93833a3b3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/778341
(cherry picked from commit 5a5dc5b5a9d38a5e8d5c1ca29dc6de425c00b605)
Reviewed-on: http://git-master/r/779070
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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gk20a_busy() was added to gk20a_channel_syncpt_update() for possible
case of channel deletion
But API to delete a channel (i.e. gk20a_free_channel()) is already
called in paths which ensure gk20a_busy() is called before
deleting the channel
Hence, remove redundant gk20a_busy()/idle() calls
This also fixes a deadlock scenario with VPR resize use case
Bug 200128257
Bug 1645760
Bug 200114947
Bug 200124519
Change-Id: I05dc739b3be88af2ba22b0a667e5004d8100bf6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/778340
(cherry picked from commit 306282aa950201cf1ae91a5cc48d75719b179d19)
Reviewed-on: http://git-master/r/779069
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Remove Tegra specific powergate and power-domain calls
from generic platform file
Change-Id: I86e263193e01150cbcf7ae50fd0c86f0b8b59b14
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/778682
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Add device-tree support for tegra power-domains and power-gating
for t186, then perform the related cleanup.
Also enable TEGRA_MC_DOMIANS, PM_GENERIC_DOMAINS_OF and
TEGRA_POWERGATE for t186.
Bug 200105664
Change-Id: I548c6b71a1577afa439a39a0eafc317a1c3cbc68
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
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As CONFIG_PM_GENERIC_DOMAINS_OF is enabled, so cleaning-up
the code which remains unused when this config is enabled.
Bug 200070810
Change-Id: I884ca3d6fb8fa6acdff8c1b2fbe66a672758274a
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
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Make modification to add DT support for gpu
power-domain for T186 chip.
Bug 200105664
Change-Id: Ief8d0a6c84918578c52d153db7eac02587b67ee7
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
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Add below sysfs to check if GPU is railgated or not :
/sys/devices/platform/gpu.0/is_railgated
Bug 200124736
Change-Id: Iafac48bbe82fcd422eeb2b948490e8dc8ad3801a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/773457
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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gk20a_pm_shutdown() is the last callback before
GPU railgate will be forced by platform code
Hence we need to call prepare_poweroff() before
returning from shutdown() to clean up below things
mainly,
1. disable interrupts to ensure that GPU is not
processing any interrupts while railgating
2. disable clocks (and related flags) to ensure
no h/w access from exported clock ops
Note that GPU railgate will be triggered by platform
code since config CONFIG_PM_GENERIC_DOMAINS_OF is
enabled by default
Bug 200123584
Change-Id: Ifaa0d1ba9b01d49bf5cc85d9c9a9feb3815866d8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/770485
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Now that the buddy allocator is merged we can increase the VA space
without dramatically increasing memory usage by the allocator.
40 bits is the max VA space available on gk20a and gm20b.
Change-Id: I7bc8d86e35b28f041e9a435f2571c8288970c8ee
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/745076
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/771152
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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The address space limit was being computed with the assumption
that the va_limit field is inclusive. The va_limit field is
actually not inclusive. It points to the first invalid byte.
Thus when generating the adr_limit register the code incorrectly
calculated that the address limit should be 0. To fix this the
computation now just uses va_limit - 1.
Also, the bitwise OR of 0xfff into the lower limit word was
incorrect. The bottom 12 bits of the lower 32 bit word are
ignored by the GPU and as such should not be populated.
Change-Id: Ifcc13343aaf50776f3cf1a1e3726e73ffde5003f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/756690
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/771151
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Fix an issue where large ( > 4GB) allocations were not being computed
correctly. The two fields, pages and page_size, were both 32 bits so
when multiplied they easily overflowed. Simple fix is to cast them to
64 bits before multiplying them.
Change-Id: I63fa54679e485de5c3a99684cbeb72c6cdc65504
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/747429
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/771148
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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While evaluating the broadcast register, use the correct max_tpc_per_gpc for gm20b.
Bug 200118793
Change-Id: Icdc506c05895e5ecdd424dfa2729d0d53460ff15
Reviewed-on: http://git-master/r/765147
(cherry picked from commit be5add9a2f13f787ea408d2a28b0b82c776227d4)
Signed-off-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-on: http://git-master/r/771254
Reviewed-by: Ken Adams <kadams@nvidia.com>
Tested-by: Ken Adams <kadams@nvidia.com>
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bug 200114561
1) when handling sched error, if CTXSW status reads switch
check FECS mailbox register to know whether next or current
channel caused error
2) Update recovery function to use ch id passed to it
3) Recovery function now passes mmu_engine_id to mmu fault
handler instead of fifo_engine_id
Change-Id: I3576cc4a90408b2f76b2c42cce19c27344531b1c
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/763538
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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if GPU is not powered before L2 is flushed, then
L2 cache flush is a noop. Same behavior as
gk20a_mm_L2_Invalidate()
bug 1661228
Change-Id: I0f590628928a73b7277d1b16a5a79a86e0213648
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/768068
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
(cherry picked from commit cb4d29d34d0736aa753afa323bfb216481cc8640)
Reviewed-on: http://git-master/r/771113
GVS: Gerrit_Virtual_Submit
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In gk20a_cde_remove_ctx(), current sequence is as below
- gk20a_channel_close()
- gk20a_deinit_cde_img()
- gk20a_free_obj_ctx()
But gk20a_free_obj_ctx() needs reference to channel and hence
below crash is seen :
[ 3901.466223] Unable to handle kernel paging request at virtual address
00001624
...
[ 3901.535218] PC is at gk20a_free_obj_ctx+0x14/0xb0
[ 3901.539910] LR is at gk20a_deinit_cde_img+0xd8/0x12c
Fix this by closing the channel after gk20a_deinit_cde_img()
Bug 1625901
Change-Id: Ic2dc5af933b6d6ef8982c2b9f0caa28df204051f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/770322
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Fixed the following sparse warning by including the "fb_gk20a.h" header file:
- fb_gk20a.c: warning: symbol 'fb_gk20a_reset' was not declared.
Should it be static?
Bug 200088648
Change-Id: I1ba6051455a22e81da6598eebdccfa8b45b78c3e
Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/768203
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/770654
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The cyclestats mode-e feature supported by userspace only
for t210 devices, so kernel should advertize it only for t210.
Also small check added to prevent BUG in dma-buf.c:826
if device has lack of memory.
Bug 1662506
Change-Id: I8417a8cdd9092e64126382f379d171932e4592a1
Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com>
Reviewed-on: http://git-master/r/767073
(cherry picked from commit 06f86b6e78bae5e26e32466716c18e7918efb1b1)
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/767148
Reviewed-by: Automatic_Commit_Validation_User
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Fixed the following sparse warning by making the local function 'static':
- warning: symbol 'gm20b_load_falcon_ucode' was not declared.
Should it be static?
Bug 200067946
Change-Id: I11beaa301dc45dfec6f2295a6a96c1571e0264c9
Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/766361
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/767991
Reviewed-by: Automatic_Commit_Validation_User
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Move rail gating sequence to happen in nvgpu driver instead of
piggybacking on Tegra power gating APIs.
Bug 200115454
Change-Id: I8514686c7b137f200021b05ead7157d0883bddc5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/761991
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eng_buf_load message structure for T18x is updated. Update kernel
code to follow.
Bug 200119744
Change-Id: Ib86c3e54ed60704470b29d9f7de612697cfd54a3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/764458
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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FB reset was added for gk20a. It should be invoked also on gm20b.
Change-Id: I0b074bc50a889108edae93d62b3194e54bfda881
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/765366
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Implement support for privileged pages. Use them for kernel allocated buffers.
Change-Id: I720fc441008077b8e2ed218a7a685b8aab2258f0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/761919
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Clock bypass divider was changed just before resetting priv ring.
Move the code to a new clk op instead so that it is executed only on
gk20a.
Change-Id: Ic8084a4a5fac23770f50b50f910ced2543ba0f28
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/764970
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add batch support for mapping and unmapping. Batching essentially
helps transform some per-map/unmap overhead to per-batch overhead,
namely gk20a_busy()/gk20a_idle() calls, GPU L2 flushes, and GPU TLB
invalidates. Batching with size 64 has been measured to yield >20x
speed-up in low-level fixed-address mapping microbenchmarks.
Bug 1614735
Bug 1623949
Change-Id: Ie22b9caea5a7c3fc68a968d1b7f8488dfce72085
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/733231
(cherry picked from commit de4a7cfb93e8228a4a0c6a2815755a8df4531c91)
Reviewed-on: http://git-master/r/763812
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: I1cd97a8ea0911a657fc4d5b7a3aee534474aea47
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/762558
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This change brings in all changes that were done for:
1. device-tree support for power domains
2. device-tree support for power-gating driver
3. Reverts of 3 changes from k3.18 power-domain
Bug 200070810
Bug 200105664
Bug 200100078
Change-Id: Iba93713180d66caa46f1f55c30e9bbde2be9dcc0
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
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As upstream has removed them, but we are still using these.
So uncommenting these callback assignment.
Bug 200070810
Change-Id: I26a221f9d76f6acef70095eb8afcf440057f464c
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
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Make modification to add DT support for gpu
power-domain for T132 chip.
Bug 200070810
Change-Id: Iac63c8fb5fc5280e9a9f5758e63c9da009f3813d
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/739698
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
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This reverts commit 83699a4ec9ebf55f6cc12c76e57dad1d4ec2fbfa.
This hack was put in place as upstream has removed of_node
field from generic_pm_domain structure. But as we are still
using it, so removing this hack.
Bug 200100078
Change-Id: I14e533786fb814e361c580e2883ceff1f63d251f
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bug 200080684
use new cmd defined in ucode for loading
GR falcons. flip PRIV load flag in lsb
header to indicate using dma. use pmu msg
as cmd completion for new cmd instead of
polling fecs mailbox. also move
check for using dma in non secure boot path
to hal.
Change-Id: I22582a705bd1ae0603f858e1fe200d72e6794a81
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/761625
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: Ie575aa3eeea8ebddf5778be0d03cf9744ec35540
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/760860
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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When flushing L2 do not check status of L2s not present in system.
Change-Id: I95703689314c146f591fea0d85b1a484fdf82cf7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/759267
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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- Fixed the following sparse warnings by making the local function as static:
warning: symbol 'balloc_alloc_buddy' was not declared. Should it be static?
Bug 200067946
Change-Id: I6eeb71f6c0d5fbfb99f6c43bbc4504fea1bc8d46
Signed-off-by: Alankrita G <alankritag@nvidia.com>
Reviewed-on: http://git-master/r/746583
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/760446
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Tested-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Client notification support is now added for the following:
- stalling and non-stalling GR sema release
- non-stalling FIFO channel intr
- non-stalling CE2 nonblockpipe intr
Bug 200097077
Change-Id: Icd3c076d7880e1c9ef1fcc0fc58eed9f23f39277
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/736064
(cherry picked from commit 0585d1f14d5a5ae1ccde8ccb7b7daa5593b3d1bc)
Reviewed-on: http://git-master/r/759824
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fixed the following sparse warning by using the proper 'NULL' instead of '0':
- fifo_gk20a.c: warning: Using plain integer as NULL pointer
Bug 200067946
Bug 200088648
Change-Id: I316b119e87b7203450ce85232398b43384ee16cc
Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/755348
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/757050
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Change-Id: Ied5b1d2e3761a2f82d6b9e3cb9a7b04ea746f1da
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755208
Reviewed-by: Automatic_Commit_Validation_User
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The allow_all checks are not required for mode-E snapshot buffers operations.
Bug 1573150
Change-Id: I570e70d7ae94b8c9bf2d3e55996442bfe5f71410
Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com>
Reviewed-on: http://git-master/r/754413
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755494
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When choosing an order of buddy to start splitting from (happens when
no buddies of the requested alloc order exist) don't sit in the while
loop past max_order. This makes no sense and hangs the system.
Bug 1647902
Change-Id: I6900597d24944d3170bc76cd75f33794b07707d1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/756591
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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If rb_erase() is called after __balloc_do_free_fixed() then the
rb_tree code crashes when trying to dereference the possibly changed
(or poisoned in the case of debugging) data in the rb_node.
Change-Id: I4a4456a5ec453fd9ab117c804dc19b2c048a61d4
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/755646
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Ian Stewart <istewart@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755816
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The WAR put into simulation to avoid a simulator crash can now be
removed (c85be1a0968de813fe9b99ebd5c261dcb0ca8875). The first issue
with the failing test was found to be GPFIFO entries that were not
invalid.
Other issues are still present with the test and are fixed in a
later commit.
Change-Id: I7d3def2e384eede82cfc82b961f09ca23b239d30
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/753378
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755815
Reviewed-by: Automatic_Commit_Validation_User
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Userspace sometimes sends GPFIFO entries with a zero length. This
is a problem when the address of the pushbuffer of zero length is
larger than 32 bits. The high bits are interpreted as an opcode and
either triggers an operation that should not happen or is trated as
invalid.
Oddly, this WAR is only necessary on simulation.
Change-Id: I8be007c50f46d3e35c6a0e8512be88a8e68ee739
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/753379
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755814
Reviewed-by: Automatic_Commit_Validation_User
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Bug 1587825
Change-Id: I66f2988b7f1884b53bb8f3cd09ad1ead1652ffda
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/751484
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: I8309837978b069fa5d416b7713654d6b71543c77
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755212
Reviewed-by: Automatic_Commit_Validation_User
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Do not preallocate cmdbuf tracking entries. Allocate them only when
needed.
Bug 200104160
Change-Id: I12f8392723c301a368af1e280893ff993480477f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/743953
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/755148
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Add reference counting for channels, and wait for reference count to
get to 0 in gk20a_channel_free() before actually freeing the channel.
Also, change free channel tracking a bit by employing a list of free
channels, which simplifies the procedure of finding available channels
with reference counting.
Each use of a channel must have a reference taken before use or held
by the caller. Taking a reference of a wild channel pointer may fail, if
the channel is either not opened or in a process of being closed. Also,
add safeguards for protecting accidental use of closed channels,
specifically, by setting ch->g = NULL in channel free. This will make it
obvious if freed channel is attempted to be used.
The last user of a channel might be the deferred interrupt handler,
so wait for deferred interrupts to be processed twice in the channel
free procedure: once for providing last notifications to the channel
and once to make sure there are no stale pointers left after referencing
to the channel has been denied.
Finally, fix some races in channel and TSG force reset IOCTL path,
by pausing the channel scheduler in gk20a_fifo_recover_ch() and
gk20a_fifo_recover_tsg(), while the affected engines have been identified,
the appropriate MMU faults triggered, and the MMU faults handled. In this
case, make sure that the MMU fault does not attempt to query the hardware
about the failing channel or TSG ids. This should make channel recovery
more safe also in the regular (i.e., not in the interrupt handler) context.
Bug 1530226
Bug 1597493
Bug 1625901
Bug 200076344
Bug 200071810
Change-Id: Ib274876908e18219c64ea41e50ca443df81d957b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/448463
(cherry picked from commit 3f03aeae64ef2af4829e06f5f63062e8ebd21353)
Reviewed-on: http://git-master/r/755147
Reviewed-by: Automatic_Commit_Validation_User
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With 4K hole T186 PMU does not boot in NS
T186 has 64 bit DMA Base. We subtract IMEM
offset from GPUVA for PMU boot DMABASE setup
It becomes above 4GB because of that
So we will use a hole which is bigger than
IMEM size.
Change-Id: Ib87c39881299a4f5b14e28415195e00800250c46
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/740656
(cherry picked from commit 6504934d5f90719a5d564174aeb92da90aafbd5b)
Reviewed-on: http://git-master/r/747742
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: I2346ed48bf82c032194264bab999097bf86404e2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/745885
(cherry picked from commit aba5f1ce08c2813c8bd570f36a5d15aa2a1aeaf8)
Reviewed-on: http://git-master/r/753286
Reviewed-by: Automatic_Commit_Validation_User
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Increase sync-unmap wait time from 5 ms to 50 ms.
6ccac11b4dd1a4eaf9c914fd567cdf7922184e28 decreased the wait tenfold, so
this puts it back.
Bug 1650025
Bug 200078514
Change-Id: I53a4ea115536ca2ff5d6aa701547c7477ac6e4ea
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/748224
(cherry picked from commit 7c22a24817f0880941e6f4343059fa303ec9eff5)
Reviewed-on: http://git-master/r/753285
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In non-silicon wait infinitely for all jobs to complete before
unmapping a fixed allocation.
Bug 200078514
Change-Id: I9196afb1d3c5f0c999113a4a17ada2989ac55707
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/744067
(cherry picked from commit 6ccac11b4dd1a4eaf9c914fd567cdf7922184e28)
Reviewed-on: http://git-master/r/753284
Reviewed-by: Automatic_Commit_Validation_User
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