| Commit message (Collapse) | Author | Age |
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This reverts commit 0b02c8589dcc507865a8fd398431c45fbda2ba9c.
Originally change was reverted as it was making ap_compute test on
embedded-qnx-hv e3550-t194 fail. With fixes related to replacing tsg
preempt with runlist preempt during teardown, preempt timeout set to
100 ms (earlier this was set to 1000ms for t194 and 3000ms for legacy
chips) and not issuing preempt timeout recovery if preempt fails, helped
resolve the issue.
Bug 200426402
Change-Id: If9a68d028a155075444cc1bdf411057e3388d48e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762563
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Moved gv11b_detect_ecc_enabled_units function
from gv11b.c to gr_gv11b.c, as this is being
used only in gr_gv11b file.
In order to avoid GR code touching fuse registers,
as it need to include fuse HW headers in GR code,
introduced two fuse HALs which are being called
from GR code. is_opt_ecc_enable for checking
whether ecc enable bit is set in fuse register
and is_opt_feature_overide_disable for checking
whether feature override disable bit is set in
fuse register.
Initialized fuse HAL functions for chips that
make use of those HAL functions.
JIRA NVGPU-615
Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775564
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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nvlink can be disabled via DT. Check if nvlink device is
present before calling nvlink specific functions to remove
the device during shutdown.
Change-Id: I33480425e2991c008f02dac989b56f21a54aa902
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1779381
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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ELPG powergate is refcounted. We should not enable/disable it,
if it's already so. Or it will break the PG disable/enable function.
Bug 200410661
Change-Id: Ife60f373b877d1ffc441578ffa53fe0d4409eba6
Signed-off-by: Daniel Fu <danifu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774265
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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nvmemleak detected memleak in the error path of gk20a_ctrl_dev_open.
nvkmemleak: Writing 'scan' to /sys/kernel/debug/kmemleak.
unreferenced object 0xffffffc0a6fffa80 (size 128):
comm "nvgpu_gpu_zcull", pid 9675, jiffies 4294948258 (age 195.764s)
hex dump (first 32 bytes):
10 28 09 ba c0 ff ff ff 00 00 69 b2 c0 ff ff ff .(........i.....
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
backtrace:
[<ffffff800824cec4>] __kmalloc+0x26c/0x308
[<ffffff8000e70990>] __nvgpu_kzalloc+0x30/0x88 [nvgpu]
[<ffffff8000e71f70>] gk20a_ctrl_dev_open+0x60/0x108 [nvgpu]
[<ffffff800827ef20>] chrdev_open+0xb8/0x1d0
[<ffffff8008274654>] do_dentry_open+0x224/0x330
[<ffffff8008275c60>] vfs_open+0x58/0x90
[<ffffff800828aeb4>] do_last+0x3e4/0xd98
[<ffffff800828b90c>] path_openat+0xa4/0x2d8
[<ffffff800828cf0c>] do_filp_open+0x84/0x108
[<ffffff800827610c>] do_sys_open+0x164/0x278
[<ffffff80082762a4>] SyS_openat+0x3c/0x50
[<ffffff8008083600>] el0_svc_naked+0x34/0x38
[<ffffffffffffffff>] 0xffffffffffffffff
Bug 200422739
Change-Id: I4ad03713ef5c8fc0e213bf4b649d38829a54a1ac
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1777656
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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NVGPU_GPUID_NEXT_2 is no more supported, hence remove it's support
from common code
Jira NVGPUT-109
Change-Id: I1bb0e5e0c19765f9a05b5a6492706090af300fd6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1764262
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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LTC register write is followed by a register read
and if data doesn't match code will report the error.
Renamed existing nvgpu_writel_check function as
nvgpu_writel_loop as it loops until the write get success.
nvgpu_writel_check function write and read back and
compare the data.
Bug 2039150
Change-Id: I0a49be36aad23936f2d58aa82872710827da1d32
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762344
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Move all FB HAL implementations to common/fb.
JIRA NVGPU-596
Change-Id: Id4ea09d608f5d6d1b245bddac09ecf1444b8ab30
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769724
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mm_gv11b.c has several direct calls to fb_gv11b.h. Redirect them to
go via a HAL. Also make sure the HALs are using parameter with
correct signedness and prefix the parameter constants with
NVGPU_FB_MMU_.
MMU buffer table indices were also defined in fb_gv11b.h, even though
the tables themselves are defined in include/nvgpu/mm.h. Move the
indices to include/nvgpu/mm.h and prefix them with NVGPU_MM_MMU_.
JIRA NVGPU-714
Change-Id: Ieeae7c5664b8f53f8313cfad0a771d14637caa08
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776131
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ucode changed so that it expects LIST_nv_perf_pma_ctx_reg
list in ctxsw buffer to be 256 byte aligned. This change
was added to gv100 before, adding similar change to gv11b.
bug 2045640
Change-Id: I1f92d38e607f70d5602ef6d5c607b9dc20807245
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1747895
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Runtime PM is enabled only for iGPU and not for dGPU. For dGPU,
the .probe() of driver pm_runtime_disable()s, if rail-gating is
not enabled. With nvgpu kernel module load/unload, .probe() is
called multiple times for same struct device *. This results
in an overflow of disable_depth (3 bit refcount) and enables
runtime PM on 8th iteration and calls RTPM routines even if it's
disabled.
To effectively manage pm_runtime_disable(), move it from common
nvgpu_remove() to iGPU/dGPU specific routines.
Also, add restore pm_runtime state of device on driver .remove().
Bug 1987855
Change-Id: I781278da546ef9c9ef7d7da7dbea0757df32716f
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770804
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On nvgpu module unload, platform_driver_unregister() detaches
driver from device (driver_detach()). As part of this,
__device_release_driver() results a race between driver's
.runtime_resume(), .remove() and .runtime_suspend().
As nvgpu's .remove() is handling all steps of cleaning up
driver state and shutting down gpu, .runtime_suspend()
shall have no work. So skip .runtime_suspend() is gk20a *g
has already been processed.
Bug 1987855
Change-Id: I024ac63d321689ea04c64b1ffc125da943d482f9
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770803
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This reverts commit 74d786dd1327bafa18b21310ac8d67db4a5614cb.
With the recent powergating changes that got merged in k4.14 and by
disabling CONFIG_PROVE_LOCKING, we no longer see any issues in T186.
The reboots observer earlier have stopped and the status of nvgpu_submit
and nvrm_gpu_tests remain the same without causing any more issues
Bug 200414723
Change-Id: Iea872612a233cb3d79df772a78fd6349c69323f2
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775199
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GK20A_DEVFREQ scaling depends on Nvidia downstream kernel
modifications to PM QoS framework. To break that dependency and to
allow devfreq based scaling to work without those changes, introduce a
Kconfig option to conditionally enable the PM Qos based constraints.
Bug 200414723
Bug 200414600
Change-Id: If39a144dfb322176c2d0e6c17d57d0cd6d885c41
Signed-off-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762987
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Hard code flags for enabling and disabling FB hub interrupts.
JIRA NVGPU-714
Change-Id: I806ef443cb9e27e221d407d633ca91d8fb40d075
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769853
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gcc-7 warns about switch statements without a break statement unless a
comment is present to indicate a deliberate fall through. Add such a
comment to allow compilation with gcc-7.3.
Bug 2224634
Change-Id: I27feec62100983e211ffd430f013d30ca56909b9
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769564
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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- For Mode-E ctxsw it is required that engine_sel
is set to 0xFFFFFFFF.
- Default 0 is a valid signal and causes problems.
Bug 2106999
Change-Id: I5cdb4441a8e6d7e8133c31a9e361b54611dd2995
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770755
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- Write new pm mode to context buffer header. Ucode use
this mode to enable mode-e context switch. This is Mode-B
context switch of PMs with Mode-E streamout on one context.
If this mode is set, Ucode makes sure that Mode-E pipe
(perfmons, routers, pma) is idle before it context switches PMs.
- This allows us to collect counters in a secure way
(i.e. on context basis) with stream out.
Bug 2106999
Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760366
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-Created common falcon function nvgpu_flcn_bl_bootstrap() to
bootstrap falcon bootloader
-Created HAL gk20a_falcon_bl_bootstrap() which does actual
bootloader bootstrap by fetching parameters and loading
code/parameters as needed.
-Created HAL ops bl_bootstrap under nvgpu_falcon_ops.
-Created struct nvgpu_falcon_bl_info to hold info required
for bootloader to pass to common function
-Removed falcons bootstrap code in multiple file & made
changes to fill struct nvgpu_falcon_bl_info & call
nvgpu_flcn_bl_bootstrap().
Change-Id: Iee275233915ff11f9afb5207ac0c3338ca9dacc1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756104
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move queries of FB MMU configuration to FB HAL. Also use g->ltc_count
instead of reading the number of LTCs from FB. These changes together
remove last direct uses of FB registers from GR.
JIRA NVGPU-714
Change-Id: I1b4b46fc2f636f5c1904e4174040a47a27948999
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1773076
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FB physical access register for simulation was programmed in GR
implementation. Move it to FB where it belongs.
JIRA NVGPU-714
Change-Id: Ic5146a61c7d45eadffdb4f3b6b08906bfcdbc224
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1772915
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In some use cases client will disable and preempt TSG and then re-enable it
using IOCTLs provided
In case there is only one context getting re-enabled and there is no other job
submission in parallel runlist fetcher will just sleep until doorbell is
received next time
This causes above mentioned test cases to stall after re-enabling TSG
until some one submits a new job and triggers a doorbell
Fix this by explicitly triggering doorbell in vgpu code
after we enable all channels in TSG.
Bug 2205192
Change-Id: I25d643e06152adc6aaf874baf610316f6cd8f13f
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1772948
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Enable replayable fault only for contexts where they are requested.
This required moving the code to initialize subcontexts to happen
later.
Fix signedness issues in definition of flags.
JIRA NVGPU-714
Change-Id: I472004e13b1ea46c1bd202f9b12d2ce221b756f9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1773262
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Do not allow enabling replayable page faults in instace block.
JIRA NVGPU-714
Change-Id: I9c48497e31798ab354a86d460a299e65774b388a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1772863
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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We do not utilize or test replayable page faults in Pascal. Remove the
code related to that.
JIRA NVGPU-714
Change-Id: I2415bde347f8b018ebf99c3f9038d47c649d9464
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769697
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gr_gv11b.c had a direct dependency to fb_gv11b.c because it calls FB
to process replayable faults while waiting for SM lockdown. Redirect
that call via HAL to remove the dependency.
JIRA NVGPU-714
Change-Id: Ie6df3658f06b1f867893bc98fe581c95813f0431
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1772884
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gp10b and gv11b variants of remove_bar2_vm are now identical, so delete
the gv11b version and use only gp10b version.
JIRA NVGPU-714
Change-Id: Ie98cb29803358ddcad8aae2cf865f3baeddebfb1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1773007
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gops.xve.enable_shadow_rom and gops.xve.disable_shadow_rom HALs could be NULL
on some platforms
Execute them only if they are defined
Jira NVGPUT-120
Change-Id: I683d74a850372f442291a419951a2376805eb1e5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1772559
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Commit c61e21c868246faf7a9ffc812590941fc362af17 fixed race codition in PMU
state transition.
- The race condition is such that PMU response(intr callback for messages) can
run faster than kthread posting commands to PMU and thus PMU message callback
may skip important pmu state change.
- Commit c61e21c868246faf7a9ffc812590941fc362af17 introduced a fix where PMU
state change was only updated from callback while other places can only update
pmu_state variable
- However, this commit introduced a regression as follows:
- When PMU state is PMU_STATE_INIT_RECEIVED, we loop over every engine
supported by GPU --> If state = PMU_STATE_INIT_RECEIVED, change the state
to PMU_STATE_ELPG_BOOTING and init ELPG else If state != PMU_STATE_INIT_RECEIVED
throw an error saying "PMU INIT not received"
- Now, if GPU supports multiple engines, first engine will check that
pmu_state is PMU_STATE_INIT_RECEIVED and change it to PMU_STATE_ELPG_BOOTING
However, from second engine onwards, since state is already changed to
PMU_STATE_ELPG_BOOTING, all engines except first engine start throwing
error "PMU INIT not received"
- This patch fixes the issue by changing pmu state from
PMU_STATE_INIT_RECEIVED to PMU_STATE_ELPG_BOOTING only once.
Bug 200372838
JIRA EVLR-2164
Change-Id: Ic8c954d14acb1d6ec3adcbc4bcf4d4745542d9f0
Signed-off-by: Deepak Bhosale <dbhosale@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769814
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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While removing nvgpu driver, devm mapped reg mappings
are released on driver_unregister. For iGPU, these
regs are explicitly unmapped with iounmap(). This
results in "Trying to vfree() nonexistent vm area"
warnings on driver removal.
Address this by using devm* variants to map all IO regions
of both iGPU and dGPU and let the driver unregister
release these mappings.
Also, lock out GPU regs in driver removal path.
Bug 1987855
Change-Id: I0388daf90bea3eaf8752255059cfd3ceabf66e7d
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730539
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In some use cases client will disable and preempt TSG and then re-enable it
using IOCTLs provided
In case there is only one context getting re-enabled and there is no other job
submission in parallel runlist fetcher will just sleep until doorbell is
received next time
This causes above mentioned test cases to stall after re-enabling TSG until
some one submits a new job and triggers a doorbell
Fix this by explicitly triggering doorbell from gv11b_fifo_enable_tsg() after
we enable all channels in TSG
Bug 2205192
Change-Id: I08e70e3d0f7e4dc6471e63809e246430cc4200c1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1772378
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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During probe of the driver, set g->log_mask to the default
value of log_mask i.e. NVGPU_DEFAULT_DBG_MASK.
Bug 1987855
Change-Id: Ia92fff2427e10f4fa9828b7b8d95f8f7b0276915
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770805
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Allocations in init_runlist can fail. Check for such
a failure during fifo setup is being done.
Bug 1987855
Change-Id: I1771a15ebeac81ab2e3ebc9a75363445a0b6f20d
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770801
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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__dma_dbg() logs func and line details of itself. Update it
to report caller details.
Bug 1987855
Change-Id: I51913b0c57c12e11880699caed557da9491304cf
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1771511
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gv11b_mm_fault_info_mem_destroy() and gv11b_mm_mmu_hw_fault_buf_deinit()
serve a similar purpose of disabling hub interrupts and deinitializing
memory related to MMU fault handling.
Out of the two the latter was called from BAR2 deinitialization, and the
former from nvgpu_remove_mm_support().
Combine the functions and leave the call from nvgpu_remove_mm_support().
This way BAR2 deinitialization can be combined with gp10b version.
JIRA NVGPU-714
Change-Id: I4050865eaba404b049c621ac2ce54c963e1aea44
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1769627
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Rename os/linux/vidmem.c to os/linux/dmabuf_vidmem.c. The code is
mainly dealing with interfacing with Linux dmabuf framework and its
responsibilities got confused with common/mm/vidmem.c.
Also move the header include/nvgpu/linux/vidmem.h to
os/linux/dmabuf_vidmem.h. It does not expose any interface to outside
Linux code.
Change-Id: I2cb1057a8934d5cb5c5860023aa12f8f048a6684
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1768261
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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vidmem.h had a forward declaration for a Linux specific struct
work_struct. Removed that.
vidmem.h also #included nvgpu_mem.h even though there was no use
for it. As a follow-up css_gr_gk20a.h did refer to nvgpu_mem but
did not #include it, so added that.
Change-Id: Ifea88adae86ed95302465641821fbb107d7cc233
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1768260
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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ioctl_dbg.h contained several unnecessary #includes. Replace them
with forward declarations. Also move all definitions only used
by ioctl_dbg.h to ioctl_dbg.c.
Change-Id: I799c8574e985f394eb653a7b7c54816ff409b058
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1768259
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The function nvgpu_sgt_create() does not exist; we never create empty
nvgpu_sgts. Delete its declaration.
Change-Id: Ib3ea975b442ffd8d50e6e1002ace10d5642f3613
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770666
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In gr_gv100_get_active_fpba_mask(), we currently use num_fbpas passed by the
caller which is usually litter (max possible on h/w) value
We should instead read the number of FBPAs from h/w instead of reading litter
value
Jira NVGPUT-117
Change-Id: I6ecd4db0fd939e1dfebf31d27e0022ae02809399
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762721
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In nvgpu_dma_alloc_flags_vid_at(), we check pending bytes of vidmem which are
yet to be cleared by reading g->mm.vidmem.bytes_pending.atomic_var
If there is something to be cleared we return EAGAIN otherwise we return ENOMEM
But to store above variable we use "int before_pending" which evaluates to zero
for sizes like 4GB and we end up returning ENOMEM instead of EAGAIN
Fix this by declaring before_pending variable as u64
Bug 200427361
Change-Id: I6ffe977e3663a5135fa17699ecafe78ac90d9314
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770384
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add new HAL gops.fb.mmu_invalidate_replay() to invalidate replay mmu fault
Use existing API gv11b_fb_mmu_invalidate_replay() to set to this HAL on all
Volta chips
Bug 2228914
Jira NVGPU-838
Jira NVGPUT-73
Change-Id: I394901857d41499f3ea44023393fe271fb664260
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1767970
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In gr_gk20a_split_ppc_broadcast_addr() we convert a PPC broadcast address to
its corresponding unicast address list
But we consider gr.pe_count_per_gpc instead of actual number of PPCs and that
leads to generating incorrect list of addresses
Fix this by using gr.gpc_ppc_count[gpc_num] which gives correct number of
PPC count
Jira NVGPUT-117
Change-Id: If7e7c19244b90cb3c405dcba4ae7a86c782972f7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1767838
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added prefix gp106_ to sec2_wait_for_halt()
& sec2_clear_halt_interrupt_status() for gp106
SEC2 HAL
- Made changes to gp106_sec2_wait_for_halt() to
read SEC2 falcon mailbox using common falcon
mailbox access functions.
- Add define for falcon mailbox
- These changes are done to reuse gp106 HAL's
for GPU_NEXT.
Change-Id: Id32a7636d775b482684212ed4ef5d01c8ea65335
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1755618
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-Do sec2 reset using common falcon HAL
nvgpu_flcn_reset() by passing sec2_flcn
struct which holds base address of SEC2
falcon as per chip specific.
JIRA NVGPUT-111
Change-Id: I2b95262a93644bbefed5b6c46dc73200afd97730
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1755617
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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In gr_gk20a_find_priv_offset_in_buffer() we right now calculate
offset of a register in gpccs segment based on register address type
Separate out sequence to find offset in gpccs segment and move it to new API
gr_gk20a_get_offset_in_gpccs_segment()
Introduce new HAL gops.gr.get_offset_in_gpccs_segment() and set above API
to this HAL
Call HAL from gr_gk20a_find_priv_offset_in_buffer() instead of calling direct
API
Jira NVGPUT-118
Change-Id: I0df798456cf63e3c3a43131f3c4ca7990b89ede0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761669
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Bug 200327089
Change-Id: Id7bd2795647f1e29dabe41acb20d0994cdd07958
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1764267
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The g->can_railgate flag is a global constant-ish property like the rest
of the flags behind nvgpu_is_enabled() API, so move it there.
Bug 200327089
Change-Id: Id1f2f16ea1975a03fb56f10c2f3c8c705574e341
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1764266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Kernel mode submits conflict with user submits, so don't allow them if a
channel user has asked for usermode submit support.
Bug 200145225
Change-Id: I3a99222b09260a1b3e116c6aa86d8da5d380d903
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1767907
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Enable ECC interrupt in Falcon interrupt source
- Enable routing of ECC interrupt to HOST.
code CL: https://git-master.nvidia.com/r/#/c/1758176/
p4 CL# 24408680
Change-Id: Ib43c80be64e29ccbc6b19168e67ac6f4d200b2d8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1758175
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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