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* gpu: nvgpu: Add a bootstrap vidmem allocatorAlex Waterman2016-09-01
| | | | | | | | | | | | | | | | Add an allocator for allocating vidmem before the CE has had a chance to be initialized (and clear the rest of vidmem). Jira DNVGPU-84 Change-Id: I5166607a712b3a6eb4c2906b8c7d002c68a6567b Signed-off-by: Alex Waterman <alexw@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1197204 (cherry picked from commit b4e68e84eedd952637b2332d8dc73a9090d6d62e) Reviewed-on: http://git-master/r/1210949 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: support GMMU mappings for vidmem page allocatorDeepak Nibade2016-09-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to use page allocator for vidmem Support GMMU mappings for page (non-contiguous page allocator) in update_gmmu_ptes_locked() If aperture is VIDMEM, traverse each chunk in an allocation and map it to GPU VA separately Fix CE page clearing to support page allocator Fix gk20a_pramin_enter() to get base address from new allocator Define API gk20a_mem_get_vidmem_addr() to get base address of allocation. Note that this API should not be used if we have more than 1 chunk Jira DNVGPU-96 Change-Id: I725422f3538aeb477ca4220ba57ef8b3c53db703 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1199177 (cherry picked from commit 1afae6ee6529ab88cedd5bcbe458fbdc0d4b1fd8) Reviewed-on: http://git-master/r/1197647 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: send only one event to the debuggerCory Perry2016-09-01
| | | | | | | | | | | | | | | | | | | | | | Event notifications on TSGs should only be sent to the channel that caused the event to happen in the first place, not evey channel in the tsg. Any more and the debugger will not be able to tell what channel actually got the event. Worse yet, if all the channels in a tsg are bound to the same debug session (as is the case with cuda-gdb), then multiple nvgpu events for the same gpu event will be triggered, causing events to be buffered and the client to get out of sync. One gpu exception, one nvgpu event per tsg. Bug 1793988 Signed-off-by: Cory Perry <cperry@nvidia.com> Change-Id: I4efb83b0593bd1af38f2342c80793d9db56e42b1 Reviewed-on: http://git-master/r/1194203 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix error handling of __semaphore_bitmap_alloc()Alex Waterman2016-08-31
| | | | | | | | | | | | | | | The return from __semaphore_bitmap_alloc() is an int for which a negative value indicates a failure. That return value was being directly cast to an unsigned int before being checked for a negative error code. This obviously isn't a good idea. Coverity ID 38754 Change-Id: I50c0478e5504988b059e69b929e9c2e465df7cc0 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1210317 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix possible overflow in buddy allocatorAlex Waterman2016-08-31
| | | | | | | | | | | | | | | Fix a possible overflow in the buddy allocator's initialization code. In practice it should never happen that pde size is greater than 32bits but this makes coverity happy. Coverity ID 54964 Change-Id: I886fd962bb3e9e328f7305bdcf69827979a39a21 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1210316 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachit Kadle <skadle@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gk20a: Use spin_lock for jobs_lockBharat Nihalani2016-08-31
| | | | | | | | | | | | | | | | | | | | This is done to boost performance of the GPU submit time, which is critical for compute use-cases. Bug 200215465 Bug 1804898 Conflicts: drivers/gpu/nvgpu/gk20a/channel_gk20a.c Change-Id: Ic4884ee4eac910b92b84a47fdc1b2e9f26b2f1f0 Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-on: http://git-master/r/1199860 Reviewed-on: http://git-master/r/1209834 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix build error when CONFIG_DEBUG_FS=nDavid Pu2016-08-31
| | | | | | | | | | | | | | | | | | adding 'ifdef CONFIG_DEBUG_FS' check to fix following compilation error when CONFIG_DEBUG_FS=n(which is used for Android 'production' build): mm_gk20a.c: In function 'gk20a_mm_debugfs_init': mm_gk20a.c:4824:2: error: implicit declaration of function 'debugfs_create_x64' [-Werror=implicit-function-declaration] Bug 1778001 Change-Id: I785288a37b96c391b84925d5971d2691cf80206e Signed-off-by: David Pu <dpu@nvidia.com> Reviewed-on: http://git-master/r/1210393 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Turn the debug macro back to pr_infoAlex Waterman2016-08-30
| | | | | | | | | | | | | | | | Instead of having the debug prints from the allocators be warnings they should be just regular prints. Bug 1799159 Change-Id: Ic6e3c38fa286c4acd6fcba51dc59158dc2d655fc Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1201372 (cherry picked from commit 107caf4ce68a7c76023ee1e66a98c5570f401059) Reviewed-on: http://git-master/r/1208478 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Clarify comment in allocator codeAlex Waterman2016-08-30
| | | | | | | | | | | | | | | | | One of the flags that is defined for allocators has not yet been imlpemented. This clarifies the comment and explains why the flag has been defined even though it is not yet implemented. Bug 1799159 Change-Id: I1e84439d63ca391941cee8e5362ffd9cc959744b Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1201371 (cherry picked from commit 8e6566b173f17d9c169a9fa0f6104f4bbf608dc1) Reviewed-on: http://git-master/r/1208477 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add checking in allocator functionsAlex Waterman2016-08-30
| | | | | | | | | | | | | | | | | | | | | | | Add checks to make sure function pointers are valid before attempting to call said function. Also, ensure that any allocator created defines the following 3 functions at minimum: alloc() free() fini() Bug 1799159 Change-Id: I4cd3d5746ccb721c723a161c9487564846027572 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1200059 (cherry picked from commit e26557a49d7ca6629ada24f12a3be396b0ae22cd) Reviewed-on: http://git-master/r/1208476 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add debugging to the semaphore codeAlex Waterman2016-08-30
| | | | | | | | | | | | | | | Add GPU debugging to the semaphore code. Bug 1732449 JIRA DNVGPU-12 Change-Id: I98466570cf8d234b49a7f85d88c834648ddaaaee Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1198594 (cherry picked from commit 420809cc31fcdddde32b8e59721676c67b45f592) Reviewed-on: http://git-master/r/1153671 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add gpu_dbg_map_v message typeAlex Waterman2016-08-30
| | | | | | | | | | | | | | | | | | | | | Add a new debug message type: gpu_dbg_map_v. This is used for mapping messages that are not specifically memory map operations. Also cleanup the memory mapping debugging a bit since there was one duplicate print and the memory map print was difficult to parse visually. As a result the message has been modified to put the most important information first in an easily readable format. Bug 1732449 JIRA DNVGPU-12 Change-Id: Ib19c9371ee958009ab5a2d89b9610e699d070ee2 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1198593 (cherry picked from commit 51dba53b06ca171cdb13d1707f2d026b0ce29f07) Reviewed-on: http://git-master/r/1147670 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add semaphore debugging infoAlex Waterman2016-08-30
| | | | | | | | | | | | | | | | Add semaphore debugging information to the gk20a channel state debug dump. Bug 1732449 JIRA DNVGPU-12 Change-Id: I7caafd4f6420e1c478be22e236513603c315ce5e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1198592 (cherry picked from commit 3fa247adf5fdd8c9b16a24fec00903fdc3abc90a) Reviewed-on: http://git-master/r/1133793 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement a vidmem allocatorAlex Waterman2016-08-30
| | | | | | | | | | | | | | | | | | | Implement an allocator suitable for managing the video memory on dGPUs. It works by allocating chunks from an underlying buddy allocator and collating the chunks together (similar to what an sgt does in the wider Linux kernel). This handles the ability to get large buffers in potentially fragmented memory. The GMMU can then obviously map the physical vidmem into contiguous GVA spaces. Jira DNVGPU-96 Change-Id: Ic1d7800b033a170b77790aa23fad6858443d0e89 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1197203 (cherry picked from commit fa44684a843956ae384fef6d7a79b9cbbd04f73e) Reviewed-on: http://git-master/r/1185231 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: do not flush FECS record on engine resetThomas Fleury2016-08-29
| | | | | | | | | | | | | | | | | | | | | | | Flushing timestamp record method can fail in case FECS is not processing the main method queue. In particular, this occurs in case of ctxsw timeout, where we process fifo sched interrupts from the host, but FECS is still waiting for idle (grWFI). In such scenario, this adds huge delay in fifo recovery procedure (timeout on FECS method). Since flushing the last (incomplete) record from FECS would only be useful in that case (context switch ongoing), remove flush operation on engine reset. Note that an explicit ENGINE_RESET event (with pid) is inserted in user-facing ctxsw buffer on engine reset. Bug 200228310 Change-Id: I885525f8f197f81266b50db161bb511867fc74f4 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1207305 (cherry picked from commit 44391b6204fd648949295f90481b0c424d9a5ddf) Reviewed-on: http://git-master/r/1208414 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix reported interleave for TSGsThomas Fleury2016-08-29
| | | | | | | | | | | | | | | If a channel is part of a TSG, report TSG's interleave in debugfs for sched parameters. Bug 200228310 Change-Id: I2eeee7aacfa92f9d5fc367225a23a663ca6ac593 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1207304 (cherry picked from commit 1950ae679f112dcf24a7f3c695d4ab098de10326) Reviewed-on: http://git-master/r/1208413 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix ctxsw timeout handling for TSGsThomas Fleury2016-08-29
| | | | | | | | | | | | | | | | | | | | | While collecting failing engine data, id type (is_tsg) was not set for ctxsw and save engine states. This could result in some ctxsw timeout interrupts to be ignored (id reported with wrong is_tsg). For TSGs, check if we made some progress on any of the channels before kicking fifo recovery. Bug 200228310 Jira EVLR-597 Change-Id: I231549ae68317919532de0f87effb78ee9c119c6 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1204035 (cherry picked from commit 7221d256fd7e9b418f7789b3d81eede8faa16f0b) Reviewed-on: http://git-master/r/1204037 Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: fix channel abortRichard Zhao2016-08-23
| | | | | | | | | | | | | set timeout for channel force reset, to prevent submit immediately. Bug 1778448 JIRA VFND-2097 Change-Id: I729597a68cbdc5ed3f6c878955a10ae7c4659fa4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1203298 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: add channel wdt supportRichard Zhao2016-08-18
| | | | | | | | | | | | | | - avoid dump gr registers for vgpu - init wdt lock Bug 1776876 JIRA VFND-2151 Change-Id: I73293e0d23b614129c763cb22b09156a8e1432cc Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1202256 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use force_reset_ch in ch wdt handlerRichard Zhao2016-08-18
| | | | | | | | | | | | | | - let force_reset_ch pass down err code - force_reset_ch callback can cover vgpu too. Bug 1776876 JIRA VFND-2151 Change-Id: I48f7890294c6455247198e0cab5f21f83f61f0e1 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1202255 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: get constants of gpc_tpc_count/mask arraysRichard Zhao2016-08-15
| | | | | | | | | | | | It'll cover multi-gpcs. JIRA VFND-2103 Change-Id: Ie82bdaad360294696c5a679d694f6f0e2364ca2e Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1194631 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add getting gr constantsRichard Zhao2016-08-15
| | | | | | | | | | | | | | | | | | | | move below attributes to constants: TEGRA_VGPU_ATTRIB_GPC_COUNT TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT TEGRA_VGPU_ATTRIB_NUM_FBPS TEGRA_VGPU_ATTRIB_FBP_EN_MASK TEGRA_VGPU_ATTRIB_MAX_LTC_PER_FBP TEGRA_VGPU_ATTRIB_MAX_LTS_PER_LTC JIRA VFND-2103 Change-Id: Ic2ac14a0f8a1cf19a996bcef20bef0003d3b9a3b Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1194630 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add getting sm version constantsRichard Zhao2016-08-15
| | | | | | | | | | | | | | move below attributes to constants: TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH JIRA VFND-2103 Change-Id: I5d6aa8f4a49e65307989ef02d223c3ee31fcdeed Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1190481 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add getting ltc constantsRichard Zhao2016-08-15
| | | | | | | | | | | | | | | | | | | move below attributes to constants: TEGRA_VGPU_ATTRIB_COMPTAG_LINES TEGRA_VGPU_ATTRIB_L2_SIZE TEGRA_VGPU_ATTRIB_CACHELINE_SIZE TEGRA_VGPU_ATTRIB_COMPTAGS_PER_CACHELINE TEGRA_VGPU_ATTRIB_SLICES_PER_LTC TEGRA_VGPU_ATTRIB_LTC_COUNT JIRA VFND-2103 Change-Id: Iecf9717ee553a16ffe8de445be5bfe5a99c3a094 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1190480 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add getting constants golden img size and zcull ctx sizeRichard Zhao2016-08-15
| | | | | | | | | | JIRA VFND-2103 Change-Id: I180324b36a1c6b39300b92a2cff6448d7665679b Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1190479 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add cmd to get RM server constantsRichard Zhao2016-08-15
| | | | | | | | | | | | | | | | Moving getting constant attributes into one cmd which will be called only once. This patch adds basic infrastructure and gpu arch info, max_freq and num_channels support. JIRA VFND-2103 Change-Id: I100599b49f29c99966f9e90ea381b1f3c09177a3 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1189832 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: vgpu: add vgpu private data and helper functionsRichard Zhao2016-08-15
| | | | | | | | | | | | | | Move vgpu private data to a dedicated structure and allocate it at probe time. Also add virt_handle helper function which is used everywhere. JIRA VFND-2103 Change-Id: I125911420be72ca9be948125d8357fa85d1d3afd Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1185206 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: fix deferred engine reset sequenceDeepak Nibade2016-08-12
| | | | | | | | | | | | | | | | | | | | | | | | | We currently store fault_id into fifo.deferred_fault_engines and use that in gk20a_fifo_reset_engine() which is incorrect Also, in deferred engine reset path during channel close, we do not check if channel is loaded on engine or not fix this with below - store engine_id bits into fifo.deferred_fault_engines - define new API gk20a_fifo_deferred_reset() to perform deferred engine reset - get all engines on which channel is loaded with gk20a_fifo_engines_on_id() - for each set bit/engine_id in fifo.deferred_fault_engines, check if channel is loaded on that engine, and if yes, reset the engine Bug 1791696 Change-Id: I1b8b1a9e3aa538fe6903a352aa732b47c95ec7d5 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1195087 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable rail gating for dGPULakshmanan M2016-08-12
| | | | | | | | | | | | | | Bug 200224907 Change-Id: I515bba1987e54fb5ab78efda85916b6f0d3a4297 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1201233 (cherry picked from commit aa45908e77d451376728860cebe3938e765c4388) Reviewed-on: http://git-master/r/1201654 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Exclude first page from vidmem sizeTerje Bergstrom2016-08-10
| | | | | | | | | | | | | | | | We initialized vidmem allocator with base=4K, and size of 4GB. This caused allocator to allocate addresses between 4K and 4GB+4K, causing a physical MMU fault. Bug 1793810 Change-Id: I554f62aeee4080acd86ef2c8011089ec9b8120df Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1196300 (cherry picked from commit 41a860e21c6da3f8fda58ceb56e78316f6987f53) Reviewed-on: http://git-master/r/1200712 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Set PCI device node permissionsTerje Bergstrom2016-08-10
| | | | | | | | | | | | | Device nodes for PCI devices need to be RW for everybody. Bug 200225622 Change-Id: I14de9d17f76ca45ba525d0c4f5e8d448bbfda98b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1198556 (cherry picked from commit 60bf9118715b61b8cd3f2379479caf280ae4e35c) Reviewed-on: http://git-master/r/1200713 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Free the channel used semaphore indexLakshmanan M2016-08-10
| | | | | | | | | | | | | | | Free the channel used semaphore index during gk20a_free_channel(). Bug 1793819 Change-Id: I4215d05f7f3ba0636e2abb1803011711c8a38301 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1196877 (cherry picked from commit 2c5720de506caac29629f6a1c578e6da80b1a135) Reviewed-on: http://git-master/r/1198883 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: post bpt events after processingDeepak Nibade2016-08-10
| | | | | | | | | | | | | | | | | | We currently post bpt events (bpt.int and bpt.pause) even before we process and clear the interrupts and this could cause races with UMD Fix this by posting bpt events only after we are done processing the interrupts Bug 200209410 Change-Id: Ic3ff7148189fccb796cb6175d6d22ac25a4097fb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1184109 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: initialize local variableDeepak Nibade2016-08-04
| | | | | | | | | | | | | | | | | Initialize character array buf in gk20a_channel_ioctl() to zero Keeping it uninitialized can result in leaking kernel stack info to user space since we pass this buffer to UMD Bug 1793398 Change-Id: Iffd654dbaca3b4e3c8fd2ac270d0febd01c165b8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1195862 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Remove early exit from mmu faultCory Perry2016-08-01
| | | | | | | | | | | | | | | Disabling / enabling of PFIFO must stay inside the isr. It cannot be held disabled outside the isr -- this causes any kind of preemption mechanism to fail in the presence of an MMU fault until the channel resets the engine. Bug 1791696 Change-Id: I16600a8571f6555262a75deb305c1d67eb29581a Signed-off-by: Cory Perry <cperry@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1191026 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move dbg_session_ops to gopsPeter Daifuku2016-07-30
| | | | | | | | | | | | | | Move dbg_session_ops to gops for better code consistency JIRA VFND-1905 Change-Id: I04a11d77dd8c26d9922e80e556822f80dd2bc36d Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1192641 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add preemption mode support for gp10xLakshmanan M2016-07-29
| | | | | | | | | | | | | | | Added preemption mode (WFI, GFXP, CTA and CILP) support for gp10x family gr class (PASCAL_B and PASCAL_COMPUTE_B). Bug 200221149 Change-Id: I859a4d2db518bca0ffeb0d85a6bb271f6b15db87 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1193207 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add check for is_fmodelSeema Khowala2016-07-27
| | | | | | | | | | | | | | | | is_fmodel flag will be set in gk20a_probe(). Updated code for is_fmodel check, instead of check for supported simulated platforms. Bug 1735760 Change-Id: I7cbac2196130fe5ce4c1a910504879e6948c13da Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1177869 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Add is_fmodel flagSeema Khowala2016-07-27
| | | | | | | | | | | | | | | | | | Added is_fmodel flag in gk20a platform data and this flag is set to true for simulated gpu platforms. Bug 1735760 Change-Id: Ib04579d2e2990ee051039bfb741d6e50523d44ac Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1177868 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-by: Ayoosh Bansal <ayooshb@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com>
* gpu: nvgpu: restore gk20a_scale_notifySachit Kadle2016-07-27
| | | | | | | | | | | | | | | Restores call to gk20a_scale_notify_busy() in gk20a_busy(), which was unintentionally removed in commit 6ac44d2813f5ab1873eb5148f26746a8f9dbd4a8 Bug 200187507 Change-Id: I96239d9e3e7cbd0911ebae358ec9dae39ec82566 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1191327 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: make func gm20b_gr_tpc_disable_override globalRichard Zhao2016-07-27
| | | | | | | | | | | | | Bug 200220632 Change-Id: I75f628c54d68bbd06d5d8aeb32b8ee145411b8da Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1185067 (cherry picked from commit 0523a71eaac9dc7751f6e0e7d280b01f3a9e4ea3) Reviewed-on: http://git-master/r/1189784 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: take platform power ref at power onSachit Kadle2016-07-27
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, host1x power refcount may decrement to 0, while GPU is still powered on and we're still servicing IRQs. So to prevent this situation,, take a ref while GPU is being powered on, and decrement it during power off. Since we are always holding one reference while GPU is powered on, we can remove this handling from gk20a_busy/idle() Bug 200187507 Change-Id: I249a4527178537c1dc53d769411f53c4451352c3 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1172320 (cherry picked from commit 3e27e6a5820f5c1ad05596553d75e8979b71f1bd) Reviewed-on: http://git-master/r/1172607 (cherry picked from commit 1e01a49fdc139b8cdf5164b4a6767d22ef4ad1d3) Reviewed-on: http://git-master/r/1185175 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: corner case failure handling in CE infra interfaceLakshmanan M2016-07-26
| | | | | | | | | | | | | | | | | This CL covers the following simple modification, 1) Linux kernel list implementation doesn't handle NULL pointer dereference at list_del() api. 2) NULL validation before access the command buffer related operations. This required for prevent the illegal/NULL memory access during gk20a_ce_create_context_with_cb() failure case. JIRA DNVGPU-53 Change-Id: I3ad178970ecb1485098124378bfc5256a9455ebd Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1184294 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: check for valid function pointersseshendra Gadagottu2016-07-25
| | | | | | | | | | | | | | | | Before calling prod settings functions, check for availability of those functions. Similar check is extended for get_clk_freqs. Bug 1735760 Change-Id: Ic4b38079043ab2049a479a2d8bb0cb6091e94f4a Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1181571 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com>
* gpu: nvgpu: avoid host1x device dependencyseshendra Gadagottu2016-07-25
| | | | | | | | | | | | | | | | | Create sysfs nodes for gpu under host1x, only when host1x device dependncy present. For all gpus create syfs nodes under generic gpu name "gpu.0" Bug 1735760 Change-Id: I4b4a984139e0c33feadd95613c2f2076bc2db33b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1181068 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com>
* nvgpu: rename Kconfig to Kconfig.nvgpudmitry pervushin2016-07-22
| | | | | | | | | | | | | Bug 1783210 Signed-off-by: dmitry pervushin <dpervushin@nvidia.com> Change-Id: Ie62dc86e6dc64c4dd939b54f806df557891fee9d Reviewed-on: http://git-master/r/1175284 Reviewed-on: http://git-master/r/1177293 GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-on: http://git-master/r/1183065
* nvgpu: rename Makefile to Makefile.nvgpudmitry pervushin2016-07-22
| | | | | | | | | | | | | Bug 1783210 Signed-off-by: dmitry pervushin <dpervushin@nvidia.com> Change-Id: I08e3ffb6b59ab145588a5ecf81b6c2346a481628 Reviewed-on: http://git-master/r/1175267 Reviewed-on: http://git-master/r/1177292 GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-on: http://git-master/r/1183064
* gpu: nvgpu: add aperture and size to map loggingKonsta Holtta2016-07-22
| | | | | | | | | | | | Include the buffer aperture flag (sysmem/vidmem/invalid) and the size of the buffer and of the mapping in logging strings during gmmu map path. Change-Id: Ie4c46bf9cb5db79b738571029d46ce8cbfc63f99 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1189492 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Full chip support for ctxswneha2016-07-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | nvgpu changes needed to handle the newly added ctxsw lists Fix regops support for ppc registers Squashed from: Change-Id: I08e6dec3bb2f7aa51de912c9d1c84a350ce07f72 Signed-off-by: neha <njoshi@nvidia.com> Reviewed-on: http://git-master/r/1151010 (cherry picked from commit fd03ad9f09e66f78db88fb7ece448e26e0515821) and: Change-Id: I75a7f810ee0b613c22ac2cef2d936563d8067f97 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1158888 (cherry picked from commit f00a7fcc57fb937b800e46760087ff6f7637520c) Bug 200180000 Bug 1771830 Reviewed-on: http://git-master/r/1164397 (cherry picked from commit 7028f051e4f37edeff90a9923f022cec6c645a8f) Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Change-Id: I796ddf93ef37170843a4a6b44190cd6780d25852 Reviewed-on: http://git-master/r/1183588 Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Ensure PDE alignment for GVA spacesAlex Waterman2016-07-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When managing GVA spaces the buddy allocator requires PDE size alignment. This is to ensure that PTE size in buddies always remains consistent. Consider the following hypothetical GVA space: it is 32 elements long, order 0 block size is 1, and PDE size is 8. This leads to: Base: 8 Size: 24 Managed space: [8, 32) The start of the space will be 8 (base must be aligned to a PDE and we need a hole at the bottom for handling errors). Size is simply the max, 32, minus what we cut out for the low hole. The two top level buddies are [8 -> 24), and [24 -> 32). Now, suppose, instead the base were 4: Base: 4 Size: 28 Managed space: [4, 32) The top level buddies would be [4 -> 20), [20 -> 28), and [28 -> 32). This presents several problems: none of the buddies are PDE aligned and one top level buddy is smaller than the PDE size. The simplest issue is how to determine the PTE size of the [28 -> 32) block. We can just set it as small but that's not ideal. The bigger issue is the mis-alignment of the larger buddies. [20 -> 28) is halfway in one PDE and halfway in another. That means the allocator would have to manage the two sub-buddies [20 -> 24) and [24 -> 28) separately. Instead of dealing with the above issues in the allocator it is much more simple to require that any GVA space is PDE aligned since they are already massive and already, in practice, have this alignment. Change-Id: I9eacd2db6485291db9f9f1d6c4c03c2a5c22de03 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1185137 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:14:54 -0500