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* gpu: nvgpu: gv100: BOOTSTRAP_GR_FALCONS using RPCMahantesh Kumbar2018-01-25
| | | | | | | | | | | | | | | - Created nv_pmu_rpc_struct_acr_bootstrap_gr_falcons struct - gv100_load_falcon_ucode() function to bootstrap GR flacons using RPC, wait for INIT_WPR_REGION before creating & executing BOOTSTRAP_GR_FALCONS RPC. - Added code to handle BOOTSTRAP_GR_FALCONS ack in RPC handler Change-Id: If70dc75bb2789970382853fb001d970a346b2915 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1613316 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: INIT WPR region using RPCMahantesh Kumbar2018-01-25
| | | | | | | | | | | | | | | | - Created nv_pmu_rpc_struct_acr_init_wpr_region struct - Function gv100_pmu_init_acr() to create & execute INIT_WPR_REGION using RPC. - Updated gv100 HAL .init_wpr_region to point to gv100_pmu_init_acr() - Added code to handle INIT_WPR_REGION ack in RPC handler. Change-Id: I699fa945790689e5f24ad5d3de022efb458662e0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1613290 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: PMU f/w updateMahantesh Kumbar2018-01-25
| | | | | | | | | | | | | | | | | | | | | | | | -Added new version of pmu init msg "pmu_init_msg_pmu_v5" -created methods to support new pmu init message parameter read based on f/w version for below ops. .get_pmu_msg_pmu_init_msg_ptr .get_pmu_init_msg_pmu_sw_mg_off .get_pmu_init_msg_pmu_sw_mg_size -Corrected PMU_DMEM_ALLOC_ALIGNMENT value to 32 bit to allocate PMU DMEM space for nvgpu -Updated PMU version of GV100/APP_VERSION_BIGGPU to 23440730 & PMU ucode CL is https://git-master.nvidia.com/r/#/c/1642432/ Change-Id: Ib1e0197b5f3a229a601e810c9c0d93f05b9d69e7 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1642229 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Smarter way to check vmalloc addressAlex Waterman2018-01-24
| | | | | | | | | | | | | | | | | | | | | | In the nvgpu_big_free() function the passed in address is checked to see what type of address it is: kmalloc or vmalloc. This change uses the is_vmalloc_addr() instead since this is a much clearer and easier way to determine if a virtual address should be vfree()ed. Anything not a vmalloc address is then assumed to be a kmalloc() address. Bug 2049449 Change-Id: I2bd9441d3c5fc455f03ec2075d012c607280ad5f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1644802 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Arun Kannan <akannan@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: disable idle clock slowdownseshendra Gadagottu2018-01-24
| | | | | | | | | | | | | | | | | | Updated thermal settings as per hw POR update: - Disabled idle clock slowdown - Updated therm_grad_stepping1_pdiv_duration as per updated hw por value. Bug 200365110 Change-Id: I0c67366ecebd5681343746e9badb57fa74dfaeaa Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1643895 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement gp10b variant of cbc_ctrlTerje Bergstrom2018-01-24
| | | | | | | | | | | | | | | | | | | | | Pascal has support for more comptags than Maxwell, but we were using gm20b definitions for cbc_ctrl on all chips. Specifically field clear_upper_bound is one bit wider in Pascal. Implement gp10b version of cbc_ctrl and take that into use in Pascal and Volta. Bug 200381317 Change-Id: I7d3cb9e92498e08f8704f156e2afb34404ce587e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1642574 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: set detach_snapshot in gv11b gopsRichard Zhao2018-01-24
| | | | | | | | | | | | | | | It has to be set to detach snapshot. We missed it somehow. Jira VFND-4703 Change-Id: Ia5842494f86fb2d788d72ba372ee8870977a2f67 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640668 GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: skip mmu fault buf alloc after resumeSeema Khowala2018-01-24
| | | | | | | | | | | | | Skip allocating memory if required s/w set up for mmu fault buffers is already done. Bug 2045228 Change-Id: Ib88e8dd4f54b3f0faf7dc9edf091ec285220f7b5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640516 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove fault_buf_status arrayAlex Waterman2018-01-24
| | | | | | | | | | | | Now that we have a consistent way to check if a mem allocation is valid this array is not necessary. The code can simply check the validity of the nvgpu_mem. Change-Id: I6aaf563ddc314cf86a2c2b98f7eb75fa7a9a1ad9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1641637 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "Revert "gpu: nvgpu: disable_syncpoints debugfs changed to read only""Inamdar Sharif2018-01-24
| | | | | | | | | | | | | | | This reverts commit 4021d42cbb37c6d7cd30bd132d1d08d004422917. Original change was reverted since that was suspected to have caused opengles test faulure on QNX, but it turned out that the original change was actually not causing the failure. Hence original change is restored. Change-Id: I64796f1a3b1f700f294c259d4426c493f2f1ad85 Signed-off-by: Inamdar Sharif <isharif@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1643309 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove extranneous linux include in mm_gv11b.cSourab Gupta2018-01-24
| | | | | | | | | | | The patch removes the extranneous linux include in the file mm_gv11b.c, which is not required. Change-Id: I6d5a5d27ec9120ad7784348ba81f9e5d0c320c19 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1643293 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Report mailbox id and value on ucode timeoutTerje Bergstrom2018-01-23
| | | | | | | | | | | | | | | | | | | | When we detect a timeout waiting for ctxsw ucode method to complete, we print an error. The error does not detail the event we are waiting which makes debugging difficult. Add the missing mailbox id and value to the error. Bug 2049965 Change-Id: I45204a2d6f1f39919a0133b1e0867213e1a5b671 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1643709 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: gv11b: enable devfreq"Konsta Holtta2018-01-23
| | | | | | | | | | | | | | | This reverts commit 968d8cd3e543b951714d9a86373bd721d08c8482. Bug 2049965 Bug 2039013 Bug 200377508 Change-Id: I813947417740f8d3a0c9bea82784df1dd4a5f1ac Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1644224 Reviewed-by: David Pu <dpu@nvidia.com> Tested-by: David Pu <dpu@nvidia.com>
* gpu: nvgpu: skip missing gpc_tpc_count in gr dumpsKonsta Holtta2018-01-23
| | | | | | | | | | | | | | | | The gv11b and gm20b gr status reg dumps can get printed so early that this array is null, so don't access it in that case. Commit 946f1e635963d20f1e9f8020024c781448bfeb2d ("gpu: nvgpu: don't read missing gpc_tpc_count in dump") fixed this for gp10b only. Bug 2049965 Change-Id: I9739fd63b5a153f43000d719a5c509e3be5135cf Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1643692 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU code cleanupMahantesh Kumbar2018-01-23
| | | | | | | | | | | | | | | | | | | | -removed unsupported PMU f/w version defines & corrected naming specific to chip -removed unsupported PMU f/w version methods which are not useful for existing ucode. -removed unsupported PMU interface which are not useful for existing ucode Change-Id: I17933ff656f48a888e049d680f108b2ef7537439 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1643399 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fold T19x code back to main code pathsTerje Bergstrom2018-01-23
| | | | | | | | | | | | | Lots of code paths were split to T19x specific code paths and structs due to split repository. Now that repositories are merged, fold all of them back to main code paths and structs and remove the T19x specific Kconfig flag. Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640606 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add sw method for SET_BES_CROP_DEBUG4seshendra Gadagottu2018-01-22
| | | | | | | | | | | | | | | | | | Added sw method support for SET_BES_CROP_DEBUG4. In this sw method: CLAMP_FP_BLEND_TO_MAXVAL forces overflow and CLAMP_FP_BLEND_TO_INF blend results to clamp to FP maxval. Added support for this sw method in gp10b/gp106/gv11b and gv100. Bug 2046636 Change-Id: I3a9e97587aca76718f7f504ea3b853f87409092a Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1641529 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: note railgate_allowed in do_idleKonsta Holtta2018-01-22
| | | | | | | | | | | | | | | | | | | | | | | | The idling and unidling of deterministic channels in the do_idle/do_unidle path assume that each deterministic channel holds a power reference. This is no longer the case if railgating has been allowed for a channel via the deterministic options ioctl which also causes the channel to drop the power ref that it holds otherwise during its lifetime. All this is happening inside the deterministic_busy rwsem, which also guards the ioctl changing those deterministic option states. Bug 200327089 Change-Id: I9ce312bbaa459b3cf4a7541fa369186b78c3afdc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1642310 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add g->sw_ready flagKonsta Holtta2018-01-20
| | | | | | | | | | | | | | | | | | | | | | | | | Fix a race condition where we'd still be booting up the gpu and/or initializing the driver but elsewhere assume that all is done already. Some userspace APIs to make sure that we're ready by testing g->gr.sw_ready, but this flag is set in the middle of bootup; there are other things after gr initialization. Add a new flag that is enabled after bootup is fully complete at the end of finalize_poweron, and change the checks in user API paths to test the new flag only. These checks are only in the ioctl paths for ctrl, dbg and tsg, and in the ctrl device's opening path. The gr.sw_ready flag is still left there to signify whether just gr has had its bookkeeping initialized. Bug 200370011 Change-Id: I2995500e06de46430d9b835de1e9d60b3f01744e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640124 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: disable_syncpoints debugfs changed to read only"Inamdar Sharif2018-01-20
| | | | | | | | | | This reverts commit c713934675b32b30f3939f3ab4dd7466eb96a523. since this change is causing ap_opengles_screen to fail on embedded-qnx-hv Change-Id: I812d3483df961def492fb49c14911f6bcca36da4 Signed-off-by: Inamdar Sharif <isharif@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1642759
* gpu: nvgpu: Use real PDE size to determine pte_blk_orderAlex Waterman2018-01-19
| | | | | | | | | | | | | | | | | | | | | In the buddy allocator use the actual size of the PDE to determine the pte_blk_order field which is used to determine what page size a buddy has (or doesn't). Previously this was just set as the large page size times 1024 which would over allocate PDE ranges for Pascal+ chips. This caused userspace, which was using the real PDE size, to sometime allocate small and large pages in what the buddy allocator mistakenly thought was one PDE. Bug 200105199 Change-Id: I7ab7db7962015fc268bad61b558a18704133e1cb Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639731 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update gk20a pde bit coverage functionAlex Waterman2018-01-19
| | | | | | | | | | | | | | | | | The mm_gk20a.c function that returns number of bits that a PDE covers is very useful for determing PDE size for all chips. Copy this into the common VM code since this applies to all chips/platforms. Bug 200105199 Change-Id: I437da4781be2fa7c540abe52b20f4c4321f6c649 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639730 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: disable_syncpoints debugfs changed to read onlySeema Khowala2018-01-19
| | | | | | | | | | | | | | | Syncpoints can longer be disabled/enabled during run time as NVGPU_HAS_SYNCPOINTS flag is set based on has_syncpoints value in platform data during probe. Based on this, either of syncpoint or semaphore pool is initialized. Bug 2040115 Change-Id: Ib256e1a6ec8b1584799adb6f183fd567aebfaf13 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640380 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: enable devfreqseshendra Gadagottu2018-01-19
| | | | | | | | | | | | | | | | | | | | | | Enable devfreq for gv11b by enabling ""nvhost_podgov" governor in platform data. Reuse scaling functions from gp10b/gk20a. Remove emc floor on railgate for power saving and make max emc frequency as floor in rail-ungate for faster gpu boot. Bug 2039013 Bug 200377508 Change-Id: I65ee7735202e3decbe3451157f7fc1f1f273c3ff Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639752 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: delete unused wfi in gk20a_fenceKonsta Holtta2018-01-19
| | | | | | | | | | | | | | | | | The boolean wfi field in struct gk20a_fence is not used for anything. Delete it and a couple of function parameters that carried the flag. Jira NVGPU-43 Change-Id: I399c8709102a3f944cab669ff806761aedaeb6d3 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1636344 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix typoAlex Waterman2018-01-19
| | | | | | | | | | | | Rename gb10b_init_bar2_vm*() to gp10b_init_bar2_vm*(). Bug 200378257 Change-Id: I9f8a9ef42c82923200d7053c61bab2652b58cbc2 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639757 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Enable perfmon.Deepak Goyal2018-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | t19x PMU ucode uses RPC mechanism for PERFMON commands. - Declared "pmu_init_perfmon", "pmu_perfmon_start_sampling", "pmu_perfmon_stop_sampling" and "pmu_perfmon_get_samples" in pmu ops to differenciate for chips using RPC & legacy cmd/msg mechanism. - Defined and used PERFMON RPC commands for t19x - INIT - START - STOP - QUERY - Adds RPC handler for PERFMON RPC commands. - For guerying GPU utilization/load, we need to send PERFMON_QUERY RPC command for gv11b. - Enables perfmon for gv11b. Bug 2039013 Change-Id: Ic32326f81d48f11bc772afb8fee2dee6e427a699 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1614114 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: RPC interface supportMahantesh Kumbar2018-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Created nv_pmu_rpc_cmd & nv_pmu_rpc_msg struct, & added member rpc under pmu_cmd & pmu_msg - Created RPC header interface - Created RPC desc struct & added as member to pmu payload - Defined PMU_RPC_EXECUTE() to convert different RPC request to make generic RPC call. - nvgpu_pmu_rpc_execute() function to execute RPC request by creating required RPC payload & send request to PMU to execute. - nvgpu_pmu_rpc_execute() function as default callback handler for RPC if caller not provided callback - Modified nvgpu_pmu_rpc_execute() function to include check of RPC payload parameter. - Modified nvgpu_pmu_cmd_post() function to handle RPC payload request. JIRA GPUT19X-137 Change-Id: Iac140eb6b98d6bae06a089e71c96f15068fe7e7b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1613266 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add cleanup in gk20a_probe()Alex Waterman2018-01-18
| | | | | | | | | | | | | | | Add cleanup to the gk20a_probe() function since it will often fail due to probe deferal. These "failures" cause this function to be called multiple times and potentially allocate many resources over and over again, leaking the old allocations. Bug 200369627 Change-Id: Ic0bba0ae6542485135d9cb7393086e4460cd271d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640628 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: railgate platform only if it is not railgatedseshendra Gadagottu2018-01-18
| | | | | | | | | | | | | | | | | Avoid railgating platform, if it is already in railgated state. This is right thing to do and it also avoids ref counting issues related to fuse clock disable. Bug 200381275 Change-Id: Id745f9b878be129bf9b0cc972fadcfc102c8ddc2 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640548 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ramin_big_page_size default val is set to 64kbSeema Khowala2018-01-18
| | | | | | | | | | | | | | | | | | | | | | | | -MMU_CTRL_USE_PDB_BIG_PAGE_SIZE is set to TRUE and hence RAMIN_BIG_PAGE_SIZE should be set to 64KB i.e. val 1. By default this is set to 128KB i.e. val 0. -This change will also fix an issue where perfbuffer_enable and nvgpu_init_hwpm function pass 0 as big page size while initializing inst_block and due to which ramin_big_page_size does not get updated to 64KB and remains set to unsupported 128KB value. -Volta supports 64KB for big pages. Selecting 128KB for big pages results in an UNBOUND_INSTANCE fault. Bug 200327596 Change-Id: Ie304e4e5ff7bedaead27e9380d64c59013dd64ca Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639540 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv1xx: remove scg_type from channel infoseshendra Gadagottu2018-01-18
| | | | | | | | | | | | | scg_type for graphics_compute0 and compute1 is deprecated for gv1xx. Remove it from setting in the channel info. Bug 1842197 Change-Id: I37354adcd82bb0ab648e0f04d47de796b79f91cd Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640440 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: bypass_smmu debugfs changed to read onlySeema Khowala2018-01-18
| | | | | | | | | | | bypass_smmu is set based on whether device_is_iommuable or not during probe. It cannot be changed during runtime. Change-Id: I69fd29c87ea3873652a4eb95764f52dc40abf483 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640381 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: print ctxsw timeout info statusSeema Khowala2018-01-18
| | | | | | | | | | | | | | | | | | For ctxsw timeout failures, fifo_intr_ctxsw_timeout_info_status was not output as error print. Add it to help debugging ctxsw timeout failures Bug 2039371 Bug 2044497 Change-Id: I79d964fcda47847fdea6e8b59b68787c02e28379 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639509 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: unexport gk20a_ce_create/delete_contextRichard Zhao2018-01-17
| | | | | | | | | | | | | | | | | No external referencing of them. Jira VFND-4713 Change-Id: If053bbdbb37e9bd4789bfd7cccb1aef035fbf317 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639674 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Make graphics context property of TSGTerje Bergstrom2018-01-17
| | | | | | | | | | | | | | | | | | | | Move graphics context ownership to TSG instead of channel. Combine channel_ctx_gk20a and gr_ctx_desc to one structure, because the split between them was arbitrary. Move context header to be property of channel. Bug 1842197 Change-Id: I410e3262f80b318d8528bcbec270b63a2d8d2ff9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1639532 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: clean-up clock gating register listseshendra Gadagottu2018-01-12
| | | | | | | | | | | | | | | | | | | | | | | | | Following fb iso register is not valid for gv11b but hw headers has it. So, removing it manually from gating register list: 0x00100D1C Following sm blcg register not hooked up correctly in gv11b. So, removing it manually from gating register list: 0x00419c84 Once hw headers are updated, gating register tool will automatically remove them from kernel code. Bug 2042775 Change-Id: I4839b857656220566e53b66d3aead676893aaa59 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1636787 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: update whitelist regsSeema Khowala2018-01-12
| | | | | | | | | | | | | | | List generated for p4 sw cl 23385063 Bug 200375131 Change-Id: I9f58d7d1ab2659a86353a368c7e1e2284e5b760c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1634954 Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: add l3 allocation supportAparna Das2018-01-12
| | | | | | | | | | | | | Modify rpc command parameter to support l3 cache allocation. Jira EVLR-1752 Change-Id: I1be00e04ee01c0763f46c0d0da6a112316cc7e1d Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616566 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: move t19x specific code to general codeRichard Zhao2018-01-12
| | | | | | | | | | | | | | - remove vgpu_t19x.h and tegra_vgpu_t19x.h - merge t19x specific ivc commands to the big enum - move TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT to constants Jira EVLR-2293 Change-Id: I34344bffa03bb69e1282b1f19382e3199f9ba105 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1636128 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Combine gk20a and gp10b free_gr_ctxTerje Bergstrom2018-01-12
| | | | | | | | | | | | | | gp10b version of free_gr_ctx was created to keep gp10b source code changes out from the mainline. gp10b was merged back to mainline a while ago, so this separation is no longer needed. Merge the two variants. Change-Id: I954b3b677e98e4248f95641ea22e0def4e583c66 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635127 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: Delete gm20b supportTerje Bergstrom2018-01-12
| | | | | | | | | | | | Delete gm20b vgpu support. It has not been supported for a long time and keeping it up-to-date is extra work. Change-Id: I3c06d29a79cb83d53a25d2242247b4eeabeab310 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635126 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add HAL for dumping ctxsw statisticsTerje Bergstrom2018-01-12
| | | | | | | | | | | | | | | | | Add HAL for dumping ctxsw statistics. The statistics are dependent on the architecture, and the function that calls this operation needs to be moved to gk20a. Bug 1842197 Change-Id: I285c74b8ddc8c7854c85b3fef4cbfc582098919e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1632681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle SM reported MMU_NACK exceptionDeepak Nibade2018-01-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upon receiving MMU_FAULT error, MMU will forward MMU_NACK to SM If MMU_NACK is masked out, SM will simply release the semaphores And if semaphores are released before MMU fault is handled, user space could see that operation as successful incorrectly Fix this by handling SM reported MMU_NACK exception Enable MMU_NACK reporting in gv11b_gr_set_hww_esr_report_mask In MMU_NACK handling path, we just set the error notifier and clear the interrupt so that the User Space sees the error as soon as semaphores are released by SM And MMU_FAULT handling path will take care of triggering RC recovery anyways Also add necessary h/w accessors for mmu_nack Bug 2040594 Jira NVGPU-473 Change-Id: Ic925c2d3f3069016c57d177713066c29ab39dc3d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631708 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: perf: fix coverity issueVijayakumar2018-01-12
| | | | | | | | | | | | | | | | remove recurring header file include coverity defect id: 2682953 bug 200291879 Change-Id: Iae53377ff1609c138a0c75a4cbf04afa3a533100 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1636579 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: runlist info mutex not needed for runlist_stateSeema Khowala2018-01-11
| | | | | | | | | | | | | | | | runlist_info mutex for the runlist being enabled or disabled in fifo_sched_disable_r is not needed to be acquired Bug 2043838 Change-Id: Ia9839ab7effbe7daf353c3a54f25a2b4914af5e8 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1630345 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: disable fifo_intr_0_runlist_eventSeema Khowala2018-01-11
| | | | | | | | | | | | | | | | | | | | | | runlist event interrupt is not needed to be enabled as s/w polls for preemption completion for preempts issued in RUNLIST_PREEMPT. Even though it is not enabled, intr will get set in fifo_intr_0 status register whenever RUNLIST_PRREMPT is successfully completed. Since intr is disabled, fifo intr will not be triggered but it will be handled during handling of other fifo interrupts whenever fifo intr is triggered. Bug 2039371 Change-Id: I0817c2b6e9f3f14958ca7c738392bc67875be5d5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1630283 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: get virtual SMs mappingThomas Fleury2018-01-10
| | | | | | | | | | | | | | | On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in vgpu constants to properly dimension the virtual SM to TPC/GPC mapping in virtualization case. Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping. Bug 2039676 Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1631203 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: protect linux include with configDeepak Nibade2018-01-10
| | | | | | | | | | | | | | | | In fence_gk20a.c protect <linux/file.h> and <linux/fs.h> includes with config CONFIG_SYNC since they are only needed with this config enabled Jira NVGPU-487 Change-Id: I6c26aa0fbb4ee284129109c625a0e324d5caf235 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635471 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use chip specific zbc_c/z format regseshendra Gadagottu2018-01-10
| | | | | | | | | | | | | | Use chip specific gpcs_swdx_dss_zbc_c_format_reg and gpcs_swdx_dss_zbc_z_format_reg. These registers are different for gv11b/gv100 from gp10b/gp106. Change-Id: I9e209c878a11edc986ba4304ff60fcccbb5087aa Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635091 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-23 14:19:19 -0400