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* gpu: nvgpu: Reorg ce2 HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ce2 sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7dfd5e8dcd4d6f3623d1b795b6b2e15ff356a13a Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509632 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: check for buffer overflow when mappingPeter Daifuku2017-07-27
| | | | | | | | | | | | | | | | | In gk20a_vm_map_buffer, return an error if the buffer size is less than offset + mapping size. Bug 1793926 Change-Id: I2209de6a6f2e2b3bd8830659208d6f88bbedc00d Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1484442 (cherry picked from commit 7e6a80cb4684a3e2534bc68cba4c1612a845a8f3) Reviewed-on: http://git-master/r/1488138 (cherry picked from commit 3331f6e47f1d214ad6aaf08ae3e7d241e31d6638) Reviewed-on: https://git-master.nvidia.com/r/1501677 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix gr ctx unmap logicAlex Waterman2017-07-27
| | | | | | | | | | | | | The GR context buffers were not being properly unmapped. The awkward VPR vs non-VPR context setup requires some extra checks when determining which nvgpu_mem is associated with what GPU VA (which are tracked separately in a different sized array). Change-Id: I4c7be1c5b7835aea4309a142df5b0bdfaae91e4c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1524689 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check for null priv in channel_releasePeter Daifuku2017-07-27
| | | | | | | | | | | | | | | | gk20a_channel_release can still get called even if the open_channel call failed (e.g., if we ran out of hw chids), in which case priv is null. Check for this case and return if null. Bug 1964531 Change-Id: I48bc88e4dbd88a1c30fc399de629d8f8b344cfd9 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1526544 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* nvgpu: linsim removalWilliam Pierce2017-07-26
| | | | | | | | | | | | | | | Removed multiple tegra_platform_is_linsim if statements because of linsim deprecation. Bug 1903831 Change-Id: I4985b0e56d26db4813e4f4235b25e5cff47745f8 Signed-off-by: William Pierce <wpierce@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1485033 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reset pm status on runtime_resume failSunny He2017-07-26
| | | | | | | | | | | | | | | | | | | | | | If an error occurs during an attempt to perform a runtime_resume, the runtime power management framework sets an error flag that prevents further attempts to resume until the error is cleared. nvgpu currently does not clear the flag, which causes nvgpu to lock up if an error occurs during runtime_resume. This change explicitly sets the device pm status to suspended on error, which clears the error flag so that subsequent attempts to resume will not be blocked. Bug 200324790 Change-Id: I3c875453670d3691ab01cff90ce31e797296662a Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1526478 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove privsecurity flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1525713 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Remove securegpccs flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace securegpccs boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_SECUREGPCCS Jira NVGPU-74 Change-Id: I46430f95063f617531cf0e5aba472051b41f4a9d Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514060 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Remove pmupstate flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace pmupstate boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_PMU_PSTATE Jira NVGPU-74 Change-Id: I4e1ba922a48145b1cf3488b6f14fde78107adb5b Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514059 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Apply GM20B dfs_det_cal maskAlex Frid2017-07-25
| | | | | | | | | | | | | | | Applied dfs_det_cal field mask when updating DFS external calibration setting to prevent overflow for negative setting (not happening so far with ADC offset always below Vmin, but may be needed if/when ADC fusing changes). Change-Id: I94b415edec84111b957b73ccfc80c1a8640b8e3a Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/1504242 (cherry picked from commit 9b8072ffcc02f6684a56609c25d1d77ed0852f7a) Reviewed-on: https://git-master.nvidia.com/r/1525831 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Change GPCPLL rev C1 control settingsAlex Frid2017-07-25
| | | | | | | | | | | | | | | | Updated DFS control settings for GPCPLL revision C1 per characterization data. Bug 1942222 Change-Id: Iab5147e13ef70df980d36589328abafd8f5495b8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/1502741 (cherry picked from commit 5ea62c9e264de86f6e5a40a7f31054ab31b3196f) Reviewed-on: https://git-master.nvidia.com/r/1525830 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Reorg fifo HAL initializationSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43d94067a1d7eafba4cdb28311e0ce25812013a7 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522553 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg priv_ring HAL initializationSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the priv_ring sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I9ebf27619f771262e5dc398b1200d6c19d6aef16 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514102 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg bus HAL initializationSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the bus sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: If03303c34d91480d41fc29e66069efd43e970d75 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514660 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg css HAL initializationSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the css sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3bf696e13d359982c964c7bc470500a30555c034 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514205 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: support etpc addresses in ext bufferSeema Khowala2017-07-19
| | | | | | | | | | Bug 1960226 Change-Id: Ifdcdff803e96c59b2794170349ec4e2c00406706 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522445 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: support context regoptype for egpc/etpcSeema Khowala2017-07-19
| | | | | | | | | | | | | | | | - add is_egpc_addr, is_etpc_addr and get_egpc_etpc_num gr ops - add gr ops for decode and create egpc/etpc priv addr - add etpc as part of ctxsw_regs JIRA GPUT19X-49 Bug 200311674 Bug 1960226 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Change-Id: I9a8be1804a9354238de2441093b3b136321b7e53 Reviewed-on: https://git-master.nvidia.com/r/1522442 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ctxheader changes for t19xSeema Khowala2017-07-19
| | | | | | | | | | | | | JIRA GPUT19X-49 Bug 200311674 Bug 1960226 Change-Id: I913e0dd16c51db3f92cb44abaf3f3afa1ce46c0e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522444 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: update_smpc_ctxsw_mode changes for t19xSeema Khowala2017-07-19
| | | | | | | | | | | | Support t19x ctx header changes Bug 200313979 Change-Id: Ide5c5f9f3227bd6aba530e736896006fb72d4d19 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1508549 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add perf gr ops to support t19xSeema Khowala2017-07-19
| | | | | | | | | | | | | Add init_ovr_sm_dsm_perf & get_ovr_perf_regs gr ops JIRA GPUT19X-49 Bug 200311674 Change-Id: If02dd9dc0e2e0eb1f68fdbaa86a37c6768eddcef Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1497403 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add esc read for PPC_COUNTSeema Khowala2017-07-19
| | | | | | | | | | | | | | | | | | Add esc read for GRCTX_REG_LIST_PPC_COUNT else gr_gk20a_determine_ppc_configuration function would return -EINVAL if num_pes_per_gpc i.e. GPU_LIT_NUM_PES_PER_GPC is > 1 JIRA GPUT19X-49 Bug 200311674 Change-Id: Iee7ee9ba14fcc7dca07c4c1dc20f8e7d018ed820 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522443 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add ctxsw etpc regsSeema Khowala2017-07-19
| | | | | | | | | | | | | | Add etpc ctxsw regs for t19x Bug 200311674 Change-Id: I2d5076cb4df8040613c20d28518325ad7c6a9145 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1520140 GVS: Gerrit_Virtual_Submit Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com> Reviewed-by: Tushar Kashalikar <tkashalikar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu : nvgpu: secure boot code unification.Deepak Goyal2017-07-18
| | | | | | | | | | | | | | This exposes all secure boot functions that can be re-used by other chips. This is the first patch in this series. Other pacthes will also follow. JIRA NVGPU-60 Change-Id: I523637bbf601166f8a01ddf29a913e193d3fdc7a Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514567 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check return value of sm exception handlerDeepak Nibade2017-07-18
| | | | | | | | | | | | | | | | | | | | | | | In gr_gp10b_handle_sm_exception(), we do not check return value of gr_gk20a_handle_sm_exception() In case SM debug mode is disabled, gr_gk20a_handle_sm_exception() returns an error. But due to uncaught error we return success from gr_gp10b_handle_sm_exception() which results in not triggering the recovery routine and fails the tests Fix this by checking return value of gr_gk20a_handle_sm_exception() We then parse ECC errors and then finally return error value back to caller Bug 200325081 Change-Id: I0c328a75494b9ca6a070f04c1f984e2653ffd90e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1521563 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Ashutosh Jain <ashutoshj@nvidia.com>
* gpu: nvgu: Support SET_BES_CROP_DEBUG3 sw methodLauri Peltonen2017-07-14
| | | | | | | | | | | | | | | The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is used by the user space driver to disable enough ROP optimizations to maintain ZBC state of target tiles. Bug 1942454 Change-Id: Id4e4d9d06c6c66080d06b6d4694546fe5cba8436 Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1516202 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gpu: Remove unnecessary hw header includesSunny He2017-07-14
| | | | | | | | | | | | | | | Remove some unnecessary hardware register header includes. Jira NVGPU-118 Change-Id: Ie05ca78bbab49c6fcc05eaa5a9a5890a0943cd8f Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1520148 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg debug HAL initializationSunny He2017-07-13
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the debug and dbg_session_ops sub-modules of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Id51feeccbea91f884a6057efc680566a7d5d0b6d Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514822 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Move gops.mc's non-fp membersSunny He2017-07-13
| | | | | | | | | | | | | | | | | | Move non-function pointer members out of the mc substruct of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. gops.mc.intr_mask_restore is now mc_intr_mask_restore Jira NVGPU-74 Change-Id: Iddf5e761012086e993c375d59e1bbdfb1e64db0c Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509602 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg mc HAL initializationSunny He2017-07-13
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I26d74c14661a193af7e8d90dd672b73010e5f841 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509601 GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg falcon HAL initializationSunny He2017-07-13
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the falcon sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ib1aaaa248b079bb591ccfada3382b689452de0e9 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514012 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add get/set PTE routinesAlex Waterman2017-07-12
| | | | | | | | | | | | | | | | | | | | | | | | | | Add new routines for accessing and modifying PTEs in situ. They are: __nvgpu_pte_words() __nvgpu_get_pte() __nvgpu_set_pte() All the details of modifying a page table entry are handled within. Note, however, that these routines will not build page tables. If a PTE does not exist then said PTE will not be created. Instead -EINVAL will be returned. But, keep in mind, a PTE marked as invalid still exists. So this API can be used to mark an invalid PTE valid. JIRA NVGPU-30 Change-Id: Ic8615f209a0c4eb6fa64af9abadcfb3b2c11ee73 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1510447 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: fix tpc exception enablementSeema Khowala2017-07-10
| | | | | | | | | | | | | | Use read modify write to enable sm exception. This is to avoid disabling alredy enabled interrupts e.g. tex etc. JIRA GPUT19X-69 Change-Id: I94f75f9a37310a8271193b4996e9b4b2ba29e4ae Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1515914 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add gr ops for mpc exception handlingSeema Khowala2017-07-10
| | | | | | | | | | | | | Required for t19x JIRA GPUT19X-69 Change-Id: I96d1ee2ae1bf310ce572cb4dc7773818a42a25a0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1515913 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add ops and var for t19x mmu faultSeema Khowala2017-07-08
| | | | | | | | | | | | | Add new ops and fields required for t19x mmu fault JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I29694c15ff9a4150bb1737adac6b58ccba76bea4 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1492640 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move dev field from gk20a to nvgpu_os_linuxTerje Bergstrom2017-07-07
| | | | | | | | | | | | | Move field "struct device *dev" from struct gk20a to struct nvgpu_os_linux. The field is valid only for Linux. JIRA NVGPU-38 Change-Id: I09286aa3a9c5a2406e5a27c1fbf21b2c515b4dd4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1514162 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use correct units for bios waitKonsta Holtta2017-07-07
| | | | | | | | | | | | | nvgpu_flcn_wait_for_halt() takes a timeout value in milliseconds, so pass it the millisecond value instead of number of iterations to sleep if one iteration took a specific amount of time, a bug left over from refactoring. Change-Id: Ifddea16522c14c52d765f1c1bfaa69d1f7dfd011 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1514396 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use u32 for timeout API durationKonsta Holtta2017-07-07
| | | | | | | | | | | | | | | | A negative value in the timeout duration does not have any special uses, so change the duration type to u32 (from just int). Delete some unnecessary typecasts to int. Also change MAX_SCHEDULE_TIMEOUT to ULONG_MAX in default gr idle timeout because the value is in milliseconds instead of scheduling units and to drop unnecessary Linux dependency. Change-Id: I5cf6febd4f1cb00c46fe159603436a9ac3b003ac Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1512565 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reorg cde HAL initializationSunny He2017-07-07
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the cde sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I9343ce4985eb941a2610f5f11e8f01269ab68481 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1511673 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorg xve HAL initializationSunny He2017-07-07
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the xve sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ieb9afc230199c341d2df1e9f75792a136a2a6067 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1510470 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Cleanup GMMU debug printingAlex Waterman2017-07-07
| | | | | | | | | | | | | | | | | | | | | | | Ensure that all debug prints are consistent from chip to chip and function to function. The following maps letters in the debug print to their meaning: C Mapping is cachable v Mapping is volatile S Mapping is sparse P Mapping is private (VPR/WPR) c Mapping is coherent V Mapping is valid JIRA NVGPU-30 Change-Id: Ia890af88677c3e6d3fdd8c4fe266158c35b8afcd Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1514903 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Tested-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add t19x GMMU attributesAlex Waterman2017-07-07
| | | | | | | | | | | | | | | | Add t19x specific flags into the GMMU attributes struct. Jira GPUT19X-10 Bug 200279508 Change-Id: Ib45b83705fa1ca4ff6d14da0a2f132050e7d2cd5 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1514876 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Tested-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: support platform specific physical address translationDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | On some GPUs certain physical address bits have special meaning. This patch adds support for setting those bits based on the GMMU attributes struct. Jira GPUT19X-10 Bug 200279508 Change-Id: I32b8a028be7fd62af06a60c393a8c9251de0ef3c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1512600 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: use coherent aperture for coherent buffersDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | | | Use sysmem_coherent aperture if the buffer mappings are requested to be IO coherent. Use sysmem_noncoherent aperture otherwise. This is implemented by adding a new coherent field to the GMMU attrs struct. Jira GPUT19X-17 Bug 1651331 Bug 200283998 Change-Id: I5cfb71b5913d4db50ebf10331b19f5a4216456bf Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1514438 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: remove coherence support from gp10bDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | | | | | | | We do not support coherence for gp10b, hence clean up related code Remove API gp10b_mm_phys_addr_translate() and use physical address instead Also, since now gp10b_mm_iova_addr() becomes equivalent to gk20a_mm_iova_addr(), remove gp10b_mm_iova_addr() altogether We first set gk20a_mm_iova_addr() to get_iova_addr() pointer anyways so we continue using gk20a version of the API Jira GPUT19X-17 Bug 1651331 Bug 200283998 Change-Id: Ic1ca198fcde7ddbcd23516bff8a2e65c9eae32b1 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1512598 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Implement PD packingAlex Waterman2017-07-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases page directories require less than a full page of memory. For example, on Pascal, the final PD level for large pages is only 256 bytes; thus 16 PDs can fit in a single page. To allocate an entire page for each of these 256 B PDs is extremely wasteful. This patch aims to alleviate the wasted DMA memory from having small PDs in a full page by packing multiple small PDs into a single page. The packing is implemented as a slab allocator - each page is a slab and from each page multiple PD instances can be allocated. Several modifications to the nvgpu_gmmu_pd struct also needed to be made to support this. The nvgpu_mem is now a pointer and there's an explicit offset into the nvgpu_mem struct so that each nvgpu_gmmu_pd knows what portion of the memory it's using. The nvgpu_pde_phys_addr() function and the pd_write() functions also require some changes since the PD no longer is always situated at the start of the nvgpu_mem. Initialization and cleanup of the page tables for each VM was slightly modified to work through the new pd_cache implementation. Some PDs (i.e the PDB), despite not being a full page, still require a full page for alignment purposes (HW requirements). Thus a direct allocation method for PDs is still provided. This is also used when a PD that could in principle be cached is greater than a page in size. Lastly a new debug flag was added for the pd_cache code. JIRA NVGPU-30 Change-Id: I64c8037fc356783c1ef203cc143c4d71bbd5d77c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1506610 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gmmu programming rewriteAlex Waterman2017-07-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the high level mapping logic. Instead of iterating over the GPU VA iterate over the scatter-gather table chunks. As a result each GMMU page table update call is simplified dramatically. This also modifies the chip level code to no longer require an SGL as an argument. Each call to the chip level code will be guaranteed to be contiguous so it only has to worry about making a mapping from virt -> phys. This removes the dependency on Linux that the chip code currently has. With this patch the core GMMU code still uses the Linux SGL but the logic is highly transferable to a different, nvgpu specific, scatter gather list format in the near future. The last major update is to push most of the page table attribute arguments to a struct. That struct is passed on through the various mapping levels. This makes the funtions calls more simple and easier to follow. JIRA NVGPU-30 Change-Id: Ibb6b11755f99818fe642622ca0bd4cbed054f602 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master/r/1484104 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add handle_tpc_sm_ecc_exception gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | Needed to handle t19x sm ecc errors per tpc JIRA GPUT19X-75 JIRA GPUT19X-109 Change-Id: I921615dd5f551f34cdf55c1b085b16f562f16eb0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514044 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add clear_sm_hww gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | Required for multiple SM support and t19x SM register address changes JIRA GPUT19X-75 Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514043 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add sm lock_down gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | | Add lock_down_sm and wait_for_sm_lock_down gr ops Required to support multiple SM and t19x SM register address changes JIRA GPUT19X-75 Change-Id: I529babde51d9b2143fe3740a4f67c582b7eb404b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514042 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add get_sm_no_lock_down_hww_global_esr_mask gr opsSeema Khowala2017-07-06
| | | | | | | | | | | | | This is required to take care of t19x changes to support multiple SM JIRA GPUT19X-75 Change-Id: Ifd2cb28ae442462fef1d2c4439baa817f00c2c9e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1514041 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-17 02:49:59 -0400