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* gpu: nvgpu: Do not use invalid engine ID in bitshiftTerje Bergstrom2016-11-11
| | | | | | | | | | | | | | | In calls to gk20a_fifo_recover() we pass a bitfield of engines to recover. We generate the bitfield by acquiring engine id from FIFO, and using BIT(). If GR engine is now known, the resulting engine ID is u32 with all bits set, which cannot be passed to BIT(). gk20a_fifo_recover() can already deal with all bits set, so pass that verbatim instead. Change-Id: Ib79d8e7e156deef0d483642cfb1ce7bf55f3c572 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249964 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Return error code on zero IOVATerje Bergstrom2016-11-11
| | | | | | | | | | | | | When buffer's IOVA is zero, treat that as error condition instead of ignoring and continuing. Change-Id: I2ede9921945645f526b0600f61f7e5ed19af6d73 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249963 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* gpu: nvgpu: Prevent integer overflow of GPU configTerje Bergstrom2016-11-11
| | | | | | | | | | | | | | In CDE GPU CONFIGURATION the result is computed using 32-bit arithmetic and returned as 64-bit unsigned integer. Cast intermediate result to u64 to prevent unintentional overflow. Change-Id: Iebe53e2b17c1aaa498245a52962c3dbad7ce893e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249962 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* gpu: nvgpu: vgpu: Do not overwrite err code on failTerje Bergstrom2016-11-11
| | | | | | | | | | | | | | vgpu_vm_alloc_share() wants to return -EINVAL if VMA areas requested do not fulfill the criteria. The error code gets overwritten by a call to vgpu_comm_sendrecv(), which makes vgpu_vm_alloc_share() always return 0. Change-Id: I93f56025f963d1d4ad2f9b06139fce742d3be41b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249961 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* gpu: nvgpu: Remove duplicate err returning pathTerje Bergstrom2016-11-11
| | | | | | | | | | | | | | | railgate_enable_store() has two places where err is checked and returned. Because we have only one place where err can be set, the second check and return are superfluous. Change-Id: Id45923fc829f061fee34fa1abca0359b443e6f0d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249960 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: Do not access alloc after freeing itTerje Bergstrom2016-11-11
| | | | | | | | | | | | | Move debug write so that we access length and base of allocation before the alloc structure gets freed. Change-Id: I02e418f423beaa2b52a32d1abcff327b68dd5fa6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249959 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* gpu: nvgpu: Do not free NULL sync_fenceTerje Bergstrom2016-11-11
| | | | | | | | | | | | | | | When allocating a fence fails, free sync_fence only if one has been created. Change-Id: I2ecefd25c4e000f415b28c7c2b01b91654d6ef43 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249958 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: Don't cast runlist size to u64Terje Bergstrom2016-11-11
| | | | | | | | | | | | | | | | We multiply integer entry size and number of runlist entries and store the result in u64. The result is used as size of memory, so it should be size_t instead. Change-Id: I0f5baa66ede259c9b42ede64c08f821c3e74a20b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249957 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: gk20a: Fix FBP/L2 masks, add GET_FBP_L2_MASKSSami Kiminki2016-11-11
| | | | | | | | | | | | | | | | | | | | Fix FBP and ROP_L2 enable masks for Maxwell+. Deprecate rop_l2_en_mask in GPU characteristics by adding _DEPRECATED postfix. The array is too small to hold ROP_L2 enable masks for desktop GPUs. Add NVGPU_GPU_IOCTL_GET_FBP_L2_MASKS to expose the ROP_L2 masks for userspace. Bug 200136909 Bug 200241845 Change-Id: I5ad5a5c09f3962ebb631b8d6e7a2f9df02f75ac7 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/1245294 (cherry picked from commit 0823b33e59defec341ea7919dae4e5f73a36d256) Reviewed-on: http://git-master/r/1249883 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: define fuse macro depend on kernel versionShardar Shariff Md2016-11-11
| | | | | | | | | | | | | | | | | | - Define fuse macros depending on kernel version as fuse offset got changed in K4.4 and for K4.4 fuse defines are defined in common header file (tegra-fuse.h) - Use fuse control read/write APIs when reading control registers for K4.4. Bug 200243956 Change-Id: I5a86ef58d9de17a273aea8d3ce8ad5772444dac2 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1245824 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Do not post events to unbound channelsTerje Bergstrom2016-11-07
| | | | | | | | | Change-Id: Ia1157198aad248e12e94823eb9f273497c724b2c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1248366 Tested-by: Sachit Kadle <skadle@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> GVS: Gerrit_Virtual_Submit
* Revert "gpu: nvgpu: vgpu: alloc hwpm ctxt buf on client"Sivaram Nair2016-11-04
| | | | | | | | | | This reverts commit 57821e215756b3df7acc9c0eb5017e39f141d381. Change-Id: Ic4801115064ccbcd1435298a61871921d056b8ea Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> Reviewed-on: http://git-master/r/1247825 Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com> Tested-by: Rakesh Babu Bodla <rbodla@nvidia.com>
* gpu: nvgpu: vgpu: alloc hwpm ctxt buf on clientPeter Daifuku2016-11-03
| | | | | | | | | | | | | | | | | | In hypervisor mode, all GPU VA allocations must be done by client; fix this for the allocation of the hwpm ctxt buffer Bug 200231611 Change-Id: I0270b1298308383a969a47d0a859ed53c20594ef Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1240913 (cherry picked from commit 49314d42b13e27dc2f8c1e569a8c3e750173148d) Reviewed-on: http://git-master/r/1245867 (cherry picked from commit d0b10e84d90d0fd61eca8be0f9e879d9cec71d3e) Reviewed-on: http://git-master/r/1246700 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add PMU thermal RPC for WARN_TEMPLakshmanan M2016-11-03
| | | | | | | | | | | | | | | Added PMU thermal slct RPC handling for WARN_TEMP threshold configuration. JIRA DNVGPU-130 Change-Id: I5011db5f08476516f72722e639838e968e7e60dd Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1242132 (cherry picked from commit 6e87a23ca04be435107da801c15f7b55a1f45e8b) Reviewed-on: http://git-master/r/1246211 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add thermal module supportLakshmanan M2016-11-03
| | | | | | | | | | | | | | | | | The following CL contains the following VBIOS thermal table parsing and PMU interface support. 1) Thermal device table 2) Thermal channel table JIRA DNVGPU-130 Change-Id: I3c1baca3fec2727b6d20aa6c007096372a6a3efe Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1240631 (cherry picked from commit 1d6fa9ab49b1c84e7f845de206821d879cbda356) Reviewed-on: http://git-master/r/1246204 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: smid programmingseshendra Gadagottu2016-11-03
| | | | | | | | | | | | | Populate chip specific sm id table. JIRA GV11B-21 Change-Id: I58869b2c3e55449a7d999ddf73d6eb7b359b2a07 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1227095 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: init mclk before pstate pmu supportMahantesh Kumbar2016-11-01
| | | | | | | | | | | JIRA DNVGPU-122 Change-Id: I8491dc0b534c99d43057de1b35d8cdacde93f658 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1224366 Reviewed-on: http://git-master/r/1245118 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: chip specific commit global timesliceseshendra Gadagottu2016-11-01
| | | | | | | | | | | | Implement chip specific commit_global_timeslice function. JIRA GV11B-21 Change-Id: I937dda77870f164d034686d6d41482c875940320 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1243944 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmu HAL updateseshendra Gadagottu2016-11-01
| | | | | | | | | | | | | | Update pmu HAL to check for pmu support. pmu initialization will check for pmu support in that platform. JIRA GV11B-21 Change-Id: Ib55be58a1540862b7a91a6162544d10be85b5eb4 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1243911 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Only set mode if ptr is validAlex Waterman2016-10-31
| | | | | | | | | | | | | | | | | | In the nvgpu_pci_devnode() function only set the mode if the mode pointer is valid. In some cases this function only needs the name of the node and not its permissions. Bug 1816516 Change-Id: I603c1499083fb29cb5fe4a871068e0bf2cbe9c3d Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1225614 (cherry picked from commit 11874ad9df49b44fac4e90d83e138ead63bbb2f9) Reviewed-on: http://git-master/r/1244907 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: update pwm source enum & VFE entryMahantesh Kumbar2016-10-30
| | | | | | | | | | | | | | JIRA DNVGPU-123 Change-Id: Ia28db5d645aa431f11dc8720bf1d08e6d756e20f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1227670 (cherry picked from commit 2c7f89ceef3f9173fefa44b1a959345744e66536) Reviewed-on: http://git-master/r/1244659 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: voltage changesMahantesh Kumbar2016-10-30
| | | | | | | | | | | | | | | | - added voltage interface & ctrl defines. JIRA DNVGPU-122 Change-Id: Ia1a4c655c3c5faa638cafcdc75bdfb0e3c3be54f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1222775 (cherry picked from commit 46ff4d54d3cc02d9f039091f09eea09a5d6c22ce) Reviewed-on: http://git-master/r/1244654 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10x: update pmu revisionVijayakumar2016-10-27
| | | | | | | | | | | JIRA DNVGPU-70 Change-Id: I927240432c4e27c01912d073ad9725f0c526288c Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1239804 Reviewed-on: http://git-master/r/1242203 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add SW_THRESHOLD policy supportLakshmanan M2016-10-27
| | | | | | | | | | | | | | Added SW_THRESHOLD policy support for over power protection. JIRA DNVGPU-70 Change-Id: I021f47f234d42be15ddbfd02a22e9299fd486636 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1233051 (cherry picked from commit 301e0ac123a7a65a7f83e5615f3a89e55253a0bd) Reviewed-on: http://git-master/r/1241958 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add pmgr supportLakshmanan M2016-10-27
| | | | | | | | | | | | | | | | | | | | | This CL covers the following implementation, 1) Power Sensor Table parsing. 2) Power Topology Table parsing. 3) Add debugfs interface to get the current power(mW), current(mA) and voltage(uV) information from PMU. 4) Power Policy Table Parsing 5) Implement PMU boardobj interface for pmgr module. 6) Over current protection. JIRA DNVGPU-47 Change-Id: I620f4470aa704f1cc920e03947831440fbb0eb05 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1217176 (cherry picked from commit ed56743c2ac8dc325c75f85a82271d2d5ed8d96a) Reviewed-on: http://git-master/r/1241952 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix semaphore wakeup logicSachit Kadle2016-10-26
| | | | | | | | | | | | | | | | | | | | | | | Currently, when we receive a semaphore wakeup interrupt, we call the channel_update callback, which schedules deferred job clean-up. For deterministic channels, we don't allow semaphore-backed syncs anyways. That means for these channels, if we get a semaphore wakeup interrupt, it must be for a userspace-managed semaphore. In this case, there is no need to call into the channel_update callback. So for deterministic channels, we skip this. Bug 1795076 Change-Id: I4cdfecd53144078c5cd4be8a41c5c3b7d74c338e Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1225620 (cherry picked from commit 64a6db0080c3b198ddc2029544f52eb590dc08ff) Reviewed-on: http://git-master/r/1225615 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove global debugfs variableAlex Waterman2016-10-26
| | | | | | | | | | | | | | | Remove a global debugfs variable and instead save the allocator debugfs root node in the gk20a struct. Bug 1799159 Change-Id: If4eed34fa24775e962001e34840b334658f2321c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1225611 (cherry picked from commit 1908fde10bb1fb60ce898ea329f5a441a3e4297a) Reviewed-on: http://git-master/r/1242390 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move CE cleanupAlex Waterman2016-10-26
| | | | | | | | | | | | | | | | Move the CE cleanup to before the FIFO cleanup. Since the CE closes a channel during its cleanup the FIFO needs to be initialized since the FIFO code maintains the vmalloc()'ed channels. Bug 1816516 Change-Id: Ia7a97059a12a0c2b52368ffe411e597f803e8e6e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1225613 (cherry picked from commit 707bd2a6d4672c6a7b7a8b2e581ea3a606ed971d) Reviewed-on: http://git-master/r/1240106 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Only cleanup existing semaphore poolsAlex Waterman2016-10-26
| | | | | | | | | | | | | | | | | | Not all VMs have semaphore pools made for them even when semaphores are going to be used. Thus only VMs with existing semaphore pools should have their pools cleaned up. Bug 1816516 Change-Id: I07828708faef451f1711f58c0d5b3f8e4d296dd0 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1225612 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> (cherry picked from commit 6cdb7b6650765465dca68dc3c23b3d795ccdafb5) Reviewed-on: http://git-master/r/1240105 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix prealloc resource alloc error handlingKonsta Holtta2016-10-26
| | | | | | | | | | | | | | | | Only free the per-channel preallocated job-tracking resources during channel allocation error path if they have actually been allocated. Bug 1795076 Change-Id: I2de90504f1042ce372337b68c5405727b4e4abb4 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1234983 (cherry picked from commit 62cb75c6baa02d0edecd1f81f1b8b80a985fd715) Reviewed-on: http://git-master/r/1238329 GVS: Gerrit_Virtual_Submit Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add proper memset size during cleanupLakshmanan M2016-10-25
| | | | | | | | | | | | | | | | This CL covers the following small modifications, 1) Add proper memset size handling during pmu surface cleanup 2) Reset the pmu surface mem desc pointer after deallocate the memory JIRA DNVGPU-47 Change-Id: I400f8c4d3f5dc650d4fc6669cef6a1e41a70f4ab Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1220100 (cherry picked from commit 1f171b977be51db20c2dfc56b3f6e3dd6b4b9095) Reviewed-on: http://git-master/r/1240881 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix compile when CONFIG_PM=nTimo Alho2016-10-25
| | | | | | | | | | | | | | nvgpu driver fails to compile when CONFIG_PM build option is set to 'n'. Fix this by guarding struct gk20a_pm_ops and the functions pointed by in that struct with #ifdefs. Bug 1827482 Change-Id: I27f3535e89cc741f79824cdc427ef3572e2779e6 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: http://git-master/r/1237110 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm206: fix out of boundary memory accessRichard Zhao2016-10-21
| | | | | | | | | | | | Avoid out of bounds when searching bit header. JIRA VFND-2826 Change-Id: Icbde7c7e04c35c29f316d8a0ad93c76fcb8fae7a Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1240185 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: make deferred clean-up conditionalSachit Kadle2016-10-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change makes the invocation of the deferred job clean-up mechanism conditional. For submissions that require job tracking, deferred clean-up is only required if any of the following conditions are met: 1) Channel's deterministic flag is not set 2) Rail-gating is enabled 3) Channel WDT is enabled 4) Buffer refcounting is enabled 5) Dependency on Sync Framework In case deferred clean-up is not needed, we clean-up a single job tracking resource in the submit path. For deterministic channels, we do not allow deferred clean-up to occur and fail any submits that require it. Bug 1795076 Change-Id: I4021dffe8a71aa58f12db6b58518d3f4021f3313 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1220920 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> (cherry picked from commit b09f7589d5ad3c496e7350f1ed583a4fe2db574a) Reviewed-on: http://git-master/r/1223941 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add flag for running preos ucodeTerje Bergstrom2016-10-20
| | | | | | | | | | | | | | | Add per-platform flag run_preos, which indicates whether to run preos ucode or not. Leave it to false for all known boards. Bug 1799537 Bug 1815139 Change-Id: I1818970b0f70f636277443d6de199d3683fc565a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1233410 (cherry picked from commit 8bea05dbfa64af88587edb8927a8ec71c6b0d807) Reviewed-on: http://git-master/r/1239956 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix page alloc slab error conditionKonsta Holtta2016-10-20
| | | | | | | | | | | | | | | | | | | Return NULL instead of ERR_PTR from __gk20a_alloc_slab to be consistent with __gk20a_alloc_pages, and thus to work with an error check in gk20a_page_alloc in out-of-memory conditions. Bug 1799159 JIRA DNVGPU-100 Change-Id: I8c3c0e121840758c6aba860baac86a38e873e359 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1227730 (cherry picked from commit 209927a6b3bae4fddc2a6a745c1b4b1f46c6675c) Reviewed-on: http://git-master/r/1235192 Reviewed-by: Alex Waterman <alexw@nvidia.com> Tested-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix coverity problemAlex Waterman2016-10-20
| | | | | | | | | | | | | | | | Coverity detected a possible overflow during the left shift. This is likely not a big problem, though, since the number of pages to allocate would have to be greater than 2^32 (that would be 4 TB of memory assuming 4k page size and the literal 1 being a signed int by default). Bug 1799159 Change-Id: Ie1d6522defd13c794eb95aeee8c5c4203db00ebf Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1238632 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fixes for 32-bit compatibilitySachit Kadle2016-10-20
| | | | | | | | | | | | | Fixes to fence framework's usage of allocator APIs to be compatible w/ 32-bit architectures. Bug 1795076 Change-Id: Ia677f9842c36d482d4e82e9fa09613702f3111b3 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1237904 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: correct gpfifo size calculationSachit Kadle2016-10-20
| | | | | | | | | | | | | | | | | | | | | | This change fixes up the calculation of gpfifo entries, to be allocated depending on the ioctl used: 1) For the legacy ALLOC_GPFIFO ioctl, we preserve the calculation of gpfifo entries within the kernel. 2) For the new ALLOC_GPFIFO_EX ioctl, we assume that userspace has pre-calculated power-of-2 value. We process this value un-modified and only verify that it is a valid power-of-2. Bug 1795076 Change-Id: I8d2ddfdae40b02fe6b81e63dfd8857ad514a3dfd Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1220968 (cherry picked from commit c42396d9836e9b7ec73e0728f0c502b63aff70db) Reviewed-on: http://git-master/r/1223937 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add deterministic submit flagSachit Kadle2016-10-20
| | | | | | | | | | | | | | | | | | | | | This change adds a new ioctl flag, NVGPU_SUBMIT_GPFIFO_FLAGS_DETERMINISTIC, which indicates that a gpfifo submission must exhibit deterministic behavior within the kernel. For submissions that require job tracking and also set this flag, we require the channel to have previously pre-allocated job tracking resources. Bug 1795076 Change-Id: I0496a2513c6c683fcda161b32db9e7ee6712d45c Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1210527 (cherry picked from commit 0a36a0ce3a6cbe398931993e742fc928f7b2c0aa) Reviewed-on: http://git-master/r/1223935 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for pre-allocated resourcesSachit Kadle2016-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | Add support for pre-allocation of job tracking resources w/ new (extended) ioctl. Goal is to avoid dynamic memory allocation in the submit path. This patch does the following: 1) Intoduces a new ioctl, NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX, which enables pre-allocation of tracking resources per job: a) 2x priv_cmd_entry b) 2x gk20a_fence 2) Implements circular ring buffer for job tracking to avoid lock contention between producer (submitter) and consumer (clean-up) Bug 1795076 Change-Id: I6b52e5c575871107ff380f9a5790f440a6969347 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1203300 (cherry picked from commit 9fd270c22b860935dffe244753dabd87454bef39) Reviewed-on: http://git-master/r/1223934 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use inplace allocation in sync frameworkSachit Kadle2016-10-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is the first of a series of changes to support the usage of pre-allocated job tracking resources in the submit path. With this change, we still maintain a dynamically-allocated joblist, but make the necessary changes in the channel_sync & fence framework to use in-place allocations. Specifically, we: 1) Update channel sync framework routines to take in pre-allocated priv_cmd_entry(s) & gk20a_fence(s) rather than dynamically allocating themselves 2) Move allocation of priv_cmd_entry(s) & gk20a_fence(s) to gk20a_submit_prepare_syncs 3) Modify fence framework to have seperate allocation and init APIs. We expose allocation as a seperate API, so the client can allocate the object before passing it into the channel sync framework. 4) Fix clean_up logic in channel sync framework Bug 1795076 Change-Id: I96db457683cd207fd029c31c45f548f98055e844 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1206725 (cherry picked from commit 9d196fd10db6c2f934c2a53b1fc0500eb4626624) Reviewed-on: http://git-master/r/1223933 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: clear events from channel/TSG while closingDeepak Nibade2016-10-20
| | | | | | | | | | | | | | | | | | | | | | | | If User does not close the event fd created on channel/TSG, it is possible that the event stays on channel/TSG structure and reappears when channel/TSG is re-opened This causes false failure when we try to enable some event of channel/TSG since we do not allow enabling same event twice on same channel/TSG Fix this by removing all enabled events from channel/TSG while closing it Bug 200243092 Bug 1818654 Change-Id: I9d5ffc89f87cf4c44124f8015c2c2f0587ad2ef4 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1237723 (cherry picked from commit 2737a5c86cf5fbfe8a04f6a87764e8ecb9b30555) Reviewed-on: http://git-master/r/1238266 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Require version 30 for device 0x1c35Terje Bergstrom2016-10-20
| | | | | | | | | | | | | Raise the minimum VBIOS version for 0x1c35 to 86.06.30.00. Bug 1811880 Change-Id: I35f7511c3346394af45b8347e8c40f8d367bf3e0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1233401 (cherry picked from commit 9a92ef0f0ccf33c08d48d3a769158b30a0a1496c) Reviewed-on: http://git-master/r/1239429 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: VBIOS version checkTerje Bergstrom2016-10-20
| | | | | | | | | | | | | | | | | | Add a minimum VBIOS version field for each SKU. This requires the gk20a_platform structure to be per SKU. Also sets power_on back to false if there was any error in booting GPU. Bug 1811880 Change-Id: I23ef312f0db7061b31a3d503ded7e41ef45ad6b3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1227229 (cherry picked from commit 69c9ab4349ec7526a7f8a2fcad01f9128ed4769c) Reviewed-on: http://git-master/r/1239428 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable probing of gp106 sku10Sachit Kadle2016-10-20
| | | | | | | | | | | | | | | | Enable probing of gp106 sku10 by adding the device id to the known device table. JIRA DNVGPU-72 Change-Id: I2c10914c8510c6081202a374f50ef40371d7d183 Signed-off-by: Sachit Kadle <skadle@nvidia.com> Reviewed-on: http://git-master/r/1221123 (cherry picked from commit 17ff6de69f19212b6c6be39496f8e76c8554b861) Reviewed-on: http://git-master/r/1239427 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add support for devinit scripts execDavid Nieto2016-10-20
| | | | | | | | | | | | JIRA DNVGPU-117 Change-Id: I8c79e5b2fcad25588c950e786289443ed64fd48d Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1223221 (cherry-picked from commit f3185ad9f141ab32a224046185d0a409a8a513ff) Reviewed-on: http://git-master/r/1227254 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move ELCG programming to thermTerje Bergstrom2016-10-19
| | | | | | | | | | | | | | | Move ELCG parameter programming to a new function in therm, elcg_init_idle_filter. Implement gk20a variant and use it for gk20a and gm20b. JIRA DNVGPU-74 Change-Id: I8ef400f3a6195311fb9e7da8db6c34993d62f461 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1220433 (cherry picked from commit f6654ae4d83d31cd40b317bf55922964bbfa575d) Reviewed-on: http://git-master/r/1239421 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: check engine ctx_status in wait_idleDeepak Nibade2016-10-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have following bug where GPU Host reports non-idle when it should report engine idle - if a context is preempted off the GPU, and there is no other context to load, NV_PGRAPH_ENGINE_STATUS will not be idle until new context is loaded - this could cause gr_gk20a_wait_idle() to fail since here we rely only on NV_PGRAPH_ENGINE_STATUS to decide if engine is busy or not To fix this, first check if context is valid or not from NV_PFIFO_ENGINE_STATUS_CTX_STATUS If context is invalid, return immediately Otherwise, continue as before Also, add accessors for invalid ctx_status Bug 1826768 Change-Id: Id627be3f02e79f4beac59a8b5195d08eabf651f2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1237521 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Avoid 64 bit divisionAlex Waterman2016-10-18
| | | | | | | | | | | | | | | Avoid doing 64bit division in the page allocator. This causes problems on 32 bit platforms. Bug 1799159 Change-Id: I5166a71a4e84454686cce6d6cdca678a862a7ae7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1236799 (cherry picked from commit 21c091d1c00433acb9965c3d348d16fbb4c50c1a) Reviewed-on: http://git-master/r/1236195 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 19:00:59 -0400